1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
4  *
5  * Copyright (C) 2021 Renesas Electronics Corp.
6  *
7  * Based on r8a779a0-cpg-mssr.c
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/kernel.h>
16 #include <linux/soc/renesas/rcar-rst.h>
17 
18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
19 
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
22 
23 enum clk_ids {
24 	/* Core Clock Outputs exported to DT */
25 	LAST_DT_CORE_CLK = R8A779F0_CLK_R,
26 
27 	/* External Input Clocks */
28 	CLK_EXTAL,
29 	CLK_EXTALR,
30 
31 	/* Internal Core Clocks */
32 	CLK_MAIN,
33 	CLK_PLL1,
34 	CLK_PLL2,
35 	CLK_PLL3,
36 	CLK_PLL5,
37 	CLK_PLL6,
38 	CLK_PLL1_DIV2,
39 	CLK_PLL2_DIV2,
40 	CLK_PLL3_DIV2,
41 	CLK_PLL5_DIV2,
42 	CLK_PLL5_DIV4,
43 	CLK_PLL6_DIV2,
44 	CLK_S0,
45 	CLK_SDSRC,
46 	CLK_RPCSRC,
47 	CLK_OCO,
48 
49 	/* Module Clocks */
50 	MOD_CLK_BASE
51 };
52 
53 static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
54 	/* External Clock Inputs */
55 	DEF_INPUT("extal",	CLK_EXTAL),
56 	DEF_INPUT("extalr",	CLK_EXTALR),
57 
58 	/* Internal Core Clocks */
59 	DEF_BASE(".main", CLK_MAIN,	CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
60 	DEF_BASE(".pll1", CLK_PLL1,	CLK_TYPE_GEN4_PLL1, CLK_MAIN),
61 	DEF_BASE(".pll2", CLK_PLL2,	CLK_TYPE_GEN4_PLL2, CLK_MAIN),
62 	DEF_BASE(".pll3", CLK_PLL3,	CLK_TYPE_GEN4_PLL3, CLK_MAIN),
63 	DEF_BASE(".pll5", CLK_PLL5,	CLK_TYPE_GEN4_PLL5, CLK_MAIN),
64 	DEF_BASE(".pll6", CLK_PLL6,	CLK_TYPE_GEN4_PLL6, CLK_MAIN),
65 
66 	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
67 	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),
68 	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),
69 	DEF_FIXED(".pll5_div2",	CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),
70 	DEF_FIXED(".pll5_div4",	CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),
71 	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),
72 	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),
73 
74 	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
75 	DEF_RATE(".oco",	CLK_OCO,	32768),
76 
77 	DEF_BASE(".rpcsrc",	CLK_RPCSRC,	CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
78 
79 	/* Core Clock Outputs */
80 	DEF_GEN4_Z("z0",	R8A779F0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 0),
81 	DEF_GEN4_Z("z1",	R8A779F0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 8),
82 	DEF_FIXED("s0d2",	R8A779F0_CLK_S0D2,	CLK_S0,		2, 1),
83 	DEF_FIXED("s0d3",	R8A779F0_CLK_S0D3,	CLK_S0,		3, 1),
84 	DEF_FIXED("s0d4",	R8A779F0_CLK_S0D4,	CLK_S0,		4, 1),
85 	DEF_FIXED("cl16m",	R8A779F0_CLK_CL16M,	CLK_S0,		48, 1),
86 	DEF_FIXED("s0d2_mm",	R8A779F0_CLK_S0D2_MM,	CLK_S0,		2, 1),
87 	DEF_FIXED("s0d3_mm",	R8A779F0_CLK_S0D3_MM,	CLK_S0,		3, 1),
88 	DEF_FIXED("s0d4_mm",	R8A779F0_CLK_S0D4_MM,	CLK_S0,		4, 1),
89 	DEF_FIXED("cl16m_mm",	R8A779F0_CLK_CL16M_MM,	CLK_S0,		48, 1),
90 	DEF_FIXED("s0d2_rt",	R8A779F0_CLK_S0D2_RT,	CLK_S0,		2, 1),
91 	DEF_FIXED("s0d3_rt",	R8A779F0_CLK_S0D3_RT,	CLK_S0,		3, 1),
92 	DEF_FIXED("s0d4_rt",	R8A779F0_CLK_S0D4_RT,	CLK_S0,		4, 1),
93 	DEF_FIXED("s0d6_rt",	R8A779F0_CLK_S0D6_RT,	CLK_S0,		6, 1),
94 	DEF_FIXED("cl16m_rt",	R8A779F0_CLK_CL16M_RT,	CLK_S0,		48, 1),
95 	DEF_FIXED("s0d3_per",	R8A779F0_CLK_S0D3_PER,	CLK_S0,		3, 1),
96 	DEF_FIXED("s0d6_per",	R8A779F0_CLK_S0D6_PER,	CLK_S0,		6, 1),
97 	DEF_FIXED("s0d12_per",	R8A779F0_CLK_S0D12_PER,	CLK_S0,		12, 1),
98 	DEF_FIXED("s0d24_per",	R8A779F0_CLK_S0D24_PER,	CLK_S0,		24, 1),
99 	DEF_FIXED("cl16m_per",	R8A779F0_CLK_CL16M_PER,	CLK_S0,		48, 1),
100 	DEF_FIXED("s0d2_hsc",	R8A779F0_CLK_S0D2_HSC,	CLK_S0,		2, 1),
101 	DEF_FIXED("s0d3_hsc",	R8A779F0_CLK_S0D3_HSC,	CLK_S0,		3, 1),
102 	DEF_FIXED("s0d4_hsc",	R8A779F0_CLK_S0D4_HSC,	CLK_S0,		4, 1),
103 	DEF_FIXED("s0d6_hsc",	R8A779F0_CLK_S0D6_HSC,	CLK_S0,		6, 1),
104 	DEF_FIXED("s0d12_hsc",	R8A779F0_CLK_S0D12_HSC,	CLK_S0,		12, 1),
105 	DEF_FIXED("cl16m_hsc",	R8A779F0_CLK_CL16M_HSC,	CLK_S0,		48, 1),
106 	DEF_FIXED("s0d2_cc",	R8A779F0_CLK_S0D2_CC,	CLK_S0,		2, 1),
107 	DEF_FIXED("rsw2",	R8A779F0_CLK_RSW2,	CLK_PLL5_DIV2,	5, 1),
108 	DEF_FIXED("cbfusa",	R8A779F0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
109 	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),
110 
111 	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	CLK_SDSRC,	0x870),
112 
113 	DEF_BASE("rpc",		R8A779F0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
114 	DEF_BASE("rpcd2",	R8A779F0_CLK_RPCD2,	CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
115 
116 	DEF_DIV6P1("mso",	R8A779F0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
117 
118 	DEF_GEN4_OSC("osc",	R8A779F0_CLK_OSC,	CLK_EXTAL,	8),
119 	DEF_GEN4_MDSEL("r",	R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
120 };
121 
122 static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
123 	DEF_MOD("hscif0",	514,	R8A779F0_CLK_S0D3),
124 	DEF_MOD("hscif1",	515,	R8A779F0_CLK_S0D3),
125 	DEF_MOD("hscif2",	516,	R8A779F0_CLK_S0D3),
126 	DEF_MOD("hscif3",	517,	R8A779F0_CLK_S0D3),
127 	DEF_MOD("i2c0",		518,	R8A779F0_CLK_S0D6_PER),
128 	DEF_MOD("i2c1",		519,	R8A779F0_CLK_S0D6_PER),
129 	DEF_MOD("i2c2",		520,	R8A779F0_CLK_S0D6_PER),
130 	DEF_MOD("i2c3",		521,	R8A779F0_CLK_S0D6_PER),
131 	DEF_MOD("i2c4",		522,	R8A779F0_CLK_S0D6_PER),
132 	DEF_MOD("i2c5",		523,	R8A779F0_CLK_S0D6_PER),
133 	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),
134 	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),
135 	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),
136 	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),
137 	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),
138 	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),
139 	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),
140 	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),
141 	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),
142 	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),
143 	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),
144 	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),
145 	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),
146 };
147 
148 static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
149 	MOD_CLK_ID(907),	/* WDT */
150 };
151 
152 /*
153  * CPG Clock Data
154  */
155 /*
156  *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC
157  * 14 13 (MHz)
158  * ------------------------------------------------------------------------
159  * 0  0	 16    / 1	x200	x150	x200	n/a	x200	x134	/15
160  * 0  1	 20    / 1	x160	x120	x160	n/a	x160	x106	/19
161  * 1  0	 Prohibited setting
162  * 1  1	 40    / 2	x160	x120	x160	n/a	x160	x106	/38
163  */
164 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \
165 					 (((md) & BIT(13)) >> 13))
166 
167 static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {
168 	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */
169 	{ 1,		200,	1,	150,	1,	200,	1,	0,	0,	200,	1,	134,	1,	15,	},
170 	{ 1,		160,	1,	120,	1,	160,	1,	0,	0,	160,	1,	106,	1,	19,	},
171 	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},
172 	{ 2,		160,	1,	120,	1,	160,	1,	0,	0,	160,	1,	106,	1,	38,	},
173 };
174 
175 static int __init r8a779f0_cpg_mssr_init(struct device *dev)
176 {
177 	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;
178 	u32 cpg_mode;
179 	int error;
180 
181 	error = rcar_rst_read_mode_pins(&cpg_mode);
182 	if (error)
183 		return error;
184 
185 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
186 	if (!cpg_pll_config->extal_div) {
187 		dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
188 		return -EINVAL;
189 	}
190 
191 	return rcar_gen4_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
192 }
193 
194 const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = {
195 	/* Core Clocks */
196 	.core_clks = r8a779f0_core_clks,
197 	.num_core_clks = ARRAY_SIZE(r8a779f0_core_clks),
198 	.last_dt_core_clk = LAST_DT_CORE_CLK,
199 	.num_total_core_clks = MOD_CLK_BASE,
200 
201 	/* Module Clocks */
202 	.mod_clks = r8a779f0_mod_clks,
203 	.num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks),
204 	.num_hw_mod_clks = 28 * 32,
205 
206 	/* Critical Module Clocks */
207 	.crit_mod_clks = r8a779f0_crit_mod_clks,
208 	.num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks),
209 
210 	/* Callbacks */
211 	.init = r8a779f0_cpg_mssr_init,
212 	.cpg_clk_register = rcar_gen4_cpg_clk_register,
213 
214 	.reg_layout = CLK_REG_LAYOUT_RCAR_GEN4,
215 };
216