1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12
13 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
14
15 #include "clk-alpha-pll.h"
16 #include "clk-branch.h"
17 #include "clk-rcg.h"
18 #include "clk-regmap.h"
19 #include "clk-regmap-divider.h"
20 #include "common.h"
21 #include "gdsc.h"
22 #include "reset.h"
23
24 enum {
25 DT_BI_TCXO,
26 };
27
28 enum {
29 P_BI_TCXO,
30 P_VIDEO_CC_PLL0_OUT_MAIN,
31 P_VIDEO_CC_PLL1_OUT_MAIN,
32 };
33
34 static const struct pll_vco lucid_ole_vco[] = {
35 { 249600000, 2300000000, 0 },
36 };
37
38 static const struct alpha_pll_config video_cc_pll0_config = {
39 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
40 .l = 0x44440025,
41 .alpha = 0x8000,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00182261,
44 .config_ctl_hi1_val = 0x82aa299c,
45 .test_ctl_val = 0x00000000,
46 .test_ctl_hi_val = 0x00000003,
47 .test_ctl_hi1_val = 0x00009000,
48 .test_ctl_hi2_val = 0x00000034,
49 .user_ctl_val = 0x00000000,
50 .user_ctl_hi_val = 0x00000005,
51 };
52
53 static struct clk_alpha_pll video_cc_pll0 = {
54 .offset = 0x0,
55 .vco_table = lucid_ole_vco,
56 .num_vco = ARRAY_SIZE(lucid_ole_vco),
57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
58 .clkr = {
59 .hw.init = &(const struct clk_init_data) {
60 .name = "video_cc_pll0",
61 .parent_data = &(const struct clk_parent_data) {
62 .index = DT_BI_TCXO,
63 },
64 .num_parents = 1,
65 .ops = &clk_alpha_pll_lucid_evo_ops,
66 },
67 },
68 };
69
70 static const struct alpha_pll_config video_cc_pll1_config = {
71 /* .l includes RINGOSC_CAL_L_VAL, CAL_L_VAL, L_VAL fields */
72 .l = 0x44440036,
73 .alpha = 0xb000,
74 .config_ctl_val = 0x20485699,
75 .config_ctl_hi_val = 0x00182261,
76 .config_ctl_hi1_val = 0x82aa299c,
77 .test_ctl_val = 0x00000000,
78 .test_ctl_hi_val = 0x00000003,
79 .test_ctl_hi1_val = 0x00009000,
80 .test_ctl_hi2_val = 0x00000034,
81 .user_ctl_val = 0x00000000,
82 .user_ctl_hi_val = 0x00000005,
83 };
84
85 static struct clk_alpha_pll video_cc_pll1 = {
86 .offset = 0x1000,
87 .vco_table = lucid_ole_vco,
88 .num_vco = ARRAY_SIZE(lucid_ole_vco),
89 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
90 .clkr = {
91 .hw.init = &(const struct clk_init_data) {
92 .name = "video_cc_pll1",
93 .parent_data = &(const struct clk_parent_data) {
94 .index = DT_BI_TCXO,
95 },
96 .num_parents = 1,
97 .ops = &clk_alpha_pll_lucid_evo_ops,
98 },
99 },
100 };
101
102 static const struct parent_map video_cc_parent_map_0[] = {
103 { P_BI_TCXO, 0 },
104 { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
105 };
106
107 static const struct clk_parent_data video_cc_parent_data_0[] = {
108 { .index = DT_BI_TCXO },
109 { .hw = &video_cc_pll0.clkr.hw },
110 };
111
112 static const struct parent_map video_cc_parent_map_1[] = {
113 { P_BI_TCXO, 0 },
114 { P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
115 };
116
117 static const struct clk_parent_data video_cc_parent_data_1[] = {
118 { .index = DT_BI_TCXO },
119 { .hw = &video_cc_pll1.clkr.hw },
120 };
121
122 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
123 F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
124 F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
125 F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
126 F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
127 F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
128 { }
129 };
130
131 static struct clk_rcg2 video_cc_mvs0_clk_src = {
132 .cmd_rcgr = 0x8000,
133 .mnd_width = 0,
134 .hid_width = 5,
135 .parent_map = video_cc_parent_map_0,
136 .freq_tbl = ftbl_video_cc_mvs0_clk_src,
137 .clkr.hw.init = &(const struct clk_init_data) {
138 .name = "video_cc_mvs0_clk_src",
139 .parent_data = video_cc_parent_data_0,
140 .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
141 .flags = CLK_SET_RATE_PARENT,
142 .ops = &clk_rcg2_shared_ops,
143 },
144 };
145
146 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
147 F(1050000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
148 F(1350000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
149 F(1500000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
150 F(1650000000, P_VIDEO_CC_PLL1_OUT_MAIN, 1, 0, 0),
151 { }
152 };
153
154 static struct clk_rcg2 video_cc_mvs1_clk_src = {
155 .cmd_rcgr = 0x8018,
156 .mnd_width = 0,
157 .hid_width = 5,
158 .parent_map = video_cc_parent_map_1,
159 .freq_tbl = ftbl_video_cc_mvs1_clk_src,
160 .clkr.hw.init = &(const struct clk_init_data) {
161 .name = "video_cc_mvs1_clk_src",
162 .parent_data = video_cc_parent_data_1,
163 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
164 .flags = CLK_SET_RATE_PARENT,
165 .ops = &clk_rcg2_shared_ops,
166 },
167 };
168
169 static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
170 .reg = 0x80c4,
171 .shift = 0,
172 .width = 4,
173 .clkr.hw.init = &(const struct clk_init_data) {
174 .name = "video_cc_mvs0_div_clk_src",
175 .parent_hws = (const struct clk_hw*[]) {
176 &video_cc_mvs0_clk_src.clkr.hw,
177 },
178 .num_parents = 1,
179 .flags = CLK_SET_RATE_PARENT,
180 .ops = &clk_regmap_div_ro_ops,
181 },
182 };
183
184 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
185 .reg = 0x8070,
186 .shift = 0,
187 .width = 4,
188 .clkr.hw.init = &(const struct clk_init_data) {
189 .name = "video_cc_mvs0c_div2_div_clk_src",
190 .parent_hws = (const struct clk_hw*[]) {
191 &video_cc_mvs0_clk_src.clkr.hw,
192 },
193 .num_parents = 1,
194 .flags = CLK_SET_RATE_PARENT,
195 .ops = &clk_regmap_div_ro_ops,
196 },
197 };
198
199 static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
200 .reg = 0x80ec,
201 .shift = 0,
202 .width = 4,
203 .clkr.hw.init = &(const struct clk_init_data) {
204 .name = "video_cc_mvs1_div_clk_src",
205 .parent_hws = (const struct clk_hw*[]) {
206 &video_cc_mvs1_clk_src.clkr.hw,
207 },
208 .num_parents = 1,
209 .flags = CLK_SET_RATE_PARENT,
210 .ops = &clk_regmap_div_ro_ops,
211 },
212 };
213
214 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
215 .reg = 0x809c,
216 .shift = 0,
217 .width = 4,
218 .clkr.hw.init = &(const struct clk_init_data) {
219 .name = "video_cc_mvs1c_div2_div_clk_src",
220 .parent_hws = (const struct clk_hw*[]) {
221 &video_cc_mvs1_clk_src.clkr.hw,
222 },
223 .num_parents = 1,
224 .flags = CLK_SET_RATE_PARENT,
225 .ops = &clk_regmap_div_ro_ops,
226 },
227 };
228
229 static struct clk_branch video_cc_mvs0_clk = {
230 .halt_reg = 0x80b8,
231 .halt_check = BRANCH_HALT_SKIP,
232 .hwcg_reg = 0x80b8,
233 .hwcg_bit = 1,
234 .clkr = {
235 .enable_reg = 0x80b8,
236 .enable_mask = BIT(0),
237 .hw.init = &(const struct clk_init_data) {
238 .name = "video_cc_mvs0_clk",
239 .parent_hws = (const struct clk_hw*[]) {
240 &video_cc_mvs0_div_clk_src.clkr.hw,
241 },
242 .num_parents = 1,
243 .flags = CLK_SET_RATE_PARENT,
244 .ops = &clk_branch2_ops,
245 },
246 },
247 };
248
249 static struct clk_branch video_cc_mvs0c_clk = {
250 .halt_reg = 0x8064,
251 .halt_check = BRANCH_HALT,
252 .clkr = {
253 .enable_reg = 0x8064,
254 .enable_mask = BIT(0),
255 .hw.init = &(const struct clk_init_data) {
256 .name = "video_cc_mvs0c_clk",
257 .parent_hws = (const struct clk_hw*[]) {
258 &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
259 },
260 .num_parents = 1,
261 .flags = CLK_SET_RATE_PARENT,
262 .ops = &clk_branch2_ops,
263 },
264 },
265 };
266
267 static struct clk_branch video_cc_mvs1_clk = {
268 .halt_reg = 0x80e0,
269 .halt_check = BRANCH_HALT_SKIP,
270 .hwcg_reg = 0x80e0,
271 .hwcg_bit = 1,
272 .clkr = {
273 .enable_reg = 0x80e0,
274 .enable_mask = BIT(0),
275 .hw.init = &(const struct clk_init_data) {
276 .name = "video_cc_mvs1_clk",
277 .parent_hws = (const struct clk_hw*[]) {
278 &video_cc_mvs1_div_clk_src.clkr.hw,
279 },
280 .num_parents = 1,
281 .flags = CLK_SET_RATE_PARENT,
282 .ops = &clk_branch2_ops,
283 },
284 },
285 };
286
287 static struct clk_branch video_cc_mvs1c_clk = {
288 .halt_reg = 0x8090,
289 .halt_check = BRANCH_HALT,
290 .clkr = {
291 .enable_reg = 0x8090,
292 .enable_mask = BIT(0),
293 .hw.init = &(const struct clk_init_data) {
294 .name = "video_cc_mvs1c_clk",
295 .parent_hws = (const struct clk_hw*[]) {
296 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
297 },
298 .num_parents = 1,
299 .flags = CLK_SET_RATE_PARENT,
300 .ops = &clk_branch2_ops,
301 },
302 },
303 };
304
305 static struct gdsc video_cc_mvs0c_gdsc = {
306 .gdscr = 0x804c,
307 .en_rest_wait_val = 0x2,
308 .en_few_wait_val = 0x2,
309 .clk_dis_wait_val = 0x6,
310 .pd = {
311 .name = "video_cc_mvs0c_gdsc",
312 },
313 .pwrsts = PWRSTS_OFF_ON,
314 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
315 };
316
317 static struct gdsc video_cc_mvs0_gdsc = {
318 .gdscr = 0x80a4,
319 .en_rest_wait_val = 0x2,
320 .en_few_wait_val = 0x2,
321 .clk_dis_wait_val = 0x6,
322 .pd = {
323 .name = "video_cc_mvs0_gdsc",
324 },
325 .pwrsts = PWRSTS_OFF_ON,
326 .parent = &video_cc_mvs0c_gdsc.pd,
327 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
328 };
329
330 static struct gdsc video_cc_mvs1c_gdsc = {
331 .gdscr = 0x8078,
332 .en_rest_wait_val = 0x2,
333 .en_few_wait_val = 0x2,
334 .clk_dis_wait_val = 0x6,
335 .pd = {
336 .name = "video_cc_mvs1c_gdsc",
337 },
338 .pwrsts = PWRSTS_OFF_ON,
339 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
340 };
341
342 static struct gdsc video_cc_mvs1_gdsc = {
343 .gdscr = 0x80cc,
344 .en_rest_wait_val = 0x2,
345 .en_few_wait_val = 0x2,
346 .clk_dis_wait_val = 0x6,
347 .pd = {
348 .name = "video_cc_mvs1_gdsc",
349 },
350 .pwrsts = PWRSTS_OFF_ON,
351 .parent = &video_cc_mvs1c_gdsc.pd,
352 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL,
353 };
354
355 static struct clk_regmap *video_cc_sm8550_clocks[] = {
356 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
357 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
358 [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
359 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
360 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
361 [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
362 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
363 [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
364 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
365 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
366 [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
367 [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
368 };
369
370 static struct gdsc *video_cc_sm8550_gdscs[] = {
371 [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
372 [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
373 [VIDEO_CC_MVS1C_GDSC] = &video_cc_mvs1c_gdsc,
374 [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
375 };
376
377 static const struct qcom_reset_map video_cc_sm8550_resets[] = {
378 [CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80f0 },
379 [CVP_VIDEO_CC_MVS0_BCR] = { 0x80a0 },
380 [CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
381 [CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
382 [CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
383 [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
384 [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
385 };
386
387 static const struct regmap_config video_cc_sm8550_regmap_config = {
388 .reg_bits = 32,
389 .reg_stride = 4,
390 .val_bits = 32,
391 .max_register = 0x9f4c,
392 .fast_io = true,
393 };
394
395 static struct qcom_cc_desc video_cc_sm8550_desc = {
396 .config = &video_cc_sm8550_regmap_config,
397 .clks = video_cc_sm8550_clocks,
398 .num_clks = ARRAY_SIZE(video_cc_sm8550_clocks),
399 .resets = video_cc_sm8550_resets,
400 .num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
401 .gdscs = video_cc_sm8550_gdscs,
402 .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
403 };
404
405 static const struct of_device_id video_cc_sm8550_match_table[] = {
406 { .compatible = "qcom,sm8550-videocc" },
407 { }
408 };
409 MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
410
video_cc_sm8550_probe(struct platform_device * pdev)411 static int video_cc_sm8550_probe(struct platform_device *pdev)
412 {
413 struct regmap *regmap;
414 int ret;
415
416 ret = devm_pm_runtime_enable(&pdev->dev);
417 if (ret)
418 return ret;
419
420 ret = pm_runtime_resume_and_get(&pdev->dev);
421 if (ret)
422 return ret;
423
424 regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
425 if (IS_ERR(regmap)) {
426 pm_runtime_put(&pdev->dev);
427 return PTR_ERR(regmap);
428 }
429
430 clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
431 clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
432
433 /*
434 * Keep clocks always enabled:
435 * video_cc_ahb_clk
436 * video_cc_sleep_clk
437 * video_cc_xo_clk
438 */
439 regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0));
440 regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
441 regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
442
443 ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
444
445 pm_runtime_put(&pdev->dev);
446
447 return ret;
448 }
449
450 static struct platform_driver video_cc_sm8550_driver = {
451 .probe = video_cc_sm8550_probe,
452 .driver = {
453 .name = "video_cc-sm8550",
454 .of_match_table = video_cc_sm8550_match_table,
455 },
456 };
457
video_cc_sm8550_init(void)458 static int __init video_cc_sm8550_init(void)
459 {
460 return platform_driver_register(&video_cc_sm8550_driver);
461 }
462 subsys_initcall(video_cc_sm8550_init);
463
video_cc_sm8550_exit(void)464 static void __exit video_cc_sm8550_exit(void)
465 {
466 platform_driver_unregister(&video_cc_sm8550_driver);
467 }
468 module_exit(video_cc_sm8550_exit);
469
470 MODULE_DESCRIPTION("QTI VIDEOCC SM8550 Driver");
471 MODULE_LICENSE("GPL");
472