xref: /openbmc/linux/drivers/clk/qcom/camcc-sm8250.c (revision 433a2210)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
11 
12 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
13 
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
16 #include "clk-rcg.h"
17 #include "clk-regmap-divider.h"
18 #include "common.h"
19 #include "gdsc.h"
20 #include "reset.h"
21 
22 enum {
23 	P_BI_TCXO,
24 	P_CAM_CC_PLL0_OUT_EVEN,
25 	P_CAM_CC_PLL0_OUT_MAIN,
26 	P_CAM_CC_PLL0_OUT_ODD,
27 	P_CAM_CC_PLL1_OUT_EVEN,
28 	P_CAM_CC_PLL2_OUT_EARLY,
29 	P_CAM_CC_PLL2_OUT_MAIN,
30 	P_CAM_CC_PLL3_OUT_EVEN,
31 	P_CAM_CC_PLL4_OUT_EVEN,
32 	P_SLEEP_CLK,
33 };
34 
35 static struct pll_vco lucid_vco[] = {
36 	{ 249600000, 2000000000, 0 },
37 };
38 
39 static struct pll_vco zonda_vco[] = {
40 	{ 595200000UL, 3600000000UL, 0 },
41 };
42 
43 static const struct alpha_pll_config cam_cc_pll0_config = {
44 	.l = 0x3e,
45 	.alpha = 0x8000,
46 	.config_ctl_val = 0x20485699,
47 	.config_ctl_hi_val = 0x00002261,
48 	.config_ctl_hi1_val = 0x329A699c,
49 	.user_ctl_val = 0x00003100,
50 	.user_ctl_hi_val = 0x00000805,
51 	.user_ctl_hi1_val = 0x00000000,
52 };
53 
54 static struct clk_alpha_pll cam_cc_pll0 = {
55 	.offset = 0x0,
56 	.vco_table = lucid_vco,
57 	.num_vco = ARRAY_SIZE(lucid_vco),
58 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
59 	.clkr = {
60 		.hw.init = &(struct clk_init_data){
61 			.name = "cam_cc_pll0",
62 			.parent_data = &(const struct clk_parent_data){
63 				.fw_name = "bi_tcxo",
64 			},
65 			.num_parents = 1,
66 			.ops = &clk_alpha_pll_lucid_ops,
67 		},
68 	},
69 };
70 
71 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
72 	{ 0x1, 2 },
73 	{ }
74 };
75 
76 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
77 	.offset = 0x0,
78 	.post_div_shift = 8,
79 	.post_div_table = post_div_table_cam_cc_pll0_out_even,
80 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
81 	.width = 4,
82 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
83 	.clkr.hw.init = &(struct clk_init_data){
84 		.name = "cam_cc_pll0_out_even",
85 		.parent_hws = (const struct clk_hw*[]){
86 			&cam_cc_pll0.clkr.hw,
87 		},
88 		.num_parents = 1,
89 		.flags = CLK_SET_RATE_PARENT,
90 		.ops = &clk_alpha_pll_postdiv_lucid_ops,
91 	},
92 };
93 
94 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
95 	{ 0x3, 3 },
96 	{ }
97 };
98 
99 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
100 	.offset = 0x0,
101 	.post_div_shift = 12,
102 	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
103 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
104 	.width = 4,
105 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
106 	.clkr.hw.init = &(struct clk_init_data){
107 		.name = "cam_cc_pll0_out_odd",
108 		.parent_hws = (const struct clk_hw*[]){
109 			&cam_cc_pll0.clkr.hw,
110 		},
111 		.num_parents = 1,
112 		.flags = CLK_SET_RATE_PARENT,
113 		.ops = &clk_alpha_pll_postdiv_lucid_ops,
114 	},
115 };
116 
117 static const struct alpha_pll_config cam_cc_pll1_config = {
118 	.l = 0x1f,
119 	.alpha = 0x4000,
120 	.config_ctl_val = 0x20485699,
121 	.config_ctl_hi_val = 0x00002261,
122 	.config_ctl_hi1_val = 0x329A699c,
123 	.user_ctl_val = 0x00000100,
124 	.user_ctl_hi_val = 0x00000805,
125 	.user_ctl_hi1_val = 0x00000000,
126 };
127 
128 static struct clk_alpha_pll cam_cc_pll1 = {
129 	.offset = 0x1000,
130 	.vco_table = lucid_vco,
131 	.num_vco = ARRAY_SIZE(lucid_vco),
132 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
133 	.clkr = {
134 		.hw.init = &(struct clk_init_data){
135 			.name = "cam_cc_pll1",
136 			.parent_data = &(const struct clk_parent_data){
137 				.fw_name = "bi_tcxo",
138 			},
139 			.num_parents = 1,
140 			.ops = &clk_alpha_pll_lucid_ops,
141 		},
142 	},
143 };
144 
145 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
146 	{ 0x1, 2 },
147 	{ }
148 };
149 
150 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
151 	.offset = 0x1000,
152 	.post_div_shift = 8,
153 	.post_div_table = post_div_table_cam_cc_pll1_out_even,
154 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
155 	.width = 4,
156 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
157 	.clkr.hw.init = &(struct clk_init_data){
158 		.name = "cam_cc_pll1_out_even",
159 		.parent_hws = (const struct clk_hw*[]){
160 			&cam_cc_pll1.clkr.hw,
161 		},
162 		.num_parents = 1,
163 		.flags = CLK_SET_RATE_PARENT,
164 		.ops = &clk_alpha_pll_postdiv_lucid_ops,
165 	},
166 };
167 
168 static const struct alpha_pll_config cam_cc_pll2_config = {
169 	.l = 0x4b,
170 	.alpha = 0x0,
171 	.config_ctl_val = 0x08200920,
172 	.config_ctl_hi_val = 0x05002015,
173 	.config_ctl_hi1_val = 0x00000000,
174 	.user_ctl_val = 0x00000100,
175 	.user_ctl_hi_val = 0x00000000,
176 	.user_ctl_hi1_val = 0x00000000,
177 };
178 
179 static struct clk_alpha_pll cam_cc_pll2 = {
180 	.offset = 0x2000,
181 	.vco_table = zonda_vco,
182 	.num_vco = ARRAY_SIZE(zonda_vco),
183 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
184 	.clkr = {
185 		.hw.init = &(struct clk_init_data){
186 			.name = "cam_cc_pll2",
187 			.parent_data = &(const struct clk_parent_data){
188 				.fw_name = "bi_tcxo",
189 			},
190 			.num_parents = 1,
191 			.ops = &clk_alpha_pll_zonda_ops,
192 		},
193 	},
194 };
195 
196 static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
197 	{ 0x1, 2 },
198 	{ }
199 };
200 
201 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
202 	.offset = 0x2000,
203 	.post_div_shift = 8,
204 	.post_div_table = post_div_table_cam_cc_pll2_out_main,
205 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
206 	.width = 2,
207 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
208 	.clkr.hw.init = &(struct clk_init_data){
209 		.name = "cam_cc_pll2_out_main",
210 		.parent_hws = (const struct clk_hw*[]){
211 			&cam_cc_pll2.clkr.hw,
212 		},
213 		.num_parents = 1,
214 		.flags = CLK_SET_RATE_PARENT,
215 		.ops = &clk_alpha_pll_postdiv_zonda_ops,
216 	},
217 };
218 
219 static const struct alpha_pll_config cam_cc_pll3_config = {
220 	.l = 0x24,
221 	.alpha = 0x7555,
222 	.config_ctl_val = 0x20485699,
223 	.config_ctl_hi_val = 0x00002261,
224 	.config_ctl_hi1_val = 0x329A699c,
225 	.user_ctl_val = 0x00000100,
226 	.user_ctl_hi_val = 0x00000805,
227 	.user_ctl_hi1_val = 0x00000000,
228 };
229 
230 static struct clk_alpha_pll cam_cc_pll3 = {
231 	.offset = 0x3000,
232 	.vco_table = lucid_vco,
233 	.num_vco = ARRAY_SIZE(lucid_vco),
234 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
235 	.clkr = {
236 		.hw.init = &(struct clk_init_data){
237 			.name = "cam_cc_pll3",
238 			.parent_data = &(const struct clk_parent_data){
239 				.fw_name = "bi_tcxo",
240 			},
241 			.num_parents = 1,
242 			.ops = &clk_alpha_pll_lucid_ops,
243 		},
244 	},
245 };
246 
247 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
248 	{ 0x1, 2 },
249 	{ }
250 };
251 
252 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
253 	.offset = 0x3000,
254 	.post_div_shift = 8,
255 	.post_div_table = post_div_table_cam_cc_pll3_out_even,
256 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
257 	.width = 4,
258 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
259 	.clkr.hw.init = &(struct clk_init_data){
260 		.name = "cam_cc_pll3_out_even",
261 		.parent_hws = (const struct clk_hw*[]){
262 			&cam_cc_pll3.clkr.hw,
263 		},
264 		.num_parents = 1,
265 		.flags = CLK_SET_RATE_PARENT,
266 		.ops = &clk_alpha_pll_postdiv_lucid_ops,
267 	},
268 };
269 
270 static const struct alpha_pll_config cam_cc_pll4_config = {
271 	.l = 0x24,
272 	.alpha = 0x7555,
273 	.config_ctl_val = 0x20485699,
274 	.config_ctl_hi_val = 0x00002261,
275 	.config_ctl_hi1_val = 0x329A699c,
276 	.user_ctl_val = 0x00000100,
277 	.user_ctl_hi_val = 0x00000805,
278 	.user_ctl_hi1_val = 0x00000000,
279 };
280 
281 static struct clk_alpha_pll cam_cc_pll4 = {
282 	.offset = 0x4000,
283 	.vco_table = lucid_vco,
284 	.num_vco = ARRAY_SIZE(lucid_vco),
285 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
286 	.clkr = {
287 		.hw.init = &(struct clk_init_data){
288 			.name = "cam_cc_pll4",
289 			.parent_data = &(const struct clk_parent_data){
290 				.fw_name = "bi_tcxo",
291 			},
292 			.num_parents = 1,
293 			.ops = &clk_alpha_pll_lucid_ops,
294 		},
295 	},
296 };
297 
298 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
299 	{ 0x1, 2 },
300 	{ }
301 };
302 
303 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
304 	.offset = 0x4000,
305 	.post_div_shift = 8,
306 	.post_div_table = post_div_table_cam_cc_pll4_out_even,
307 	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
308 	.width = 4,
309 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
310 	.clkr.hw.init = &(struct clk_init_data){
311 		.name = "cam_cc_pll4_out_even",
312 		.parent_hws = (const struct clk_hw*[]){
313 			&cam_cc_pll4.clkr.hw,
314 		},
315 		.num_parents = 1,
316 		.flags = CLK_SET_RATE_PARENT,
317 		.ops = &clk_alpha_pll_postdiv_lucid_ops,
318 	},
319 };
320 
321 static const struct parent_map cam_cc_parent_map_0[] = {
322 	{ P_BI_TCXO, 0 },
323 	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
324 	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
325 	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
326 	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
327 };
328 
329 static const struct clk_parent_data cam_cc_parent_data_0[] = {
330 	{ .fw_name = "bi_tcxo" },
331 	{ .hw = &cam_cc_pll0.clkr.hw },
332 	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
333 	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
334 	{ .hw = &cam_cc_pll2_out_main.clkr.hw },
335 };
336 
337 static const struct parent_map cam_cc_parent_map_1[] = {
338 	{ P_BI_TCXO, 0 },
339 	{ P_CAM_CC_PLL2_OUT_EARLY, 5 },
340 };
341 
342 static const struct clk_parent_data cam_cc_parent_data_1[] = {
343 	{ .fw_name = "bi_tcxo" },
344 	{ .hw = &cam_cc_pll2.clkr.hw },
345 };
346 
347 static const struct parent_map cam_cc_parent_map_2[] = {
348 	{ P_BI_TCXO, 0 },
349 	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
350 };
351 
352 static const struct clk_parent_data cam_cc_parent_data_2[] = {
353 	{ .fw_name = "bi_tcxo" },
354 	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
355 };
356 
357 static const struct parent_map cam_cc_parent_map_3[] = {
358 	{ P_BI_TCXO, 0 },
359 	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
360 };
361 
362 static const struct clk_parent_data cam_cc_parent_data_3[] = {
363 	{ .fw_name = "bi_tcxo" },
364 	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
365 };
366 
367 static const struct parent_map cam_cc_parent_map_4[] = {
368 	{ P_BI_TCXO, 0 },
369 	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
370 };
371 
372 static const struct clk_parent_data cam_cc_parent_data_4[] = {
373 	{ .fw_name = "bi_tcxo" },
374 	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
375 };
376 
377 static const struct parent_map cam_cc_parent_map_5[] = {
378 	{ P_SLEEP_CLK, 0 },
379 };
380 
381 static const struct clk_parent_data cam_cc_parent_data_5[] = {
382 	{ .fw_name = "sleep_clk" },
383 };
384 
385 static const struct parent_map cam_cc_parent_map_6[] = {
386 	{ P_BI_TCXO, 0 },
387 };
388 
389 static const struct clk_parent_data cam_cc_parent_data_6[] = {
390 	{ .fw_name = "bi_tcxo" },
391 };
392 
393 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
394 	F(19200000, P_BI_TCXO, 1, 0, 0),
395 	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
396 	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
397 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
398 	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
399 	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
400 	{ }
401 };
402 
403 static struct clk_rcg2 cam_cc_bps_clk_src = {
404 	.cmd_rcgr = 0x7010,
405 	.mnd_width = 0,
406 	.hid_width = 5,
407 	.parent_map = cam_cc_parent_map_0,
408 	.freq_tbl = ftbl_cam_cc_bps_clk_src,
409 	.clkr.hw.init = &(struct clk_init_data){
410 		.name = "cam_cc_bps_clk_src",
411 		.parent_data = cam_cc_parent_data_0,
412 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
413 		.flags = CLK_SET_RATE_PARENT,
414 		.ops = &clk_rcg2_ops,
415 	},
416 };
417 
418 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
419 	F(19200000, P_BI_TCXO, 1, 0, 0),
420 	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
421 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
422 	{ }
423 };
424 
425 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
426 	.cmd_rcgr = 0xc0f8,
427 	.mnd_width = 0,
428 	.hid_width = 5,
429 	.parent_map = cam_cc_parent_map_0,
430 	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
431 	.clkr.hw.init = &(struct clk_init_data){
432 		.name = "cam_cc_camnoc_axi_clk_src",
433 		.parent_data = cam_cc_parent_data_0,
434 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
435 		.flags = CLK_SET_RATE_PARENT,
436 		.ops = &clk_rcg2_ops,
437 	},
438 };
439 
440 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
441 	F(19200000, P_BI_TCXO, 1, 0, 0),
442 	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
443 	{ }
444 };
445 
446 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
447 	.cmd_rcgr = 0xc0bc,
448 	.mnd_width = 8,
449 	.hid_width = 5,
450 	.parent_map = cam_cc_parent_map_0,
451 	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
452 	.clkr.hw.init = &(struct clk_init_data){
453 		.name = "cam_cc_cci_0_clk_src",
454 		.parent_data = cam_cc_parent_data_0,
455 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
456 		.flags = CLK_SET_RATE_PARENT,
457 		.ops = &clk_rcg2_ops,
458 	},
459 };
460 
461 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
462 	.cmd_rcgr = 0xc0d8,
463 	.mnd_width = 8,
464 	.hid_width = 5,
465 	.parent_map = cam_cc_parent_map_0,
466 	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
467 	.clkr.hw.init = &(struct clk_init_data){
468 		.name = "cam_cc_cci_1_clk_src",
469 		.parent_data = cam_cc_parent_data_0,
470 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
471 		.flags = CLK_SET_RATE_PARENT,
472 		.ops = &clk_rcg2_ops,
473 	},
474 };
475 
476 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
477 	F(19200000, P_BI_TCXO, 1, 0, 0),
478 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
479 	{ }
480 };
481 
482 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
483 	.cmd_rcgr = 0xa068,
484 	.mnd_width = 0,
485 	.hid_width = 5,
486 	.parent_map = cam_cc_parent_map_0,
487 	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
488 	.clkr.hw.init = &(struct clk_init_data){
489 		.name = "cam_cc_cphy_rx_clk_src",
490 		.parent_data = cam_cc_parent_data_0,
491 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
492 		.flags = CLK_SET_RATE_PARENT,
493 		.ops = &clk_rcg2_ops,
494 	},
495 };
496 
497 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
498 	F(19200000, P_BI_TCXO, 1, 0, 0),
499 	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
500 	{ }
501 };
502 
503 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
504 	.cmd_rcgr = 0x6000,
505 	.mnd_width = 0,
506 	.hid_width = 5,
507 	.parent_map = cam_cc_parent_map_0,
508 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
509 	.clkr.hw.init = &(struct clk_init_data){
510 		.name = "cam_cc_csi0phytimer_clk_src",
511 		.parent_data = cam_cc_parent_data_0,
512 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
513 		.flags = CLK_SET_RATE_PARENT,
514 		.ops = &clk_rcg2_ops,
515 	},
516 };
517 
518 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
519 	.cmd_rcgr = 0x6020,
520 	.mnd_width = 0,
521 	.hid_width = 5,
522 	.parent_map = cam_cc_parent_map_0,
523 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
524 	.clkr.hw.init = &(struct clk_init_data){
525 		.name = "cam_cc_csi1phytimer_clk_src",
526 		.parent_data = cam_cc_parent_data_0,
527 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
528 		.flags = CLK_SET_RATE_PARENT,
529 		.ops = &clk_rcg2_ops,
530 	},
531 };
532 
533 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
534 	.cmd_rcgr = 0x6040,
535 	.mnd_width = 0,
536 	.hid_width = 5,
537 	.parent_map = cam_cc_parent_map_0,
538 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
539 	.clkr.hw.init = &(struct clk_init_data){
540 		.name = "cam_cc_csi2phytimer_clk_src",
541 		.parent_data = cam_cc_parent_data_0,
542 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
543 		.flags = CLK_SET_RATE_PARENT,
544 		.ops = &clk_rcg2_ops,
545 	},
546 };
547 
548 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
549 	.cmd_rcgr = 0x6060,
550 	.mnd_width = 0,
551 	.hid_width = 5,
552 	.parent_map = cam_cc_parent_map_0,
553 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
554 	.clkr.hw.init = &(struct clk_init_data){
555 		.name = "cam_cc_csi3phytimer_clk_src",
556 		.parent_data = cam_cc_parent_data_0,
557 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
558 		.flags = CLK_SET_RATE_PARENT,
559 		.ops = &clk_rcg2_ops,
560 	},
561 };
562 
563 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
564 	.cmd_rcgr = 0x6080,
565 	.mnd_width = 0,
566 	.hid_width = 5,
567 	.parent_map = cam_cc_parent_map_0,
568 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
569 	.clkr.hw.init = &(struct clk_init_data){
570 		.name = "cam_cc_csi4phytimer_clk_src",
571 		.parent_data = cam_cc_parent_data_0,
572 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
573 		.flags = CLK_SET_RATE_PARENT,
574 		.ops = &clk_rcg2_ops,
575 	},
576 };
577 
578 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
579 	.cmd_rcgr = 0x60a0,
580 	.mnd_width = 0,
581 	.hid_width = 5,
582 	.parent_map = cam_cc_parent_map_0,
583 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
584 	.clkr.hw.init = &(struct clk_init_data){
585 		.name = "cam_cc_csi5phytimer_clk_src",
586 		.parent_data = cam_cc_parent_data_0,
587 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
588 		.flags = CLK_SET_RATE_PARENT,
589 		.ops = &clk_rcg2_ops,
590 	},
591 };
592 
593 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
594 	F(19200000, P_BI_TCXO, 1, 0, 0),
595 	F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
596 	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
597 	F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
598 	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
599 	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
600 	{ }
601 };
602 
603 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
604 	.cmd_rcgr = 0x703c,
605 	.mnd_width = 0,
606 	.hid_width = 5,
607 	.parent_map = cam_cc_parent_map_0,
608 	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
609 	.clkr.hw.init = &(struct clk_init_data){
610 		.name = "cam_cc_fast_ahb_clk_src",
611 		.parent_data = cam_cc_parent_data_0,
612 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
613 		.flags = CLK_SET_RATE_PARENT,
614 		.ops = &clk_rcg2_ops,
615 	},
616 };
617 
618 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
619 	F(19200000, P_BI_TCXO, 1, 0, 0),
620 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
621 	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
622 	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
623 	{ }
624 };
625 
626 static struct clk_rcg2 cam_cc_fd_core_clk_src = {
627 	.cmd_rcgr = 0xc098,
628 	.mnd_width = 0,
629 	.hid_width = 5,
630 	.parent_map = cam_cc_parent_map_0,
631 	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
632 	.clkr.hw.init = &(struct clk_init_data){
633 		.name = "cam_cc_fd_core_clk_src",
634 		.parent_data = cam_cc_parent_data_0,
635 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
636 		.flags = CLK_SET_RATE_PARENT,
637 		.ops = &clk_rcg2_ops,
638 	},
639 };
640 
641 static struct clk_rcg2 cam_cc_icp_clk_src = {
642 	.cmd_rcgr = 0xc074,
643 	.mnd_width = 0,
644 	.hid_width = 5,
645 	.parent_map = cam_cc_parent_map_0,
646 	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
647 	.clkr.hw.init = &(struct clk_init_data){
648 		.name = "cam_cc_icp_clk_src",
649 		.parent_data = cam_cc_parent_data_0,
650 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
651 		.flags = CLK_SET_RATE_PARENT,
652 		.ops = &clk_rcg2_ops,
653 	},
654 };
655 
656 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
657 	F(19200000, P_BI_TCXO, 1, 0, 0),
658 	F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
659 	F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
660 	F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
661 	F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
662 	{ }
663 };
664 
665 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
666 	.cmd_rcgr = 0xa010,
667 	.mnd_width = 0,
668 	.hid_width = 5,
669 	.parent_map = cam_cc_parent_map_2,
670 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
671 	.clkr.hw.init = &(struct clk_init_data){
672 		.name = "cam_cc_ife_0_clk_src",
673 		.parent_data = cam_cc_parent_data_2,
674 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
675 		.flags = CLK_SET_RATE_PARENT,
676 		.ops = &clk_rcg2_ops,
677 	},
678 };
679 
680 static struct clk_regmap_div cam_cc_sbi_div_clk_src = {
681 	.reg = 0x9010,
682 	.shift = 0,
683 	.width = 3,
684 	.clkr.hw.init = &(struct clk_init_data) {
685 		.name = "cam_cc_sbi_div_clk_src",
686 		.parent_hws = (const struct clk_hw*[]){
687 			&cam_cc_ife_0_clk_src.clkr.hw,
688 		},
689 		.num_parents = 1,
690 		.flags = CLK_SET_RATE_PARENT,
691 		.ops = &clk_regmap_div_ro_ops,
692 	},
693 };
694 
695 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
696 	F(19200000, P_BI_TCXO, 1, 0, 0),
697 	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
698 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
699 	{ }
700 };
701 
702 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
703 	.cmd_rcgr = 0xa040,
704 	.mnd_width = 0,
705 	.hid_width = 5,
706 	.parent_map = cam_cc_parent_map_0,
707 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
708 	.clkr.hw.init = &(struct clk_init_data){
709 		.name = "cam_cc_ife_0_csid_clk_src",
710 		.parent_data = cam_cc_parent_data_0,
711 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
712 		.flags = CLK_SET_RATE_PARENT,
713 		.ops = &clk_rcg2_ops,
714 	},
715 };
716 
717 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
718 	F(19200000, P_BI_TCXO, 1, 0, 0),
719 	F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
720 	F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
721 	F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
722 	F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
723 	{ }
724 };
725 
726 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
727 	.cmd_rcgr = 0xb010,
728 	.mnd_width = 0,
729 	.hid_width = 5,
730 	.parent_map = cam_cc_parent_map_3,
731 	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
732 	.clkr.hw.init = &(struct clk_init_data){
733 		.name = "cam_cc_ife_1_clk_src",
734 		.parent_data = cam_cc_parent_data_3,
735 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
736 		.flags = CLK_SET_RATE_PARENT,
737 		.ops = &clk_rcg2_ops,
738 	},
739 };
740 
741 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
742 	.cmd_rcgr = 0xb040,
743 	.mnd_width = 0,
744 	.hid_width = 5,
745 	.parent_map = cam_cc_parent_map_0,
746 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
747 	.clkr.hw.init = &(struct clk_init_data){
748 		.name = "cam_cc_ife_1_csid_clk_src",
749 		.parent_data = cam_cc_parent_data_0,
750 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
751 		.flags = CLK_SET_RATE_PARENT,
752 		.ops = &clk_rcg2_ops,
753 	},
754 };
755 
756 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
757 	F(19200000, P_BI_TCXO, 1, 0, 0),
758 	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
759 	F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
760 	{ }
761 };
762 
763 static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
764 	.cmd_rcgr = 0xc000,
765 	.mnd_width = 0,
766 	.hid_width = 5,
767 	.parent_map = cam_cc_parent_map_0,
768 	.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
769 	.clkr.hw.init = &(struct clk_init_data){
770 		.name = "cam_cc_ife_lite_clk_src",
771 		.parent_data = cam_cc_parent_data_0,
772 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
773 		.flags = CLK_SET_RATE_PARENT,
774 		.ops = &clk_rcg2_ops,
775 	},
776 };
777 
778 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
779 	.cmd_rcgr = 0xc01c,
780 	.mnd_width = 0,
781 	.hid_width = 5,
782 	.parent_map = cam_cc_parent_map_0,
783 	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
784 	.clkr.hw.init = &(struct clk_init_data){
785 		.name = "cam_cc_ife_lite_csid_clk_src",
786 		.parent_data = cam_cc_parent_data_0,
787 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
788 		.flags = CLK_SET_RATE_PARENT,
789 		.ops = &clk_rcg2_ops,
790 	},
791 };
792 
793 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
794 	F(19200000, P_BI_TCXO, 1, 0, 0),
795 	F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
796 	F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
797 	F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
798 	F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
799 	{ }
800 };
801 
802 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
803 	.cmd_rcgr = 0x8010,
804 	.mnd_width = 0,
805 	.hid_width = 5,
806 	.parent_map = cam_cc_parent_map_4,
807 	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
808 	.clkr.hw.init = &(struct clk_init_data){
809 		.name = "cam_cc_ipe_0_clk_src",
810 		.parent_data = cam_cc_parent_data_4,
811 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
812 		.flags = CLK_SET_RATE_PARENT,
813 		.ops = &clk_rcg2_ops,
814 	},
815 };
816 
817 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
818 	.cmd_rcgr = 0xc048,
819 	.mnd_width = 0,
820 	.hid_width = 5,
821 	.parent_map = cam_cc_parent_map_0,
822 	.freq_tbl = ftbl_cam_cc_bps_clk_src,
823 	.clkr.hw.init = &(struct clk_init_data){
824 		.name = "cam_cc_jpeg_clk_src",
825 		.parent_data = cam_cc_parent_data_0,
826 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
827 		.flags = CLK_SET_RATE_PARENT,
828 		.ops = &clk_rcg2_ops,
829 	},
830 };
831 
832 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
833 	F(19200000, P_BI_TCXO, 1, 0, 0),
834 	F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
835 	F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21),
836 	{ }
837 };
838 
839 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
840 	.cmd_rcgr = 0x5000,
841 	.mnd_width = 8,
842 	.hid_width = 5,
843 	.parent_map = cam_cc_parent_map_1,
844 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
845 	.clkr.hw.init = &(struct clk_init_data){
846 		.name = "cam_cc_mclk0_clk_src",
847 		.parent_data = cam_cc_parent_data_1,
848 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
849 		.flags = CLK_SET_RATE_PARENT,
850 		.ops = &clk_rcg2_ops,
851 	},
852 };
853 
854 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
855 	.cmd_rcgr = 0x501c,
856 	.mnd_width = 8,
857 	.hid_width = 5,
858 	.parent_map = cam_cc_parent_map_1,
859 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
860 	.clkr.hw.init = &(struct clk_init_data){
861 		.name = "cam_cc_mclk1_clk_src",
862 		.parent_data = cam_cc_parent_data_1,
863 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
864 		.flags = CLK_SET_RATE_PARENT,
865 		.ops = &clk_rcg2_ops,
866 	},
867 };
868 
869 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
870 	.cmd_rcgr = 0x5038,
871 	.mnd_width = 8,
872 	.hid_width = 5,
873 	.parent_map = cam_cc_parent_map_1,
874 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
875 	.clkr.hw.init = &(struct clk_init_data){
876 		.name = "cam_cc_mclk2_clk_src",
877 		.parent_data = cam_cc_parent_data_1,
878 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
879 		.flags = CLK_SET_RATE_PARENT,
880 		.ops = &clk_rcg2_ops,
881 	},
882 };
883 
884 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
885 	.cmd_rcgr = 0x5054,
886 	.mnd_width = 8,
887 	.hid_width = 5,
888 	.parent_map = cam_cc_parent_map_1,
889 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
890 	.clkr.hw.init = &(struct clk_init_data){
891 		.name = "cam_cc_mclk3_clk_src",
892 		.parent_data = cam_cc_parent_data_1,
893 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
894 		.flags = CLK_SET_RATE_PARENT,
895 		.ops = &clk_rcg2_ops,
896 	},
897 };
898 
899 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
900 	.cmd_rcgr = 0x5070,
901 	.mnd_width = 8,
902 	.hid_width = 5,
903 	.parent_map = cam_cc_parent_map_1,
904 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
905 	.clkr.hw.init = &(struct clk_init_data){
906 		.name = "cam_cc_mclk4_clk_src",
907 		.parent_data = cam_cc_parent_data_1,
908 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
909 		.flags = CLK_SET_RATE_PARENT,
910 		.ops = &clk_rcg2_ops,
911 	},
912 };
913 
914 static struct clk_rcg2 cam_cc_mclk5_clk_src = {
915 	.cmd_rcgr = 0x508c,
916 	.mnd_width = 8,
917 	.hid_width = 5,
918 	.parent_map = cam_cc_parent_map_1,
919 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
920 	.clkr.hw.init = &(struct clk_init_data){
921 		.name = "cam_cc_mclk5_clk_src",
922 		.parent_data = cam_cc_parent_data_1,
923 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
924 		.flags = CLK_SET_RATE_PARENT,
925 		.ops = &clk_rcg2_ops,
926 	},
927 };
928 
929 static struct clk_rcg2 cam_cc_mclk6_clk_src = {
930 	.cmd_rcgr = 0x50a8,
931 	.mnd_width = 8,
932 	.hid_width = 5,
933 	.parent_map = cam_cc_parent_map_1,
934 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
935 	.clkr.hw.init = &(struct clk_init_data){
936 		.name = "cam_cc_mclk6_clk_src",
937 		.parent_data = cam_cc_parent_data_1,
938 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
939 		.flags = CLK_SET_RATE_PARENT,
940 		.ops = &clk_rcg2_ops,
941 	},
942 };
943 
944 static struct clk_rcg2 cam_cc_sbi_csid_clk_src = {
945 	.cmd_rcgr = 0x901c,
946 	.mnd_width = 0,
947 	.hid_width = 5,
948 	.parent_map = cam_cc_parent_map_0,
949 	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
950 	.clkr.hw.init = &(struct clk_init_data){
951 		.name = "cam_cc_sbi_csid_clk_src",
952 		.parent_data = cam_cc_parent_data_0,
953 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
954 		.flags = CLK_SET_RATE_PARENT,
955 		.ops = &clk_rcg2_ops,
956 	},
957 };
958 
959 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
960 	F(32768, P_SLEEP_CLK, 1, 0, 0),
961 	{ }
962 };
963 
964 static struct clk_rcg2 cam_cc_sleep_clk_src = {
965 	.cmd_rcgr = 0xc170,
966 	.mnd_width = 0,
967 	.hid_width = 5,
968 	.parent_map = cam_cc_parent_map_5,
969 	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
970 	.clkr.hw.init = &(struct clk_init_data){
971 		.name = "cam_cc_sleep_clk_src",
972 		.parent_data = cam_cc_parent_data_5,
973 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
974 		.flags = CLK_SET_RATE_PARENT,
975 		.ops = &clk_rcg2_ops,
976 	},
977 };
978 
979 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
980 	F(19200000, P_BI_TCXO, 1, 0, 0),
981 	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
982 	{ }
983 };
984 
985 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
986 	.cmd_rcgr = 0x7058,
987 	.mnd_width = 8,
988 	.hid_width = 5,
989 	.parent_map = cam_cc_parent_map_0,
990 	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
991 	.clkr.hw.init = &(struct clk_init_data){
992 		.name = "cam_cc_slow_ahb_clk_src",
993 		.parent_data = cam_cc_parent_data_0,
994 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
995 		.flags = CLK_SET_RATE_PARENT,
996 		.ops = &clk_rcg2_ops,
997 	},
998 };
999 
1000 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1001 	F(19200000, P_BI_TCXO, 1, 0, 0),
1002 	{ }
1003 };
1004 
1005 static struct clk_rcg2 cam_cc_xo_clk_src = {
1006 	.cmd_rcgr = 0xc154,
1007 	.mnd_width = 0,
1008 	.hid_width = 5,
1009 	.parent_map = cam_cc_parent_map_6,
1010 	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1011 	.clkr.hw.init = &(struct clk_init_data){
1012 		.name = "cam_cc_xo_clk_src",
1013 		.parent_data = cam_cc_parent_data_6,
1014 		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1015 		.flags = CLK_SET_RATE_PARENT,
1016 		.ops = &clk_rcg2_ops,
1017 	},
1018 };
1019 
1020 static struct clk_branch cam_cc_bps_ahb_clk = {
1021 	.halt_reg = 0x7070,
1022 	.halt_check = BRANCH_HALT,
1023 	.clkr = {
1024 		.enable_reg = 0x7070,
1025 		.enable_mask = BIT(0),
1026 		.hw.init = &(struct clk_init_data){
1027 			.name = "cam_cc_bps_ahb_clk",
1028 			.parent_hws = (const struct clk_hw*[]){
1029 				&cam_cc_slow_ahb_clk_src.clkr.hw
1030 			},
1031 			.num_parents = 1,
1032 			.flags = CLK_SET_RATE_PARENT,
1033 			.ops = &clk_branch2_ops,
1034 		},
1035 	},
1036 };
1037 
1038 static struct clk_branch cam_cc_bps_areg_clk = {
1039 	.halt_reg = 0x7054,
1040 	.halt_check = BRANCH_HALT,
1041 	.clkr = {
1042 		.enable_reg = 0x7054,
1043 		.enable_mask = BIT(0),
1044 		.hw.init = &(struct clk_init_data){
1045 			.name = "cam_cc_bps_areg_clk",
1046 			.parent_hws = (const struct clk_hw*[]){
1047 				&cam_cc_fast_ahb_clk_src.clkr.hw
1048 			},
1049 			.num_parents = 1,
1050 			.flags = CLK_SET_RATE_PARENT,
1051 			.ops = &clk_branch2_ops,
1052 		},
1053 	},
1054 };
1055 
1056 static struct clk_branch cam_cc_bps_axi_clk = {
1057 	.halt_reg = 0x7038,
1058 	.halt_check = BRANCH_HALT,
1059 	.clkr = {
1060 		.enable_reg = 0x7038,
1061 		.enable_mask = BIT(0),
1062 		.hw.init = &(struct clk_init_data){
1063 			.name = "cam_cc_bps_axi_clk",
1064 			.parent_hws = (const struct clk_hw*[]){
1065 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1066 			},
1067 			.num_parents = 1,
1068 			.flags = CLK_SET_RATE_PARENT,
1069 			.ops = &clk_branch2_ops,
1070 		},
1071 	},
1072 };
1073 
1074 static struct clk_branch cam_cc_bps_clk = {
1075 	.halt_reg = 0x7028,
1076 	.halt_check = BRANCH_HALT,
1077 	.clkr = {
1078 		.enable_reg = 0x7028,
1079 		.enable_mask = BIT(0),
1080 		.hw.init = &(struct clk_init_data){
1081 			.name = "cam_cc_bps_clk",
1082 			.parent_hws = (const struct clk_hw*[]){
1083 				&cam_cc_bps_clk_src.clkr.hw
1084 			},
1085 			.num_parents = 1,
1086 			.flags = CLK_SET_RATE_PARENT,
1087 			.ops = &clk_branch2_ops,
1088 		},
1089 	},
1090 };
1091 
1092 static struct clk_branch cam_cc_camnoc_axi_clk = {
1093 	.halt_reg = 0xc114,
1094 	.halt_check = BRANCH_HALT,
1095 	.clkr = {
1096 		.enable_reg = 0xc114,
1097 		.enable_mask = BIT(0),
1098 		.hw.init = &(struct clk_init_data){
1099 			.name = "cam_cc_camnoc_axi_clk",
1100 			.parent_hws = (const struct clk_hw*[]){
1101 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1102 			},
1103 			.num_parents = 1,
1104 			.flags = CLK_SET_RATE_PARENT,
1105 			.ops = &clk_branch2_ops,
1106 		},
1107 	},
1108 };
1109 
1110 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1111 	.halt_reg = 0xc11c,
1112 	.halt_check = BRANCH_HALT,
1113 	.clkr = {
1114 		.enable_reg = 0xc11c,
1115 		.enable_mask = BIT(0),
1116 		.hw.init = &(struct clk_init_data){
1117 			.name = "cam_cc_camnoc_dcd_xo_clk",
1118 			.parent_hws = (const struct clk_hw*[]){
1119 				&cam_cc_xo_clk_src.clkr.hw
1120 			},
1121 			.num_parents = 1,
1122 			.flags = CLK_SET_RATE_PARENT,
1123 			.ops = &clk_branch2_ops,
1124 		},
1125 	},
1126 };
1127 
1128 static struct clk_branch cam_cc_cci_0_clk = {
1129 	.halt_reg = 0xc0d4,
1130 	.halt_check = BRANCH_HALT,
1131 	.clkr = {
1132 		.enable_reg = 0xc0d4,
1133 		.enable_mask = BIT(0),
1134 		.hw.init = &(struct clk_init_data){
1135 			.name = "cam_cc_cci_0_clk",
1136 			.parent_hws = (const struct clk_hw*[]){
1137 				&cam_cc_cci_0_clk_src.clkr.hw
1138 			},
1139 			.num_parents = 1,
1140 			.flags = CLK_SET_RATE_PARENT,
1141 			.ops = &clk_branch2_ops,
1142 		},
1143 	},
1144 };
1145 
1146 static struct clk_branch cam_cc_cci_1_clk = {
1147 	.halt_reg = 0xc0f0,
1148 	.halt_check = BRANCH_HALT,
1149 	.clkr = {
1150 		.enable_reg = 0xc0f0,
1151 		.enable_mask = BIT(0),
1152 		.hw.init = &(struct clk_init_data){
1153 			.name = "cam_cc_cci_1_clk",
1154 			.parent_hws = (const struct clk_hw*[]){
1155 				&cam_cc_cci_1_clk_src.clkr.hw
1156 			},
1157 			.num_parents = 1,
1158 			.flags = CLK_SET_RATE_PARENT,
1159 			.ops = &clk_branch2_ops,
1160 		},
1161 	},
1162 };
1163 
1164 static struct clk_branch cam_cc_core_ahb_clk = {
1165 	.halt_reg = 0xc150,
1166 	.halt_check = BRANCH_HALT_DELAY,
1167 	.clkr = {
1168 		.enable_reg = 0xc150,
1169 		.enable_mask = BIT(0),
1170 		.hw.init = &(struct clk_init_data){
1171 			.name = "cam_cc_core_ahb_clk",
1172 			.parent_hws = (const struct clk_hw*[]){
1173 				&cam_cc_slow_ahb_clk_src.clkr.hw
1174 			},
1175 			.num_parents = 1,
1176 			.flags = CLK_SET_RATE_PARENT,
1177 			.ops = &clk_branch2_ops,
1178 		},
1179 	},
1180 };
1181 
1182 static struct clk_branch cam_cc_cpas_ahb_clk = {
1183 	.halt_reg = 0xc0f4,
1184 	.halt_check = BRANCH_HALT,
1185 	.clkr = {
1186 		.enable_reg = 0xc0f4,
1187 		.enable_mask = BIT(0),
1188 		.hw.init = &(struct clk_init_data){
1189 			.name = "cam_cc_cpas_ahb_clk",
1190 			.parent_hws = (const struct clk_hw*[]){
1191 				&cam_cc_slow_ahb_clk_src.clkr.hw
1192 			},
1193 			.num_parents = 1,
1194 			.flags = CLK_SET_RATE_PARENT,
1195 			.ops = &clk_branch2_ops,
1196 		},
1197 	},
1198 };
1199 
1200 static struct clk_branch cam_cc_csi0phytimer_clk = {
1201 	.halt_reg = 0x6018,
1202 	.halt_check = BRANCH_HALT,
1203 	.clkr = {
1204 		.enable_reg = 0x6018,
1205 		.enable_mask = BIT(0),
1206 		.hw.init = &(struct clk_init_data){
1207 			.name = "cam_cc_csi0phytimer_clk",
1208 			.parent_hws = (const struct clk_hw*[]){
1209 				&cam_cc_csi0phytimer_clk_src.clkr.hw
1210 			},
1211 			.num_parents = 1,
1212 			.flags = CLK_SET_RATE_PARENT,
1213 			.ops = &clk_branch2_ops,
1214 		},
1215 	},
1216 };
1217 
1218 static struct clk_branch cam_cc_csi1phytimer_clk = {
1219 	.halt_reg = 0x6038,
1220 	.halt_check = BRANCH_HALT,
1221 	.clkr = {
1222 		.enable_reg = 0x6038,
1223 		.enable_mask = BIT(0),
1224 		.hw.init = &(struct clk_init_data){
1225 			.name = "cam_cc_csi1phytimer_clk",
1226 			.parent_hws = (const struct clk_hw*[]){
1227 				&cam_cc_csi1phytimer_clk_src.clkr.hw
1228 			},
1229 			.num_parents = 1,
1230 			.flags = CLK_SET_RATE_PARENT,
1231 			.ops = &clk_branch2_ops,
1232 		},
1233 	},
1234 };
1235 
1236 static struct clk_branch cam_cc_csi2phytimer_clk = {
1237 	.halt_reg = 0x6058,
1238 	.halt_check = BRANCH_HALT,
1239 	.clkr = {
1240 		.enable_reg = 0x6058,
1241 		.enable_mask = BIT(0),
1242 		.hw.init = &(struct clk_init_data){
1243 			.name = "cam_cc_csi2phytimer_clk",
1244 			.parent_hws = (const struct clk_hw*[]){
1245 				&cam_cc_csi2phytimer_clk_src.clkr.hw
1246 			},
1247 			.num_parents = 1,
1248 			.flags = CLK_SET_RATE_PARENT,
1249 			.ops = &clk_branch2_ops,
1250 		},
1251 	},
1252 };
1253 
1254 static struct clk_branch cam_cc_csi3phytimer_clk = {
1255 	.halt_reg = 0x6078,
1256 	.halt_check = BRANCH_HALT,
1257 	.clkr = {
1258 		.enable_reg = 0x6078,
1259 		.enable_mask = BIT(0),
1260 		.hw.init = &(struct clk_init_data){
1261 			.name = "cam_cc_csi3phytimer_clk",
1262 			.parent_hws = (const struct clk_hw*[]){
1263 				&cam_cc_csi3phytimer_clk_src.clkr.hw
1264 			},
1265 			.num_parents = 1,
1266 			.flags = CLK_SET_RATE_PARENT,
1267 			.ops = &clk_branch2_ops,
1268 		},
1269 	},
1270 };
1271 
1272 static struct clk_branch cam_cc_csi4phytimer_clk = {
1273 	.halt_reg = 0x6098,
1274 	.halt_check = BRANCH_HALT,
1275 	.clkr = {
1276 		.enable_reg = 0x6098,
1277 		.enable_mask = BIT(0),
1278 		.hw.init = &(struct clk_init_data){
1279 			.name = "cam_cc_csi4phytimer_clk",
1280 			.parent_hws = (const struct clk_hw*[]){
1281 				&cam_cc_csi4phytimer_clk_src.clkr.hw
1282 			},
1283 			.num_parents = 1,
1284 			.flags = CLK_SET_RATE_PARENT,
1285 			.ops = &clk_branch2_ops,
1286 		},
1287 	},
1288 };
1289 
1290 static struct clk_branch cam_cc_csi5phytimer_clk = {
1291 	.halt_reg = 0x60b8,
1292 	.halt_check = BRANCH_HALT,
1293 	.clkr = {
1294 		.enable_reg = 0x60b8,
1295 		.enable_mask = BIT(0),
1296 		.hw.init = &(struct clk_init_data){
1297 			.name = "cam_cc_csi5phytimer_clk",
1298 			.parent_hws = (const struct clk_hw*[]){
1299 				&cam_cc_csi5phytimer_clk_src.clkr.hw
1300 			},
1301 			.num_parents = 1,
1302 			.flags = CLK_SET_RATE_PARENT,
1303 			.ops = &clk_branch2_ops,
1304 		},
1305 	},
1306 };
1307 
1308 static struct clk_branch cam_cc_csiphy0_clk = {
1309 	.halt_reg = 0x601c,
1310 	.halt_check = BRANCH_HALT,
1311 	.clkr = {
1312 		.enable_reg = 0x601c,
1313 		.enable_mask = BIT(0),
1314 		.hw.init = &(struct clk_init_data){
1315 			.name = "cam_cc_csiphy0_clk",
1316 			.parent_hws = (const struct clk_hw*[]){
1317 				&cam_cc_cphy_rx_clk_src.clkr.hw
1318 			},
1319 			.num_parents = 1,
1320 			.flags = CLK_SET_RATE_PARENT,
1321 			.ops = &clk_branch2_ops,
1322 		},
1323 	},
1324 };
1325 
1326 static struct clk_branch cam_cc_csiphy1_clk = {
1327 	.halt_reg = 0x603c,
1328 	.halt_check = BRANCH_HALT,
1329 	.clkr = {
1330 		.enable_reg = 0x603c,
1331 		.enable_mask = BIT(0),
1332 		.hw.init = &(struct clk_init_data){
1333 			.name = "cam_cc_csiphy1_clk",
1334 			.parent_hws = (const struct clk_hw*[]){
1335 				&cam_cc_cphy_rx_clk_src.clkr.hw
1336 			},
1337 			.num_parents = 1,
1338 			.flags = CLK_SET_RATE_PARENT,
1339 			.ops = &clk_branch2_ops,
1340 		},
1341 	},
1342 };
1343 
1344 static struct clk_branch cam_cc_csiphy2_clk = {
1345 	.halt_reg = 0x605c,
1346 	.halt_check = BRANCH_HALT,
1347 	.clkr = {
1348 		.enable_reg = 0x605c,
1349 		.enable_mask = BIT(0),
1350 		.hw.init = &(struct clk_init_data){
1351 			.name = "cam_cc_csiphy2_clk",
1352 			.parent_hws = (const struct clk_hw*[]){
1353 				&cam_cc_cphy_rx_clk_src.clkr.hw
1354 			},
1355 			.num_parents = 1,
1356 			.flags = CLK_SET_RATE_PARENT,
1357 			.ops = &clk_branch2_ops,
1358 		},
1359 	},
1360 };
1361 
1362 static struct clk_branch cam_cc_csiphy3_clk = {
1363 	.halt_reg = 0x607c,
1364 	.halt_check = BRANCH_HALT,
1365 	.clkr = {
1366 		.enable_reg = 0x607c,
1367 		.enable_mask = BIT(0),
1368 		.hw.init = &(struct clk_init_data){
1369 			.name = "cam_cc_csiphy3_clk",
1370 			.parent_hws = (const struct clk_hw*[]){
1371 				&cam_cc_cphy_rx_clk_src.clkr.hw
1372 			},
1373 			.num_parents = 1,
1374 			.flags = CLK_SET_RATE_PARENT,
1375 			.ops = &clk_branch2_ops,
1376 		},
1377 	},
1378 };
1379 
1380 static struct clk_branch cam_cc_csiphy4_clk = {
1381 	.halt_reg = 0x609c,
1382 	.halt_check = BRANCH_HALT,
1383 	.clkr = {
1384 		.enable_reg = 0x609c,
1385 		.enable_mask = BIT(0),
1386 		.hw.init = &(struct clk_init_data){
1387 			.name = "cam_cc_csiphy4_clk",
1388 			.parent_hws = (const struct clk_hw*[]){
1389 				&cam_cc_cphy_rx_clk_src.clkr.hw
1390 			},
1391 			.num_parents = 1,
1392 			.flags = CLK_SET_RATE_PARENT,
1393 			.ops = &clk_branch2_ops,
1394 		},
1395 	},
1396 };
1397 
1398 static struct clk_branch cam_cc_csiphy5_clk = {
1399 	.halt_reg = 0x60bc,
1400 	.halt_check = BRANCH_HALT,
1401 	.clkr = {
1402 		.enable_reg = 0x60bc,
1403 		.enable_mask = BIT(0),
1404 		.hw.init = &(struct clk_init_data){
1405 			.name = "cam_cc_csiphy5_clk",
1406 			.parent_hws = (const struct clk_hw*[]){
1407 				&cam_cc_cphy_rx_clk_src.clkr.hw
1408 			},
1409 			.num_parents = 1,
1410 			.flags = CLK_SET_RATE_PARENT,
1411 			.ops = &clk_branch2_ops,
1412 		},
1413 	},
1414 };
1415 
1416 static struct clk_branch cam_cc_fd_core_clk = {
1417 	.halt_reg = 0xc0b0,
1418 	.halt_check = BRANCH_HALT,
1419 	.clkr = {
1420 		.enable_reg = 0xc0b0,
1421 		.enable_mask = BIT(0),
1422 		.hw.init = &(struct clk_init_data){
1423 			.name = "cam_cc_fd_core_clk",
1424 			.parent_hws = (const struct clk_hw*[]){
1425 				&cam_cc_fd_core_clk_src.clkr.hw
1426 			},
1427 			.num_parents = 1,
1428 			.flags = CLK_SET_RATE_PARENT,
1429 			.ops = &clk_branch2_ops,
1430 		},
1431 	},
1432 };
1433 
1434 static struct clk_branch cam_cc_fd_core_uar_clk = {
1435 	.halt_reg = 0xc0b8,
1436 	.halt_check = BRANCH_HALT,
1437 	.clkr = {
1438 		.enable_reg = 0xc0b8,
1439 		.enable_mask = BIT(0),
1440 		.hw.init = &(struct clk_init_data){
1441 			.name = "cam_cc_fd_core_uar_clk",
1442 			.parent_hws = (const struct clk_hw*[]){
1443 				&cam_cc_fd_core_clk_src.clkr.hw
1444 			},
1445 			.num_parents = 1,
1446 			.flags = CLK_SET_RATE_PARENT,
1447 			.ops = &clk_branch2_ops,
1448 		},
1449 	},
1450 };
1451 
1452 static struct clk_branch cam_cc_gdsc_clk = {
1453 	.halt_reg = 0xc16c,
1454 	.halt_check = BRANCH_HALT,
1455 	.clkr = {
1456 		.enable_reg = 0xc16c,
1457 		.enable_mask = BIT(0),
1458 		.hw.init = &(struct clk_init_data){
1459 			.name = "cam_cc_gdsc_clk",
1460 			.parent_hws = (const struct clk_hw*[]){
1461 				&cam_cc_xo_clk_src.clkr.hw
1462 			},
1463 			.num_parents = 1,
1464 			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1465 			.ops = &clk_branch2_ops,
1466 		},
1467 	},
1468 };
1469 
1470 static struct clk_branch cam_cc_icp_ahb_clk = {
1471 	.halt_reg = 0xc094,
1472 	.halt_check = BRANCH_HALT,
1473 	.clkr = {
1474 		.enable_reg = 0xc094,
1475 		.enable_mask = BIT(0),
1476 		.hw.init = &(struct clk_init_data){
1477 			.name = "cam_cc_icp_ahb_clk",
1478 			.parent_hws = (const struct clk_hw*[]){
1479 				&cam_cc_slow_ahb_clk_src.clkr.hw
1480 			},
1481 			.num_parents = 1,
1482 			.flags = CLK_SET_RATE_PARENT,
1483 			.ops = &clk_branch2_ops,
1484 		},
1485 	},
1486 };
1487 
1488 static struct clk_branch cam_cc_icp_clk = {
1489 	.halt_reg = 0xc08c,
1490 	.halt_check = BRANCH_HALT,
1491 	.clkr = {
1492 		.enable_reg = 0xc08c,
1493 		.enable_mask = BIT(0),
1494 		.hw.init = &(struct clk_init_data){
1495 			.name = "cam_cc_icp_clk",
1496 			.parent_hws = (const struct clk_hw*[]){
1497 				&cam_cc_icp_clk_src.clkr.hw
1498 			},
1499 			.num_parents = 1,
1500 			.flags = CLK_SET_RATE_PARENT,
1501 			.ops = &clk_branch2_ops,
1502 		},
1503 	},
1504 };
1505 
1506 static struct clk_branch cam_cc_ife_0_ahb_clk = {
1507 	.halt_reg = 0xa088,
1508 	.halt_check = BRANCH_HALT,
1509 	.clkr = {
1510 		.enable_reg = 0xa088,
1511 		.enable_mask = BIT(0),
1512 		.hw.init = &(struct clk_init_data){
1513 			.name = "cam_cc_ife_0_ahb_clk",
1514 			.parent_hws = (const struct clk_hw*[]){
1515 				&cam_cc_slow_ahb_clk_src.clkr.hw
1516 			},
1517 			.num_parents = 1,
1518 			.flags = CLK_SET_RATE_PARENT,
1519 			.ops = &clk_branch2_ops,
1520 		},
1521 	},
1522 };
1523 
1524 static struct clk_branch cam_cc_ife_0_areg_clk = {
1525 	.halt_reg = 0xa030,
1526 	.halt_check = BRANCH_HALT,
1527 	.clkr = {
1528 		.enable_reg = 0xa030,
1529 		.enable_mask = BIT(0),
1530 		.hw.init = &(struct clk_init_data){
1531 			.name = "cam_cc_ife_0_areg_clk",
1532 			.parent_hws = (const struct clk_hw*[]){
1533 				&cam_cc_fast_ahb_clk_src.clkr.hw
1534 			},
1535 			.num_parents = 1,
1536 			.flags = CLK_SET_RATE_PARENT,
1537 			.ops = &clk_branch2_ops,
1538 		},
1539 	},
1540 };
1541 
1542 static struct clk_branch cam_cc_ife_0_axi_clk = {
1543 	.halt_reg = 0xa084,
1544 	.halt_check = BRANCH_HALT,
1545 	.clkr = {
1546 		.enable_reg = 0xa084,
1547 		.enable_mask = BIT(0),
1548 		.hw.init = &(struct clk_init_data){
1549 			.name = "cam_cc_ife_0_axi_clk",
1550 			.parent_hws = (const struct clk_hw*[]){
1551 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1552 			},
1553 			.num_parents = 1,
1554 			.flags = CLK_SET_RATE_PARENT,
1555 			.ops = &clk_branch2_ops,
1556 		},
1557 	},
1558 };
1559 
1560 static struct clk_branch cam_cc_ife_0_clk = {
1561 	.halt_reg = 0xa028,
1562 	.halt_check = BRANCH_HALT,
1563 	.clkr = {
1564 		.enable_reg = 0xa028,
1565 		.enable_mask = BIT(0),
1566 		.hw.init = &(struct clk_init_data){
1567 			.name = "cam_cc_ife_0_clk",
1568 			.parent_hws = (const struct clk_hw*[]){
1569 				&cam_cc_ife_0_clk_src.clkr.hw
1570 			},
1571 			.num_parents = 1,
1572 			.flags = CLK_SET_RATE_PARENT,
1573 			.ops = &clk_branch2_ops,
1574 		},
1575 	},
1576 };
1577 
1578 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1579 	.halt_reg = 0xa080,
1580 	.halt_check = BRANCH_HALT,
1581 	.clkr = {
1582 		.enable_reg = 0xa080,
1583 		.enable_mask = BIT(0),
1584 		.hw.init = &(struct clk_init_data){
1585 			.name = "cam_cc_ife_0_cphy_rx_clk",
1586 			.parent_hws = (const struct clk_hw*[]){
1587 				&cam_cc_cphy_rx_clk_src.clkr.hw
1588 			},
1589 			.num_parents = 1,
1590 			.flags = CLK_SET_RATE_PARENT,
1591 			.ops = &clk_branch2_ops,
1592 		},
1593 	},
1594 };
1595 
1596 static struct clk_branch cam_cc_ife_0_csid_clk = {
1597 	.halt_reg = 0xa058,
1598 	.halt_check = BRANCH_HALT,
1599 	.clkr = {
1600 		.enable_reg = 0xa058,
1601 		.enable_mask = BIT(0),
1602 		.hw.init = &(struct clk_init_data){
1603 			.name = "cam_cc_ife_0_csid_clk",
1604 			.parent_hws = (const struct clk_hw*[]){
1605 				&cam_cc_ife_0_csid_clk_src.clkr.hw
1606 			},
1607 			.num_parents = 1,
1608 			.flags = CLK_SET_RATE_PARENT,
1609 			.ops = &clk_branch2_ops,
1610 		},
1611 	},
1612 };
1613 
1614 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1615 	.halt_reg = 0xa03c,
1616 	.halt_check = BRANCH_HALT,
1617 	.clkr = {
1618 		.enable_reg = 0xa03c,
1619 		.enable_mask = BIT(0),
1620 		.hw.init = &(struct clk_init_data){
1621 			.name = "cam_cc_ife_0_dsp_clk",
1622 			.parent_hws = (const struct clk_hw*[]){
1623 				&cam_cc_ife_0_clk_src.clkr.hw
1624 			},
1625 			.num_parents = 1,
1626 			.flags = CLK_SET_RATE_PARENT,
1627 			.ops = &clk_branch2_ops,
1628 		},
1629 	},
1630 };
1631 
1632 static struct clk_branch cam_cc_ife_1_ahb_clk = {
1633 	.halt_reg = 0xb068,
1634 	.halt_check = BRANCH_HALT,
1635 	.clkr = {
1636 		.enable_reg = 0xb068,
1637 		.enable_mask = BIT(0),
1638 		.hw.init = &(struct clk_init_data){
1639 			.name = "cam_cc_ife_1_ahb_clk",
1640 			.parent_hws = (const struct clk_hw*[]){
1641 				&cam_cc_slow_ahb_clk_src.clkr.hw
1642 			},
1643 			.num_parents = 1,
1644 			.flags = CLK_SET_RATE_PARENT,
1645 			.ops = &clk_branch2_ops,
1646 		},
1647 	},
1648 };
1649 
1650 static struct clk_branch cam_cc_ife_1_areg_clk = {
1651 	.halt_reg = 0xb030,
1652 	.halt_check = BRANCH_HALT,
1653 	.clkr = {
1654 		.enable_reg = 0xb030,
1655 		.enable_mask = BIT(0),
1656 		.hw.init = &(struct clk_init_data){
1657 			.name = "cam_cc_ife_1_areg_clk",
1658 			.parent_hws = (const struct clk_hw*[]){
1659 				&cam_cc_fast_ahb_clk_src.clkr.hw
1660 			},
1661 			.num_parents = 1,
1662 			.flags = CLK_SET_RATE_PARENT,
1663 			.ops = &clk_branch2_ops,
1664 		},
1665 	},
1666 };
1667 
1668 static struct clk_branch cam_cc_ife_1_axi_clk = {
1669 	.halt_reg = 0xb064,
1670 	.halt_check = BRANCH_HALT,
1671 	.clkr = {
1672 		.enable_reg = 0xb064,
1673 		.enable_mask = BIT(0),
1674 		.hw.init = &(struct clk_init_data){
1675 			.name = "cam_cc_ife_1_axi_clk",
1676 			.parent_hws = (const struct clk_hw*[]){
1677 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1678 			},
1679 			.num_parents = 1,
1680 			.flags = CLK_SET_RATE_PARENT,
1681 			.ops = &clk_branch2_ops,
1682 		},
1683 	},
1684 };
1685 
1686 static struct clk_branch cam_cc_ife_1_clk = {
1687 	.halt_reg = 0xb028,
1688 	.halt_check = BRANCH_HALT,
1689 	.clkr = {
1690 		.enable_reg = 0xb028,
1691 		.enable_mask = BIT(0),
1692 		.hw.init = &(struct clk_init_data){
1693 			.name = "cam_cc_ife_1_clk",
1694 			.parent_hws = (const struct clk_hw*[]){
1695 				&cam_cc_ife_1_clk_src.clkr.hw
1696 			},
1697 			.num_parents = 1,
1698 			.flags = CLK_SET_RATE_PARENT,
1699 			.ops = &clk_branch2_ops,
1700 		},
1701 	},
1702 };
1703 
1704 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1705 	.halt_reg = 0xb060,
1706 	.halt_check = BRANCH_HALT,
1707 	.clkr = {
1708 		.enable_reg = 0xb060,
1709 		.enable_mask = BIT(0),
1710 		.hw.init = &(struct clk_init_data){
1711 			.name = "cam_cc_ife_1_cphy_rx_clk",
1712 			.parent_hws = (const struct clk_hw*[]){
1713 				&cam_cc_cphy_rx_clk_src.clkr.hw
1714 			},
1715 			.num_parents = 1,
1716 			.flags = CLK_SET_RATE_PARENT,
1717 			.ops = &clk_branch2_ops,
1718 		},
1719 	},
1720 };
1721 
1722 static struct clk_branch cam_cc_ife_1_csid_clk = {
1723 	.halt_reg = 0xb058,
1724 	.halt_check = BRANCH_HALT,
1725 	.clkr = {
1726 		.enable_reg = 0xb058,
1727 		.enable_mask = BIT(0),
1728 		.hw.init = &(struct clk_init_data){
1729 			.name = "cam_cc_ife_1_csid_clk",
1730 			.parent_hws = (const struct clk_hw*[]){
1731 				&cam_cc_ife_1_csid_clk_src.clkr.hw
1732 			},
1733 			.num_parents = 1,
1734 			.flags = CLK_SET_RATE_PARENT,
1735 			.ops = &clk_branch2_ops,
1736 		},
1737 	},
1738 };
1739 
1740 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1741 	.halt_reg = 0xb03c,
1742 	.halt_check = BRANCH_HALT,
1743 	.clkr = {
1744 		.enable_reg = 0xb03c,
1745 		.enable_mask = BIT(0),
1746 		.hw.init = &(struct clk_init_data){
1747 			.name = "cam_cc_ife_1_dsp_clk",
1748 			.parent_hws = (const struct clk_hw*[]){
1749 				&cam_cc_ife_1_clk_src.clkr.hw
1750 			},
1751 			.num_parents = 1,
1752 			.flags = CLK_SET_RATE_PARENT,
1753 			.ops = &clk_branch2_ops,
1754 		},
1755 	},
1756 };
1757 
1758 static struct clk_branch cam_cc_ife_lite_ahb_clk = {
1759 	.halt_reg = 0xc040,
1760 	.halt_check = BRANCH_HALT,
1761 	.clkr = {
1762 		.enable_reg = 0xc040,
1763 		.enable_mask = BIT(0),
1764 		.hw.init = &(struct clk_init_data){
1765 			.name = "cam_cc_ife_lite_ahb_clk",
1766 			.parent_hws = (const struct clk_hw*[]){
1767 				&cam_cc_slow_ahb_clk_src.clkr.hw
1768 			},
1769 			.num_parents = 1,
1770 			.flags = CLK_SET_RATE_PARENT,
1771 			.ops = &clk_branch2_ops,
1772 		},
1773 	},
1774 };
1775 
1776 static struct clk_branch cam_cc_ife_lite_axi_clk = {
1777 	.halt_reg = 0xc044,
1778 	.halt_check = BRANCH_HALT,
1779 	.clkr = {
1780 		.enable_reg = 0xc044,
1781 		.enable_mask = BIT(0),
1782 		.hw.init = &(struct clk_init_data){
1783 			.name = "cam_cc_ife_lite_axi_clk",
1784 			.parent_hws = (const struct clk_hw*[]){
1785 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1786 			},
1787 			.num_parents = 1,
1788 			.flags = CLK_SET_RATE_PARENT,
1789 			.ops = &clk_branch2_ops,
1790 		},
1791 	},
1792 };
1793 
1794 static struct clk_branch cam_cc_ife_lite_clk = {
1795 	.halt_reg = 0xc018,
1796 	.halt_check = BRANCH_HALT,
1797 	.clkr = {
1798 		.enable_reg = 0xc018,
1799 		.enable_mask = BIT(0),
1800 		.hw.init = &(struct clk_init_data){
1801 			.name = "cam_cc_ife_lite_clk",
1802 			.parent_hws = (const struct clk_hw*[]){
1803 				&cam_cc_ife_lite_clk_src.clkr.hw
1804 			},
1805 			.num_parents = 1,
1806 			.flags = CLK_SET_RATE_PARENT,
1807 			.ops = &clk_branch2_ops,
1808 		},
1809 	},
1810 };
1811 
1812 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1813 	.halt_reg = 0xc03c,
1814 	.halt_check = BRANCH_HALT,
1815 	.clkr = {
1816 		.enable_reg = 0xc03c,
1817 		.enable_mask = BIT(0),
1818 		.hw.init = &(struct clk_init_data){
1819 			.name = "cam_cc_ife_lite_cphy_rx_clk",
1820 			.parent_hws = (const struct clk_hw*[]){
1821 				&cam_cc_cphy_rx_clk_src.clkr.hw
1822 			},
1823 			.num_parents = 1,
1824 			.flags = CLK_SET_RATE_PARENT,
1825 			.ops = &clk_branch2_ops,
1826 		},
1827 	},
1828 };
1829 
1830 static struct clk_branch cam_cc_ife_lite_csid_clk = {
1831 	.halt_reg = 0xc034,
1832 	.halt_check = BRANCH_HALT,
1833 	.clkr = {
1834 		.enable_reg = 0xc034,
1835 		.enable_mask = BIT(0),
1836 		.hw.init = &(struct clk_init_data){
1837 			.name = "cam_cc_ife_lite_csid_clk",
1838 			.parent_hws = (const struct clk_hw*[]){
1839 				&cam_cc_ife_lite_csid_clk_src.clkr.hw
1840 			},
1841 			.num_parents = 1,
1842 			.flags = CLK_SET_RATE_PARENT,
1843 			.ops = &clk_branch2_ops,
1844 		},
1845 	},
1846 };
1847 
1848 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1849 	.halt_reg = 0x8040,
1850 	.halt_check = BRANCH_HALT,
1851 	.clkr = {
1852 		.enable_reg = 0x8040,
1853 		.enable_mask = BIT(0),
1854 		.hw.init = &(struct clk_init_data){
1855 			.name = "cam_cc_ipe_0_ahb_clk",
1856 			.parent_hws = (const struct clk_hw*[]){
1857 				&cam_cc_slow_ahb_clk_src.clkr.hw
1858 			},
1859 			.num_parents = 1,
1860 			.flags = CLK_SET_RATE_PARENT,
1861 			.ops = &clk_branch2_ops,
1862 		},
1863 	},
1864 };
1865 
1866 static struct clk_branch cam_cc_ipe_0_areg_clk = {
1867 	.halt_reg = 0x803c,
1868 	.halt_check = BRANCH_HALT,
1869 	.clkr = {
1870 		.enable_reg = 0x803c,
1871 		.enable_mask = BIT(0),
1872 		.hw.init = &(struct clk_init_data){
1873 			.name = "cam_cc_ipe_0_areg_clk",
1874 			.parent_hws = (const struct clk_hw*[]){
1875 				&cam_cc_fast_ahb_clk_src.clkr.hw
1876 			},
1877 			.num_parents = 1,
1878 			.flags = CLK_SET_RATE_PARENT,
1879 			.ops = &clk_branch2_ops,
1880 		},
1881 	},
1882 };
1883 
1884 static struct clk_branch cam_cc_ipe_0_axi_clk = {
1885 	.halt_reg = 0x8038,
1886 	.halt_check = BRANCH_HALT,
1887 	.clkr = {
1888 		.enable_reg = 0x8038,
1889 		.enable_mask = BIT(0),
1890 		.hw.init = &(struct clk_init_data){
1891 			.name = "cam_cc_ipe_0_axi_clk",
1892 			.parent_hws = (const struct clk_hw*[]){
1893 				&cam_cc_camnoc_axi_clk_src.clkr.hw
1894 			},
1895 			.num_parents = 1,
1896 			.flags = CLK_SET_RATE_PARENT,
1897 			.ops = &clk_branch2_ops,
1898 		},
1899 	},
1900 };
1901 
1902 static struct clk_branch cam_cc_ipe_0_clk = {
1903 	.halt_reg = 0x8028,
1904 	.halt_check = BRANCH_HALT,
1905 	.clkr = {
1906 		.enable_reg = 0x8028,
1907 		.enable_mask = BIT(0),
1908 		.hw.init = &(struct clk_init_data){
1909 			.name = "cam_cc_ipe_0_clk",
1910 			.parent_hws = (const struct clk_hw*[]){
1911 				&cam_cc_ipe_0_clk_src.clkr.hw
1912 			},
1913 			.num_parents = 1,
1914 			.flags = CLK_SET_RATE_PARENT,
1915 			.ops = &clk_branch2_ops,
1916 		},
1917 	},
1918 };
1919 
1920 static struct clk_branch cam_cc_jpeg_clk = {
1921 	.halt_reg = 0xc060,
1922 	.halt_check = BRANCH_HALT,
1923 	.clkr = {
1924 		.enable_reg = 0xc060,
1925 		.enable_mask = BIT(0),
1926 		.hw.init = &(struct clk_init_data){
1927 			.name = "cam_cc_jpeg_clk",
1928 			.parent_hws = (const struct clk_hw*[]){
1929 				&cam_cc_jpeg_clk_src.clkr.hw
1930 			},
1931 			.num_parents = 1,
1932 			.flags = CLK_SET_RATE_PARENT,
1933 			.ops = &clk_branch2_ops,
1934 		},
1935 	},
1936 };
1937 
1938 static struct clk_branch cam_cc_mclk0_clk = {
1939 	.halt_reg = 0x5018,
1940 	.halt_check = BRANCH_HALT,
1941 	.clkr = {
1942 		.enable_reg = 0x5018,
1943 		.enable_mask = BIT(0),
1944 		.hw.init = &(struct clk_init_data){
1945 			.name = "cam_cc_mclk0_clk",
1946 			.parent_hws = (const struct clk_hw*[]){
1947 				&cam_cc_mclk0_clk_src.clkr.hw
1948 			},
1949 			.num_parents = 1,
1950 			.flags = CLK_SET_RATE_PARENT,
1951 			.ops = &clk_branch2_ops,
1952 		},
1953 	},
1954 };
1955 
1956 static struct clk_branch cam_cc_mclk1_clk = {
1957 	.halt_reg = 0x5034,
1958 	.halt_check = BRANCH_HALT,
1959 	.clkr = {
1960 		.enable_reg = 0x5034,
1961 		.enable_mask = BIT(0),
1962 		.hw.init = &(struct clk_init_data){
1963 			.name = "cam_cc_mclk1_clk",
1964 			.parent_hws = (const struct clk_hw*[]){
1965 				&cam_cc_mclk1_clk_src.clkr.hw
1966 			},
1967 			.num_parents = 1,
1968 			.flags = CLK_SET_RATE_PARENT,
1969 			.ops = &clk_branch2_ops,
1970 		},
1971 	},
1972 };
1973 
1974 static struct clk_branch cam_cc_mclk2_clk = {
1975 	.halt_reg = 0x5050,
1976 	.halt_check = BRANCH_HALT,
1977 	.clkr = {
1978 		.enable_reg = 0x5050,
1979 		.enable_mask = BIT(0),
1980 		.hw.init = &(struct clk_init_data){
1981 			.name = "cam_cc_mclk2_clk",
1982 			.parent_hws = (const struct clk_hw*[]){
1983 				&cam_cc_mclk2_clk_src.clkr.hw
1984 			},
1985 			.num_parents = 1,
1986 			.flags = CLK_SET_RATE_PARENT,
1987 			.ops = &clk_branch2_ops,
1988 		},
1989 	},
1990 };
1991 
1992 static struct clk_branch cam_cc_mclk3_clk = {
1993 	.halt_reg = 0x506c,
1994 	.halt_check = BRANCH_HALT,
1995 	.clkr = {
1996 		.enable_reg = 0x506c,
1997 		.enable_mask = BIT(0),
1998 		.hw.init = &(struct clk_init_data){
1999 			.name = "cam_cc_mclk3_clk",
2000 			.parent_hws = (const struct clk_hw*[]){
2001 				&cam_cc_mclk3_clk_src.clkr.hw
2002 			},
2003 			.num_parents = 1,
2004 			.flags = CLK_SET_RATE_PARENT,
2005 			.ops = &clk_branch2_ops,
2006 		},
2007 	},
2008 };
2009 
2010 static struct clk_branch cam_cc_mclk4_clk = {
2011 	.halt_reg = 0x5088,
2012 	.halt_check = BRANCH_HALT,
2013 	.clkr = {
2014 		.enable_reg = 0x5088,
2015 		.enable_mask = BIT(0),
2016 		.hw.init = &(struct clk_init_data){
2017 			.name = "cam_cc_mclk4_clk",
2018 			.parent_hws = (const struct clk_hw*[]){
2019 				&cam_cc_mclk4_clk_src.clkr.hw
2020 			},
2021 			.num_parents = 1,
2022 			.flags = CLK_SET_RATE_PARENT,
2023 			.ops = &clk_branch2_ops,
2024 		},
2025 	},
2026 };
2027 
2028 static struct clk_branch cam_cc_mclk5_clk = {
2029 	.halt_reg = 0x50a4,
2030 	.halt_check = BRANCH_HALT,
2031 	.clkr = {
2032 		.enable_reg = 0x50a4,
2033 		.enable_mask = BIT(0),
2034 		.hw.init = &(struct clk_init_data){
2035 			.name = "cam_cc_mclk5_clk",
2036 			.parent_hws = (const struct clk_hw*[]){
2037 				&cam_cc_mclk5_clk_src.clkr.hw
2038 			},
2039 			.num_parents = 1,
2040 			.flags = CLK_SET_RATE_PARENT,
2041 			.ops = &clk_branch2_ops,
2042 		},
2043 	},
2044 };
2045 
2046 static struct clk_branch cam_cc_mclk6_clk = {
2047 	.halt_reg = 0x50c0,
2048 	.halt_check = BRANCH_HALT,
2049 	.clkr = {
2050 		.enable_reg = 0x50c0,
2051 		.enable_mask = BIT(0),
2052 		.hw.init = &(struct clk_init_data){
2053 			.name = "cam_cc_mclk6_clk",
2054 			.parent_hws = (const struct clk_hw*[]){
2055 				&cam_cc_mclk6_clk_src.clkr.hw
2056 			},
2057 			.num_parents = 1,
2058 			.flags = CLK_SET_RATE_PARENT,
2059 			.ops = &clk_branch2_ops,
2060 		},
2061 	},
2062 };
2063 
2064 static struct clk_branch cam_cc_sbi_ahb_clk = {
2065 	.halt_reg = 0x9040,
2066 	.halt_check = BRANCH_HALT,
2067 	.clkr = {
2068 		.enable_reg = 0x9040,
2069 		.enable_mask = BIT(0),
2070 		.hw.init = &(struct clk_init_data){
2071 			.name = "cam_cc_sbi_ahb_clk",
2072 			.parent_hws = (const struct clk_hw*[]){
2073 				&cam_cc_slow_ahb_clk_src.clkr.hw
2074 			},
2075 			.num_parents = 1,
2076 			.flags = CLK_SET_RATE_PARENT,
2077 			.ops = &clk_branch2_ops,
2078 		},
2079 	},
2080 };
2081 
2082 static struct clk_branch cam_cc_sbi_axi_clk = {
2083 	.halt_reg = 0x903c,
2084 	.halt_check = BRANCH_HALT,
2085 	.clkr = {
2086 		.enable_reg = 0x903c,
2087 		.enable_mask = BIT(0),
2088 		.hw.init = &(struct clk_init_data){
2089 			.name = "cam_cc_sbi_axi_clk",
2090 			.parent_hws = (const struct clk_hw*[]){
2091 				&cam_cc_camnoc_axi_clk_src.clkr.hw
2092 			},
2093 			.num_parents = 1,
2094 			.flags = CLK_SET_RATE_PARENT,
2095 			.ops = &clk_branch2_ops,
2096 		},
2097 	},
2098 };
2099 
2100 static struct clk_branch cam_cc_sbi_clk = {
2101 	.halt_reg = 0x9014,
2102 	.halt_check = BRANCH_HALT,
2103 	.clkr = {
2104 		.enable_reg = 0x9014,
2105 		.enable_mask = BIT(0),
2106 		.hw.init = &(struct clk_init_data){
2107 			.name = "cam_cc_sbi_clk",
2108 			.parent_hws = (const struct clk_hw*[]){
2109 				&cam_cc_sbi_div_clk_src.clkr.hw
2110 			},
2111 			.num_parents = 1,
2112 			.flags = CLK_SET_RATE_PARENT,
2113 			.ops = &clk_branch2_ops,
2114 		},
2115 	},
2116 };
2117 
2118 static struct clk_branch cam_cc_sbi_cphy_rx_clk = {
2119 	.halt_reg = 0x9038,
2120 	.halt_check = BRANCH_HALT,
2121 	.clkr = {
2122 		.enable_reg = 0x9038,
2123 		.enable_mask = BIT(0),
2124 		.hw.init = &(struct clk_init_data){
2125 			.name = "cam_cc_sbi_cphy_rx_clk",
2126 			.parent_hws = (const struct clk_hw*[]){
2127 				&cam_cc_cphy_rx_clk_src.clkr.hw
2128 			},
2129 			.num_parents = 1,
2130 			.flags = CLK_SET_RATE_PARENT,
2131 			.ops = &clk_branch2_ops,
2132 		},
2133 	},
2134 };
2135 
2136 static struct clk_branch cam_cc_sbi_csid_clk = {
2137 	.halt_reg = 0x9034,
2138 	.halt_check = BRANCH_HALT,
2139 	.clkr = {
2140 		.enable_reg = 0x9034,
2141 		.enable_mask = BIT(0),
2142 		.hw.init = &(struct clk_init_data){
2143 			.name = "cam_cc_sbi_csid_clk",
2144 			.parent_hws = (const struct clk_hw*[]){
2145 				&cam_cc_sbi_csid_clk_src.clkr.hw
2146 			},
2147 			.num_parents = 1,
2148 			.flags = CLK_SET_RATE_PARENT,
2149 			.ops = &clk_branch2_ops,
2150 		},
2151 	},
2152 };
2153 
2154 static struct clk_branch cam_cc_sbi_ife_0_clk = {
2155 	.halt_reg = 0x9044,
2156 	.halt_check = BRANCH_HALT,
2157 	.clkr = {
2158 		.enable_reg = 0x9044,
2159 		.enable_mask = BIT(0),
2160 		.hw.init = &(struct clk_init_data){
2161 			.name = "cam_cc_sbi_ife_0_clk",
2162 			.parent_hws = (const struct clk_hw*[]){
2163 				&cam_cc_ife_0_clk_src.clkr.hw
2164 			},
2165 			.num_parents = 1,
2166 			.flags = CLK_SET_RATE_PARENT,
2167 			.ops = &clk_branch2_ops,
2168 		},
2169 	},
2170 };
2171 
2172 static struct clk_branch cam_cc_sbi_ife_1_clk = {
2173 	.halt_reg = 0x9048,
2174 	.halt_check = BRANCH_HALT,
2175 	.clkr = {
2176 		.enable_reg = 0x9048,
2177 		.enable_mask = BIT(0),
2178 		.hw.init = &(struct clk_init_data){
2179 			.name = "cam_cc_sbi_ife_1_clk",
2180 			.parent_hws = (const struct clk_hw*[]){
2181 				&cam_cc_ife_1_clk_src.clkr.hw
2182 			},
2183 			.num_parents = 1,
2184 			.flags = CLK_SET_RATE_PARENT,
2185 			.ops = &clk_branch2_ops,
2186 		},
2187 	},
2188 };
2189 
2190 static struct clk_branch cam_cc_sleep_clk = {
2191 	.halt_reg = 0xc188,
2192 	.halt_check = BRANCH_HALT,
2193 	.clkr = {
2194 		.enable_reg = 0xc188,
2195 		.enable_mask = BIT(0),
2196 		.hw.init = &(struct clk_init_data){
2197 			.name = "cam_cc_sleep_clk",
2198 			.parent_hws = (const struct clk_hw*[]){
2199 				&cam_cc_sleep_clk_src.clkr.hw
2200 			},
2201 			.num_parents = 1,
2202 			.flags = CLK_SET_RATE_PARENT,
2203 			.ops = &clk_branch2_ops,
2204 		},
2205 	},
2206 };
2207 
2208 static struct gdsc titan_top_gdsc;
2209 
2210 static struct gdsc bps_gdsc = {
2211 	.gdscr = 0x7004,
2212 	.pd = {
2213 		.name = "bps_gdsc",
2214 	},
2215 	.flags = HW_CTRL | POLL_CFG_GDSCR,
2216 	.pwrsts = PWRSTS_OFF_ON,
2217 };
2218 
2219 static struct gdsc ipe_0_gdsc = {
2220 	.gdscr = 0x8004,
2221 	.pd = {
2222 		.name = "ipe_0_gdsc",
2223 	},
2224 	.flags = HW_CTRL | POLL_CFG_GDSCR,
2225 	.pwrsts = PWRSTS_OFF_ON,
2226 };
2227 
2228 static struct gdsc sbi_gdsc = {
2229 	.gdscr = 0x9004,
2230 	.pd = {
2231 		.name = "sbi_gdsc",
2232 	},
2233 	.flags = HW_CTRL | POLL_CFG_GDSCR,
2234 	.pwrsts = PWRSTS_OFF_ON,
2235 };
2236 
2237 static struct gdsc ife_0_gdsc = {
2238 	.gdscr = 0xa004,
2239 	.pd = {
2240 		.name = "ife_0_gdsc",
2241 	},
2242 	.flags = POLL_CFG_GDSCR,
2243 	.parent = &titan_top_gdsc.pd,
2244 	.pwrsts = PWRSTS_OFF_ON,
2245 };
2246 
2247 static struct gdsc ife_1_gdsc = {
2248 	.gdscr = 0xb004,
2249 	.pd = {
2250 		.name = "ife_1_gdsc",
2251 	},
2252 	.flags = POLL_CFG_GDSCR,
2253 	.parent = &titan_top_gdsc.pd,
2254 	.pwrsts = PWRSTS_OFF_ON,
2255 };
2256 
2257 static struct gdsc titan_top_gdsc = {
2258 	.gdscr = 0xc144,
2259 	.pd = {
2260 		.name = "titan_top_gdsc",
2261 	},
2262 	.flags = POLL_CFG_GDSCR,
2263 	.pwrsts = PWRSTS_OFF_ON,
2264 };
2265 
2266 static struct clk_regmap *cam_cc_sm8250_clocks[] = {
2267 	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2268 	[CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
2269 	[CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
2270 	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2271 	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2272 	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2273 	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2274 	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2275 	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2276 	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2277 	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2278 	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2279 	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2280 	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2281 	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2282 	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2283 	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2284 	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2285 	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2286 	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2287 	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2288 	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2289 	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2290 	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2291 	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2292 	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2293 	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2294 	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2295 	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2296 	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2297 	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2298 	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2299 	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2300 	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2301 	[CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
2302 	[CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
2303 	[CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
2304 	[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2305 	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2306 	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2307 	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2308 	[CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr,
2309 	[CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr,
2310 	[CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2311 	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2312 	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2313 	[CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2314 	[CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2315 	[CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2316 	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2317 	[CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr,
2318 	[CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr,
2319 	[CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2320 	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2321 	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2322 	[CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2323 	[CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2324 	[CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2325 	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2326 	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2327 	[CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr,
2328 	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2329 	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2330 	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2331 	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2332 	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2333 	[CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2334 	[CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2335 	[CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2336 	[CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2337 	[CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2338 	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2339 	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2340 	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2341 	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2342 	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2343 	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2344 	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2345 	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2346 	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2347 	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2348 	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2349 	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2350 	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2351 	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2352 	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2353 	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2354 	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2355 	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2356 	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2357 	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2358 	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2359 	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2360 	[CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
2361 	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2362 	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2363 	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2364 	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2365 	[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2366 	[CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr,
2367 	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2368 	[CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,
2369 	[CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,
2370 	[CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,
2371 	[CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,
2372 	[CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,
2373 	[CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,
2374 	[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2375 	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2376 	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2377 	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2378 };
2379 
2380 static struct gdsc *cam_cc_sm8250_gdscs[] = {
2381 	[BPS_GDSC] = &bps_gdsc,
2382 	[IPE_0_GDSC] = &ipe_0_gdsc,
2383 	[SBI_GDSC] = &sbi_gdsc,
2384 	[IFE_0_GDSC] = &ife_0_gdsc,
2385 	[IFE_1_GDSC] = &ife_1_gdsc,
2386 	[TITAN_TOP_GDSC] = &titan_top_gdsc,
2387 };
2388 
2389 static const struct qcom_reset_map cam_cc_sm8250_resets[] = {
2390 	[CAM_CC_BPS_BCR] = { 0x7000 },
2391 	[CAM_CC_ICP_BCR] = { 0xc070 },
2392 	[CAM_CC_IFE_0_BCR] = { 0xa000 },
2393 	[CAM_CC_IFE_1_BCR] = { 0xb000 },
2394 	[CAM_CC_IPE_0_BCR] = { 0x8000 },
2395 	[CAM_CC_SBI_BCR] = { 0x9000 },
2396 };
2397 
2398 static const struct regmap_config cam_cc_sm8250_regmap_config = {
2399 	.reg_bits = 32,
2400 	.reg_stride = 4,
2401 	.val_bits = 32,
2402 	.max_register = 0xe004,
2403 	.fast_io = true,
2404 };
2405 
2406 static const struct qcom_cc_desc cam_cc_sm8250_desc = {
2407 	.config = &cam_cc_sm8250_regmap_config,
2408 	.clks = cam_cc_sm8250_clocks,
2409 	.num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks),
2410 	.resets = cam_cc_sm8250_resets,
2411 	.num_resets = ARRAY_SIZE(cam_cc_sm8250_resets),
2412 	.gdscs = cam_cc_sm8250_gdscs,
2413 	.num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs),
2414 };
2415 
2416 static const struct of_device_id cam_cc_sm8250_match_table[] = {
2417 	{ .compatible = "qcom,sm8250-camcc" },
2418 	{ }
2419 };
2420 MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table);
2421 
cam_cc_sm8250_probe(struct platform_device * pdev)2422 static int cam_cc_sm8250_probe(struct platform_device *pdev)
2423 {
2424 	struct regmap *regmap;
2425 
2426 	regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
2427 	if (IS_ERR(regmap))
2428 		return PTR_ERR(regmap);
2429 
2430 	clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2431 	clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2432 	clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2433 	clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2434 	clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2435 
2436 	return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
2437 }
2438 
2439 static struct platform_driver cam_cc_sm8250_driver = {
2440 	.probe = cam_cc_sm8250_probe,
2441 	.driver = {
2442 		.name = "cam_cc-sm8250",
2443 		.of_match_table = cam_cc_sm8250_match_table,
2444 	},
2445 };
2446 
2447 module_platform_driver(cam_cc_sm8250_driver);
2448 
2449 MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
2450 MODULE_LICENSE("GPL v2");
2451