1 /* 2 * Marvell EBU SoC common clock handling 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #ifndef __CLK_MVEBU_COMMON_H_ 16 #define __CLK_MVEBU_COMMON_H_ 17 18 #include <linux/kernel.h> 19 20 extern spinlock_t ctrl_gating_lock; 21 22 struct device_node; 23 24 struct coreclk_ratio { 25 int id; 26 const char *name; 27 }; 28 29 struct coreclk_soc_desc { 30 u32 (*get_tclk_freq)(void __iomem *sar); 31 u32 (*get_cpu_freq)(void __iomem *sar); 32 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 33 bool (*is_sscg_enabled)(void __iomem *sar); 34 u32 (*fix_sscg_deviation)(u32 system_clk); 35 const struct coreclk_ratio *ratios; 36 int num_ratios; 37 }; 38 39 struct clk_gating_soc_desc { 40 const char *name; 41 const char *parent; 42 int bit_idx; 43 unsigned long flags; 44 }; 45 46 void __init mvebu_coreclk_setup(struct device_node *np, 47 const struct coreclk_soc_desc *desc); 48 49 void __init mvebu_clk_gating_setup(struct device_node *np, 50 const struct clk_gating_soc_desc *desc); 51 52 /* 53 * This function is shared among the Kirkwood, Armada 370, Armada XP 54 * and Armada 375 SoC 55 */ 56 u32 kirkwood_fix_sscg_deviation(u32 system_clk); 57 #endif 58