1c3828949SGregory CLEMENT /* SPDX-License-Identifier: GPL-2.0 */ 2a4518409SSebastian Hesselbarth /* 3a4518409SSebastian Hesselbarth * Marvell EBU SoC common clock handling 4a4518409SSebastian Hesselbarth * 5a4518409SSebastian Hesselbarth * Copyright (C) 2012 Marvell 6a4518409SSebastian Hesselbarth * 7a4518409SSebastian Hesselbarth * Gregory CLEMENT <gregory.clement@free-electrons.com> 8a4518409SSebastian Hesselbarth * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9a4518409SSebastian Hesselbarth * Andrew Lunn <andrew@lunn.ch> 10a4518409SSebastian Hesselbarth * 11a4518409SSebastian Hesselbarth */ 12a4518409SSebastian Hesselbarth 13a4518409SSebastian Hesselbarth #ifndef __CLK_MVEBU_COMMON_H_ 14a4518409SSebastian Hesselbarth #define __CLK_MVEBU_COMMON_H_ 15a4518409SSebastian Hesselbarth 16a4518409SSebastian Hesselbarth #include <linux/kernel.h> 17a4518409SSebastian Hesselbarth 1887e39216SMike Turquette extern spinlock_t ctrl_gating_lock; 1987e39216SMike Turquette 20a4518409SSebastian Hesselbarth struct device_node; 21a4518409SSebastian Hesselbarth 22a4518409SSebastian Hesselbarth struct coreclk_ratio { 23a4518409SSebastian Hesselbarth int id; 24a4518409SSebastian Hesselbarth const char *name; 25a4518409SSebastian Hesselbarth }; 26a4518409SSebastian Hesselbarth 27a4518409SSebastian Hesselbarth struct coreclk_soc_desc { 28a4518409SSebastian Hesselbarth u32 (*get_tclk_freq)(void __iomem *sar); 29a4518409SSebastian Hesselbarth u32 (*get_cpu_freq)(void __iomem *sar); 30a4518409SSebastian Hesselbarth void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 3142b5f406SThomas Petazzoni u32 (*get_refclk_freq)(void __iomem *sar); 3215917b16SGregory CLEMENT bool (*is_sscg_enabled)(void __iomem *sar); 335f093ee7SThomas Petazzoni u32 (*fix_sscg_deviation)(u32 system_clk); 34a4518409SSebastian Hesselbarth const struct coreclk_ratio *ratios; 35a4518409SSebastian Hesselbarth int num_ratios; 36a4518409SSebastian Hesselbarth }; 37a4518409SSebastian Hesselbarth 38a4518409SSebastian Hesselbarth struct clk_gating_soc_desc { 39a4518409SSebastian Hesselbarth const char *name; 40a4518409SSebastian Hesselbarth const char *parent; 41a4518409SSebastian Hesselbarth int bit_idx; 42a4518409SSebastian Hesselbarth unsigned long flags; 43a4518409SSebastian Hesselbarth }; 44a4518409SSebastian Hesselbarth 45a4518409SSebastian Hesselbarth void __init mvebu_coreclk_setup(struct device_node *np, 46a4518409SSebastian Hesselbarth const struct coreclk_soc_desc *desc); 47a4518409SSebastian Hesselbarth 48a4518409SSebastian Hesselbarth void __init mvebu_clk_gating_setup(struct device_node *np, 49a4518409SSebastian Hesselbarth const struct clk_gating_soc_desc *desc); 50a4518409SSebastian Hesselbarth 5115917b16SGregory CLEMENT /* 5215917b16SGregory CLEMENT * This function is shared among the Kirkwood, Armada 370, Armada XP 5315917b16SGregory CLEMENT * and Armada 375 SoC 5415917b16SGregory CLEMENT */ 555f093ee7SThomas Petazzoni u32 kirkwood_fix_sscg_deviation(u32 system_clk); 56a4518409SSebastian Hesselbarth #endif 57