1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Ingenic SoC CGU driver 4 * 5 * Copyright (c) 2013-2015 Imagination Technologies 6 * Author: Paul Burton <paul.burton@mips.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/clkdev.h> 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/math64.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include "cgu.h" 21 22 #define MHZ (1000 * 1000) 23 24 /** 25 * ingenic_cgu_gate_get() - get the value of clock gate register bit 26 * @cgu: reference to the CGU whose registers should be read 27 * @info: info struct describing the gate bit 28 * 29 * Retrieves the state of the clock gate bit described by info. The 30 * caller must hold cgu->lock. 31 * 32 * Return: true if the gate bit is set, else false. 33 */ 34 static inline bool 35 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, 36 const struct ingenic_cgu_gate_info *info) 37 { 38 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) 39 ^ info->clear_to_gate; 40 } 41 42 /** 43 * ingenic_cgu_gate_set() - set the value of clock gate register bit 44 * @cgu: reference to the CGU whose registers should be modified 45 * @info: info struct describing the gate bit 46 * @val: non-zero to gate a clock, otherwise zero 47 * 48 * Sets the given gate bit in order to gate or ungate a clock. 49 * 50 * The caller must hold cgu->lock. 51 */ 52 static inline void 53 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, 54 const struct ingenic_cgu_gate_info *info, bool val) 55 { 56 u32 clkgr = readl(cgu->base + info->reg); 57 58 if (val ^ info->clear_to_gate) 59 clkgr |= BIT(info->bit); 60 else 61 clkgr &= ~BIT(info->bit); 62 63 writel(clkgr, cgu->base + info->reg); 64 } 65 66 /* 67 * PLL operations 68 */ 69 70 static unsigned long 71 ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 72 { 73 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 74 struct ingenic_cgu *cgu = ingenic_clk->cgu; 75 const struct ingenic_cgu_clk_info *clk_info; 76 const struct ingenic_cgu_pll_info *pll_info; 77 unsigned m, n, od_enc, od; 78 bool bypass; 79 u32 ctl; 80 81 clk_info = &cgu->clock_info[ingenic_clk->idx]; 82 BUG_ON(clk_info->type != CGU_CLK_PLL); 83 pll_info = &clk_info->pll; 84 85 ctl = readl(cgu->base + pll_info->reg); 86 87 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); 88 m += pll_info->m_offset; 89 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); 90 n += pll_info->n_offset; 91 od_enc = ctl >> pll_info->od_shift; 92 od_enc &= GENMASK(pll_info->od_bits - 1, 0); 93 94 ctl = readl(cgu->base + pll_info->bypass_reg); 95 96 bypass = !pll_info->no_bypass_bit && 97 !!(ctl & BIT(pll_info->bypass_bit)); 98 99 if (bypass) 100 return parent_rate; 101 102 for (od = 0; od < pll_info->od_max; od++) { 103 if (pll_info->od_encoding[od] == od_enc) 104 break; 105 } 106 BUG_ON(od == pll_info->od_max); 107 od++; 108 109 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, 110 n * od); 111 } 112 113 static unsigned long 114 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, 115 unsigned long rate, unsigned long parent_rate, 116 unsigned *pm, unsigned *pn, unsigned *pod) 117 { 118 const struct ingenic_cgu_pll_info *pll_info; 119 unsigned m, n, od; 120 121 pll_info = &clk_info->pll; 122 od = 1; 123 124 /* 125 * The frequency after the input divider must be between 10 and 50 MHz. 126 * The highest divider yields the best resolution. 127 */ 128 n = parent_rate / (10 * MHZ); 129 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits); 130 n = max_t(unsigned, n, pll_info->n_offset); 131 132 m = (rate / MHZ) * od * n / (parent_rate / MHZ); 133 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits); 134 m = max_t(unsigned, m, pll_info->m_offset); 135 136 if (pm) 137 *pm = m; 138 if (pn) 139 *pn = n; 140 if (pod) 141 *pod = od; 142 143 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier, 144 n * od); 145 } 146 147 static inline const struct ingenic_cgu_clk_info *to_clk_info( 148 struct ingenic_clk *ingenic_clk) 149 { 150 struct ingenic_cgu *cgu = ingenic_clk->cgu; 151 const struct ingenic_cgu_clk_info *clk_info; 152 153 clk_info = &cgu->clock_info[ingenic_clk->idx]; 154 BUG_ON(clk_info->type != CGU_CLK_PLL); 155 156 return clk_info; 157 } 158 159 static long 160 ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate, 161 unsigned long *prate) 162 { 163 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 164 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 165 166 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); 167 } 168 169 static int 170 ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, 171 unsigned long parent_rate) 172 { 173 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 174 struct ingenic_cgu *cgu = ingenic_clk->cgu; 175 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 176 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 177 unsigned long rate, flags; 178 unsigned int m, n, od; 179 u32 ctl; 180 181 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, 182 &m, &n, &od); 183 if (rate != req_rate) 184 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n", 185 clk_info->name, req_rate, rate); 186 187 spin_lock_irqsave(&cgu->lock, flags); 188 ctl = readl(cgu->base + pll_info->reg); 189 190 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); 191 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; 192 193 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); 194 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; 195 196 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); 197 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift; 198 199 writel(ctl, cgu->base + pll_info->reg); 200 spin_unlock_irqrestore(&cgu->lock, flags); 201 202 return 0; 203 } 204 205 static int ingenic_pll_enable(struct clk_hw *hw) 206 { 207 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 208 struct ingenic_cgu *cgu = ingenic_clk->cgu; 209 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 210 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 211 const unsigned int timeout = 100; 212 unsigned long flags; 213 unsigned int i; 214 u32 ctl; 215 216 spin_lock_irqsave(&cgu->lock, flags); 217 ctl = readl(cgu->base + pll_info->bypass_reg); 218 219 ctl &= ~BIT(pll_info->bypass_bit); 220 221 writel(ctl, cgu->base + pll_info->bypass_reg); 222 223 ctl = readl(cgu->base + pll_info->reg); 224 225 ctl |= BIT(pll_info->enable_bit); 226 227 writel(ctl, cgu->base + pll_info->reg); 228 229 /* wait for the PLL to stabilise */ 230 for (i = 0; i < timeout; i++) { 231 ctl = readl(cgu->base + pll_info->reg); 232 if (ctl & BIT(pll_info->stable_bit)) 233 break; 234 mdelay(1); 235 } 236 237 spin_unlock_irqrestore(&cgu->lock, flags); 238 239 if (i == timeout) 240 return -EBUSY; 241 242 return 0; 243 } 244 245 static void ingenic_pll_disable(struct clk_hw *hw) 246 { 247 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 248 struct ingenic_cgu *cgu = ingenic_clk->cgu; 249 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 250 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 251 unsigned long flags; 252 u32 ctl; 253 254 spin_lock_irqsave(&cgu->lock, flags); 255 ctl = readl(cgu->base + pll_info->reg); 256 257 ctl &= ~BIT(pll_info->enable_bit); 258 259 writel(ctl, cgu->base + pll_info->reg); 260 spin_unlock_irqrestore(&cgu->lock, flags); 261 } 262 263 static int ingenic_pll_is_enabled(struct clk_hw *hw) 264 { 265 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 266 struct ingenic_cgu *cgu = ingenic_clk->cgu; 267 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); 268 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; 269 u32 ctl; 270 271 ctl = readl(cgu->base + pll_info->reg); 272 273 return !!(ctl & BIT(pll_info->enable_bit)); 274 } 275 276 static const struct clk_ops ingenic_pll_ops = { 277 .recalc_rate = ingenic_pll_recalc_rate, 278 .round_rate = ingenic_pll_round_rate, 279 .set_rate = ingenic_pll_set_rate, 280 281 .enable = ingenic_pll_enable, 282 .disable = ingenic_pll_disable, 283 .is_enabled = ingenic_pll_is_enabled, 284 }; 285 286 /* 287 * Operations for all non-PLL clocks 288 */ 289 290 static u8 ingenic_clk_get_parent(struct clk_hw *hw) 291 { 292 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 293 struct ingenic_cgu *cgu = ingenic_clk->cgu; 294 const struct ingenic_cgu_clk_info *clk_info; 295 u32 reg; 296 u8 i, hw_idx, idx = 0; 297 298 clk_info = &cgu->clock_info[ingenic_clk->idx]; 299 300 if (clk_info->type & CGU_CLK_MUX) { 301 reg = readl(cgu->base + clk_info->mux.reg); 302 hw_idx = (reg >> clk_info->mux.shift) & 303 GENMASK(clk_info->mux.bits - 1, 0); 304 305 /* 306 * Convert the hardware index to the parent index by skipping 307 * over any -1's in the parents array. 308 */ 309 for (i = 0; i < hw_idx; i++) { 310 if (clk_info->parents[i] != -1) 311 idx++; 312 } 313 } 314 315 return idx; 316 } 317 318 static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx) 319 { 320 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 321 struct ingenic_cgu *cgu = ingenic_clk->cgu; 322 const struct ingenic_cgu_clk_info *clk_info; 323 unsigned long flags; 324 u8 curr_idx, hw_idx, num_poss; 325 u32 reg, mask; 326 327 clk_info = &cgu->clock_info[ingenic_clk->idx]; 328 329 if (clk_info->type & CGU_CLK_MUX) { 330 /* 331 * Convert the parent index to the hardware index by adding 332 * 1 for any -1 in the parents array preceding the given 333 * index. That is, we want the index of idx'th entry in 334 * clk_info->parents which does not equal -1. 335 */ 336 hw_idx = curr_idx = 0; 337 num_poss = 1 << clk_info->mux.bits; 338 for (; hw_idx < num_poss; hw_idx++) { 339 if (clk_info->parents[hw_idx] == -1) 340 continue; 341 if (curr_idx == idx) 342 break; 343 curr_idx++; 344 } 345 346 /* idx should always be a valid parent */ 347 BUG_ON(curr_idx != idx); 348 349 mask = GENMASK(clk_info->mux.bits - 1, 0); 350 mask <<= clk_info->mux.shift; 351 352 spin_lock_irqsave(&cgu->lock, flags); 353 354 /* write the register */ 355 reg = readl(cgu->base + clk_info->mux.reg); 356 reg &= ~mask; 357 reg |= hw_idx << clk_info->mux.shift; 358 writel(reg, cgu->base + clk_info->mux.reg); 359 360 spin_unlock_irqrestore(&cgu->lock, flags); 361 return 0; 362 } 363 364 return idx ? -EINVAL : 0; 365 } 366 367 static unsigned long 368 ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 369 { 370 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 371 struct ingenic_cgu *cgu = ingenic_clk->cgu; 372 const struct ingenic_cgu_clk_info *clk_info; 373 unsigned long rate = parent_rate; 374 u32 div_reg, div; 375 376 clk_info = &cgu->clock_info[ingenic_clk->idx]; 377 378 if (clk_info->type & CGU_CLK_DIV) { 379 div_reg = readl(cgu->base + clk_info->div.reg); 380 div = (div_reg >> clk_info->div.shift) & 381 GENMASK(clk_info->div.bits - 1, 0); 382 383 if (clk_info->div.div_table) 384 div = clk_info->div.div_table[div]; 385 else 386 div = (div + 1) * clk_info->div.div; 387 388 rate /= div; 389 } else if (clk_info->type & CGU_CLK_FIXDIV) { 390 rate /= clk_info->fixdiv.div; 391 } 392 393 return rate; 394 } 395 396 static unsigned int 397 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, 398 unsigned int div) 399 { 400 unsigned int i; 401 402 for (i = 0; i < (1 << clk_info->div.bits) 403 && clk_info->div.div_table[i]; i++) { 404 if (clk_info->div.div_table[i] >= div) 405 return i; 406 } 407 408 return i - 1; 409 } 410 411 static unsigned 412 ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info, 413 unsigned long parent_rate, unsigned long req_rate) 414 { 415 unsigned int div, hw_div; 416 417 /* calculate the divide */ 418 div = DIV_ROUND_UP(parent_rate, req_rate); 419 420 if (clk_info->div.div_table) { 421 hw_div = ingenic_clk_calc_hw_div(clk_info, div); 422 423 return clk_info->div.div_table[hw_div]; 424 } 425 426 /* Impose hardware constraints */ 427 div = min_t(unsigned, div, 1 << clk_info->div.bits); 428 div = max_t(unsigned, div, 1); 429 430 /* 431 * If the divider value itself must be divided before being written to 432 * the divider register, we must ensure we don't have any bits set that 433 * would be lost as a result of doing so. 434 */ 435 div /= clk_info->div.div; 436 div *= clk_info->div.div; 437 438 return div; 439 } 440 441 static long 442 ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate, 443 unsigned long *parent_rate) 444 { 445 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 446 struct ingenic_cgu *cgu = ingenic_clk->cgu; 447 const struct ingenic_cgu_clk_info *clk_info; 448 unsigned int div = 1; 449 450 clk_info = &cgu->clock_info[ingenic_clk->idx]; 451 452 if (clk_info->type & CGU_CLK_DIV) 453 div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate); 454 else if (clk_info->type & CGU_CLK_FIXDIV) 455 div = clk_info->fixdiv.div; 456 457 return DIV_ROUND_UP(*parent_rate, div); 458 } 459 460 static int 461 ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate, 462 unsigned long parent_rate) 463 { 464 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 465 struct ingenic_cgu *cgu = ingenic_clk->cgu; 466 const struct ingenic_cgu_clk_info *clk_info; 467 const unsigned timeout = 100; 468 unsigned long rate, flags; 469 unsigned int hw_div, div, i; 470 u32 reg, mask; 471 int ret = 0; 472 473 clk_info = &cgu->clock_info[ingenic_clk->idx]; 474 475 if (clk_info->type & CGU_CLK_DIV) { 476 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate); 477 rate = DIV_ROUND_UP(parent_rate, div); 478 479 if (rate != req_rate) 480 return -EINVAL; 481 482 if (clk_info->div.div_table) 483 hw_div = ingenic_clk_calc_hw_div(clk_info, div); 484 else 485 hw_div = ((div / clk_info->div.div) - 1); 486 487 spin_lock_irqsave(&cgu->lock, flags); 488 reg = readl(cgu->base + clk_info->div.reg); 489 490 /* update the divide */ 491 mask = GENMASK(clk_info->div.bits - 1, 0); 492 reg &= ~(mask << clk_info->div.shift); 493 reg |= hw_div << clk_info->div.shift; 494 495 /* clear the stop bit */ 496 if (clk_info->div.stop_bit != -1) 497 reg &= ~BIT(clk_info->div.stop_bit); 498 499 /* set the change enable bit */ 500 if (clk_info->div.ce_bit != -1) 501 reg |= BIT(clk_info->div.ce_bit); 502 503 /* update the hardware */ 504 writel(reg, cgu->base + clk_info->div.reg); 505 506 /* wait for the change to take effect */ 507 if (clk_info->div.busy_bit != -1) { 508 for (i = 0; i < timeout; i++) { 509 reg = readl(cgu->base + clk_info->div.reg); 510 if (!(reg & BIT(clk_info->div.busy_bit))) 511 break; 512 mdelay(1); 513 } 514 if (i == timeout) 515 ret = -EBUSY; 516 } 517 518 spin_unlock_irqrestore(&cgu->lock, flags); 519 return ret; 520 } 521 522 return -EINVAL; 523 } 524 525 static int ingenic_clk_enable(struct clk_hw *hw) 526 { 527 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 528 struct ingenic_cgu *cgu = ingenic_clk->cgu; 529 const struct ingenic_cgu_clk_info *clk_info; 530 unsigned long flags; 531 532 clk_info = &cgu->clock_info[ingenic_clk->idx]; 533 534 if (clk_info->type & CGU_CLK_GATE) { 535 /* ungate the clock */ 536 spin_lock_irqsave(&cgu->lock, flags); 537 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); 538 spin_unlock_irqrestore(&cgu->lock, flags); 539 540 if (clk_info->gate.delay_us) 541 udelay(clk_info->gate.delay_us); 542 } 543 544 return 0; 545 } 546 547 static void ingenic_clk_disable(struct clk_hw *hw) 548 { 549 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 550 struct ingenic_cgu *cgu = ingenic_clk->cgu; 551 const struct ingenic_cgu_clk_info *clk_info; 552 unsigned long flags; 553 554 clk_info = &cgu->clock_info[ingenic_clk->idx]; 555 556 if (clk_info->type & CGU_CLK_GATE) { 557 /* gate the clock */ 558 spin_lock_irqsave(&cgu->lock, flags); 559 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); 560 spin_unlock_irqrestore(&cgu->lock, flags); 561 } 562 } 563 564 static int ingenic_clk_is_enabled(struct clk_hw *hw) 565 { 566 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw); 567 struct ingenic_cgu *cgu = ingenic_clk->cgu; 568 const struct ingenic_cgu_clk_info *clk_info; 569 int enabled = 1; 570 571 clk_info = &cgu->clock_info[ingenic_clk->idx]; 572 573 if (clk_info->type & CGU_CLK_GATE) 574 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); 575 576 return enabled; 577 } 578 579 static const struct clk_ops ingenic_clk_ops = { 580 .get_parent = ingenic_clk_get_parent, 581 .set_parent = ingenic_clk_set_parent, 582 583 .recalc_rate = ingenic_clk_recalc_rate, 584 .round_rate = ingenic_clk_round_rate, 585 .set_rate = ingenic_clk_set_rate, 586 587 .enable = ingenic_clk_enable, 588 .disable = ingenic_clk_disable, 589 .is_enabled = ingenic_clk_is_enabled, 590 }; 591 592 /* 593 * Setup functions. 594 */ 595 596 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx) 597 { 598 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; 599 struct clk_init_data clk_init; 600 struct ingenic_clk *ingenic_clk = NULL; 601 struct clk *clk, *parent; 602 const char *parent_names[4]; 603 unsigned caps, i, num_possible; 604 int err = -EINVAL; 605 606 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); 607 608 if (clk_info->type == CGU_CLK_EXT) { 609 clk = of_clk_get_by_name(cgu->np, clk_info->name); 610 if (IS_ERR(clk)) { 611 pr_err("%s: no external clock '%s' provided\n", 612 __func__, clk_info->name); 613 err = -ENODEV; 614 goto out; 615 } 616 err = clk_register_clkdev(clk, clk_info->name, NULL); 617 if (err) { 618 clk_put(clk); 619 goto out; 620 } 621 cgu->clocks.clks[idx] = clk; 622 return 0; 623 } 624 625 if (!clk_info->type) { 626 pr_err("%s: no clock type specified for '%s'\n", __func__, 627 clk_info->name); 628 goto out; 629 } 630 631 ingenic_clk = kzalloc(sizeof(*ingenic_clk), GFP_KERNEL); 632 if (!ingenic_clk) { 633 err = -ENOMEM; 634 goto out; 635 } 636 637 ingenic_clk->hw.init = &clk_init; 638 ingenic_clk->cgu = cgu; 639 ingenic_clk->idx = idx; 640 641 clk_init.name = clk_info->name; 642 clk_init.flags = 0; 643 clk_init.parent_names = parent_names; 644 645 caps = clk_info->type; 646 647 if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) { 648 clk_init.num_parents = 0; 649 650 if (caps & CGU_CLK_MUX) 651 num_possible = 1 << clk_info->mux.bits; 652 else 653 num_possible = ARRAY_SIZE(clk_info->parents); 654 655 for (i = 0; i < num_possible; i++) { 656 if (clk_info->parents[i] == -1) 657 continue; 658 659 parent = cgu->clocks.clks[clk_info->parents[i]]; 660 parent_names[clk_init.num_parents] = 661 __clk_get_name(parent); 662 clk_init.num_parents++; 663 } 664 665 BUG_ON(!clk_init.num_parents); 666 BUG_ON(clk_init.num_parents > ARRAY_SIZE(parent_names)); 667 } else { 668 BUG_ON(clk_info->parents[0] == -1); 669 clk_init.num_parents = 1; 670 parent = cgu->clocks.clks[clk_info->parents[0]]; 671 parent_names[0] = __clk_get_name(parent); 672 } 673 674 if (caps & CGU_CLK_CUSTOM) { 675 clk_init.ops = clk_info->custom.clk_ops; 676 677 caps &= ~CGU_CLK_CUSTOM; 678 679 if (caps) { 680 pr_err("%s: custom clock may not be combined with type 0x%x\n", 681 __func__, caps); 682 goto out; 683 } 684 } else if (caps & CGU_CLK_PLL) { 685 clk_init.ops = &ingenic_pll_ops; 686 clk_init.flags |= CLK_SET_RATE_GATE; 687 688 caps &= ~CGU_CLK_PLL; 689 690 if (caps) { 691 pr_err("%s: PLL may not be combined with type 0x%x\n", 692 __func__, caps); 693 goto out; 694 } 695 } else { 696 clk_init.ops = &ingenic_clk_ops; 697 } 698 699 /* nothing to do for gates or fixed dividers */ 700 caps &= ~(CGU_CLK_GATE | CGU_CLK_FIXDIV); 701 702 if (caps & CGU_CLK_MUX) { 703 if (!(caps & CGU_CLK_MUX_GLITCHFREE)) 704 clk_init.flags |= CLK_SET_PARENT_GATE; 705 706 caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE); 707 } 708 709 if (caps & CGU_CLK_DIV) { 710 caps &= ~CGU_CLK_DIV; 711 } else { 712 /* pass rate changes to the parent clock */ 713 clk_init.flags |= CLK_SET_RATE_PARENT; 714 } 715 716 if (caps) { 717 pr_err("%s: unknown clock type 0x%x\n", __func__, caps); 718 goto out; 719 } 720 721 clk = clk_register(NULL, &ingenic_clk->hw); 722 if (IS_ERR(clk)) { 723 pr_err("%s: failed to register clock '%s'\n", __func__, 724 clk_info->name); 725 err = PTR_ERR(clk); 726 goto out; 727 } 728 729 err = clk_register_clkdev(clk, clk_info->name, NULL); 730 if (err) 731 goto out; 732 733 cgu->clocks.clks[idx] = clk; 734 out: 735 if (err) 736 kfree(ingenic_clk); 737 return err; 738 } 739 740 struct ingenic_cgu * 741 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 742 unsigned num_clocks, struct device_node *np) 743 { 744 struct ingenic_cgu *cgu; 745 746 cgu = kzalloc(sizeof(*cgu), GFP_KERNEL); 747 if (!cgu) 748 goto err_out; 749 750 cgu->base = of_iomap(np, 0); 751 if (!cgu->base) { 752 pr_err("%s: failed to map CGU registers\n", __func__); 753 goto err_out_free; 754 } 755 756 cgu->np = np; 757 cgu->clock_info = clock_info; 758 cgu->clocks.clk_num = num_clocks; 759 760 spin_lock_init(&cgu->lock); 761 762 return cgu; 763 764 err_out_free: 765 kfree(cgu); 766 err_out: 767 return NULL; 768 } 769 770 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu) 771 { 772 unsigned i; 773 int err; 774 775 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *), 776 GFP_KERNEL); 777 if (!cgu->clocks.clks) { 778 err = -ENOMEM; 779 goto err_out; 780 } 781 782 for (i = 0; i < cgu->clocks.clk_num; i++) { 783 err = ingenic_register_clock(cgu, i); 784 if (err) 785 goto err_out_unregister; 786 } 787 788 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get, 789 &cgu->clocks); 790 if (err) 791 goto err_out_unregister; 792 793 return 0; 794 795 err_out_unregister: 796 for (i = 0; i < cgu->clocks.clk_num; i++) { 797 if (!cgu->clocks.clks[i]) 798 continue; 799 if (cgu->clock_info[i].type & CGU_CLK_EXT) 800 clk_put(cgu->clocks.clks[i]); 801 else 802 clk_unregister(cgu->clocks.clks[i]); 803 } 804 kfree(cgu->clocks.clks); 805 err_out: 806 return err; 807 } 808