Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28 |
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#
fa0dadde |
| 05-May-2023 |
Maxime Ripard <maxime@cerno.tech> |
clk: ingenic: cgu: Switch to determine_rate
The Ingenic CGU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent(
clk: ingenic: cgu: Switch to determine_rate
The Ingenic CGU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation.
This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate.
The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock.
So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent().
The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent.
However, It's hard to tell whether it's been done on purpose or not.
Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on.
Cc: Paul Cercueil <paul@crapouillou.net> Cc: linux-mips@vger.kernel.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-59-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6 |
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#
c799a777 |
| 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be up
clk: ingenic: Add .set_rate_hook() for PLL clocks
The set rate hook is called immediately after updating the clock register but before the spinlock is released. This allows another register to be updated alongside the main one, which is needed to handle the I2S divider on some SoCs.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
d84bf9d6 |
| 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined
clk: ingenic: Make PLL clock enable_bit and stable_bit optional
When the enable bit is undefined, the clock is assumed to be always on and enable/disable is a no-op. When the stable bit is undefined, the PLL stable check is a no-op.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-3-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
83b975b5 |
| 26-Oct-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Make PLL clock "od" field optional
Add support for defining PLL clocks with od_bits = 0, meaning that OD is fixed to 1 and there is no OD field in the register. In this case od_max mus
clk: ingenic: Make PLL clock "od" field optional
Add support for defining PLL clocks with od_bits = 0, meaning that OD is fixed to 1 and there is no OD field in the register. In this case od_max must also be 0, which is enforced with BUG_ON().
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/r/20221026194345.243007-2-aidanmacdonald.0x0@gmail.com Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37 |
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#
bacf743e |
| 28-Apr-2022 |
Aidan MacDonald <aidanmacdonald.0x0@gmail.com> |
clk: ingenic: Allow specifying common clock flags
Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks.
clk: ingenic: Allow specifying common clock flags
Provide a flags field for clocks under the ingenic-cgu driver, which can be used to set generic common clock framework flags on the created clocks. For example, the CLK_IS_CRITICAL flag is needed for some clocks (such as CPU or memory) to stop them being automatically disabled.
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220428164454.17908-2-aidanmacdonald.0x0@gmail.com Tested-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> # On X1000 and X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10 |
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#
ed84ef1c |
| 01-Oct-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Fix bugs with divided dividers
Two fixes in one:
- In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit i
clk: ingenic: Fix bugs with divided dividers
Two fixes in one:
- In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit in the register area, but this totally ignored the fact that the divider value can itself have a fixed divider.
- The code that made sure that the divider value returned by the function was a multiple of its own fixed divider could result in a wrong value being calculated, because it was rounded down instead of rounded up.
Fixes: 4afe2d1a6ed5 ("clk: ingenic: Allow divider value to be divided") Co-developed-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
3024018b |
| 01-Oct-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Fix bugs with divided dividers
[ Upstream commit ed84ef1cd7eddf933d4ffce2caa8161d6f947245 ]
Two fixes in one:
- In the "impose hardware constraints" block, the "logical" divider va
clk: ingenic: Fix bugs with divided dividers
[ Upstream commit ed84ef1cd7eddf933d4ffce2caa8161d6f947245 ]
Two fixes in one:
- In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit in the register area, but this totally ignored the fact that the divider value can itself have a fixed divider.
- The code that made sure that the divider value returned by the function was a multiple of its own fixed divider could result in a wrong value being calculated, because it was rounded down instead of rounded up.
Fixes: 4afe2d1a6ed5 ("clk: ingenic: Allow divider value to be divided") Co-developed-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42 |
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#
b60b0b55 |
| 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way.
Signed-off-by: Paul Cercueil <p
clk: ingenic: Support overriding PLLs M/N/OD calc algorithm
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
037f1ffd |
| 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.n
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
315a8423 |
| 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality.
Signed-off-by: Paul Cercueil
clk: ingenic: Read bypass register only when there is one
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
249592bf |
| 30-May-2021 |
Paul Cercueil <paul@crapouillou.net> |
clk: Support bypassing dividers
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second.
On the JZ4760, and maybe on some
clk: Support bypassing dividers
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second.
On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux.
This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks.
Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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#
11a163f2 |
| 12-Dec-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Fix divider calculation with div tables
The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an i
clk: ingenic: Fix divider calculation with div tables
The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise.
Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
070e3867 |
| 12-Dec-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Fix divider calculation with div tables
commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.
The previous code assumed that a higher hardware value always resulted in a bigger di
clk: ingenic: Fix divider calculation with div tables
commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.
The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise.
Fixes: a9fa2893fcc6 ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62 |
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#
1a3c4dd4 |
| 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation s
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation should modify the value pointed to by parent_rate, in order to propagate the rate change to the parent, as explained in the documentation of clk_set_rate().
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
2e4ee634 |
| 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PAR
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
3860dc59 |
| 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs.
Signed-off-by: Paul C
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
21534fe3 |
| 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Use readl_poll_timeout instead of custom loop
Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler.
Signed-off-by: Paul Cercue
clk: ingenic: Use readl_poll_timeout instead of custom loop
Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
29c37341 |
| 02-Sep-2020 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Use to_clk_info() macro for all clocks
The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same
clk: ingenic: Use to_clk_info() macro for all clocks
The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same thing the macro does, in-line.
Move the to_clk_info() macro to the top of the file, remove the hardcoded BUG_ON(), and use it everywhere it makes sense.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7 |
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#
9d9cc58a |
| 27-May-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
15e3ae36 |
| 27-May-2020 |
周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> |
clk: Ingenic: Remove unnecessary spinlock when reading registers.
It is not necessary to use spinlock when reading registers, so remove it from cgu.c.
Suggested-by: Paul Cercueil <paul@crapouillou.
clk: Ingenic: Remove unnecessary spinlock when reading registers.
It is not necessary to use spinlock when reading registers, so remove it from cgu.c.
Suggested-by: Paul Cercueil <paul@crapouillou.net> Suggested-by: Paul Burton <paulburton@kernel.org> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-2-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12 |
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#
a9fa2893 |
| 02-May-2019 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Add support for divider tables
Some clocks provided on Ingenic SoCs have dividers, whose hardware value as written in the register cannot be expressed as an affine function to the actu
clk: ingenic: Add support for divider tables
Some clocks provided on Ingenic SoCs have dividers, whose hardware value as written in the register cannot be expressed as an affine function to the actual divider value.
For instance, for the CPU clock on the JZ4770, the dividers are coded as follows:
------------------ | Bits | Div | ------------------ | 0 0 0 | 1 | | 0 0 1 | 2 | | 0 1 0 | 3 | | 0 1 1 | 4 | | 1 0 0 | 6 | | 1 0 1 | 8 | | 1 1 0 | 12 | ------------------
To support this setup, we introduce a new field in the ingenic_cgu_div_info structure that allows to specify the divider table.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c942fddf |
| 27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Based on 3 normalized pattern(s):
this program is free software you can redistribute it and or modify it under the terms of th
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Based on 3 normalized pattern(s):
this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details
this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details
this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version [author] [graeme] [gregory] [gg]@[slimlogic] [co] [uk] [author] [kishon] [vijay] [abraham] [i] [kishon]@[ti] [com] [based] [on] [twl6030]_[usb] [c] [author] [hema] [hk] [hemahk]@[ti] [com] this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-or-later
has been chosen to replace the boilerplate/reference in 1105 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.202006027@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v5.0.11, v5.0.10, v5.0.9 |
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#
62e59c4e |
| 18-Apr-2019 |
Stephen Boyd <sboyd@kernel.org> |
clk: Remove io.h from clk-provider.h
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including t
clk: Remove io.h from clk-provider.h
Now that we've gotten rid of clk_readl() we can remove io.h from the clk-provider header and push out the io.h include to any code that isn't already including the io.h header but using things like readl/writel, etc.
Found with this grep:
git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \ xargs git grep -l \ -e '\<__iowrite32_copy\>' --or \ -e '\<__ioread32_copy\>' --or \ -e '\<__iowrite64_copy\>' --or \ -e '\<ioremap_page_range\>' --or \ -e '\<ioremap_huge_init\>' --or \ -e '\<arch_ioremap_pud_supported\>' --or \ -e '\<arch_ioremap_pmd_supported\>' --or \ -e '\<devm_ioport_map\>' --or \ -e '\<devm_ioport_unmap\>' --or \ -e '\<IOMEM_ERR_PTR\>' --or \ -e '\<devm_ioremap\>' --or \ -e '\<devm_ioremap_nocache\>' --or \ -e '\<devm_ioremap_wc\>' --or \ -e '\<devm_iounmap\>' --or \ -e '\<devm_ioremap_release\>' --or \ -e '\<devm_memremap\>' --or \ -e '\<devm_memunmap\>' --or \ -e '\<__devm_memremap_pages\>' --or \ -e '\<pci_remap_cfgspace\>' --or \ -e '\<arch_has_dev_port\>' --or \ -e '\<arch_phys_wc_add\>' --or \ -e '\<arch_phys_wc_del\>' --or \ -e '\<memremap\>' --or \ -e '\<memunmap\>' --or \ -e '\<arch_io_reserve_memtype_wc\>' --or \ -e '\<arch_io_free_memtype_wc\>' --or \ -e '\<__io_aw\>' --or \ -e '\<__io_pbw\>' --or \ -e '\<__io_paw\>' --or \ -e '\<__io_pbr\>' --or \ -e '\<__io_par\>' --or \ -e '\<__raw_readb\>' --or \ -e '\<__raw_readw\>' --or \ -e '\<__raw_readl\>' --or \ -e '\<__raw_readq\>' --or \ -e '\<__raw_writeb\>' --or \ -e '\<__raw_writew\>' --or \ -e '\<__raw_writel\>' --or \ -e '\<__raw_writeq\>' --or \ -e '\<readb\>' --or \ -e '\<readw\>' --or \ -e '\<readl\>' --or \ -e '\<readq\>' --or \ -e '\<writeb\>' --or \ -e '\<writew\>' --or \ -e '\<writel\>' --or \ -e '\<writeq\>' --or \ -e '\<readb_relaxed\>' --or \ -e '\<readw_relaxed\>' --or \ -e '\<readl_relaxed\>' --or \ -e '\<readq_relaxed\>' --or \ -e '\<writeb_relaxed\>' --or \ -e '\<writew_relaxed\>' --or \ -e '\<writel_relaxed\>' --or \ -e '\<writeq_relaxed\>' --or \ -e '\<readsb\>' --or \ -e '\<readsw\>' --or \ -e '\<readsl\>' --or \ -e '\<readsq\>' --or \ -e '\<writesb\>' --or \ -e '\<writesw\>' --or \ -e '\<writesl\>' --or \ -e '\<writesq\>' --or \ -e '\<inb\>' --or \ -e '\<inw\>' --or \ -e '\<inl\>' --or \ -e '\<outb\>' --or \ -e '\<outw\>' --or \ -e '\<outl\>' --or \ -e '\<inb_p\>' --or \ -e '\<inw_p\>' --or \ -e '\<inl_p\>' --or \ -e '\<outb_p\>' --or \ -e '\<outw_p\>' --or \ -e '\<outl_p\>' --or \ -e '\<insb\>' --or \ -e '\<insw\>' --or \ -e '\<insl\>' --or \ -e '\<outsb\>' --or \ -e '\<outsw\>' --or \ -e '\<outsl\>' --or \ -e '\<insb_p\>' --or \ -e '\<insw_p\>' --or \ -e '\<insl_p\>' --or \ -e '\<outsb_p\>' --or \ -e '\<outsw_p\>' --or \ -e '\<outsl_p\>' --or \ -e '\<ioread8\>' --or \ -e '\<ioread16\>' --or \ -e '\<ioread32\>' --or \ -e '\<ioread64\>' --or \ -e '\<iowrite8\>' --or \ -e '\<iowrite16\>' --or \ -e '\<iowrite32\>' --or \ -e '\<iowrite64\>' --or \ -e '\<ioread16be\>' --or \ -e '\<ioread32be\>' --or \ -e '\<ioread64be\>' --or \ -e '\<iowrite16be\>' --or \ -e '\<iowrite32be\>' --or \ -e '\<iowrite64be\>' --or \ -e '\<ioread8_rep\>' --or \ -e '\<ioread16_rep\>' --or \ -e '\<ioread32_rep\>' --or \ -e '\<ioread64_rep\>' --or \ -e '\<iowrite8_rep\>' --or \ -e '\<iowrite16_rep\>' --or \ -e '\<iowrite32_rep\>' --or \ -e '\<iowrite64_rep\>' --or \ -e '\<__io_virt\>' --or \ -e '\<pci_iounmap\>' --or \ -e '\<virt_to_phys\>' --or \ -e '\<phys_to_virt\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap\>' --or \ -e '\<__ioremap\>' --or \ -e '\<iounmap\>' --or \ -e '\<ioremap\>' --or \ -e '\<ioremap_nocache\>' --or \ -e '\<ioremap_uc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wc\>' --or \ -e '\<ioremap_wt\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<ioport_map\>' --or \ -e '\<ioport_unmap\>' --or \ -e '\<xlate_dev_kmem_ptr\>' --or \ -e '\<xlate_dev_mem_ptr\>' --or \ -e '\<unxlate_dev_mem_ptr\>' --or \ -e '\<virt_to_bus\>' --or \ -e '\<bus_to_virt\>' --or \ -e '\<memset_io\>' --or \ -e '\<memcpy_fromio\>' --or \ -e '\<memcpy_toio\>'
I also reordered a couple includes when they weren't alphabetical and removed clk.h from kona, replacing it with clk-provider.h because that driver doesn't use clk consumer APIs.
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Mark Brown <broonie@kernel.org> Cc: Chris Zankel <chris@zankel.net> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: John Crispin <john@phrozen.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v5.0.8, v5.0.7, v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26 |
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#
635bd69b |
| 25-Feb-2019 |
YueHaibing <yuehaibing@huawei.com> |
clk: ingenic: Remove set but not used variable 'enable'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/clk/ingenic/cgu.c: In function 'ingenic_pll_recalc_rate': drivers/clk/ingenic/cgu.c:86
clk: ingenic: Remove set but not used variable 'enable'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/clk/ingenic/cgu.c: In function 'ingenic_pll_recalc_rate': drivers/clk/ingenic/cgu.c:86:15: warning: variable 'enable' set but not used [-Wunused-but-set-variable]
It's not used after commit ab27eb4bc365 ("clk: ingenic: Add code to enable/disable PLLs")
Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Revision tags: v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19 |
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bc5d922c |
| 27-Jan-2019 |
Paul Cercueil <paul@crapouillou.net> |
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz. This results in a theorical divider of 41.999993 which is then
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz. This results in a theorical divider of 41.999993 which is then rounded up to 42. The .round_rate function would then return (180 MHz / 42) as the clock, rounded down, so 4.285714 MHz.
Calling clk_set_rate on 4.285714 MHz would round the rate again, and give a theorical divider of 42,0000028, now rounded up to 43, and the rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not what we requested.
Fix this by rounding up the divisions.
Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: Maarten ter Huurne <maarten@treewalker.org> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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