1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/spinlock.h> 6 #include <linux/clk-provider.h> 7 8 extern spinlock_t imx_ccm_lock; 9 10 void imx_check_clocks(struct clk *clks[], unsigned int count); 11 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 12 void imx_register_uart_clocks(struct clk ** const clks[]); 13 14 extern void imx_cscmr1_fixup(u32 *val); 15 16 enum imx_pllv1_type { 17 IMX_PLLV1_IMX1, 18 IMX_PLLV1_IMX21, 19 IMX_PLLV1_IMX25, 20 IMX_PLLV1_IMX27, 21 IMX_PLLV1_IMX31, 22 IMX_PLLV1_IMX35, 23 }; 24 25 enum imx_sccg_pll_type { 26 SCCG_PLL1, 27 SCCG_PLL2, 28 }; 29 30 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 31 const char *parent, void __iomem *base); 32 33 struct clk *imx_clk_pllv2(const char *name, const char *parent, 34 void __iomem *base); 35 36 struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, 37 void __iomem *base); 38 39 struct clk *imx_clk_sccg_pll(const char *name, const char *parent_name, 40 void __iomem *base, 41 enum imx_sccg_pll_type pll_type); 42 43 enum imx_pllv3_type { 44 IMX_PLLV3_GENERIC, 45 IMX_PLLV3_SYS, 46 IMX_PLLV3_USB, 47 IMX_PLLV3_USB_VF610, 48 IMX_PLLV3_AV, 49 IMX_PLLV3_ENET, 50 IMX_PLLV3_ENET_IMX7, 51 IMX_PLLV3_SYS_VF610, 52 IMX_PLLV3_DDR_IMX7, 53 }; 54 55 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 56 const char *parent_name, void __iomem *base, u32 div_mask); 57 58 struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name, 59 void __iomem *base); 60 61 struct clk *clk_register_gate2(struct device *dev, const char *name, 62 const char *parent_name, unsigned long flags, 63 void __iomem *reg, u8 bit_idx, u8 cgr_val, 64 u8 clk_gate_flags, spinlock_t *lock, 65 unsigned int *share_count); 66 67 struct clk * imx_obtain_fixed_clock( 68 const char *name, unsigned long rate); 69 70 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, 71 const char *name); 72 73 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 74 void __iomem *reg, u8 shift, u32 exclusive_mask); 75 76 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 77 void __iomem *reg, u8 idx); 78 79 struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name, 80 void __iomem *reg, u8 idx); 81 82 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 83 void __iomem *reg, u8 shift, u8 width, 84 void __iomem *busy_reg, u8 busy_shift); 85 86 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 87 u8 width, void __iomem *busy_reg, u8 busy_shift, 88 const char * const *parent_names, int num_parents); 89 90 struct clk_hw *imx7ulp_clk_composite(const char *name, 91 const char * const *parent_names, 92 int num_parents, bool mux_present, 93 bool rate_present, bool gate_present, 94 void __iomem *reg); 95 96 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 97 void __iomem *reg, u8 shift, u8 width, 98 void (*fixup)(u32 *val)); 99 100 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 101 u8 shift, u8 width, const char * const *parents, 102 int num_parents, void (*fixup)(u32 *val)); 103 104 static inline struct clk *imx_clk_fixed(const char *name, int rate) 105 { 106 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 107 } 108 109 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) 110 { 111 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 112 } 113 114 static inline struct clk_hw *imx_get_clk_hw_fixed(const char *name, int rate) 115 { 116 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 117 } 118 119 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, 120 u8 shift, u8 width, const char * const *parents, 121 int num_parents) 122 { 123 return clk_register_mux(NULL, name, parents, num_parents, 124 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 125 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 126 } 127 128 static inline struct clk *imx_clk_fixed_factor(const char *name, 129 const char *parent, unsigned int mult, unsigned int div) 130 { 131 return clk_register_fixed_factor(NULL, name, parent, 132 CLK_SET_RATE_PARENT, mult, div); 133 } 134 135 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 136 void __iomem *reg, u8 shift, u8 width) 137 { 138 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 139 reg, shift, width, 0, &imx_ccm_lock); 140 } 141 142 static inline struct clk_hw *imx_clk_hw_divider(const char *name, 143 const char *parent, 144 void __iomem *reg, u8 shift, 145 u8 width) 146 { 147 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 148 reg, shift, width, 0, &imx_ccm_lock); 149 } 150 151 static inline struct clk *imx_clk_divider_flags(const char *name, 152 const char *parent, void __iomem *reg, u8 shift, u8 width, 153 unsigned long flags) 154 { 155 return clk_register_divider(NULL, name, parent, flags, 156 reg, shift, width, 0, &imx_ccm_lock); 157 } 158 159 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, 160 const char *parent, 161 void __iomem *reg, u8 shift, 162 u8 width, unsigned long flags) 163 { 164 return clk_hw_register_divider(NULL, name, parent, flags, 165 reg, shift, width, 0, &imx_ccm_lock); 166 } 167 168 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 169 void __iomem *reg, u8 shift, u8 width) 170 { 171 return clk_register_divider(NULL, name, parent, 172 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 173 reg, shift, width, 0, &imx_ccm_lock); 174 } 175 176 static inline struct clk *imx_clk_divider2_flags(const char *name, 177 const char *parent, void __iomem *reg, u8 shift, u8 width, 178 unsigned long flags) 179 { 180 return clk_register_divider(NULL, name, parent, 181 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 182 reg, shift, width, 0, &imx_ccm_lock); 183 } 184 185 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 186 void __iomem *reg, u8 shift) 187 { 188 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 189 shift, 0, &imx_ccm_lock); 190 } 191 192 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent, 193 void __iomem *reg, u8 shift, unsigned long flags) 194 { 195 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 196 shift, 0, &imx_ccm_lock); 197 } 198 199 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, 200 void __iomem *reg, u8 shift) 201 { 202 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 203 shift, 0, &imx_ccm_lock); 204 } 205 206 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 207 void __iomem *reg, u8 shift) 208 { 209 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 210 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 211 } 212 213 static inline struct clk *imx_clk_gate_dis_flags(const char *name, const char *parent, 214 void __iomem *reg, u8 shift, unsigned long flags) 215 { 216 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 217 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 218 } 219 220 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 221 void __iomem *reg, u8 shift) 222 { 223 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 224 shift, 0x3, 0, &imx_ccm_lock, NULL); 225 } 226 227 static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent, 228 void __iomem *reg, u8 shift, unsigned long flags) 229 { 230 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 231 shift, 0x3, 0, &imx_ccm_lock, NULL); 232 } 233 234 static inline struct clk *imx_clk_gate2_shared(const char *name, 235 const char *parent, void __iomem *reg, u8 shift, 236 unsigned int *share_count) 237 { 238 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 239 shift, 0x3, 0, &imx_ccm_lock, share_count); 240 } 241 242 static inline struct clk *imx_clk_gate2_shared2(const char *name, 243 const char *parent, void __iomem *reg, u8 shift, 244 unsigned int *share_count) 245 { 246 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 247 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 248 &imx_ccm_lock, share_count); 249 } 250 251 static inline struct clk *imx_clk_gate2_cgr(const char *name, 252 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 253 { 254 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 255 shift, cgr_val, 0, &imx_ccm_lock, NULL); 256 } 257 258 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 259 void __iomem *reg, u8 shift) 260 { 261 return clk_register_gate(NULL, name, parent, 262 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 263 reg, shift, 0, &imx_ccm_lock); 264 } 265 266 static inline struct clk *imx_clk_gate3_flags(const char *name, 267 const char *parent, void __iomem *reg, u8 shift, 268 unsigned long flags) 269 { 270 return clk_register_gate(NULL, name, parent, 271 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 272 reg, shift, 0, &imx_ccm_lock); 273 } 274 275 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 276 void __iomem *reg, u8 shift) 277 { 278 return clk_register_gate2(NULL, name, parent, 279 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 280 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 281 } 282 283 static inline struct clk *imx_clk_gate4_flags(const char *name, 284 const char *parent, void __iomem *reg, u8 shift, 285 unsigned long flags) 286 { 287 return clk_register_gate2(NULL, name, parent, 288 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 289 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 290 } 291 292 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 293 u8 shift, u8 width, const char * const *parents, 294 int num_parents) 295 { 296 return clk_register_mux(NULL, name, parents, num_parents, 297 CLK_SET_RATE_NO_REPARENT, reg, shift, 298 width, 0, &imx_ccm_lock); 299 } 300 301 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 302 u8 shift, u8 width, const char * const *parents, 303 int num_parents) 304 { 305 return clk_register_mux(NULL, name, parents, num_parents, 306 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 307 reg, shift, width, 0, &imx_ccm_lock); 308 } 309 310 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, 311 u8 shift, u8 width, 312 const char * const *parents, 313 int num_parents) 314 { 315 return clk_hw_register_mux(NULL, name, parents, num_parents, 316 CLK_SET_RATE_NO_REPARENT | 317 CLK_OPS_PARENT_ENABLE, 318 reg, shift, width, 0, &imx_ccm_lock); 319 } 320 321 static inline struct clk *imx_clk_mux_flags(const char *name, 322 void __iomem *reg, u8 shift, u8 width, 323 const char * const *parents, int num_parents, 324 unsigned long flags) 325 { 326 return clk_register_mux(NULL, name, parents, num_parents, 327 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 328 &imx_ccm_lock); 329 } 330 331 static inline struct clk *imx_clk_mux2_flags(const char *name, 332 void __iomem *reg, u8 shift, u8 width, const char **parents, 333 int num_parents, unsigned long flags) 334 { 335 return clk_register_mux(NULL, name, parents, num_parents, 336 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 337 reg, shift, width, 0, &imx_ccm_lock); 338 } 339 340 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, 341 void __iomem *reg, u8 shift, 342 u8 width, 343 const char * const *parents, 344 int num_parents, 345 unsigned long flags) 346 { 347 return clk_hw_register_mux(NULL, name, parents, num_parents, 348 flags | CLK_SET_RATE_NO_REPARENT, 349 reg, shift, width, 0, &imx_ccm_lock); 350 } 351 352 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 353 struct clk *div, struct clk *mux, struct clk *pll, 354 struct clk *step); 355 356 struct clk *imx8m_clk_composite_flags(const char *name, 357 const char **parent_names, 358 int num_parents, void __iomem *reg, 359 unsigned long flags); 360 361 #define __imx8m_clk_composite(name, parent_names, reg, flags) \ 362 imx8m_clk_composite_flags(name, parent_names, \ 363 ARRAY_SIZE(parent_names), reg, \ 364 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 365 366 #define imx8m_clk_composite(name, parent_names, reg) \ 367 __imx8m_clk_composite(name, parent_names, reg, 0) 368 369 #define imx8m_clk_composite_critical(name, parent_names, reg) \ 370 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) 371 372 struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, 373 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 374 u8 clk_divider_flags, const struct clk_div_table *table, 375 spinlock_t *lock); 376 #endif 377