1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/spinlock.h> 6 #include <linux/clk-provider.h> 7 8 #define IMX_CLK_GATE2_SINGLE_BIT 1 9 10 extern spinlock_t imx_ccm_lock; 11 12 void imx_check_clocks(struct clk *clks[], unsigned int count); 13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 14 void imx_register_uart_clocks(struct clk ** const clks[]); 15 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); 16 void imx_unregister_clocks(struct clk *clks[], unsigned int count); 17 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); 18 19 extern void imx_cscmr1_fixup(u32 *val); 20 21 enum imx_pllv1_type { 22 IMX_PLLV1_IMX1, 23 IMX_PLLV1_IMX21, 24 IMX_PLLV1_IMX25, 25 IMX_PLLV1_IMX27, 26 IMX_PLLV1_IMX31, 27 IMX_PLLV1_IMX35, 28 }; 29 30 enum imx_sscg_pll_type { 31 SCCG_PLL1, 32 SCCG_PLL2, 33 }; 34 35 enum imx_pll14xx_type { 36 PLL_1416X, 37 PLL_1443X, 38 }; 39 40 /* NOTE: Rate table should be kept sorted in descending order. */ 41 struct imx_pll14xx_rate_table { 42 unsigned int rate; 43 unsigned int pdiv; 44 unsigned int mdiv; 45 unsigned int sdiv; 46 unsigned int kdiv; 47 }; 48 49 struct imx_pll14xx_clk { 50 enum imx_pll14xx_type type; 51 const struct imx_pll14xx_rate_table *rate_table; 52 int rate_count; 53 int flags; 54 }; 55 56 extern struct imx_pll14xx_clk imx_1416x_pll; 57 extern struct imx_pll14xx_clk imx_1443x_pll; 58 extern struct imx_pll14xx_clk imx_1443x_dram_pll; 59 60 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ 61 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) 62 63 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 64 cgr_val, clk_gate_flags, lock, share_count) \ 65 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 66 cgr_val, clk_gate_flags, lock, share_count)) 67 68 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ 69 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)) 70 71 #define imx_clk_pfd(name, parent_name, reg, idx) \ 72 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx)) 73 74 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ 75 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)) 76 77 #define imx_clk_fixed(name, rate) \ 78 to_clk(imx_clk_hw_fixed(name, rate)) 79 80 #define imx_clk_fixed_factor(name, parent, mult, div) \ 81 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div)) 82 83 #define imx_clk_divider(name, parent, reg, shift, width) \ 84 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width)) 85 86 #define imx_clk_divider2(name, parent, reg, shift, width) \ 87 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width)) 88 89 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ 90 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags)) 91 92 #define imx_clk_gate(name, parent, reg, shift) \ 93 to_clk(imx_clk_hw_gate(name, parent, reg, shift)) 94 95 #define imx_clk_gate_dis(name, parent, reg, shift) \ 96 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift)) 97 98 #define imx_clk_gate2(name, parent, reg, shift) \ 99 to_clk(imx_clk_hw_gate2(name, parent, reg, shift)) 100 101 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ 102 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)) 103 104 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \ 105 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)) 106 107 #define imx_clk_gate3(name, parent, reg, shift) \ 108 to_clk(imx_clk_hw_gate3(name, parent, reg, shift)) 109 110 #define imx_clk_gate4(name, parent, reg, shift) \ 111 to_clk(imx_clk_hw_gate4(name, parent, reg, shift)) 112 113 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ 114 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)) 115 116 #define imx_clk_pllv1(type, name, parent, base) \ 117 to_clk(imx_clk_hw_pllv1(type, name, parent, base)) 118 119 #define imx_clk_pllv2(name, parent, base) \ 120 to_clk(imx_clk_hw_pllv2(name, parent, base)) 121 122 #define imx_clk_frac_pll(name, parent_name, base) \ 123 to_clk(imx_clk_hw_frac_pll(name, parent_name, base)) 124 125 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\ 126 bypass1, bypass2, base, flags) \ 127 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\ 128 bypass1, bypass2, base, flags)) 129 130 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, 131 void __iomem *base, const struct imx_pll14xx_clk *pll_clk); 132 133 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \ 134 to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk)) 135 136 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, 137 const char *parent_name, void __iomem *base, 138 const struct imx_pll14xx_clk *pll_clk); 139 140 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, 141 const char *parent, void __iomem *base); 142 143 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, 144 void __iomem *base); 145 146 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, 147 void __iomem *base); 148 149 struct clk_hw *imx_clk_hw_sscg_pll(const char *name, 150 const char * const *parent_names, 151 u8 num_parents, 152 u8 parent, u8 bypass1, u8 bypass2, 153 void __iomem *base, 154 unsigned long flags); 155 156 enum imx_pllv3_type { 157 IMX_PLLV3_GENERIC, 158 IMX_PLLV3_SYS, 159 IMX_PLLV3_USB, 160 IMX_PLLV3_USB_VF610, 161 IMX_PLLV3_AV, 162 IMX_PLLV3_ENET, 163 IMX_PLLV3_ENET_IMX7, 164 IMX_PLLV3_SYS_VF610, 165 IMX_PLLV3_DDR_IMX7, 166 IMX_PLLV3_AV_IMX7, 167 }; 168 169 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, 170 const char *parent_name, void __iomem *base, u32 div_mask); 171 172 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ 173 { \ 174 .rate = (_rate), \ 175 .mdiv = (_m), \ 176 .pdiv = (_p), \ 177 .sdiv = (_s), \ 178 } 179 180 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ 181 { \ 182 .rate = (_rate), \ 183 .mdiv = (_m), \ 184 .pdiv = (_p), \ 185 .sdiv = (_s), \ 186 .kdiv = (_k), \ 187 } 188 189 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name, 190 void __iomem *base); 191 192 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, 193 const char *parent_name, unsigned long flags, 194 void __iomem *reg, u8 bit_idx, u8 cgr_val, 195 u8 clk_gate_flags, spinlock_t *lock, 196 unsigned int *share_count); 197 198 struct clk * imx_obtain_fixed_clock( 199 const char *name, unsigned long rate); 200 201 struct clk_hw *imx_obtain_fixed_clock_hw( 202 const char *name, unsigned long rate); 203 204 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np, 205 const char *name); 206 207 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, 208 void __iomem *reg, u8 shift, u32 exclusive_mask); 209 210 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name, 211 void __iomem *reg, u8 idx); 212 213 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name, 214 void __iomem *reg, u8 idx); 215 216 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name, 217 void __iomem *reg, u8 shift, u8 width, 218 void __iomem *busy_reg, u8 busy_shift); 219 220 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, 221 u8 width, void __iomem *busy_reg, u8 busy_shift, 222 const char * const *parent_names, int num_parents); 223 224 struct clk_hw *imx7ulp_clk_hw_composite(const char *name, 225 const char * const *parent_names, 226 int num_parents, bool mux_present, 227 bool rate_present, bool gate_present, 228 void __iomem *reg); 229 230 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, 231 void __iomem *reg, u8 shift, u8 width, 232 void (*fixup)(u32 *val)); 233 234 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, 235 u8 shift, u8 width, const char * const *parents, 236 int num_parents, void (*fixup)(u32 *val)); 237 238 static inline struct clk *to_clk(struct clk_hw *hw) 239 { 240 if (IS_ERR_OR_NULL(hw)) 241 return ERR_CAST(hw); 242 return hw->clk; 243 } 244 245 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name, 246 void __iomem *base, 247 const struct imx_pll14xx_clk *pll_clk) 248 { 249 return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk); 250 } 251 252 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) 253 { 254 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 255 } 256 257 static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg, 258 u8 shift, u8 width, const char * const *parents, 259 int num_parents) 260 { 261 return clk_hw_register_mux(NULL, name, parents, num_parents, 262 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 263 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 264 } 265 266 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, 267 const char *parent, unsigned int mult, unsigned int div) 268 { 269 return clk_hw_register_fixed_factor(NULL, name, parent, 270 CLK_SET_RATE_PARENT, mult, div); 271 } 272 273 static inline struct clk_hw *imx_clk_hw_divider(const char *name, 274 const char *parent, 275 void __iomem *reg, u8 shift, 276 u8 width) 277 { 278 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 279 reg, shift, width, 0, &imx_ccm_lock); 280 } 281 282 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name, 283 const char *parent, 284 void __iomem *reg, u8 shift, 285 u8 width, unsigned long flags) 286 { 287 return clk_hw_register_divider(NULL, name, parent, flags, 288 reg, shift, width, 0, &imx_ccm_lock); 289 } 290 291 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent, 292 void __iomem *reg, u8 shift, u8 width) 293 { 294 return clk_hw_register_divider(NULL, name, parent, 295 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 296 reg, shift, width, 0, &imx_ccm_lock); 297 } 298 299 static inline struct clk *imx_clk_divider2_flags(const char *name, 300 const char *parent, void __iomem *reg, u8 shift, u8 width, 301 unsigned long flags) 302 { 303 return clk_register_divider(NULL, name, parent, 304 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 305 reg, shift, width, 0, &imx_ccm_lock); 306 } 307 308 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent, 309 void __iomem *reg, u8 shift, unsigned long flags) 310 { 311 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 312 shift, 0, &imx_ccm_lock); 313 } 314 315 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent, 316 void __iomem *reg, u8 shift) 317 { 318 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 319 shift, 0, &imx_ccm_lock); 320 } 321 322 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name, 323 const char *parent, void __iomem *reg, u8 shift) 324 { 325 return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg, 326 shift, 0, &imx_ccm_lock); 327 } 328 329 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent, 330 void __iomem *reg, u8 shift) 331 { 332 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 333 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 334 } 335 336 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent, 337 void __iomem *reg, u8 shift, unsigned long flags) 338 { 339 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 340 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 341 } 342 343 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent, 344 void __iomem *reg, u8 shift) 345 { 346 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 347 shift, 0x3, 0, &imx_ccm_lock, NULL); 348 } 349 350 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent, 351 void __iomem *reg, u8 shift, unsigned long flags) 352 { 353 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 354 shift, 0x3, 0, &imx_ccm_lock, NULL); 355 } 356 357 static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name, 358 const char *parent, void __iomem *reg, u8 shift, 359 unsigned int *share_count) 360 { 361 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 362 shift, 0x3, 0, &imx_ccm_lock, share_count); 363 } 364 365 static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name, 366 const char *parent, void __iomem *reg, u8 shift, 367 unsigned int *share_count) 368 { 369 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 370 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 371 &imx_ccm_lock, share_count); 372 } 373 374 static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev, 375 const char *name, const char *parent, 376 void __iomem *reg, u8 shift, 377 unsigned int *share_count) 378 { 379 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 380 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 381 IMX_CLK_GATE2_SINGLE_BIT, 382 &imx_ccm_lock, share_count); 383 } 384 385 static inline struct clk *imx_clk_gate2_cgr(const char *name, 386 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 387 { 388 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 389 shift, cgr_val, 0, &imx_ccm_lock, NULL); 390 } 391 392 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent, 393 void __iomem *reg, u8 shift) 394 { 395 return clk_hw_register_gate(NULL, name, parent, 396 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 397 reg, shift, 0, &imx_ccm_lock); 398 } 399 400 static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name, 401 const char *parent, void __iomem *reg, u8 shift, 402 unsigned long flags) 403 { 404 return clk_hw_register_gate(NULL, name, parent, 405 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 406 reg, shift, 0, &imx_ccm_lock); 407 } 408 409 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \ 410 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags)) 411 412 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent, 413 void __iomem *reg, u8 shift) 414 { 415 return clk_hw_register_gate2(NULL, name, parent, 416 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 417 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 418 } 419 420 static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name, 421 const char *parent, void __iomem *reg, u8 shift, 422 unsigned long flags) 423 { 424 return clk_hw_register_gate2(NULL, name, parent, 425 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 426 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 427 } 428 429 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \ 430 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags)) 431 432 static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg, 433 u8 shift, u8 width, const char * const *parents, 434 int num_parents) 435 { 436 return clk_hw_register_mux(NULL, name, parents, num_parents, 437 CLK_SET_RATE_NO_REPARENT, reg, shift, 438 width, 0, &imx_ccm_lock); 439 } 440 441 static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev, 442 const char *name, void __iomem *reg, u8 shift, 443 u8 width, const char * const *parents, int num_parents) 444 { 445 return clk_hw_register_mux(dev, name, parents, num_parents, 446 CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE, 447 reg, shift, width, 0, &imx_ccm_lock); 448 } 449 450 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 451 u8 shift, u8 width, const char * const *parents, 452 int num_parents) 453 { 454 return clk_register_mux(NULL, name, parents, num_parents, 455 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 456 reg, shift, width, 0, &imx_ccm_lock); 457 } 458 459 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg, 460 u8 shift, u8 width, 461 const char * const *parents, 462 int num_parents) 463 { 464 return clk_hw_register_mux(NULL, name, parents, num_parents, 465 CLK_SET_RATE_NO_REPARENT | 466 CLK_OPS_PARENT_ENABLE, 467 reg, shift, width, 0, &imx_ccm_lock); 468 } 469 470 static inline struct clk *imx_clk_mux_flags(const char *name, 471 void __iomem *reg, u8 shift, u8 width, 472 const char * const *parents, int num_parents, 473 unsigned long flags) 474 { 475 return clk_register_mux(NULL, name, parents, num_parents, 476 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 477 &imx_ccm_lock); 478 } 479 480 static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name, 481 void __iomem *reg, u8 shift, u8 width, 482 const char * const *parents, 483 int num_parents, unsigned long flags) 484 { 485 return clk_hw_register_mux(NULL, name, parents, num_parents, 486 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 487 reg, shift, width, 0, &imx_ccm_lock); 488 } 489 490 static inline struct clk *imx_clk_mux2_flags(const char *name, 491 void __iomem *reg, u8 shift, u8 width, 492 const char * const *parents, 493 int num_parents, unsigned long flags) 494 { 495 return clk_register_mux(NULL, name, parents, num_parents, 496 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 497 reg, shift, width, 0, &imx_ccm_lock); 498 } 499 500 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name, 501 void __iomem *reg, u8 shift, 502 u8 width, 503 const char * const *parents, 504 int num_parents, 505 unsigned long flags) 506 { 507 return clk_hw_register_mux(NULL, name, parents, num_parents, 508 flags | CLK_SET_RATE_NO_REPARENT, 509 reg, shift, width, 0, &imx_ccm_lock); 510 } 511 512 static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev, 513 const char *name, 514 void __iomem *reg, u8 shift, 515 u8 width, 516 const char * const *parents, 517 int num_parents, 518 unsigned long flags) 519 { 520 return clk_hw_register_mux(dev, name, parents, num_parents, 521 flags | CLK_SET_RATE_NO_REPARENT, 522 reg, shift, width, 0, &imx_ccm_lock); 523 } 524 525 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, 526 struct clk *div, struct clk *mux, struct clk *pll, 527 struct clk *step); 528 529 #define IMX_COMPOSITE_CORE BIT(0) 530 #define IMX_COMPOSITE_BUS BIT(1) 531 532 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, 533 const char * const *parent_names, 534 int num_parents, 535 void __iomem *reg, 536 u32 composite_flags, 537 unsigned long flags); 538 539 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ 540 imx8m_clk_hw_composite_flags(name, parent_names, \ 541 ARRAY_SIZE(parent_names), reg, \ 542 IMX_COMPOSITE_BUS, \ 543 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 544 545 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ 546 imx8m_clk_hw_composite_flags(name, parent_names, \ 547 ARRAY_SIZE(parent_names), reg, \ 548 IMX_COMPOSITE_CORE, \ 549 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 550 551 #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \ 552 flags) \ 553 to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ 554 num_parents, reg, 0, flags)) 555 556 #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ 557 imx8m_clk_hw_composite_flags(name, parent_names, \ 558 ARRAY_SIZE(parent_names), reg, 0, \ 559 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 560 561 #define __imx8m_clk_composite(name, parent_names, reg, flags) \ 562 to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags)) 563 564 #define imx8m_clk_hw_composite(name, parent_names, reg) \ 565 __imx8m_clk_hw_composite(name, parent_names, reg, 0) 566 567 #define imx8m_clk_composite(name, parent_names, reg) \ 568 __imx8m_clk_composite(name, parent_names, reg, 0) 569 570 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ 571 __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL) 572 573 #define imx8m_clk_composite_critical(name, parent_names, reg) \ 574 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) 575 576 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, 577 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 578 u8 clk_divider_flags, const struct clk_div_table *table, 579 spinlock_t *lock); 580 #endif 581