1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __MACH_IMX_CLK_H 3 #define __MACH_IMX_CLK_H 4 5 #include <linux/bits.h> 6 #include <linux/spinlock.h> 7 #include <linux/clk-provider.h> 8 9 extern spinlock_t imx_ccm_lock; 10 extern bool mcore_booted; 11 12 void imx_check_clocks(struct clk *clks[], unsigned int count); 13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 14 #ifndef MODULE 15 void imx_register_uart_clocks(unsigned int clk_count); 16 #else 17 static inline void imx_register_uart_clocks(unsigned int clk_count) 18 { 19 } 20 #endif 21 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); 22 void imx_unregister_clocks(struct clk *clks[], unsigned int count); 23 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); 24 25 extern void imx_cscmr1_fixup(u32 *val); 26 27 enum imx_pllv1_type { 28 IMX_PLLV1_IMX1, 29 IMX_PLLV1_IMX21, 30 IMX_PLLV1_IMX25, 31 IMX_PLLV1_IMX27, 32 IMX_PLLV1_IMX31, 33 IMX_PLLV1_IMX35, 34 }; 35 36 enum imx_sscg_pll_type { 37 SCCG_PLL1, 38 SCCG_PLL2, 39 }; 40 41 enum imx_pll14xx_type { 42 PLL_1416X, 43 PLL_1443X, 44 }; 45 46 enum imx_pllv4_type { 47 IMX_PLLV4_IMX7ULP, 48 IMX_PLLV4_IMX8ULP, 49 }; 50 51 enum imx_pfdv2_type { 52 IMX_PFDV2_IMX7ULP, 53 IMX_PFDV2_IMX8ULP, 54 }; 55 56 /* NOTE: Rate table should be kept sorted in descending order. */ 57 struct imx_pll14xx_rate_table { 58 unsigned int rate; 59 unsigned int pdiv; 60 unsigned int mdiv; 61 unsigned int sdiv; 62 unsigned int kdiv; 63 }; 64 65 struct imx_pll14xx_clk { 66 enum imx_pll14xx_type type; 67 const struct imx_pll14xx_rate_table *rate_table; 68 int rate_count; 69 int flags; 70 }; 71 72 extern struct imx_pll14xx_clk imx_1416x_pll; 73 extern struct imx_pll14xx_clk imx_1443x_pll; 74 extern struct imx_pll14xx_clk imx_1443x_dram_pll; 75 76 /* NOTE: Rate table should be kept sorted in descending order. */ 77 struct imx_fracn_gppll_rate_table { 78 unsigned int rate; 79 unsigned int mfi; 80 unsigned int mfn; 81 unsigned int mfd; 82 unsigned int rdiv; 83 unsigned int odiv; 84 }; 85 86 struct imx_fracn_gppll_clk { 87 const struct imx_fracn_gppll_rate_table *rate_table; 88 int rate_count; 89 int flags; 90 }; 91 92 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, 93 const struct imx_fracn_gppll_clk *pll_clk); 94 95 extern struct imx_fracn_gppll_clk imx_fracn_gppll; 96 97 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ 98 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) 99 100 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 101 cgr_val, cgr_mask, clk_gate_flags, lock, share_count) \ 102 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ 103 cgr_val, cgr_mask, clk_gate_flags, lock, share_count)) 104 105 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ 106 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)) 107 108 #define imx_clk_pfd(name, parent_name, reg, idx) \ 109 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx)) 110 111 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ 112 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)) 113 114 #define imx_clk_fixed(name, rate) \ 115 to_clk(imx_clk_hw_fixed(name, rate)) 116 117 #define imx_clk_fixed_factor(name, parent, mult, div) \ 118 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div)) 119 120 #define imx_clk_divider(name, parent, reg, shift, width) \ 121 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width)) 122 123 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ 124 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags)) 125 126 #define imx_clk_gate(name, parent, reg, shift) \ 127 to_clk(imx_clk_hw_gate(name, parent, reg, shift)) 128 129 #define imx_clk_gate_dis(name, parent, reg, shift) \ 130 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift)) 131 132 #define imx_clk_gate2(name, parent, reg, shift) \ 133 to_clk(imx_clk_hw_gate2(name, parent, reg, shift)) 134 135 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ 136 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL)) 137 138 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ 139 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)) 140 141 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ 142 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)) 143 144 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ 145 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags)) 146 147 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ 148 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags)) 149 150 #define imx_clk_pllv1(type, name, parent, base) \ 151 to_clk(imx_clk_hw_pllv1(type, name, parent, base)) 152 153 #define imx_clk_pllv2(name, parent, base) \ 154 to_clk(imx_clk_hw_pllv2(name, parent, base)) 155 156 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ 157 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags)) 158 159 #define imx_clk_hw_gate(name, parent, reg, shift) \ 160 imx_clk_hw_gate_flags(name, parent, reg, shift, 0) 161 162 #define imx_clk_hw_gate2(name, parent, reg, shift) \ 163 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0) 164 165 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ 166 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0) 167 168 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ 169 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE) 170 171 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ 172 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0) 173 174 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ 175 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL) 176 177 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ 178 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count) 179 180 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ 181 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count) 182 183 #define imx_clk_hw_gate3(name, parent, reg, shift) \ 184 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0) 185 186 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ 187 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0) 188 189 #define imx_clk_hw_gate4(name, parent, reg, shift) \ 190 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0) 191 192 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ 193 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE) 194 195 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ 196 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0) 197 198 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ 199 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0) 200 201 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ 202 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0) 203 204 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ 205 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY) 206 207 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ 208 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0) 209 210 #define imx_clk_hw_divider(name, parent, reg, shift, width) \ 211 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT) 212 213 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \ 214 __imx_clk_hw_divider(name, parent, reg, shift, width, \ 215 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE) 216 217 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \ 218 __imx_clk_hw_divider(name, parent, reg, shift, width, flags) 219 220 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \ 221 imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk) 222 223 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, 224 const char *parent_name, void __iomem *base, 225 const struct imx_pll14xx_clk *pll_clk); 226 227 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, 228 const char *parent, void __iomem *base); 229 230 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, 231 void __iomem *base); 232 233 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, 234 void __iomem *base); 235 236 struct clk_hw *imx_clk_hw_sscg_pll(const char *name, 237 const char * const *parent_names, 238 u8 num_parents, 239 u8 parent, u8 bypass1, u8 bypass2, 240 void __iomem *base, 241 unsigned long flags); 242 243 enum imx_pllv3_type { 244 IMX_PLLV3_GENERIC, 245 IMX_PLLV3_SYS, 246 IMX_PLLV3_USB, 247 IMX_PLLV3_USB_VF610, 248 IMX_PLLV3_AV, 249 IMX_PLLV3_ENET, 250 IMX_PLLV3_ENET_IMX7, 251 IMX_PLLV3_SYS_VF610, 252 IMX_PLLV3_DDR_IMX7, 253 IMX_PLLV3_AV_IMX7, 254 }; 255 256 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, 257 const char *parent_name, void __iomem *base, u32 div_mask); 258 259 #define PLL_1416X_RATE(_rate, _m, _p, _s) \ 260 { \ 261 .rate = (_rate), \ 262 .mdiv = (_m), \ 263 .pdiv = (_p), \ 264 .sdiv = (_s), \ 265 } 266 267 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \ 268 { \ 269 .rate = (_rate), \ 270 .mdiv = (_m), \ 271 .pdiv = (_p), \ 272 .sdiv = (_s), \ 273 .kdiv = (_k), \ 274 } 275 276 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, 277 const char *parent_name, void __iomem *base); 278 279 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, 280 const char *parent_name, unsigned long flags, 281 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, 282 u8 clk_gate_flags, spinlock_t *lock, 283 unsigned int *share_count); 284 285 struct clk * imx_obtain_fixed_clock( 286 const char *name, unsigned long rate); 287 288 struct clk_hw *imx_obtain_fixed_clock_hw( 289 const char *name, unsigned long rate); 290 291 struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name); 292 293 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, 294 void __iomem *reg, u8 shift, u32 exclusive_mask); 295 296 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name, 297 void __iomem *reg, u8 idx); 298 299 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name, 300 const char *parent_name, void __iomem *reg, u8 idx); 301 302 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name, 303 void __iomem *reg, u8 shift, u8 width, 304 void __iomem *busy_reg, u8 busy_shift); 305 306 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, 307 u8 width, void __iomem *busy_reg, u8 busy_shift, 308 const char * const *parent_names, int num_parents); 309 310 struct clk_hw *imx7ulp_clk_hw_composite(const char *name, 311 const char * const *parent_names, 312 int num_parents, bool mux_present, 313 bool rate_present, bool gate_present, 314 void __iomem *reg); 315 316 struct clk_hw *imx8ulp_clk_hw_composite(const char *name, 317 const char * const *parent_names, 318 int num_parents, bool mux_present, 319 bool rate_present, bool gate_present, 320 void __iomem *reg, bool has_swrst); 321 322 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, 323 void __iomem *reg, u8 shift, u8 width, 324 void (*fixup)(u32 *val)); 325 326 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, 327 u8 shift, u8 width, const char * const *parents, 328 int num_parents, void (*fixup)(u32 *val)); 329 330 static inline struct clk *to_clk(struct clk_hw *hw) 331 { 332 if (IS_ERR_OR_NULL(hw)) 333 return ERR_CAST(hw); 334 return hw->clk; 335 } 336 337 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) 338 { 339 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate); 340 } 341 342 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, 343 const char *parent, unsigned int mult, unsigned int div) 344 { 345 return clk_hw_register_fixed_factor(NULL, name, parent, 346 CLK_SET_RATE_PARENT, mult, div); 347 } 348 349 static inline struct clk_hw *__imx_clk_hw_divider(const char *name, 350 const char *parent, 351 void __iomem *reg, u8 shift, 352 u8 width, unsigned long flags) 353 { 354 return clk_hw_register_divider(NULL, name, parent, flags, 355 reg, shift, width, 0, &imx_ccm_lock); 356 } 357 358 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, 359 void __iomem *reg, u8 shift, 360 unsigned long flags, 361 unsigned long clk_gate_flags) 362 { 363 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 364 shift, clk_gate_flags, &imx_ccm_lock); 365 } 366 367 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, 368 void __iomem *reg, u8 shift, u8 cgr_val, 369 unsigned long flags, 370 unsigned int *share_count) 371 { 372 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg, 373 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count); 374 } 375 376 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, 377 u8 shift, u8 width, const char * const *parents, 378 int num_parents, unsigned long flags, unsigned long clk_mux_flags) 379 { 380 return clk_hw_register_mux(NULL, name, parents, num_parents, 381 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, 382 width, clk_mux_flags, &imx_ccm_lock); 383 } 384 385 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, 386 struct clk *div, struct clk *mux, struct clk *pll, 387 struct clk *step); 388 389 #define IMX_COMPOSITE_CORE BIT(0) 390 #define IMX_COMPOSITE_BUS BIT(1) 391 #define IMX_COMPOSITE_FW_MANAGED BIT(2) 392 393 #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT \ 394 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 395 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL \ 396 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_IS_CRITICAL) 397 #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE \ 398 (IMX_COMPOSITE_CLK_FLAGS_DEFAULT | CLK_GET_RATE_NOCACHE) 399 #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE \ 400 (IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE | CLK_IS_CRITICAL) 401 402 struct clk_hw *__imx8m_clk_hw_composite(const char *name, 403 const char * const *parent_names, 404 int num_parents, 405 void __iomem *reg, 406 u32 composite_flags, 407 unsigned long flags); 408 409 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \ 410 __imx8m_clk_hw_composite(name, parent_names, \ 411 ARRAY_SIZE(parent_names), reg, composite_flags, flags) 412 413 #define imx8m_clk_hw_composite(name, parent_names, reg) \ 414 _imx8m_clk_hw_composite(name, parent_names, reg, \ 415 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 416 417 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ 418 _imx8m_clk_hw_composite(name, parent_names, reg, \ 419 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) 420 421 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \ 422 _imx8m_clk_hw_composite(name, parent_names, reg, \ 423 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 424 425 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \ 426 _imx8m_clk_hw_composite(name, parent_names, reg, \ 427 IMX_COMPOSITE_BUS, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) 428 429 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \ 430 _imx8m_clk_hw_composite(name, parent_names, reg, \ 431 IMX_COMPOSITE_CORE, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) 432 433 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \ 434 _imx8m_clk_hw_composite(name, parent_names, reg, \ 435 IMX_COMPOSITE_FW_MANAGED, \ 436 IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE) 437 438 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \ 439 _imx8m_clk_hw_composite(name, parent_names, reg, \ 440 IMX_COMPOSITE_FW_MANAGED, \ 441 IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE) 442 443 struct clk_hw *imx93_clk_composite_flags(const char *name, 444 const char * const *parent_names, 445 int num_parents, 446 void __iomem *reg, 447 u32 domain_id, 448 unsigned long flags); 449 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ 450 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ 451 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) 452 453 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, 454 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, 455 u32 mask, u32 domain_id, unsigned int *share_count); 456 457 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, 458 unsigned long flags, void __iomem *reg, u8 shift, u8 width, 459 u8 clk_divider_flags, const struct clk_div_table *table, 460 spinlock_t *lock); 461 #endif 462