1 #ifndef __MACH_IMX_CLK_H 2 #define __MACH_IMX_CLK_H 3 4 #include <linux/spinlock.h> 5 #include <linux/clk-provider.h> 6 7 extern spinlock_t imx_ccm_lock; 8 9 void imx_check_clocks(struct clk *clks[], unsigned int count); 10 void imx_register_uart_clocks(struct clk ** const clks[]); 11 12 extern void imx_cscmr1_fixup(u32 *val); 13 14 enum imx_pllv1_type { 15 IMX_PLLV1_IMX1, 16 IMX_PLLV1_IMX21, 17 IMX_PLLV1_IMX25, 18 IMX_PLLV1_IMX27, 19 IMX_PLLV1_IMX31, 20 IMX_PLLV1_IMX35, 21 }; 22 23 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 24 const char *parent, void __iomem *base); 25 26 struct clk *imx_clk_pllv2(const char *name, const char *parent, 27 void __iomem *base); 28 29 enum imx_pllv3_type { 30 IMX_PLLV3_GENERIC, 31 IMX_PLLV3_SYS, 32 IMX_PLLV3_USB, 33 IMX_PLLV3_USB_VF610, 34 IMX_PLLV3_AV, 35 IMX_PLLV3_ENET, 36 IMX_PLLV3_ENET_IMX7, 37 }; 38 39 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 40 const char *parent_name, void __iomem *base, u32 div_mask); 41 42 struct clk *clk_register_gate2(struct device *dev, const char *name, 43 const char *parent_name, unsigned long flags, 44 void __iomem *reg, u8 bit_idx, u8 cgr_val, 45 u8 clk_gate_flags, spinlock_t *lock, 46 unsigned int *share_count); 47 48 struct clk * imx_obtain_fixed_clock( 49 const char *name, unsigned long rate); 50 51 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 52 void __iomem *reg, u8 shift, u32 exclusive_mask); 53 54 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 55 void __iomem *reg, u8 idx); 56 57 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 58 void __iomem *reg, u8 shift, u8 width, 59 void __iomem *busy_reg, u8 busy_shift); 60 61 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 62 u8 width, void __iomem *busy_reg, u8 busy_shift, 63 const char **parent_names, int num_parents); 64 65 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 66 void __iomem *reg, u8 shift, u8 width, 67 void (*fixup)(u32 *val)); 68 69 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 70 u8 shift, u8 width, const char **parents, 71 int num_parents, void (*fixup)(u32 *val)); 72 73 static inline struct clk *imx_clk_fixed(const char *name, int rate) 74 { 75 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 76 } 77 78 static inline struct clk *imx_clk_fixed_factor(const char *name, 79 const char *parent, unsigned int mult, unsigned int div) 80 { 81 return clk_register_fixed_factor(NULL, name, parent, 82 CLK_SET_RATE_PARENT, mult, div); 83 } 84 85 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 86 void __iomem *reg, u8 shift, u8 width) 87 { 88 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 89 reg, shift, width, 0, &imx_ccm_lock); 90 } 91 92 static inline struct clk *imx_clk_divider_flags(const char *name, 93 const char *parent, void __iomem *reg, u8 shift, u8 width, 94 unsigned long flags) 95 { 96 return clk_register_divider(NULL, name, parent, flags, 97 reg, shift, width, 0, &imx_ccm_lock); 98 } 99 100 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 101 void __iomem *reg, u8 shift, u8 width) 102 { 103 return clk_register_divider(NULL, name, parent, 104 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 105 reg, shift, width, 0, &imx_ccm_lock); 106 } 107 108 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 109 void __iomem *reg, u8 shift) 110 { 111 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 112 shift, 0, &imx_ccm_lock); 113 } 114 115 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 116 void __iomem *reg, u8 shift) 117 { 118 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 119 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 120 } 121 122 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 123 void __iomem *reg, u8 shift) 124 { 125 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 126 shift, 0x3, 0, &imx_ccm_lock, NULL); 127 } 128 129 static inline struct clk *imx_clk_gate2_shared(const char *name, 130 const char *parent, void __iomem *reg, u8 shift, 131 unsigned int *share_count) 132 { 133 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 134 shift, 0x3, 0, &imx_ccm_lock, share_count); 135 } 136 137 static inline struct clk *imx_clk_gate2_cgr(const char *name, 138 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 139 { 140 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 141 shift, cgr_val, 0, &imx_ccm_lock, NULL); 142 } 143 144 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 145 void __iomem *reg, u8 shift) 146 { 147 return clk_register_gate(NULL, name, parent, 148 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 149 reg, shift, 0, &imx_ccm_lock); 150 } 151 152 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 153 void __iomem *reg, u8 shift) 154 { 155 return clk_register_gate2(NULL, name, parent, 156 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 157 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 158 } 159 160 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 161 u8 shift, u8 width, const char **parents, int num_parents) 162 { 163 return clk_register_mux(NULL, name, parents, num_parents, 164 CLK_SET_RATE_NO_REPARENT, reg, shift, 165 width, 0, &imx_ccm_lock); 166 } 167 168 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 169 u8 shift, u8 width, const char **parents, int num_parents) 170 { 171 return clk_register_mux(NULL, name, parents, num_parents, 172 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 173 reg, shift, width, 0, &imx_ccm_lock); 174 } 175 176 static inline struct clk *imx_clk_mux_flags(const char *name, 177 void __iomem *reg, u8 shift, u8 width, const char **parents, 178 int num_parents, unsigned long flags) 179 { 180 return clk_register_mux(NULL, name, parents, num_parents, 181 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 182 &imx_ccm_lock); 183 } 184 185 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 186 struct clk *div, struct clk *mux, struct clk *pll, 187 struct clk *step); 188 189 #endif 190