1 #ifndef __MACH_IMX_CLK_H 2 #define __MACH_IMX_CLK_H 3 4 #include <linux/spinlock.h> 5 #include <linux/clk-provider.h> 6 7 extern spinlock_t imx_ccm_lock; 8 9 void imx_check_clocks(struct clk *clks[], unsigned int count); 10 void imx_register_uart_clocks(struct clk ** const clks[]); 11 12 extern void imx_cscmr1_fixup(u32 *val); 13 14 enum imx_pllv1_type { 15 IMX_PLLV1_IMX1, 16 IMX_PLLV1_IMX21, 17 IMX_PLLV1_IMX25, 18 IMX_PLLV1_IMX27, 19 IMX_PLLV1_IMX31, 20 IMX_PLLV1_IMX35, 21 }; 22 23 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name, 24 const char *parent, void __iomem *base); 25 26 struct clk *imx_clk_pllv2(const char *name, const char *parent, 27 void __iomem *base); 28 29 enum imx_pllv3_type { 30 IMX_PLLV3_GENERIC, 31 IMX_PLLV3_SYS, 32 IMX_PLLV3_USB, 33 IMX_PLLV3_USB_VF610, 34 IMX_PLLV3_AV, 35 IMX_PLLV3_ENET, 36 IMX_PLLV3_ENET_IMX7, 37 IMX_PLLV3_SYS_VF610, 38 }; 39 40 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 41 const char *parent_name, void __iomem *base, u32 div_mask); 42 43 struct clk *clk_register_gate2(struct device *dev, const char *name, 44 const char *parent_name, unsigned long flags, 45 void __iomem *reg, u8 bit_idx, u8 cgr_val, 46 u8 clk_gate_flags, spinlock_t *lock, 47 unsigned int *share_count); 48 49 struct clk * imx_obtain_fixed_clock( 50 const char *name, unsigned long rate); 51 52 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent, 53 void __iomem *reg, u8 shift, u32 exclusive_mask); 54 55 struct clk *imx_clk_pfd(const char *name, const char *parent_name, 56 void __iomem *reg, u8 idx); 57 58 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name, 59 void __iomem *reg, u8 shift, u8 width, 60 void __iomem *busy_reg, u8 busy_shift); 61 62 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, 63 u8 width, void __iomem *busy_reg, u8 busy_shift, 64 const char **parent_names, int num_parents); 65 66 struct clk *imx_clk_fixup_divider(const char *name, const char *parent, 67 void __iomem *reg, u8 shift, u8 width, 68 void (*fixup)(u32 *val)); 69 70 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg, 71 u8 shift, u8 width, const char **parents, 72 int num_parents, void (*fixup)(u32 *val)); 73 74 static inline struct clk *imx_clk_fixed(const char *name, int rate) 75 { 76 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 77 } 78 79 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg, 80 u8 shift, u8 width, const char **parents, int num_parents) 81 { 82 return clk_register_mux(NULL, name, parents, num_parents, 83 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg, 84 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock); 85 } 86 87 static inline struct clk *imx_clk_fixed_factor(const char *name, 88 const char *parent, unsigned int mult, unsigned int div) 89 { 90 return clk_register_fixed_factor(NULL, name, parent, 91 CLK_SET_RATE_PARENT, mult, div); 92 } 93 94 static inline struct clk *imx_clk_divider(const char *name, const char *parent, 95 void __iomem *reg, u8 shift, u8 width) 96 { 97 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT, 98 reg, shift, width, 0, &imx_ccm_lock); 99 } 100 101 static inline struct clk *imx_clk_divider_flags(const char *name, 102 const char *parent, void __iomem *reg, u8 shift, u8 width, 103 unsigned long flags) 104 { 105 return clk_register_divider(NULL, name, parent, flags, 106 reg, shift, width, 0, &imx_ccm_lock); 107 } 108 109 static inline struct clk *imx_clk_divider2(const char *name, const char *parent, 110 void __iomem *reg, u8 shift, u8 width) 111 { 112 return clk_register_divider(NULL, name, parent, 113 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 114 reg, shift, width, 0, &imx_ccm_lock); 115 } 116 117 static inline struct clk *imx_clk_gate(const char *name, const char *parent, 118 void __iomem *reg, u8 shift) 119 { 120 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 121 shift, 0, &imx_ccm_lock); 122 } 123 124 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, 125 void __iomem *reg, u8 shift) 126 { 127 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 128 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock); 129 } 130 131 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 132 void __iomem *reg, u8 shift) 133 { 134 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 135 shift, 0x3, 0, &imx_ccm_lock, NULL); 136 } 137 138 static inline struct clk *imx_clk_gate2_shared(const char *name, 139 const char *parent, void __iomem *reg, u8 shift, 140 unsigned int *share_count) 141 { 142 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 143 shift, 0x3, 0, &imx_ccm_lock, share_count); 144 } 145 146 static inline struct clk *imx_clk_gate2_shared2(const char *name, 147 const char *parent, void __iomem *reg, u8 shift, 148 unsigned int *share_count) 149 { 150 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT | 151 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0, 152 &imx_ccm_lock, share_count); 153 } 154 155 static inline struct clk *imx_clk_gate2_cgr(const char *name, 156 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val) 157 { 158 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 159 shift, cgr_val, 0, &imx_ccm_lock, NULL); 160 } 161 162 static inline struct clk *imx_clk_gate3(const char *name, const char *parent, 163 void __iomem *reg, u8 shift) 164 { 165 return clk_register_gate(NULL, name, parent, 166 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 167 reg, shift, 0, &imx_ccm_lock); 168 } 169 170 static inline struct clk *imx_clk_gate4(const char *name, const char *parent, 171 void __iomem *reg, u8 shift) 172 { 173 return clk_register_gate2(NULL, name, parent, 174 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, 175 reg, shift, 0x3, 0, &imx_ccm_lock, NULL); 176 } 177 178 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 179 u8 shift, u8 width, const char **parents, int num_parents) 180 { 181 return clk_register_mux(NULL, name, parents, num_parents, 182 CLK_SET_RATE_NO_REPARENT, reg, shift, 183 width, 0, &imx_ccm_lock); 184 } 185 186 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, 187 u8 shift, u8 width, const char **parents, int num_parents) 188 { 189 return clk_register_mux(NULL, name, parents, num_parents, 190 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE, 191 reg, shift, width, 0, &imx_ccm_lock); 192 } 193 194 static inline struct clk *imx_clk_mux_flags(const char *name, 195 void __iomem *reg, u8 shift, u8 width, const char **parents, 196 int num_parents, unsigned long flags) 197 { 198 return clk_register_mux(NULL, name, parents, num_parents, 199 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0, 200 &imx_ccm_lock); 201 } 202 203 struct clk *imx_clk_cpu(const char *name, const char *parent_name, 204 struct clk *div, struct clk *mux, struct clk *pll, 205 struct clk *step); 206 207 #endif 208