1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2018-2019 NXP. 4 */ 5 6 #include <dt-bindings/clock/imx8mn-clock.h> 7 #include <linux/clk.h> 8 #include <linux/err.h> 9 #include <linux/init.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/platform_device.h> 15 #include <linux/types.h> 16 17 #include "clk.h" 18 19 static u32 share_count_sai2; 20 static u32 share_count_sai3; 21 static u32 share_count_sai5; 22 static u32 share_count_sai6; 23 static u32 share_count_sai7; 24 static u32 share_count_disp; 25 static u32 share_count_pdm; 26 static u32 share_count_nand; 27 28 enum { 29 ARM_PLL, 30 GPU_PLL, 31 VPU_PLL, 32 SYS_PLL1, 33 SYS_PLL2, 34 SYS_PLL3, 35 DRAM_PLL, 36 AUDIO_PLL1, 37 AUDIO_PLL2, 38 VIDEO_PLL2, 39 NR_PLLS, 40 }; 41 42 static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = { 43 PLL_1416X_RATE(1800000000U, 225, 3, 0), 44 PLL_1416X_RATE(1600000000U, 200, 3, 0), 45 PLL_1416X_RATE(1500000000U, 375, 3, 1), 46 PLL_1416X_RATE(1400000000U, 350, 3, 1), 47 PLL_1416X_RATE(1200000000U, 300, 3, 1), 48 PLL_1416X_RATE(1000000000U, 250, 3, 1), 49 PLL_1416X_RATE(800000000U, 200, 3, 1), 50 PLL_1416X_RATE(750000000U, 250, 2, 2), 51 PLL_1416X_RATE(700000000U, 350, 3, 2), 52 PLL_1416X_RATE(600000000U, 300, 3, 2), 53 }; 54 55 static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = { 56 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437), 57 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511), 58 }; 59 60 static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = { 61 PLL_1443X_RATE(650000000U, 325, 3, 2, 0), 62 PLL_1443X_RATE(594000000U, 198, 2, 2, 0), 63 }; 64 65 static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = { 66 PLL_1443X_RATE(650000000U, 325, 3, 2, 0), 67 }; 68 69 static struct imx_pll14xx_clk imx8mn_audio_pll = { 70 .type = PLL_1443X, 71 .rate_table = imx8mn_audiopll_tbl, 72 .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl), 73 }; 74 75 static struct imx_pll14xx_clk imx8mn_video_pll = { 76 .type = PLL_1443X, 77 .rate_table = imx8mn_videopll_tbl, 78 .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl), 79 }; 80 81 static struct imx_pll14xx_clk imx8mn_dram_pll = { 82 .type = PLL_1443X, 83 .rate_table = imx8mn_drampll_tbl, 84 .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl), 85 }; 86 87 static struct imx_pll14xx_clk imx8mn_arm_pll = { 88 .type = PLL_1416X, 89 .rate_table = imx8mn_pll1416x_tbl, 90 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl), 91 }; 92 93 static struct imx_pll14xx_clk imx8mn_gpu_pll = { 94 .type = PLL_1416X, 95 .rate_table = imx8mn_pll1416x_tbl, 96 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl), 97 }; 98 99 static struct imx_pll14xx_clk imx8mn_vpu_pll = { 100 .type = PLL_1416X, 101 .rate_table = imx8mn_pll1416x_tbl, 102 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl), 103 }; 104 105 static struct imx_pll14xx_clk imx8mn_sys_pll = { 106 .type = PLL_1416X, 107 .rate_table = imx8mn_pll1416x_tbl, 108 .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl), 109 }; 110 111 static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; 112 static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; 113 static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; 114 static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; 115 static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; 116 static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; 117 static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; 118 static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; 119 static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; 120 static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; 121 static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; 122 123 static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", 124 "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", 125 "audio_pll1_out", "sys_pll3_out", }; 126 127 static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 128 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 129 "video_pll1_out", "audio_pll2_out", }; 130 131 static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", 132 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 133 "video_pll1_out", "audio_pll2_out", }; 134 135 static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", 136 "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", 137 "video_pll1_out", "sys_pll1_100m",}; 138 139 static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", 140 "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", 141 "video_pll1_out", "sys_pll3_out", }; 142 143 static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", 144 "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", 145 "sys_pll2_250m", "audio_pll1_out", }; 146 147 static const char * const imx8mn_disp_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", 148 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", 149 "clk_ext1", "clk_ext4", }; 150 151 static const char * const imx8mn_disp_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", 152 "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", 153 "clk_ext1", "clk_ext3", }; 154 155 static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", 156 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 157 "clk_ext4", "audio_pll2_out", }; 158 159 static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 160 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 161 "video_pll1_out", "audio_pll2_out", }; 162 163 static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", 164 "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", 165 "video_pll1_out", "audio_pll2_out", }; 166 167 static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", 168 "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", 169 "video_pll1_out", "audio_pll2_out", }; 170 171 static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", 172 "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", 173 "audio_pll1_out", "video_pll1_out", }; 174 175 static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", 176 "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", 177 "audio_pll1_out", "video_pll1_out", }; 178 179 static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", 180 "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", 181 "audio_pll1_out", "sys_pll1_266m", }; 182 183 static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 184 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 185 "sys_pll2_250m", "audio_pll2_out", }; 186 187 static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", 188 "audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m", 189 "sys_pll3_out", "clk_ext4", }; 190 191 static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 192 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 193 "clk_ext3", "clk_ext4", }; 194 195 static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 196 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 197 "clk_ext3", "clk_ext4", }; 198 199 static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 200 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 201 "clk_ext2", "clk_ext3", }; 202 203 static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 204 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 205 "clk_ext3", "clk_ext4", }; 206 207 static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 208 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 209 "clk_ext3", "clk_ext4", }; 210 211 static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", 212 "video_pll1_out", "sys_pll1_133m", "osc_hdmi", 213 "clk_ext2", "clk_ext3", }; 214 215 static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", 216 "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", 217 "video_pll1_out", "clk_ext4", }; 218 219 static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", 220 "clk_ext1", "clk_ext2", "clk_ext3", 221 "clk_ext4", "video_pll1_out", }; 222 223 static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", 224 "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", 225 "audio_pll2_out", }; 226 227 static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", 228 "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", 229 "sys_pll2_250m", "video_pll1_out", }; 230 231 static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", 232 "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", 233 "sys_pll3_out", "sys_pll1_100m", }; 234 235 static const char * const imx8mn_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 236 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 237 "audio_pll2_out", "sys_pll1_100m", }; 238 239 static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 240 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 241 "audio_pll2_out", "sys_pll1_100m", }; 242 243 static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 244 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 245 "audio_pll2_out", "sys_pll1_133m", }; 246 247 static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 248 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 249 "audio_pll2_out", "sys_pll1_133m", }; 250 251 static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 252 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 253 "audio_pll2_out", "sys_pll1_133m", }; 254 255 static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", 256 "sys_pll3_out", "audio_pll1_out", "video_pll1_out", 257 "audio_pll2_out", "sys_pll1_133m", }; 258 259 static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 260 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 261 "clk_ext4", "audio_pll2_out", }; 262 263 static const char * const imx8mn_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 264 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 265 "clk_ext3", "audio_pll2_out", }; 266 267 static const char * const imx8mn_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 268 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 269 "clk_ext4", "audio_pll2_out", }; 270 271 static const char * const imx8mn_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", 272 "sys_pll2_100m", "sys_pll3_out", "clk_ext2", 273 "clk_ext3", "audio_pll2_out", }; 274 275 static const char * const imx8mn_usb_core_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", 276 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 277 "clk_ext3", "audio_pll2_out", }; 278 279 static const char * const imx8mn_usb_phy_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", 280 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", 281 "clk_ext3", "audio_pll2_out", }; 282 283 static const char * const imx8mn_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 284 "sys_pll2_100m", "sys_pll1_800m", "clk_ext2", 285 "clk_ext4", "audio_pll2_out" }; 286 287 static const char * const imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 288 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 289 "sys_pll2_250m", "audio_pll2_out", }; 290 291 static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 292 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 293 "sys_pll2_250m", "audio_pll2_out", }; 294 295 static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 296 "sys_pll1_40m", "sys_pll3_out", "clk_ext1", 297 "sys_pll1_80m", "video_pll1_out", }; 298 299 static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 300 "sys_pll1_40m", "sys_pll3_out", "clk_ext1", 301 "sys_pll1_80m", "video_pll1_out", }; 302 303 static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 304 "sys_pll1_40m", "sys_pll3_out", "clk_ext2", 305 "sys_pll1_80m", "video_pll1_out", }; 306 307 static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", 308 "sys_pll1_40m", "sys_pll3_out", "clk_ext2", 309 "sys_pll1_80m", "video_pll1_out", }; 310 311 static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", 312 "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", 313 "sys_pll1_80m", "sys_pll2_166m", }; 314 315 static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", 316 "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", 317 "sys_pll2_500m", "sys_pll1_100m", }; 318 319 static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 320 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 321 "audio_pll2_out", "video_pll1_out", }; 322 323 static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m", 324 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", 325 "audio_pll2_out", "video_pll1_out", }; 326 327 static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m", 328 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 329 "audio_pll2_out", "video_pll1_out", }; 330 331 static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", 332 "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", 333 "audio_pll2_out", "sys_pll1_100m", }; 334 335 static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", 336 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 337 "audio_pll2_out", "video_pll1_out", }; 338 339 static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", 340 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", 341 "audio_pll2_out", "video_pll1_out", }; 342 343 static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", 344 "sys_pll1_800m", "sys_pll2_1000m", "clk_ext2", 345 "audio_pll2_out", "video_pll1_out", }; 346 347 static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", 348 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 349 "clk_ext3", "audio_pll2_out", }; 350 351 static const char * const imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", 352 "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", 353 "sys_pll2_250m", "audio_pll2_out", }; 354 355 static const char * const imx8mn_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", 356 "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", 357 "clk_ext3", "audio_pll2_out", }; 358 359 static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; 360 361 static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "osc_27m", 362 "sys_pll1_200m", "audio_pll2_out", "vpu_pll", 363 "sys_pll1_80m", }; 364 static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", 365 "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", 366 "video_pll1_out", "osc_32k", }; 367 368 static struct clk *clks[IMX8MN_CLK_END]; 369 static struct clk_onecell_data clk_data; 370 371 static struct clk ** const uart_clks[] = { 372 &clks[IMX8MN_CLK_UART1_ROOT], 373 &clks[IMX8MN_CLK_UART2_ROOT], 374 &clks[IMX8MN_CLK_UART3_ROOT], 375 &clks[IMX8MN_CLK_UART4_ROOT], 376 NULL 377 }; 378 379 static int imx8mn_clocks_probe(struct platform_device *pdev) 380 { 381 struct device *dev = &pdev->dev; 382 struct device_node *np = dev->of_node; 383 void __iomem *base; 384 int ret; 385 386 clks[IMX8MN_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 387 clks[IMX8MN_CLK_24M] = of_clk_get_by_name(np, "osc_24m"); 388 clks[IMX8MN_CLK_32K] = of_clk_get_by_name(np, "osc_32k"); 389 clks[IMX8MN_CLK_EXT1] = of_clk_get_by_name(np, "clk_ext1"); 390 clks[IMX8MN_CLK_EXT2] = of_clk_get_by_name(np, "clk_ext2"); 391 clks[IMX8MN_CLK_EXT3] = of_clk_get_by_name(np, "clk_ext3"); 392 clks[IMX8MN_CLK_EXT4] = of_clk_get_by_name(np, "clk_ext4"); 393 394 np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop"); 395 base = of_iomap(np, 0); 396 if (WARN_ON(!base)) { 397 ret = -ENOMEM; 398 goto unregister_clks; 399 } 400 401 clks[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 402 clks[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 403 clks[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 404 clks[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 405 clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 406 clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 407 clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 408 clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 409 clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 410 clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 411 412 clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll); 413 clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll); 414 clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll); 415 clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll); 416 clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll); 417 clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll); 418 clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll); 419 clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll); 420 clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll); 421 clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll); 422 423 /* PLL bypass out */ 424 clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); 425 clks[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); 426 clks[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT); 427 clks[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); 428 clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 429 clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT); 430 clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); 431 clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT); 432 clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT); 433 clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); 434 435 /* PLL out gate */ 436 clks[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_gate("audio_pll1_out", "audio_pll1_bypass", base, 13); 437 clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13); 438 clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13); 439 clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13); 440 clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11); 441 clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11); 442 clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11); 443 clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11); 444 clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11); 445 clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11); 446 447 /* SYS PLL fixed output */ 448 clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); 449 clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); 450 clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); 451 clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); 452 clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); 453 clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); 454 clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); 455 clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); 456 clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); 457 458 clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); 459 clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); 460 clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); 461 clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); 462 clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); 463 clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); 464 clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); 465 clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); 466 clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); 467 468 np = dev->of_node; 469 base = devm_platform_ioremap_resource(pdev, 0); 470 if (WARN_ON(IS_ERR(base))) { 471 ret = PTR_ERR(base); 472 goto unregister_clks; 473 } 474 475 /* CORE */ 476 clks[IMX8MN_CLK_A53_SRC] = imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3, imx8mn_a53_sels, ARRAY_SIZE(imx8mn_a53_sels)); 477 clks[IMX8MN_CLK_GPU_CORE_SRC] = imx_clk_mux2("gpu_core_src", base + 0x8180, 24, 3, imx8mn_gpu_core_sels, ARRAY_SIZE(imx8mn_gpu_core_sels)); 478 clks[IMX8MN_CLK_GPU_SHADER_SRC] = imx_clk_mux2("gpu_shader_src", base + 0x8200, 24, 3, imx8mn_gpu_shader_sels, ARRAY_SIZE(imx8mn_gpu_shader_sels)); 479 clks[IMX8MN_CLK_A53_CG] = imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28); 480 clks[IMX8MN_CLK_GPU_CORE_CG] = imx_clk_gate3("gpu_core_cg", "gpu_core_src", base + 0x8180, 28); 481 clks[IMX8MN_CLK_GPU_SHADER_CG] = imx_clk_gate3("gpu_shader_cg", "gpu_shader_src", base + 0x8200, 28); 482 483 clks[IMX8MN_CLK_A53_DIV] = imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3); 484 clks[IMX8MN_CLK_GPU_CORE_DIV] = imx_clk_divider2("gpu_core_div", "gpu_core_cg", base + 0x8180, 0, 3); 485 clks[IMX8MN_CLK_GPU_SHADER_DIV] = imx_clk_divider2("gpu_shader_div", "gpu_shader_cg", base + 0x8200, 0, 3); 486 487 /* BUS */ 488 clks[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_composite_critical("main_axi", imx8mn_main_axi_sels, base + 0x8800); 489 clks[IMX8MN_CLK_ENET_AXI] = imx8m_clk_composite("enet_axi", imx8mn_enet_axi_sels, base + 0x8880); 490 clks[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_composite("nand_usdhc_bus", imx8mn_nand_usdhc_sels, base + 0x8900); 491 clks[IMX8MN_CLK_DISP_AXI] = imx8m_clk_composite("disp_axi", imx8mn_disp_axi_sels, base + 0x8a00); 492 clks[IMX8MN_CLK_DISP_APB] = imx8m_clk_composite("disp_apb", imx8mn_disp_apb_sels, base + 0x8a80); 493 clks[IMX8MN_CLK_USB_BUS] = imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80); 494 clks[IMX8MN_CLK_GPU_AXI] = imx8m_clk_composite("gpu_axi", imx8mn_gpu_axi_sels, base + 0x8c00); 495 clks[IMX8MN_CLK_GPU_AHB] = imx8m_clk_composite("gpu_ahb", imx8mn_gpu_ahb_sels, base + 0x8c80); 496 clks[IMX8MN_CLK_NOC] = imx8m_clk_composite_critical("noc", imx8mn_noc_sels, base + 0x8d00); 497 498 clks[IMX8MN_CLK_AHB] = imx8m_clk_composite_critical("ahb", imx8mn_ahb_sels, base + 0x9000); 499 clks[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_composite("audio_ahb", imx8mn_audio_ahb_sels, base + 0x9100); 500 clks[IMX8MN_CLK_IPG_ROOT] = imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1); 501 clks[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_divider2("ipg_audio_root", "audio_ahb", base + 0x9180, 0, 1); 502 clks[IMX8MN_CLK_DRAM_CORE] = imx_clk_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL); 503 clks[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); 504 clks[IMX8MN_CLK_DRAM_APB] = imx8m_clk_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); 505 clks[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); 506 clks[IMX8MN_CLK_SAI2] = imx8m_clk_composite("sai2", imx8mn_sai2_sels, base + 0xa600); 507 clks[IMX8MN_CLK_SAI3] = imx8m_clk_composite("sai3", imx8mn_sai3_sels, base + 0xa680); 508 clks[IMX8MN_CLK_SAI5] = imx8m_clk_composite("sai5", imx8mn_sai5_sels, base + 0xa780); 509 clks[IMX8MN_CLK_SAI6] = imx8m_clk_composite("sai6", imx8mn_sai6_sels, base + 0xa800); 510 clks[IMX8MN_CLK_SPDIF1] = imx8m_clk_composite("spdif1", imx8mn_spdif1_sels, base + 0xa880); 511 clks[IMX8MN_CLK_ENET_REF] = imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels, base + 0xa980); 512 clks[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_composite("enet_timer", imx8mn_enet_timer_sels, base + 0xaa00); 513 clks[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_composite("enet_phy", imx8mn_enet_phy_sels, base + 0xaa80); 514 clks[IMX8MN_CLK_NAND] = imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00); 515 clks[IMX8MN_CLK_QSPI] = imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80); 516 clks[IMX8MN_CLK_USDHC1] = imx8m_clk_composite("usdhc1", imx8mn_usdhc1_sels, base + 0xac00); 517 clks[IMX8MN_CLK_USDHC2] = imx8m_clk_composite("usdhc2", imx8mn_usdhc2_sels, base + 0xac80); 518 clks[IMX8MN_CLK_I2C1] = imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00); 519 clks[IMX8MN_CLK_I2C2] = imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80); 520 clks[IMX8MN_CLK_I2C3] = imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00); 521 clks[IMX8MN_CLK_I2C4] = imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80); 522 clks[IMX8MN_CLK_UART1] = imx8m_clk_composite("uart1", imx8mn_uart1_sels, base + 0xaf00); 523 clks[IMX8MN_CLK_UART2] = imx8m_clk_composite("uart2", imx8mn_uart2_sels, base + 0xaf80); 524 clks[IMX8MN_CLK_UART3] = imx8m_clk_composite("uart3", imx8mn_uart3_sels, base + 0xb000); 525 clks[IMX8MN_CLK_UART4] = imx8m_clk_composite("uart4", imx8mn_uart4_sels, base + 0xb080); 526 clks[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100); 527 clks[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180); 528 clks[IMX8MN_CLK_GIC] = imx8m_clk_composite_critical("gic", imx8mn_gic_sels, base + 0xb200); 529 clks[IMX8MN_CLK_ECSPI1] = imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280); 530 clks[IMX8MN_CLK_ECSPI2] = imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300); 531 clks[IMX8MN_CLK_PWM1] = imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380); 532 clks[IMX8MN_CLK_PWM2] = imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400); 533 clks[IMX8MN_CLK_PWM3] = imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480); 534 clks[IMX8MN_CLK_PWM4] = imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500); 535 clks[IMX8MN_CLK_WDOG] = imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900); 536 clks[IMX8MN_CLK_WRCLK] = imx8m_clk_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980); 537 clks[IMX8MN_CLK_CLKO1] = imx8m_clk_composite("clko1", imx8mn_clko1_sels, base + 0xba00); 538 clks[IMX8MN_CLK_CLKO2] = imx8m_clk_composite("clko2", imx8mn_clko2_sels, base + 0xba80); 539 clks[IMX8MN_CLK_DSI_CORE] = imx8m_clk_composite("dsi_core", imx8mn_dsi_core_sels, base + 0xbb00); 540 clks[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_composite("dsi_phy_ref", imx8mn_dsi_phy_sels, base + 0xbb80); 541 clks[IMX8MN_CLK_DSI_DBI] = imx8m_clk_composite("dsi_dbi", imx8mn_dsi_dbi_sels, base + 0xbc00); 542 clks[IMX8MN_CLK_USDHC3] = imx8m_clk_composite("usdhc3", imx8mn_usdhc3_sels, base + 0xbc80); 543 clks[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_composite("camera_pixel", imx8mn_camera_pixel_sels, base + 0xbd00); 544 clks[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_composite("csi1_phy_ref", imx8mn_csi1_phy_sels, base + 0xbd80); 545 clks[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_composite("csi2_phy_ref", imx8mn_csi2_phy_sels, base + 0xbf00); 546 clks[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_composite("csi2_esc", imx8mn_csi2_esc_sels, base + 0xbf80); 547 clks[IMX8MN_CLK_ECSPI3] = imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180); 548 clks[IMX8MN_CLK_PDM] = imx8m_clk_composite("pdm", imx8mn_pdm_sels, base + 0xc200); 549 clks[IMX8MN_CLK_SAI7] = imx8m_clk_composite("sai7", imx8mn_sai7_sels, base + 0xc300); 550 551 clks[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0); 552 clks[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0); 553 clks[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0); 554 clks[IMX8MN_CLK_ENET1_ROOT] = imx_clk_gate4("enet1_root_clk", "enet_axi", base + 0x40a0, 0); 555 clks[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_gate4("gpio1_root_clk", "ipg_root", base + 0x40b0, 0); 556 clks[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_gate4("gpio2_root_clk", "ipg_root", base + 0x40c0, 0); 557 clks[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0); 558 clks[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0); 559 clks[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0); 560 clks[IMX8MN_CLK_I2C1_ROOT] = imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0); 561 clks[IMX8MN_CLK_I2C2_ROOT] = imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0); 562 clks[IMX8MN_CLK_I2C3_ROOT] = imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0); 563 clks[IMX8MN_CLK_I2C4_ROOT] = imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0); 564 clks[IMX8MN_CLK_MU_ROOT] = imx_clk_gate4("mu_root_clk", "ipg_root", base + 0x4210, 0); 565 clks[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0); 566 clks[IMX8MN_CLK_PWM1_ROOT] = imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0); 567 clks[IMX8MN_CLK_PWM2_ROOT] = imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0); 568 clks[IMX8MN_CLK_PWM3_ROOT] = imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0); 569 clks[IMX8MN_CLK_PWM4_ROOT] = imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0); 570 clks[IMX8MN_CLK_QSPI_ROOT] = imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0); 571 clks[IMX8MN_CLK_NAND_ROOT] = imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand); 572 clks[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_nand); 573 clks[IMX8MN_CLK_SAI2_ROOT] = imx_clk_gate2_shared2("sai2_root_clk", "sai2", base + 0x4340, 0, &share_count_sai2); 574 clks[IMX8MN_CLK_SAI2_IPG] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_audio_root", base + 0x4340, 0, &share_count_sai2); 575 clks[IMX8MN_CLK_SAI3_ROOT] = imx_clk_gate2_shared2("sai3_root_clk", "sai3", base + 0x4350, 0, &share_count_sai3); 576 clks[IMX8MN_CLK_SAI3_IPG] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_audio_root", base + 0x4350, 0, &share_count_sai3); 577 clks[IMX8MN_CLK_SAI5_ROOT] = imx_clk_gate2_shared2("sai5_root_clk", "sai5", base + 0x4370, 0, &share_count_sai5); 578 clks[IMX8MN_CLK_SAI5_IPG] = imx_clk_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); 579 clks[IMX8MN_CLK_SAI6_ROOT] = imx_clk_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); 580 clks[IMX8MN_CLK_SAI6_IPG] = imx_clk_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); 581 clks[IMX8MN_CLK_UART1_ROOT] = imx_clk_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); 582 clks[IMX8MN_CLK_UART2_ROOT] = imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); 583 clks[IMX8MN_CLK_UART3_ROOT] = imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); 584 clks[IMX8MN_CLK_UART4_ROOT] = imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0); 585 clks[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_gate4("usb1_ctrl_root_clk", "usb_core_ref", base + 0x44d0, 0); 586 clks[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_gate4("gpu_core_root_clk", "gpu_core_div", base + 0x44f0, 0); 587 clks[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0); 588 clks[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0); 589 clks[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0); 590 clks[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0); 591 clks[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0); 592 clks[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_gate4("gpu_root_clk", "gpu_axi", base + 0x4570, 0); 593 clks[IMX8MN_CLK_ASRC_ROOT] = imx_clk_gate4("asrc_root_clk", "audio_ahb", base + 0x4580, 0); 594 clks[IMX8MN_CLK_PDM_ROOT] = imx_clk_gate2_shared2("pdm_root_clk", "pdm", base + 0x45b0, 0, &share_count_pdm); 595 clks[IMX8MN_CLK_PDM_IPG] = imx_clk_gate2_shared2("pdm_ipg_clk", "ipg_audio_root", base + 0x45b0, 0, &share_count_pdm); 596 clks[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_gate2_shared2("disp_axi_root_clk", "disp_axi", base + 0x45d0, 0, &share_count_disp); 597 clks[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_gate2_shared2("disp_apb_root_clk", "disp_apb", base + 0x45d0, 0, &share_count_disp); 598 clks[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_gate2_shared2("camera_pixel_clk", "camera_pixel", base + 0x45d0, 0, &share_count_disp); 599 clks[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_gate2_shared2("disp_pixel_clk", "disp_pixel", base + 0x45d0, 0, &share_count_disp); 600 clks[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0); 601 clks[IMX8MN_CLK_TMU_ROOT] = imx_clk_gate4("tmu_root_clk", "ipg_root", base + 0x4620, 0); 602 clks[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_gate4("sdma1_clk", "ipg_root", base + 0x43a0, 0); 603 clks[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_gate4("sdma2_clk", "ipg_audio_root", base + 0x43b0, 0); 604 clks[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0); 605 clks[IMX8MN_CLK_SAI7_ROOT] = imx_clk_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7); 606 607 clks[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_fixed_factor("dram_alt_root", "dram_alt", 1, 4); 608 609 clks[IMX8MN_CLK_ARM] = imx_clk_cpu("arm", "arm_a53_div", 610 clks[IMX8MN_CLK_A53_DIV], 611 clks[IMX8MN_CLK_A53_SRC], 612 clks[IMX8MN_ARM_PLL_OUT], 613 clks[IMX8MN_CLK_24M]); 614 615 imx_check_clocks(clks, ARRAY_SIZE(clks)); 616 617 clk_data.clks = clks; 618 clk_data.clk_num = ARRAY_SIZE(clks); 619 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 620 if (ret < 0) { 621 dev_err(dev, "failed to register clks for i.MX8MN\n"); 622 goto unregister_clks; 623 } 624 625 imx_register_uart_clocks(uart_clks); 626 627 return 0; 628 629 unregister_clks: 630 imx_unregister_clocks(clks, ARRAY_SIZE(clks)); 631 632 return ret; 633 } 634 635 static const struct of_device_id imx8mn_clk_of_match[] = { 636 { .compatible = "fsl,imx8mn-ccm" }, 637 { /* Sentinel */ }, 638 }; 639 MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match); 640 641 static struct platform_driver imx8mn_clk_driver = { 642 .probe = imx8mn_clocks_probe, 643 .driver = { 644 .name = "imx8mn-ccm", 645 .of_match_table = of_match_ptr(imx8mn_clk_of_match), 646 }, 647 }; 648 module_platform_driver(imx8mn_clk_driver); 649