xref: /openbmc/linux/drivers/atm/lanai.c (revision b6dcefde)
1 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
2  *
3  *  This program is free software; you can redistribute it and/or
4  *  modify it under the terms of the GNU General Public License
5  *  as published by the Free Software Foundation; either version
6  *  2 of the License, or (at your option) any later version.
7  *
8  * This driver supports ATM cards based on the Efficient "Lanai"
9  * chipset such as the Speedstream 3010 and the ENI-25p.  The
10  * Speedstream 3060 is currently not supported since we don't
11  * have the code to drive the on-board Alcatel DSL chipset (yet).
12  *
13  * Thanks to Efficient for supporting this project with hardware,
14  * documentation, and by answering my questions.
15  *
16  * Things not working yet:
17  *
18  * o  We don't support the Speedstream 3060 yet - this card has
19  *    an on-board DSL modem chip by Alcatel and the driver will
20  *    need some extra code added to handle it
21  *
22  * o  Note that due to limitations of the Lanai only one VCC can be
23  *    in CBR at once
24  *
25  * o We don't currently parse the EEPROM at all.  The code is all
26  *   there as per the spec, but it doesn't actually work.  I think
27  *   there may be some issues with the docs.  Anyway, do NOT
28  *   enable it yet - bugs in that code may actually damage your
29  *   hardware!  Because of this you should hardware an ESI before
30  *   trying to use this in a LANE or MPOA environment.
31  *
32  * o  AAL0 is stubbed in but the actual rx/tx path isn't written yet:
33  *	vcc_tx_aal0() needs to send or queue a SKB
34  *	vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
35  *	vcc_rx_aal0() needs to handle AAL0 interrupts
36  *    This isn't too much work - I just wanted to get other things
37  *    done first.
38  *
39  * o  lanai_change_qos() isn't written yet
40  *
41  * o  There aren't any ioctl's yet -- I'd like to eventually support
42  *    setting loopback and LED modes that way.
43  *
44  * o  If the segmentation engine or DMA gets shut down we should restart
45  *    card as per section 17.0i.  (see lanai_reset)
46  *
47  * o setsockopt(SO_CIRANGE) isn't done (although despite what the
48  *   API says it isn't exactly commonly implemented)
49  */
50 
51 /* Version history:
52  *   v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
53  *   v.0.02 -- 11-JAN-2000 -- Endian fixes
54  *   v.0.01 -- 30-NOV-1999 -- Initial release
55  */
56 
57 #include <linux/module.h>
58 #include <linux/mm.h>
59 #include <linux/atmdev.h>
60 #include <asm/io.h>
61 #include <asm/byteorder.h>
62 #include <linux/spinlock.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/interrupt.h>
68 
69 /* -------------------- TUNABLE PARAMATERS: */
70 
71 /*
72  * Maximum number of VCIs per card.  Setting it lower could theoretically
73  * save some memory, but since we allocate our vcc list with get_free_pages,
74  * it's not really likely for most architectures
75  */
76 #define NUM_VCI			(1024)
77 
78 /*
79  * Enable extra debugging
80  */
81 #define DEBUG
82 /*
83  * Debug _all_ register operations with card, except the memory test.
84  * Also disables the timed poll to prevent extra chattiness.  This
85  * isn't for normal use
86  */
87 #undef DEBUG_RW
88 
89 /*
90  * The programming guide specifies a full test of the on-board SRAM
91  * at initialization time.  Undefine to remove this
92  */
93 #define FULL_MEMORY_TEST
94 
95 /*
96  * This is the number of (4 byte) service entries that we will
97  * try to allocate at startup.  Note that we will end up with
98  * one PAGE_SIZE's worth regardless of what this is set to
99  */
100 #define SERVICE_ENTRIES		(1024)
101 /* TODO: make above a module load-time option */
102 
103 /*
104  * We normally read the onboard EEPROM in order to discover our MAC
105  * address.  Undefine to _not_ do this
106  */
107 /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
108 /* TODO: make above a module load-time option (also) */
109 
110 /*
111  * Depth of TX fifo (in 128 byte units; range 2-31)
112  * Smaller numbers are better for network latency
113  * Larger numbers are better for PCI latency
114  * I'm really sure where the best tradeoff is, but the BSD driver uses
115  * 7 and it seems to work ok.
116  */
117 #define TX_FIFO_DEPTH		(7)
118 /* TODO: make above a module load-time option */
119 
120 /*
121  * How often (in jiffies) we will try to unstick stuck connections -
122  * shouldn't need to happen much
123  */
124 #define LANAI_POLL_PERIOD	(10*HZ)
125 /* TODO: make above a module load-time option */
126 
127 /*
128  * When allocating an AAL5 receiving buffer, try to make it at least
129  * large enough to hold this many max_sdu sized PDUs
130  */
131 #define AAL5_RX_MULTIPLIER	(3)
132 /* TODO: make above a module load-time option */
133 
134 /*
135  * Same for transmitting buffer
136  */
137 #define AAL5_TX_MULTIPLIER	(3)
138 /* TODO: make above a module load-time option */
139 
140 /*
141  * When allocating an AAL0 transmiting buffer, how many cells should fit.
142  * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
143  * really critical
144  */
145 #define AAL0_TX_MULTIPLIER	(40)
146 /* TODO: make above a module load-time option */
147 
148 /*
149  * How large should we make the AAL0 receiving buffer.  Remember that this
150  * is shared between all AAL0 VC's
151  */
152 #define AAL0_RX_BUFFER_SIZE	(PAGE_SIZE)
153 /* TODO: make above a module load-time option */
154 
155 /*
156  * Should we use Lanai's "powerdown" feature when no vcc's are bound?
157  */
158 /* #define USE_POWERDOWN */
159 /* TODO: make above a module load-time option (also) */
160 
161 /* -------------------- DEBUGGING AIDS: */
162 
163 #define DEV_LABEL "lanai"
164 
165 #ifdef DEBUG
166 
167 #define DPRINTK(format, args...) \
168 	printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
169 #define APRINTK(truth, format, args...) \
170 	do { \
171 		if (unlikely(!(truth))) \
172 			printk(KERN_ERR DEV_LABEL ": " format, ##args); \
173 	} while (0)
174 
175 #else /* !DEBUG */
176 
177 #define DPRINTK(format, args...)
178 #define APRINTK(truth, format, args...)
179 
180 #endif /* DEBUG */
181 
182 #ifdef DEBUG_RW
183 #define RWDEBUG(format, args...) \
184 	printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
185 #else /* !DEBUG_RW */
186 #define RWDEBUG(format, args...)
187 #endif
188 
189 /* -------------------- DATA DEFINITIONS: */
190 
191 #define LANAI_MAPPING_SIZE	(0x40000)
192 #define LANAI_EEPROM_SIZE	(128)
193 
194 typedef int vci_t;
195 typedef void __iomem *bus_addr_t;
196 
197 /* DMA buffer in host memory for TX, RX, or service list. */
198 struct lanai_buffer {
199 	u32 *start;	/* From get_free_pages */
200 	u32 *end;	/* One past last byte */
201 	u32 *ptr;	/* Pointer to current host location */
202 	dma_addr_t dmaaddr;
203 };
204 
205 struct lanai_vcc_stats {
206 	unsigned rx_nomem;
207 	union {
208 		struct {
209 			unsigned rx_badlen;
210 			unsigned service_trash;
211 			unsigned service_stream;
212 			unsigned service_rxcrc;
213 		} aal5;
214 		struct {
215 		} aal0;
216 	} x;
217 };
218 
219 struct lanai_dev;			/* Forward declaration */
220 
221 /*
222  * This is the card-specific per-vcc data.  Note that unlike some other
223  * drivers there is NOT a 1-to-1 correspondance between these and
224  * atm_vcc's - each one of these represents an actual 2-way vcc, but
225  * an atm_vcc can be 1-way and share with a 1-way vcc in the other
226  * direction.  To make it weirder, there can even be 0-way vccs
227  * bound to us, waiting to do a change_qos
228  */
229 struct lanai_vcc {
230 	bus_addr_t vbase;		/* Base of VCC's registers */
231 	struct lanai_vcc_stats stats;
232 	int nref;			/* # of atm_vcc's who reference us */
233 	vci_t vci;
234 	struct {
235 		struct lanai_buffer buf;
236 		struct atm_vcc *atmvcc;	/* atm_vcc who is receiver */
237 	} rx;
238 	struct {
239 		struct lanai_buffer buf;
240 		struct atm_vcc *atmvcc;	/* atm_vcc who is transmitter */
241 		int endptr;		/* last endptr from service entry */
242 		struct sk_buff_head backlog;
243 		void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
244 	} tx;
245 };
246 
247 enum lanai_type {
248 	lanai2	= PCI_DEVICE_ID_EF_ATM_LANAI2,
249 	lanaihb	= PCI_DEVICE_ID_EF_ATM_LANAIHB
250 };
251 
252 struct lanai_dev_stats {
253 	unsigned ovfl_trash;	/* # of cells dropped - buffer overflow */
254 	unsigned vci_trash;	/* # of cells dropped - closed vci */
255 	unsigned hec_err;	/* # of cells dropped - bad HEC */
256 	unsigned atm_ovfl;	/* # of cells dropped - rx fifo overflow */
257 	unsigned pcierr_parity_detect;
258 	unsigned pcierr_serr_set;
259 	unsigned pcierr_master_abort;
260 	unsigned pcierr_m_target_abort;
261 	unsigned pcierr_s_target_abort;
262 	unsigned pcierr_master_parity;
263 	unsigned service_notx;
264 	unsigned service_norx;
265 	unsigned service_rxnotaal5;
266 	unsigned dma_reenable;
267 	unsigned card_reset;
268 };
269 
270 struct lanai_dev {
271 	bus_addr_t base;
272 	struct lanai_dev_stats stats;
273 	struct lanai_buffer service;
274 	struct lanai_vcc **vccs;
275 #ifdef USE_POWERDOWN
276 	int nbound;			/* number of bound vccs */
277 #endif
278 	enum lanai_type type;
279 	vci_t num_vci;			/* Currently just NUM_VCI */
280 	u8 eeprom[LANAI_EEPROM_SIZE];
281 	u32 serialno, magicno;
282 	struct pci_dev *pci;
283 	DECLARE_BITMAP(backlog_vccs, NUM_VCI);   /* VCCs with tx backlog */
284 	DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
285 	struct timer_list timer;
286 	int naal0;
287 	struct lanai_buffer aal0buf;	/* AAL0 RX buffers */
288 	u32 conf1, conf2;		/* CONFIG[12] registers */
289 	u32 status;			/* STATUS register */
290 	spinlock_t endtxlock;
291 	spinlock_t servicelock;
292 	struct atm_vcc *cbrvcc;
293 	int number;
294 	int board_rev;
295 /* TODO - look at race conditions with maintence of conf1/conf2 */
296 /* TODO - transmit locking: should we use _irq not _irqsave? */
297 /* TODO - organize above in some rational fashion (see <asm/cache.h>) */
298 };
299 
300 /*
301  * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
302  * This function iterates one of these, calling a given function for each
303  * vci with their bit set
304  */
305 static void vci_bitfield_iterate(struct lanai_dev *lanai,
306 	const unsigned long *lp,
307 	void (*func)(struct lanai_dev *,vci_t vci))
308 {
309 	vci_t vci = find_first_bit(lp, NUM_VCI);
310 	while (vci < NUM_VCI) {
311 		func(lanai, vci);
312 		vci = find_next_bit(lp, NUM_VCI, vci + 1);
313 	}
314 }
315 
316 /* -------------------- BUFFER  UTILITIES: */
317 
318 /*
319  * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
320  * usually any page allocation will do.  Just to be safe in case
321  * PAGE_SIZE is insanely tiny, though...
322  */
323 #define LANAI_PAGE_SIZE   ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
324 
325 /*
326  * Allocate a buffer in host RAM for service list, RX, or TX
327  * Returns buf->start==NULL if no memory
328  * Note that the size will be rounded up 2^n bytes, and
329  * if we can't allocate that we'll settle for something smaller
330  * until minbytes
331  */
332 static void lanai_buf_allocate(struct lanai_buffer *buf,
333 	size_t bytes, size_t minbytes, struct pci_dev *pci)
334 {
335 	int size;
336 
337 	if (bytes > (128 * 1024))	/* max lanai buffer size */
338 		bytes = 128 * 1024;
339 	for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
340 		;
341 	if (minbytes < LANAI_PAGE_SIZE)
342 		minbytes = LANAI_PAGE_SIZE;
343 	do {
344 		/*
345 		 * Technically we could use non-consistent mappings for
346 		 * everything, but the way the lanai uses DMA memory would
347 		 * make that a terrific pain.  This is much simpler.
348 		 */
349 		buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr);
350 		if (buf->start != NULL) {	/* Success */
351 			/* Lanai requires 256-byte alignment of DMA bufs */
352 			APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
353 			    "bad dmaaddr: 0x%lx\n",
354 			    (unsigned long) buf->dmaaddr);
355 			buf->ptr = buf->start;
356 			buf->end = (u32 *)
357 			    (&((unsigned char *) buf->start)[size]);
358 			memset(buf->start, 0, size);
359 			break;
360 		}
361 		size /= 2;
362 	} while (size >= minbytes);
363 }
364 
365 /* size of buffer in bytes */
366 static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
367 {
368 	return ((unsigned long) buf->end) - ((unsigned long) buf->start);
369 }
370 
371 static void lanai_buf_deallocate(struct lanai_buffer *buf,
372 	struct pci_dev *pci)
373 {
374 	if (buf->start != NULL) {
375 		pci_free_consistent(pci, lanai_buf_size(buf),
376 		    buf->start, buf->dmaaddr);
377 		buf->start = buf->end = buf->ptr = NULL;
378 	}
379 }
380 
381 /* size of buffer as "card order" (0=1k .. 7=128k) */
382 static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
383 {
384 	int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
385 
386 	/* This can only happen if PAGE_SIZE is gigantic, but just in case */
387 	if (order > 7)
388 		order = 7;
389 	return order;
390 }
391 
392 /* -------------------- PORT I/O UTILITIES: */
393 
394 /* Registers (and their bit-fields) */
395 enum lanai_register {
396 	Reset_Reg		= 0x00,	/* Reset; read for chip type; bits: */
397 #define   RESET_GET_BOARD_REV(x)    (((x)>> 0)&0x03)	/* Board revision */
398 #define   RESET_GET_BOARD_ID(x)	    (((x)>> 2)&0x03)	/* Board ID */
399 #define     BOARD_ID_LANAI256		(0)	/* 25.6M adapter card */
400 	Endian_Reg		= 0x04,	/* Endian setting */
401 	IntStatus_Reg		= 0x08,	/* Interrupt status */
402 	IntStatusMasked_Reg	= 0x0C,	/* Interrupt status (masked) */
403 	IntAck_Reg		= 0x10,	/* Interrupt acknowledge */
404 	IntAckMasked_Reg	= 0x14,	/* Interrupt acknowledge (masked) */
405 	IntStatusSet_Reg	= 0x18,	/* Get status + enable/disable */
406 	IntStatusSetMasked_Reg	= 0x1C,	/* Get status + en/di (masked) */
407 	IntControlEna_Reg	= 0x20,	/* Interrupt control enable */
408 	IntControlDis_Reg	= 0x24,	/* Interrupt control disable */
409 	Status_Reg		= 0x28,	/* Status */
410 #define   STATUS_PROMDATA	 (0x00000001)	/* PROM_DATA pin */
411 #define   STATUS_WAITING	 (0x00000002)	/* Interrupt being delayed */
412 #define	  STATUS_SOOL		 (0x00000004)	/* SOOL alarm */
413 #define   STATUS_LOCD		 (0x00000008)	/* LOCD alarm */
414 #define	  STATUS_LED		 (0x00000010)	/* LED (HAPPI) output */
415 #define   STATUS_GPIN		 (0x00000020)	/* GPIN pin */
416 #define   STATUS_BUTTBUSY	 (0x00000040)	/* Butt register is pending */
417 	Config1_Reg		= 0x2C,	/* Config word 1; bits: */
418 #define   CONFIG1_PROMDATA	 (0x00000001)	/* PROM_DATA pin */
419 #define   CONFIG1_PROMCLK	 (0x00000002)	/* PROM_CLK pin */
420 #define   CONFIG1_SET_READMODE(x) ((x)*0x004)	/* PCI BM reads; values: */
421 #define     READMODE_PLAIN	    (0)		/*   Plain memory read */
422 #define     READMODE_LINE	    (2)		/*   Memory read line */
423 #define     READMODE_MULTIPLE	    (3)		/*   Memory read multiple */
424 #define   CONFIG1_DMA_ENABLE	 (0x00000010)	/* Turn on DMA */
425 #define   CONFIG1_POWERDOWN	 (0x00000020)	/* Turn off clocks */
426 #define   CONFIG1_SET_LOOPMODE(x) ((x)*0x080)	/* Clock&loop mode; values: */
427 #define     LOOPMODE_NORMAL	    (0)		/*   Normal - no loop */
428 #define     LOOPMODE_TIME	    (1)
429 #define     LOOPMODE_DIAG	    (2)
430 #define     LOOPMODE_LINE	    (3)
431 #define   CONFIG1_MASK_LOOPMODE  (0x00000180)
432 #define   CONFIG1_SET_LEDMODE(x) ((x)*0x0200)	/* Mode of LED; values: */
433 #define     LEDMODE_NOT_SOOL	    (0)		/*   !SOOL */
434 #define	    LEDMODE_OFF		    (1)		/*   0     */
435 #define	    LEDMODE_ON		    (2)		/*   1     */
436 #define	    LEDMODE_NOT_LOCD	    (3)		/*   !LOCD */
437 #define	    LEDMORE_GPIN	    (4)		/*   GPIN  */
438 #define     LEDMODE_NOT_GPIN	    (7)		/*   !GPIN */
439 #define   CONFIG1_MASK_LEDMODE	 (0x00000E00)
440 #define   CONFIG1_GPOUT1	 (0x00001000)	/* Toggle for reset */
441 #define   CONFIG1_GPOUT2	 (0x00002000)	/* Loopback PHY */
442 #define   CONFIG1_GPOUT3	 (0x00004000)	/* Loopback lanai */
443 	Config2_Reg		= 0x30,	/* Config word 2; bits: */
444 #define   CONFIG2_HOWMANY	 (0x00000001)	/* >512 VCIs? */
445 #define   CONFIG2_PTI7_MODE	 (0x00000002)	/* Make PTI=7 RM, not OAM */
446 #define   CONFIG2_VPI_CHK_DIS	 (0x00000004)	/* Ignore RX VPI value */
447 #define   CONFIG2_HEC_DROP	 (0x00000008)	/* Drop cells w/ HEC errors */
448 #define   CONFIG2_VCI0_NORMAL	 (0x00000010)	/* Treat VCI=0 normally */
449 #define   CONFIG2_CBR_ENABLE	 (0x00000020)	/* Deal with CBR traffic */
450 #define   CONFIG2_TRASH_ALL	 (0x00000040)	/* Trashing incoming cells */
451 #define   CONFIG2_TX_DISABLE	 (0x00000080)	/* Trashing outgoing cells */
452 #define   CONFIG2_SET_TRASH	 (0x00000100)	/* Turn trashing on */
453 	Statistics_Reg		= 0x34,	/* Statistics; bits: */
454 #define   STATS_GET_FIFO_OVFL(x)    (((x)>> 0)&0xFF)	/* FIFO overflowed */
455 #define   STATS_GET_HEC_ERR(x)      (((x)>> 8)&0xFF)	/* HEC was bad */
456 #define   STATS_GET_BAD_VCI(x)      (((x)>>16)&0xFF)	/* VCI not open */
457 #define   STATS_GET_BUF_OVFL(x)     (((x)>>24)&0xFF)	/* VCC buffer full */
458 	ServiceStuff_Reg	= 0x38,	/* Service stuff; bits: */
459 #define   SSTUFF_SET_SIZE(x) ((x)*0x20000000)	/* size of service buffer */
460 #define   SSTUFF_SET_ADDR(x)	    ((x)>>8)	/* set address of buffer */
461 	ServWrite_Reg		= 0x3C,	/* ServWrite Pointer */
462 	ServRead_Reg		= 0x40,	/* ServRead Pointer */
463 	TxDepth_Reg		= 0x44,	/* FIFO Transmit Depth */
464 	Butt_Reg		= 0x48,	/* Butt register */
465 	CBR_ICG_Reg		= 0x50,
466 	CBR_PTR_Reg		= 0x54,
467 	PingCount_Reg		= 0x58,	/* Ping count */
468 	DMA_Addr_Reg		= 0x5C	/* DMA address */
469 };
470 
471 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
472 	enum lanai_register reg)
473 {
474 	return lanai->base + reg;
475 }
476 
477 static inline u32 reg_read(const struct lanai_dev *lanai,
478 	enum lanai_register reg)
479 {
480 	u32 t;
481 	t = readl(reg_addr(lanai, reg));
482 	RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
483 	    (int) reg, t);
484 	return t;
485 }
486 
487 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
488 	enum lanai_register reg)
489 {
490 	RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
491 	    (int) reg, val);
492 	writel(val, reg_addr(lanai, reg));
493 }
494 
495 static inline void conf1_write(const struct lanai_dev *lanai)
496 {
497 	reg_write(lanai, lanai->conf1, Config1_Reg);
498 }
499 
500 static inline void conf2_write(const struct lanai_dev *lanai)
501 {
502 	reg_write(lanai, lanai->conf2, Config2_Reg);
503 }
504 
505 /* Same as conf2_write(), but defers I/O if we're powered down */
506 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
507 {
508 #ifdef USE_POWERDOWN
509 	if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
510 		return;
511 #endif /* USE_POWERDOWN */
512 	conf2_write(lanai);
513 }
514 
515 static inline void reset_board(const struct lanai_dev *lanai)
516 {
517 	DPRINTK("about to reset board\n");
518 	reg_write(lanai, 0, Reset_Reg);
519 	/*
520 	 * If we don't delay a little while here then we can end up
521 	 * leaving the card in a VERY weird state and lock up the
522 	 * PCI bus.  This isn't documented anywhere but I've convinced
523 	 * myself after a lot of painful experimentation
524 	 */
525 	udelay(5);
526 }
527 
528 /* -------------------- CARD SRAM UTILITIES: */
529 
530 /* The SRAM is mapped into normal PCI memory space - the only catch is
531  * that it is only 16-bits wide but must be accessed as 32-bit.  The
532  * 16 high bits will be zero.  We don't hide this, since they get
533  * programmed mostly like discrete registers anyway
534  */
535 #define SRAM_START (0x20000)
536 #define SRAM_BYTES (0x20000)	/* Again, half don't really exist */
537 
538 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
539 {
540 	return lanai->base + SRAM_START + offset;
541 }
542 
543 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
544 {
545 	return readl(sram_addr(lanai, offset));
546 }
547 
548 static inline void sram_write(const struct lanai_dev *lanai,
549 	u32 val, int offset)
550 {
551 	writel(val, sram_addr(lanai, offset));
552 }
553 
554 static int __devinit sram_test_word(const struct lanai_dev *lanai,
555 				    int offset, u32 pattern)
556 {
557 	u32 readback;
558 	sram_write(lanai, pattern, offset);
559 	readback = sram_read(lanai, offset);
560 	if (likely(readback == pattern))
561 		return 0;
562 	printk(KERN_ERR DEV_LABEL
563 	    "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
564 	    lanai->number, offset,
565 	    (unsigned int) pattern, (unsigned int) readback);
566 	return -EIO;
567 }
568 
569 static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
570 {
571 	int offset, result = 0;
572 	for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
573 		result = sram_test_word(lanai, offset, pattern);
574 	return result;
575 }
576 
577 static int __devinit sram_test_and_clear(const struct lanai_dev *lanai)
578 {
579 #ifdef FULL_MEMORY_TEST
580 	int result;
581 	DPRINTK("testing SRAM\n");
582 	if ((result = sram_test_pass(lanai, 0x5555)) != 0)
583 		return result;
584 	if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
585 		return result;
586 #endif
587 	DPRINTK("clearing SRAM\n");
588 	return sram_test_pass(lanai, 0x0000);
589 }
590 
591 /* -------------------- CARD-BASED VCC TABLE UTILITIES: */
592 
593 /* vcc table */
594 enum lanai_vcc_offset {
595 	vcc_rxaddr1		= 0x00,	/* Location1, plus bits: */
596 #define   RXADDR1_SET_SIZE(x) ((x)*0x0000100)	/* size of RX buffer */
597 #define   RXADDR1_SET_RMMODE(x) ((x)*0x00800)	/* RM cell action; values: */
598 #define     RMMODE_TRASH	  (0)		/*   discard */
599 #define     RMMODE_PRESERVE	  (1)		/*   input as AAL0 */
600 #define     RMMODE_PIPE		  (2)		/*   pipe to coscheduler */
601 #define     RMMODE_PIPEALL	  (3)		/*   pipe non-RM too */
602 #define   RXADDR1_OAM_PRESERVE	 (0x00002000)	/* Input OAM cells as AAL0 */
603 #define   RXADDR1_SET_MODE(x) ((x)*0x0004000)	/* Reassembly mode */
604 #define     RXMODE_TRASH	  (0)		/*   discard */
605 #define     RXMODE_AAL0		  (1)		/*   non-AAL5 mode */
606 #define     RXMODE_AAL5		  (2)		/*   AAL5, intr. each PDU */
607 #define     RXMODE_AAL5_STREAM	  (3)		/*   AAL5 w/o per-PDU intr */
608 	vcc_rxaddr2		= 0x04,	/* Location2 */
609 	vcc_rxcrc1		= 0x08,	/* RX CRC claculation space */
610 	vcc_rxcrc2		= 0x0C,
611 	vcc_rxwriteptr		= 0x10, /* RX writeptr, plus bits: */
612 #define   RXWRITEPTR_LASTEFCI	 (0x00002000)	/* Last PDU had EFCI bit */
613 #define   RXWRITEPTR_DROPPING	 (0x00004000)	/* Had error, dropping */
614 #define   RXWRITEPTR_TRASHING	 (0x00008000)	/* Trashing */
615 	vcc_rxbufstart		= 0x14,	/* RX bufstart, plus bits: */
616 #define   RXBUFSTART_CLP	 (0x00004000)
617 #define   RXBUFSTART_CI		 (0x00008000)
618 	vcc_rxreadptr		= 0x18,	/* RX readptr */
619 	vcc_txicg		= 0x1C, /* TX ICG */
620 	vcc_txaddr1		= 0x20,	/* Location1, plus bits: */
621 #define   TXADDR1_SET_SIZE(x) ((x)*0x0000100)	/* size of TX buffer */
622 #define   TXADDR1_ABR		 (0x00008000)	/* use ABR (doesn't work) */
623 	vcc_txaddr2		= 0x24,	/* Location2 */
624 	vcc_txcrc1		= 0x28,	/* TX CRC claculation space */
625 	vcc_txcrc2		= 0x2C,
626 	vcc_txreadptr		= 0x30, /* TX Readptr, plus bits: */
627 #define   TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
628 #define   TXREADPTR_MASK_DELTA	(0x0000E000)	/* ? */
629 	vcc_txendptr		= 0x34, /* TX Endptr, plus bits: */
630 #define   TXENDPTR_CLP		(0x00002000)
631 #define   TXENDPTR_MASK_PDUMODE	(0x0000C000)	/* PDU mode; values: */
632 #define     PDUMODE_AAL0	 (0*0x04000)
633 #define     PDUMODE_AAL5	 (2*0x04000)
634 #define     PDUMODE_AAL5STREAM	 (3*0x04000)
635 	vcc_txwriteptr		= 0x38,	/* TX Writeptr */
636 #define   TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
637 	vcc_txcbr_next		= 0x3C	/* # of next CBR VCI in ring */
638 #define   TXCBR_NEXT_BOZO	(0x00008000)	/* "bozo bit" */
639 };
640 
641 #define CARDVCC_SIZE	(0x40)
642 
643 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
644 	vci_t vci)
645 {
646 	return sram_addr(lanai, vci * CARDVCC_SIZE);
647 }
648 
649 static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
650 	enum lanai_vcc_offset offset)
651 {
652 	u32 val;
653 	APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
654 	val= readl(lvcc->vbase + offset);
655 	RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
656 	    lvcc->vci, (int) offset, val);
657 	return val;
658 }
659 
660 static inline void cardvcc_write(const struct lanai_vcc *lvcc,
661 	u32 val, enum lanai_vcc_offset offset)
662 {
663 	APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
664 	APRINTK((val & ~0xFFFF) == 0,
665 	    "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
666 	    (unsigned int) val, lvcc->vci, (unsigned int) offset);
667 	RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
668 	    lvcc->vci, (unsigned int) offset, (unsigned int) val);
669 	writel(val, lvcc->vbase + offset);
670 }
671 
672 /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
673 
674 /* How many bytes will an AAL5 PDU take to transmit - remember that:
675  *   o  we need to add 8 bytes for length, CPI, UU, and CRC
676  *   o  we need to round up to 48 bytes for cells
677  */
678 static inline int aal5_size(int size)
679 {
680 	int cells = (size + 8 + 47) / 48;
681 	return cells * 48;
682 }
683 
684 /* How many bytes can we send if we have "space" space, assuming we have
685  * to send full cells
686  */
687 static inline int aal5_spacefor(int space)
688 {
689 	int cells = space / 48;
690 	return cells * 48;
691 }
692 
693 /* -------------------- FREE AN ATM SKB: */
694 
695 static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
696 {
697 	if (atmvcc->pop != NULL)
698 		atmvcc->pop(atmvcc, skb);
699 	else
700 		dev_kfree_skb_any(skb);
701 }
702 
703 /* -------------------- TURN VCCS ON AND OFF: */
704 
705 static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
706 {
707 	u32 addr1;
708 	if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
709 		dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
710 		cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
711 		cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
712 		cardvcc_write(lvcc, 0, vcc_rxwriteptr);
713 		cardvcc_write(lvcc, 0, vcc_rxbufstart);
714 		cardvcc_write(lvcc, 0, vcc_rxreadptr);
715 		cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
716 		addr1 = ((dmaaddr >> 8) & 0xFF) |
717 		    RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
718 		    RXADDR1_SET_RMMODE(RMMODE_TRASH) |	/* ??? */
719 		 /* RXADDR1_OAM_PRESERVE |	--- no OAM support yet */
720 		    RXADDR1_SET_MODE(RXMODE_AAL5);
721 	} else
722 		addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
723 		    RXADDR1_OAM_PRESERVE |		      /* ??? */
724 		    RXADDR1_SET_MODE(RXMODE_AAL0);
725 	/* This one must be last! */
726 	cardvcc_write(lvcc, addr1, vcc_rxaddr1);
727 }
728 
729 static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
730 {
731 	dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
732 	cardvcc_write(lvcc, 0, vcc_txicg);
733 	cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
734 	cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
735 	cardvcc_write(lvcc, 0, vcc_txreadptr);
736 	cardvcc_write(lvcc, 0, vcc_txendptr);
737 	cardvcc_write(lvcc, 0, vcc_txwriteptr);
738 	cardvcc_write(lvcc,
739 		(lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
740 		TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
741 	cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
742 	cardvcc_write(lvcc,
743 	    ((dmaaddr >> 8) & 0xFF) |
744 	    TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
745 	    vcc_txaddr1);
746 }
747 
748 /* Shutdown receiving on card */
749 static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
750 {
751 	if (lvcc->vbase == NULL)	/* We were never bound to a VCI */
752 		return;
753 	/* 15.1.1 - set to trashing, wait one cell time (15us) */
754 	cardvcc_write(lvcc,
755 	    RXADDR1_SET_RMMODE(RMMODE_TRASH) |
756 	    RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
757 	udelay(15);
758 	/* 15.1.2 - clear rest of entries */
759 	cardvcc_write(lvcc, 0, vcc_rxaddr2);
760 	cardvcc_write(lvcc, 0, vcc_rxcrc1);
761 	cardvcc_write(lvcc, 0, vcc_rxcrc2);
762 	cardvcc_write(lvcc, 0, vcc_rxwriteptr);
763 	cardvcc_write(lvcc, 0, vcc_rxbufstart);
764 	cardvcc_write(lvcc, 0, vcc_rxreadptr);
765 }
766 
767 /* Shutdown transmitting on card.
768  * Unfortunately the lanai needs us to wait until all the data
769  * drains out of the buffer before we can dealloc it, so this
770  * can take awhile -- up to 370ms for a full 128KB buffer
771  * assuming everone else is quiet.  In theory the time is
772  * boundless if there's a CBR VCC holding things up.
773  */
774 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
775 	struct lanai_vcc *lvcc)
776 {
777 	struct sk_buff *skb;
778 	unsigned long flags, timeout;
779 	int read, write, lastread = -1;
780 	APRINTK(!in_interrupt(),
781 	    "lanai_shutdown_tx_vci called w/o process context!\n");
782 	if (lvcc->vbase == NULL)	/* We were never bound to a VCI */
783 		return;
784 	/* 15.2.1 - wait for queue to drain */
785 	while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
786 		lanai_free_skb(lvcc->tx.atmvcc, skb);
787 	read_lock_irqsave(&vcc_sklist_lock, flags);
788 	__clear_bit(lvcc->vci, lanai->backlog_vccs);
789 	read_unlock_irqrestore(&vcc_sklist_lock, flags);
790 	/*
791 	 * We need to wait for the VCC to drain but don't wait forever.  We
792 	 * give each 1K of buffer size 1/128th of a second to clear out.
793 	 * TODO: maybe disable CBR if we're about to timeout?
794 	 */
795 	timeout = jiffies +
796 	    (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
797 	write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
798 	for (;;) {
799 		read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
800 		if (read == write &&	   /* Is TX buffer empty? */
801 		    (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
802 		    (cardvcc_read(lvcc, vcc_txcbr_next) &
803 		    TXCBR_NEXT_BOZO) == 0))
804 			break;
805 		if (read != lastread) {	   /* Has there been any progress? */
806 			lastread = read;
807 			timeout += HZ / 10;
808 		}
809 		if (unlikely(time_after(jiffies, timeout))) {
810 			printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
811 			    "backlog closing vci %d\n",
812 			    lvcc->tx.atmvcc->dev->number, lvcc->vci);
813 			DPRINTK("read, write = %d, %d\n", read, write);
814 			break;
815 		}
816 		msleep(40);
817 	}
818 	/* 15.2.2 - clear out all tx registers */
819 	cardvcc_write(lvcc, 0, vcc_txreadptr);
820 	cardvcc_write(lvcc, 0, vcc_txwriteptr);
821 	cardvcc_write(lvcc, 0, vcc_txendptr);
822 	cardvcc_write(lvcc, 0, vcc_txcrc1);
823 	cardvcc_write(lvcc, 0, vcc_txcrc2);
824 	cardvcc_write(lvcc, 0, vcc_txaddr2);
825 	cardvcc_write(lvcc, 0, vcc_txaddr1);
826 }
827 
828 /* -------------------- MANAGING AAL0 RX BUFFER: */
829 
830 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
831 {
832 	DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
833 	lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
834 			   lanai->pci);
835 	return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
836 }
837 
838 static inline void aal0_buffer_free(struct lanai_dev *lanai)
839 {
840 	DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
841 	lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
842 }
843 
844 /* -------------------- EEPROM UTILITIES: */
845 
846 /* Offsets of data in the EEPROM */
847 #define EEPROM_COPYRIGHT	(0)
848 #define EEPROM_COPYRIGHT_LEN	(44)
849 #define EEPROM_CHECKSUM		(62)
850 #define EEPROM_CHECKSUM_REV	(63)
851 #define EEPROM_MAC		(64)
852 #define EEPROM_MAC_REV		(70)
853 #define EEPROM_SERIAL		(112)
854 #define EEPROM_SERIAL_REV	(116)
855 #define EEPROM_MAGIC		(120)
856 #define EEPROM_MAGIC_REV	(124)
857 
858 #define EEPROM_MAGIC_VALUE	(0x5AB478D2)
859 
860 #ifndef READ_EEPROM
861 
862 /* Stub functions to use if EEPROM reading is disabled */
863 static int __devinit eeprom_read(struct lanai_dev *lanai)
864 {
865 	printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
866 	    lanai->number);
867 	memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
868 	return 0;
869 }
870 
871 static int __devinit eeprom_validate(struct lanai_dev *lanai)
872 {
873 	lanai->serialno = 0;
874 	lanai->magicno = EEPROM_MAGIC_VALUE;
875 	return 0;
876 }
877 
878 #else /* READ_EEPROM */
879 
880 static int __devinit eeprom_read(struct lanai_dev *lanai)
881 {
882 	int i, address;
883 	u8 data;
884 	u32 tmp;
885 #define set_config1(x)   do { lanai->conf1 = x; conf1_write(lanai); \
886 			    } while (0)
887 #define clock_h()	 set_config1(lanai->conf1 | CONFIG1_PROMCLK)
888 #define clock_l()	 set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
889 #define data_h()	 set_config1(lanai->conf1 | CONFIG1_PROMDATA)
890 #define data_l()	 set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
891 #define pre_read()	 do { data_h(); clock_h(); udelay(5); } while (0)
892 #define read_pin()	 (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
893 #define send_stop()	 do { data_l(); udelay(5); clock_h(); udelay(5); \
894 			      data_h(); udelay(5); } while (0)
895 	/* start with both clock and data high */
896 	data_h(); clock_h(); udelay(5);
897 	for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
898 		data = (address << 1) | 1;	/* Command=read + address */
899 		/* send start bit */
900 		data_l(); udelay(5);
901 		clock_l(); udelay(5);
902 		for (i = 128; i != 0; i >>= 1) {   /* write command out */
903 			tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
904 			    ((data & i) ? CONFIG1_PROMDATA : 0);
905 			if (lanai->conf1 != tmp) {
906 				set_config1(tmp);
907 				udelay(5);	/* Let new data settle */
908 			}
909 			clock_h(); udelay(5); clock_l(); udelay(5);
910 		}
911 		/* look for ack */
912 		data_h(); clock_h(); udelay(5);
913 		if (read_pin() != 0)
914 			goto error;	/* No ack seen */
915 		clock_l(); udelay(5);
916 		/* read back result */
917 		for (data = 0, i = 7; i >= 0; i--) {
918 			data_h(); clock_h(); udelay(5);
919 			data = (data << 1) | !!read_pin();
920 			clock_l(); udelay(5);
921 		}
922 		/* look again for ack */
923 		data_h(); clock_h(); udelay(5);
924 		if (read_pin() == 0)
925 			goto error;	/* Spurious ack */
926 		clock_l(); udelay(5);
927 		send_stop();
928 		lanai->eeprom[address] = data;
929 		DPRINTK("EEPROM 0x%04X %02X\n",
930 		    (unsigned int) address, (unsigned int) data);
931 	}
932 	return 0;
933     error:
934 	clock_l(); udelay(5);		/* finish read */
935 	send_stop();
936 	printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
937 	    lanai->number, address);
938 	return -EIO;
939 #undef set_config1
940 #undef clock_h
941 #undef clock_l
942 #undef data_h
943 #undef data_l
944 #undef pre_read
945 #undef read_pin
946 #undef send_stop
947 }
948 
949 /* read a big-endian 4-byte value out of eeprom */
950 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
951 {
952 	return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
953 }
954 
955 /* Checksum/validate EEPROM contents */
956 static int __devinit eeprom_validate(struct lanai_dev *lanai)
957 {
958 	int i, s;
959 	u32 v;
960 	const u8 *e = lanai->eeprom;
961 #ifdef DEBUG
962 	/* First, see if we can get an ASCIIZ string out of the copyright */
963 	for (i = EEPROM_COPYRIGHT;
964 	    i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
965 		if (e[i] < 0x20 || e[i] > 0x7E)
966 			break;
967 	if ( i != EEPROM_COPYRIGHT &&
968 	    i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
969 		DPRINTK("eeprom: copyright = \"%s\"\n",
970 		    (char *) &e[EEPROM_COPYRIGHT]);
971 	else
972 		DPRINTK("eeprom: copyright not found\n");
973 #endif
974 	/* Validate checksum */
975 	for (i = s = 0; i < EEPROM_CHECKSUM; i++)
976 		s += e[i];
977 	s &= 0xFF;
978 	if (s != e[EEPROM_CHECKSUM]) {
979 		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
980 		    "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
981 		    (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
982 		return -EIO;
983 	}
984 	s ^= 0xFF;
985 	if (s != e[EEPROM_CHECKSUM_REV]) {
986 		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
987 		    "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
988 		    (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
989 		return -EIO;
990 	}
991 	/* Verify MAC address */
992 	for (i = 0; i < 6; i++)
993 		if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
994 			printk(KERN_ERR DEV_LABEL
995 			    "(itf %d) : EEPROM MAC addresses don't match "
996 			    "(0x%02X, inverse 0x%02X)\n", lanai->number,
997 			    (unsigned int) e[EEPROM_MAC + i],
998 			    (unsigned int) e[EEPROM_MAC_REV + i]);
999 			return -EIO;
1000 		}
1001 	DPRINTK("eeprom: MAC address = %02X:%02X:%02X:%02X:%02X:%02X\n",
1002 		e[EEPROM_MAC + 0], e[EEPROM_MAC + 1], e[EEPROM_MAC + 2],
1003 		e[EEPROM_MAC + 3], e[EEPROM_MAC + 4], e[EEPROM_MAC + 5]);
1004 	/* Verify serial number */
1005 	lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
1006 	v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
1007 	if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
1008 		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
1009 		    "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1010 		    (unsigned int) lanai->serialno, (unsigned int) v);
1011 		return -EIO;
1012 	}
1013 	DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1014 	/* Verify magic number */
1015 	lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1016 	v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1017 	if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1018 		printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
1019 		    "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1020 		    lanai->magicno, v);
1021 		return -EIO;
1022 	}
1023 	DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1024 	if (lanai->magicno != EEPROM_MAGIC_VALUE)
1025 		printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
1026 		    "magic not what expected (got 0x%08X, not 0x%08X)\n",
1027 		    lanai->number, (unsigned int) lanai->magicno,
1028 		    (unsigned int) EEPROM_MAGIC_VALUE);
1029 	return 0;
1030 }
1031 
1032 #endif /* READ_EEPROM */
1033 
1034 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1035 {
1036 	return &lanai->eeprom[EEPROM_MAC];
1037 }
1038 
1039 /* -------------------- INTERRUPT HANDLING UTILITIES: */
1040 
1041 /* Interrupt types */
1042 #define INT_STATS	(0x00000002)	/* Statistics counter overflow */
1043 #define INT_SOOL	(0x00000004)	/* SOOL changed state */
1044 #define INT_LOCD	(0x00000008)	/* LOCD changed state */
1045 #define INT_LED		(0x00000010)	/* LED (HAPPI) changed state */
1046 #define INT_GPIN	(0x00000020)	/* GPIN changed state */
1047 #define INT_PING	(0x00000040)	/* PING_COUNT fulfilled */
1048 #define INT_WAKE	(0x00000080)	/* Lanai wants bus */
1049 #define INT_CBR0	(0x00000100)	/* CBR sched hit VCI 0 */
1050 #define INT_LOCK	(0x00000200)	/* Service list overflow */
1051 #define INT_MISMATCH	(0x00000400)	/* TX magic list mismatch */
1052 #define INT_AAL0_STR	(0x00000800)	/* Non-AAL5 buffer half filled */
1053 #define INT_AAL0	(0x00001000)	/* Non-AAL5 data available */
1054 #define INT_SERVICE	(0x00002000)	/* Service list entries available */
1055 #define INT_TABORTSENT	(0x00004000)	/* Target abort sent by lanai */
1056 #define INT_TABORTBM	(0x00008000)	/* Abort rcv'd as bus master */
1057 #define INT_TIMEOUTBM	(0x00010000)	/* No response to bus master */
1058 #define INT_PCIPARITY	(0x00020000)	/* Parity error on PCI */
1059 
1060 /* Sets of the above */
1061 #define INT_ALL		(0x0003FFFE)	/* All interrupts */
1062 #define INT_STATUS	(0x0000003C)	/* Some status pin changed */
1063 #define INT_DMASHUT	(0x00038000)	/* DMA engine got shut down */
1064 #define INT_SEGSHUT	(0x00000700)	/* Segmentation got shut down */
1065 
1066 static inline u32 intr_pending(const struct lanai_dev *lanai)
1067 {
1068 	return reg_read(lanai, IntStatusMasked_Reg);
1069 }
1070 
1071 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1072 {
1073 	reg_write(lanai, i, IntControlEna_Reg);
1074 }
1075 
1076 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1077 {
1078 	reg_write(lanai, i, IntControlDis_Reg);
1079 }
1080 
1081 /* -------------------- CARD/PCI STATUS: */
1082 
1083 static void status_message(int itf, const char *name, int status)
1084 {
1085 	static const char *onoff[2] = { "off to on", "on to off" };
1086 	printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
1087 	    itf, name, onoff[!status]);
1088 }
1089 
1090 static void lanai_check_status(struct lanai_dev *lanai)
1091 {
1092 	u32 new = reg_read(lanai, Status_Reg);
1093 	u32 changes = new ^ lanai->status;
1094 	lanai->status = new;
1095 #define e(flag, name) \
1096 		if (changes & flag) \
1097 			status_message(lanai->number, name, new & flag)
1098 	e(STATUS_SOOL, "SOOL");
1099 	e(STATUS_LOCD, "LOCD");
1100 	e(STATUS_LED, "LED");
1101 	e(STATUS_GPIN, "GPIN");
1102 #undef e
1103 }
1104 
1105 static void pcistatus_got(int itf, const char *name)
1106 {
1107 	printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
1108 }
1109 
1110 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1111 {
1112 	u16 s;
1113 	int result;
1114 	result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1115 	if (result != PCIBIOS_SUCCESSFUL) {
1116 		printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
1117 		    "%d\n", lanai->number, result);
1118 		return;
1119 	}
1120 	s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
1121 	    PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
1122 	    PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
1123 	if (s == 0)
1124 		return;
1125 	result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1126 	if (result != PCIBIOS_SUCCESSFUL)
1127 		printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
1128 		    "%d\n", lanai->number, result);
1129 	if (clearonly)
1130 		return;
1131 #define e(flag, name, stat) \
1132 		if (s & flag) { \
1133 			pcistatus_got(lanai->number, name); \
1134 			++lanai->stats.pcierr_##stat; \
1135 		}
1136 	e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
1137 	e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
1138 	e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
1139 	e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
1140 	e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
1141 	e(PCI_STATUS_PARITY, "master parity", master_parity);
1142 #undef e
1143 }
1144 
1145 /* -------------------- VCC TX BUFFER UTILITIES: */
1146 
1147 /* space left in tx buffer in bytes */
1148 static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
1149 {
1150 	int r;
1151 	r = endptr * 16;
1152 	r -= ((unsigned long) lvcc->tx.buf.ptr) -
1153 	    ((unsigned long) lvcc->tx.buf.start);
1154 	r -= 16;	/* Leave "bubble" - if start==end it looks empty */
1155 	if (r < 0)
1156 		r += lanai_buf_size(&lvcc->tx.buf);
1157 	return r;
1158 }
1159 
1160 /* test if VCC is currently backlogged */
1161 static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
1162 {
1163 	return !skb_queue_empty(&lvcc->tx.backlog);
1164 }
1165 
1166 /* Bit fields in the segmentation buffer descriptor */
1167 #define DESCRIPTOR_MAGIC	(0xD0000000)
1168 #define DESCRIPTOR_AAL5		(0x00008000)
1169 #define DESCRIPTOR_AAL5_STREAM	(0x00004000)
1170 #define DESCRIPTOR_CLP		(0x00002000)
1171 
1172 /* Add 32-bit descriptor with its padding */
1173 static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
1174 	u32 flags, int len)
1175 {
1176 	int pos;
1177 	APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
1178 	    "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
1179 	lvcc->tx.buf.ptr += 4;	/* Hope the values REALLY don't matter */
1180 	pos = ((unsigned char *) lvcc->tx.buf.ptr) -
1181 	    (unsigned char *) lvcc->tx.buf.start;
1182 	APRINTK((pos & ~0x0001FFF0) == 0,
1183 	    "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
1184 	    "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1185 	    lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1186 	pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
1187 	APRINTK((pos & ~0x0001FFF0) == 0,
1188 	    "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
1189 	    "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1190 	    lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1191 	lvcc->tx.buf.ptr[-1] =
1192 	    cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
1193 	    ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
1194 	    DESCRIPTOR_CLP : 0) | flags | pos >> 4);
1195 	if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1196 		lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1197 }
1198 
1199 /* Add 32-bit AAL5 trailer and leave room for its CRC */
1200 static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
1201 	int len, int cpi, int uu)
1202 {
1203 	APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
1204 	    "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
1205 	lvcc->tx.buf.ptr += 2;
1206 	lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
1207 	if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1208 		lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1209 }
1210 
1211 static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
1212 	const unsigned char *src, int n)
1213 {
1214 	unsigned char *e;
1215 	int m;
1216 	e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1217 	m = e - (unsigned char *) lvcc->tx.buf.end;
1218 	if (m < 0)
1219 		m = 0;
1220 	memcpy(lvcc->tx.buf.ptr, src, n - m);
1221 	if (m != 0) {
1222 		memcpy(lvcc->tx.buf.start, src + n - m, m);
1223 		e = ((unsigned char *) lvcc->tx.buf.start) + m;
1224 	}
1225 	lvcc->tx.buf.ptr = (u32 *) e;
1226 }
1227 
1228 static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
1229 {
1230 	unsigned char *e;
1231 	int m;
1232 	if (n == 0)
1233 		return;
1234 	e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1235 	m = e - (unsigned char *) lvcc->tx.buf.end;
1236 	if (m < 0)
1237 		m = 0;
1238 	memset(lvcc->tx.buf.ptr, 0, n - m);
1239 	if (m != 0) {
1240 		memset(lvcc->tx.buf.start, 0, m);
1241 		e = ((unsigned char *) lvcc->tx.buf.start) + m;
1242 	}
1243 	lvcc->tx.buf.ptr = (u32 *) e;
1244 }
1245 
1246 /* Update "butt" register to specify new WritePtr */
1247 static inline void lanai_endtx(struct lanai_dev *lanai,
1248 	const struct lanai_vcc *lvcc)
1249 {
1250 	int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
1251 	    (unsigned char *) lvcc->tx.buf.start;
1252 	APRINTK((ptr & ~0x0001FFF0) == 0,
1253 	    "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
1254 	    ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
1255 	    lvcc->tx.buf.end);
1256 
1257 	/*
1258 	 * Since the "butt register" is a shared resounce on the card we
1259 	 * serialize all accesses to it through this spinlock.  This is
1260 	 * mostly just paranoia sicne the register is rarely "busy" anyway
1261 	 * but is needed for correctness.
1262 	 */
1263 	spin_lock(&lanai->endtxlock);
1264 	/*
1265 	 * We need to check if the "butt busy" bit is set before
1266 	 * updating the butt register.  In theory this should
1267 	 * never happen because the ATM card is plenty fast at
1268 	 * updating the register.  Still, we should make sure
1269 	 */
1270 	for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1271 		if (unlikely(i > 50)) {
1272 			printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
1273 			    "always busy!\n", lanai->number);
1274 			break;
1275 		}
1276 		udelay(5);
1277 	}
1278 	/*
1279 	 * Before we tall the card to start work we need to be sure 100% of
1280 	 * the info in the service buffer has been written before we tell
1281 	 * the card about it
1282 	 */
1283 	wmb();
1284 	reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1285 	spin_unlock(&lanai->endtxlock);
1286 }
1287 
1288 /*
1289  * Add one AAL5 PDU to lvcc's transmit buffer.  Caller garauntees there's
1290  * space available.  "pdusize" is the number of bytes the PDU will take
1291  */
1292 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1293 	struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
1294 {
1295 	int pad;
1296 	APRINTK(pdusize == aal5_size(skb->len),
1297 	    "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
1298 	    pdusize, aal5_size(skb->len));
1299 	vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
1300 	pad = pdusize - skb->len - 8;
1301 	APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
1302 	APRINTK(pad < 48, "pad is too big (%d)\n", pad);
1303 	vcc_tx_memcpy(lvcc, skb->data, skb->len);
1304 	vcc_tx_memzero(lvcc, pad);
1305 	vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
1306 	lanai_endtx(lanai, lvcc);
1307 	lanai_free_skb(lvcc->tx.atmvcc, skb);
1308 	atomic_inc(&lvcc->tx.atmvcc->stats->tx);
1309 }
1310 
1311 /* Try to fill the buffer - don't call unless there is backlog */
1312 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1313 	struct lanai_vcc *lvcc, int endptr)
1314 {
1315 	int n;
1316 	struct sk_buff *skb;
1317 	int space = vcc_tx_space(lvcc, endptr);
1318 	APRINTK(vcc_is_backlogged(lvcc),
1319 	    "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
1320 	    lvcc->vci);
1321 	while (space >= 64) {
1322 		skb = skb_dequeue(&lvcc->tx.backlog);
1323 		if (skb == NULL)
1324 			goto no_backlog;
1325 		n = aal5_size(skb->len);
1326 		if (n + 16 > space) {
1327 			/* No room for this packet - put it back on queue */
1328 			skb_queue_head(&lvcc->tx.backlog, skb);
1329 			return;
1330 		}
1331 		lanai_send_one_aal5(lanai, lvcc, skb, n);
1332 		space -= n + 16;
1333 	}
1334 	if (!vcc_is_backlogged(lvcc)) {
1335 	    no_backlog:
1336 		__clear_bit(lvcc->vci, lanai->backlog_vccs);
1337 	}
1338 }
1339 
1340 /* Given an skb that we want to transmit either send it now or queue */
1341 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1342 	struct sk_buff *skb)
1343 {
1344 	int space, n;
1345 	if (vcc_is_backlogged(lvcc))		/* Already backlogged */
1346 		goto queue_it;
1347 	space = vcc_tx_space(lvcc,
1348 		    TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
1349 	n = aal5_size(skb->len);
1350 	APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
1351 	if (space < n + 16) {			/* No space for this PDU */
1352 		__set_bit(lvcc->vci, lanai->backlog_vccs);
1353 	    queue_it:
1354 		skb_queue_tail(&lvcc->tx.backlog, skb);
1355 		return;
1356 	}
1357 	lanai_send_one_aal5(lanai, lvcc, skb, n);
1358 }
1359 
1360 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1361 	struct lanai_vcc *lvcc, int endptr)
1362 {
1363 	printk(KERN_INFO DEV_LABEL
1364 	    ": vcc_tx_unqueue_aal0: not implemented\n");
1365 }
1366 
1367 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1368 	struct sk_buff *skb)
1369 {
1370 	printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
1371 	/* Remember to increment lvcc->tx.atmvcc->stats->tx */
1372 	lanai_free_skb(lvcc->tx.atmvcc, skb);
1373 }
1374 
1375 /* -------------------- VCC RX BUFFER UTILITIES: */
1376 
1377 /* unlike the _tx_ cousins, this doesn't update ptr */
1378 static inline void vcc_rx_memcpy(unsigned char *dest,
1379 	const struct lanai_vcc *lvcc, int n)
1380 {
1381 	int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
1382 	    ((const unsigned char *) (lvcc->rx.buf.end));
1383 	if (m < 0)
1384 		m = 0;
1385 	memcpy(dest, lvcc->rx.buf.ptr, n - m);
1386 	memcpy(dest + n - m, lvcc->rx.buf.start, m);
1387 	/* Make sure that these copies don't get reordered */
1388 	barrier();
1389 }
1390 
1391 /* Receive AAL5 data on a VCC with a particular endptr */
1392 static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
1393 {
1394 	int size;
1395 	struct sk_buff *skb;
1396 	const u32 *x;
1397 	u32 *end = &lvcc->rx.buf.start[endptr * 4];
1398 	int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
1399 	if (n < 0)
1400 		n += lanai_buf_size(&lvcc->rx.buf);
1401 	APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
1402 	    "vcc_rx_aal5: n out of range (%d/%Zu)\n",
1403 	    n, lanai_buf_size(&lvcc->rx.buf));
1404 	/* Recover the second-to-last word to get true pdu length */
1405 	if ((x = &end[-2]) < lvcc->rx.buf.start)
1406 		x = &lvcc->rx.buf.end[-2];
1407 	/*
1408 	 * Before we actually read from the buffer, make sure the memory
1409 	 * changes have arrived
1410 	 */
1411 	rmb();
1412 	size = be32_to_cpup(x) & 0xffff;
1413 	if (unlikely(n != aal5_size(size))) {
1414 		/* Make sure size matches padding */
1415 		printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
1416 		    "on vci=%d - size=%d n=%d\n",
1417 		    lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
1418 		lvcc->stats.x.aal5.rx_badlen++;
1419 		goto out;
1420 	}
1421 	skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
1422 	if (unlikely(skb == NULL)) {
1423 		lvcc->stats.rx_nomem++;
1424 		goto out;
1425 	}
1426 	skb_put(skb, size);
1427 	vcc_rx_memcpy(skb->data, lvcc, size);
1428 	ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
1429 	__net_timestamp(skb);
1430 	lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
1431 	atomic_inc(&lvcc->rx.atmvcc->stats->rx);
1432     out:
1433 	lvcc->rx.buf.ptr = end;
1434 	cardvcc_write(lvcc, endptr, vcc_rxreadptr);
1435 }
1436 
1437 static void vcc_rx_aal0(struct lanai_dev *lanai)
1438 {
1439 	printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
1440 	/* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
1441 	/* Remember to increment lvcc->rx.atmvcc->stats->rx */
1442 }
1443 
1444 /* -------------------- MANAGING HOST-BASED VCC TABLE: */
1445 
1446 /* Decide whether to use vmalloc or get_zeroed_page for VCC table */
1447 #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
1448 #define VCCTABLE_GETFREEPAGE
1449 #else
1450 #include <linux/vmalloc.h>
1451 #endif
1452 
1453 static int __devinit vcc_table_allocate(struct lanai_dev *lanai)
1454 {
1455 #ifdef VCCTABLE_GETFREEPAGE
1456 	APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1457 	    "vcc table > PAGE_SIZE!");
1458 	lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1459 	return (lanai->vccs == NULL) ? -ENOMEM : 0;
1460 #else
1461 	int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1462 	lanai->vccs = (struct lanai_vcc **) vmalloc(bytes);
1463 	if (unlikely(lanai->vccs == NULL))
1464 		return -ENOMEM;
1465 	memset(lanai->vccs, 0, bytes);
1466 	return 0;
1467 #endif
1468 }
1469 
1470 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1471 {
1472 #ifdef VCCTABLE_GETFREEPAGE
1473 	free_page((unsigned long) lanai->vccs);
1474 #else
1475 	vfree(lanai->vccs);
1476 #endif
1477 }
1478 
1479 /* Allocate a fresh lanai_vcc, with the appropriate things cleared */
1480 static inline struct lanai_vcc *new_lanai_vcc(void)
1481 {
1482 	struct lanai_vcc *lvcc;
1483 	lvcc =  kzalloc(sizeof(*lvcc), GFP_KERNEL);
1484 	if (likely(lvcc != NULL)) {
1485 		skb_queue_head_init(&lvcc->tx.backlog);
1486 #ifdef DEBUG
1487 		lvcc->vci = -1;
1488 #endif
1489 	}
1490 	return lvcc;
1491 }
1492 
1493 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1494 	struct lanai_buffer *buf, int max_sdu, int multiplier,
1495 	const char *name)
1496 {
1497 	int size;
1498 	if (unlikely(max_sdu < 1))
1499 		max_sdu = 1;
1500 	max_sdu = aal5_size(max_sdu);
1501 	size = (max_sdu + 16) * multiplier + 16;
1502 	lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1503 	if (unlikely(buf->start == NULL))
1504 		return -ENOMEM;
1505 	if (unlikely(lanai_buf_size(buf) < size))
1506 		printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
1507 		    "for %s buffer, got only %Zu\n", lanai->number, size,
1508 		    name, lanai_buf_size(buf));
1509 	DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name);
1510 	return 0;
1511 }
1512 
1513 /* Setup a RX buffer for a currently unbound AAL5 vci */
1514 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1515 	struct lanai_vcc *lvcc, const struct atm_qos *qos)
1516 {
1517 	return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1518 	    qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
1519 }
1520 
1521 /* Setup a TX buffer for a currently unbound AAL5 vci */
1522 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1523 	const struct atm_qos *qos)
1524 {
1525 	int max_sdu, multiplier;
1526 	if (qos->aal == ATM_AAL0) {
1527 		lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
1528 		max_sdu = ATM_CELL_SIZE - 1;
1529 		multiplier = AAL0_TX_MULTIPLIER;
1530 	} else {
1531 		lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
1532 		max_sdu = qos->txtp.max_sdu;
1533 		multiplier = AAL5_TX_MULTIPLIER;
1534 	}
1535 	return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1536 	    multiplier, "TX");
1537 }
1538 
1539 static inline void host_vcc_bind(struct lanai_dev *lanai,
1540 	struct lanai_vcc *lvcc, vci_t vci)
1541 {
1542 	if (lvcc->vbase != NULL)
1543 		return;    /* We already were bound in the other direction */
1544 	DPRINTK("Binding vci %d\n", vci);
1545 #ifdef USE_POWERDOWN
1546 	if (lanai->nbound++ == 0) {
1547 		DPRINTK("Coming out of powerdown\n");
1548 		lanai->conf1 &= ~CONFIG1_POWERDOWN;
1549 		conf1_write(lanai);
1550 		conf2_write(lanai);
1551 	}
1552 #endif
1553 	lvcc->vbase = cardvcc_addr(lanai, vci);
1554 	lanai->vccs[lvcc->vci = vci] = lvcc;
1555 }
1556 
1557 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1558 	struct lanai_vcc *lvcc)
1559 {
1560 	if (lvcc->vbase == NULL)
1561 		return;	/* This vcc was never bound */
1562 	DPRINTK("Unbinding vci %d\n", lvcc->vci);
1563 	lvcc->vbase = NULL;
1564 	lanai->vccs[lvcc->vci] = NULL;
1565 #ifdef USE_POWERDOWN
1566 	if (--lanai->nbound == 0) {
1567 		DPRINTK("Going into powerdown\n");
1568 		lanai->conf1 |= CONFIG1_POWERDOWN;
1569 		conf1_write(lanai);
1570 	}
1571 #endif
1572 }
1573 
1574 /* -------------------- RESET CARD: */
1575 
1576 static void lanai_reset(struct lanai_dev *lanai)
1577 {
1578 	printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not "
1579 	    "implemented\n", lanai->number);
1580 	/* TODO */
1581 	/* The following is just a hack until we write the real
1582 	 * resetter - at least ack whatever interrupt sent us
1583 	 * here
1584 	 */
1585 	reg_write(lanai, INT_ALL, IntAck_Reg);
1586 	lanai->stats.card_reset++;
1587 }
1588 
1589 /* -------------------- SERVICE LIST UTILITIES: */
1590 
1591 /*
1592  * Allocate service buffer and tell card about it
1593  */
1594 static int __devinit service_buffer_allocate(struct lanai_dev *lanai)
1595 {
1596 	lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1597 	    lanai->pci);
1598 	if (unlikely(lanai->service.start == NULL))
1599 		return -ENOMEM;
1600 	DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n",
1601 	    (unsigned long) lanai->service.start,
1602 	    lanai_buf_size(&lanai->service),
1603 	    lanai_buf_size_cardorder(&lanai->service));
1604 	/* Clear ServWrite register to be safe */
1605 	reg_write(lanai, 0, ServWrite_Reg);
1606 	/* ServiceStuff register contains size and address of buffer */
1607 	reg_write(lanai,
1608 	    SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1609 	    SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1610 	    ServiceStuff_Reg);
1611 	return 0;
1612 }
1613 
1614 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1615 {
1616 	lanai_buf_deallocate(&lanai->service, lanai->pci);
1617 }
1618 
1619 /* Bitfields in service list */
1620 #define SERVICE_TX	(0x80000000)	/* Was from transmission */
1621 #define SERVICE_TRASH	(0x40000000)	/* RXed PDU was trashed */
1622 #define SERVICE_CRCERR	(0x20000000)	/* RXed PDU had CRC error */
1623 #define SERVICE_CI	(0x10000000)	/* RXed PDU had CI set */
1624 #define SERVICE_CLP	(0x08000000)	/* RXed PDU had CLP set */
1625 #define SERVICE_STREAM	(0x04000000)	/* RX Stream mode */
1626 #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
1627 #define SERVICE_GET_END(x) ((x)&0x1FFF)
1628 
1629 /* Handle one thing from the service list - returns true if it marked a
1630  * VCC ready for xmit
1631  */
1632 static int handle_service(struct lanai_dev *lanai, u32 s)
1633 {
1634 	vci_t vci = SERVICE_GET_VCI(s);
1635 	struct lanai_vcc *lvcc;
1636 	read_lock(&vcc_sklist_lock);
1637 	lvcc = lanai->vccs[vci];
1638 	if (unlikely(lvcc == NULL)) {
1639 		read_unlock(&vcc_sklist_lock);
1640 		DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
1641 		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1642 		if (s & SERVICE_TX)
1643 			lanai->stats.service_notx++;
1644 		else
1645 			lanai->stats.service_norx++;
1646 		return 0;
1647 	}
1648 	if (s & SERVICE_TX) {			/* segmentation interrupt */
1649 		if (unlikely(lvcc->tx.atmvcc == NULL)) {
1650 			read_unlock(&vcc_sklist_lock);
1651 			DPRINTK("(itf %d) got service entry 0x%X for non-TX "
1652 			    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1653 			lanai->stats.service_notx++;
1654 			return 0;
1655 		}
1656 		__set_bit(vci, lanai->transmit_ready);
1657 		lvcc->tx.endptr = SERVICE_GET_END(s);
1658 		read_unlock(&vcc_sklist_lock);
1659 		return 1;
1660 	}
1661 	if (unlikely(lvcc->rx.atmvcc == NULL)) {
1662 		read_unlock(&vcc_sklist_lock);
1663 		DPRINTK("(itf %d) got service entry 0x%X for non-RX "
1664 		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1665 		lanai->stats.service_norx++;
1666 		return 0;
1667 	}
1668 	if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
1669 		read_unlock(&vcc_sklist_lock);
1670 		DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
1671 		    "vcc %d\n", lanai->number, (unsigned int) s, vci);
1672 		lanai->stats.service_rxnotaal5++;
1673 		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1674 		return 0;
1675 	}
1676 	if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
1677 		vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
1678 		read_unlock(&vcc_sklist_lock);
1679 		return 0;
1680 	}
1681 	if (s & SERVICE_TRASH) {
1682 		int bytes;
1683 		read_unlock(&vcc_sklist_lock);
1684 		DPRINTK("got trashed rx pdu on vci %d\n", vci);
1685 		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1686 		lvcc->stats.x.aal5.service_trash++;
1687 		bytes = (SERVICE_GET_END(s) * 16) -
1688 		    (((unsigned long) lvcc->rx.buf.ptr) -
1689 		    ((unsigned long) lvcc->rx.buf.start)) + 47;
1690 		if (bytes < 0)
1691 			bytes += lanai_buf_size(&lvcc->rx.buf);
1692 		lanai->stats.ovfl_trash += (bytes / 48);
1693 		return 0;
1694 	}
1695 	if (s & SERVICE_STREAM) {
1696 		read_unlock(&vcc_sklist_lock);
1697 		atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1698 		lvcc->stats.x.aal5.service_stream++;
1699 		printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
1700 		    "PDU on VCI %d!\n", lanai->number, vci);
1701 		lanai_reset(lanai);
1702 		return 0;
1703 	}
1704 	DPRINTK("got rx crc error on vci %d\n", vci);
1705 	atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1706 	lvcc->stats.x.aal5.service_rxcrc++;
1707 	lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
1708 	cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
1709 	read_unlock(&vcc_sklist_lock);
1710 	return 0;
1711 }
1712 
1713 /* Try transmitting on all VCIs that we marked ready to serve */
1714 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1715 {
1716 	struct lanai_vcc *lvcc = lanai->vccs[vci];
1717 	if (vcc_is_backlogged(lvcc))
1718 		lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1719 }
1720 
1721 /* Run service queue -- called from interrupt context or with
1722  * interrupts otherwise disabled and with the lanai->servicelock
1723  * lock held
1724  */
1725 static void run_service(struct lanai_dev *lanai)
1726 {
1727 	int ntx = 0;
1728 	u32 wreg = reg_read(lanai, ServWrite_Reg);
1729 	const u32 *end = lanai->service.start + wreg;
1730 	while (lanai->service.ptr != end) {
1731 		ntx += handle_service(lanai,
1732 		    le32_to_cpup(lanai->service.ptr++));
1733 		if (lanai->service.ptr >= lanai->service.end)
1734 			lanai->service.ptr = lanai->service.start;
1735 	}
1736 	reg_write(lanai, wreg, ServRead_Reg);
1737 	if (ntx != 0) {
1738 		read_lock(&vcc_sklist_lock);
1739 		vci_bitfield_iterate(lanai, lanai->transmit_ready,
1740 		    iter_transmit);
1741 		bitmap_zero(lanai->transmit_ready, NUM_VCI);
1742 		read_unlock(&vcc_sklist_lock);
1743 	}
1744 }
1745 
1746 /* -------------------- GATHER STATISTICS: */
1747 
1748 static void get_statistics(struct lanai_dev *lanai)
1749 {
1750 	u32 statreg = reg_read(lanai, Statistics_Reg);
1751 	lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1752 	lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1753 	lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1754 	lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1755 }
1756 
1757 /* -------------------- POLLING TIMER: */
1758 
1759 #ifndef DEBUG_RW
1760 /* Try to undequeue 1 backlogged vcc */
1761 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1762 {
1763 	struct lanai_vcc *lvcc = lanai->vccs[vci];
1764 	int endptr;
1765 	if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
1766 	    !vcc_is_backlogged(lvcc)) {
1767 		__clear_bit(vci, lanai->backlog_vccs);
1768 		return;
1769 	}
1770 	endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
1771 	lvcc->tx.unqueue(lanai, lvcc, endptr);
1772 }
1773 #endif /* !DEBUG_RW */
1774 
1775 static void lanai_timed_poll(unsigned long arg)
1776 {
1777 	struct lanai_dev *lanai = (struct lanai_dev *) arg;
1778 #ifndef DEBUG_RW
1779 	unsigned long flags;
1780 #ifdef USE_POWERDOWN
1781 	if (lanai->conf1 & CONFIG1_POWERDOWN)
1782 		return;
1783 #endif /* USE_POWERDOWN */
1784 	local_irq_save(flags);
1785 	/* If we can grab the spinlock, check if any services need to be run */
1786 	if (spin_trylock(&lanai->servicelock)) {
1787 		run_service(lanai);
1788 		spin_unlock(&lanai->servicelock);
1789 	}
1790 	/* ...and see if any backlogged VCs can make progress */
1791 	/* unfortunately linux has no read_trylock() currently */
1792 	read_lock(&vcc_sklist_lock);
1793 	vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1794 	read_unlock(&vcc_sklist_lock);
1795 	local_irq_restore(flags);
1796 
1797 	get_statistics(lanai);
1798 #endif /* !DEBUG_RW */
1799 	mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1800 }
1801 
1802 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1803 {
1804 	init_timer(&lanai->timer);
1805 	lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1806 	lanai->timer.data = (unsigned long) lanai;
1807 	lanai->timer.function = lanai_timed_poll;
1808 	add_timer(&lanai->timer);
1809 }
1810 
1811 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1812 {
1813 	del_timer_sync(&lanai->timer);
1814 }
1815 
1816 /* -------------------- INTERRUPT SERVICE: */
1817 
1818 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1819 {
1820 	u32 ack = 0;
1821 	if (reason & INT_SERVICE) {
1822 		ack = INT_SERVICE;
1823 		spin_lock(&lanai->servicelock);
1824 		run_service(lanai);
1825 		spin_unlock(&lanai->servicelock);
1826 	}
1827 	if (reason & (INT_AAL0_STR | INT_AAL0)) {
1828 		ack |= reason & (INT_AAL0_STR | INT_AAL0);
1829 		vcc_rx_aal0(lanai);
1830 	}
1831 	/* The rest of the interrupts are pretty rare */
1832 	if (ack == reason)
1833 		goto done;
1834 	if (reason & INT_STATS) {
1835 		reason &= ~INT_STATS;	/* No need to ack */
1836 		get_statistics(lanai);
1837 	}
1838 	if (reason & INT_STATUS) {
1839 		ack |= reason & INT_STATUS;
1840 		lanai_check_status(lanai);
1841 	}
1842 	if (unlikely(reason & INT_DMASHUT)) {
1843 		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
1844 		    "shutdown, reason=0x%08X, address=0x%08X\n",
1845 		    lanai->number, (unsigned int) (reason & INT_DMASHUT),
1846 		    (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1847 		if (reason & INT_TABORTBM) {
1848 			lanai_reset(lanai);
1849 			return;
1850 		}
1851 		ack |= (reason & INT_DMASHUT);
1852 		printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
1853 		    lanai->number);
1854 		conf1_write(lanai);
1855 		lanai->stats.dma_reenable++;
1856 		pcistatus_check(lanai, 0);
1857 	}
1858 	if (unlikely(reason & INT_TABORTSENT)) {
1859 		ack |= (reason & INT_TABORTSENT);
1860 		printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
1861 		    lanai->number);
1862 		pcistatus_check(lanai, 0);
1863 	}
1864 	if (unlikely(reason & INT_SEGSHUT)) {
1865 		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1866 		    "segmentation shutdown, reason=0x%08X\n", lanai->number,
1867 		    (unsigned int) (reason & INT_SEGSHUT));
1868 		lanai_reset(lanai);
1869 		return;
1870 	}
1871 	if (unlikely(reason & (INT_PING | INT_WAKE))) {
1872 		printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1873 		    "unexpected interrupt 0x%08X, resetting\n",
1874 		    lanai->number,
1875 		    (unsigned int) (reason & (INT_PING | INT_WAKE)));
1876 		lanai_reset(lanai);
1877 		return;
1878 	}
1879 #ifdef DEBUG
1880 	if (unlikely(ack != reason)) {
1881 		DPRINTK("unacked ints: 0x%08X\n",
1882 		    (unsigned int) (reason & ~ack));
1883 		ack = reason;
1884 	}
1885 #endif
1886    done:
1887 	if (ack != 0)
1888 		reg_write(lanai, ack, IntAck_Reg);
1889 }
1890 
1891 static irqreturn_t lanai_int(int irq, void *devid)
1892 {
1893 	struct lanai_dev *lanai = devid;
1894 	u32 reason;
1895 
1896 #ifdef USE_POWERDOWN
1897 	/*
1898 	 * If we're powered down we shouldn't be generating any interrupts -
1899 	 * so assume that this is a shared interrupt line and it's for someone
1900 	 * else
1901 	 */
1902 	if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1903 		return IRQ_NONE;
1904 #endif
1905 
1906 	reason = intr_pending(lanai);
1907 	if (reason == 0)
1908 		return IRQ_NONE;	/* Must be for someone else */
1909 
1910 	do {
1911 		if (unlikely(reason == 0xFFFFFFFF))
1912 			break;		/* Maybe we've been unplugged? */
1913 		lanai_int_1(lanai, reason);
1914 		reason = intr_pending(lanai);
1915 	} while (reason != 0);
1916 
1917 	return IRQ_HANDLED;
1918 }
1919 
1920 /* TODO - it would be nice if we could use the "delayed interrupt" system
1921  *   to some advantage
1922  */
1923 
1924 /* -------------------- CHECK BOARD ID/REV: */
1925 
1926 /*
1927  * The board id and revision are stored both in the reset register and
1928  * in the PCI configuration space - the documentation says to check
1929  * each of them.  If revp!=NULL we store the revision there
1930  */
1931 static int check_board_id_and_rev(const char *name, u32 val, int *revp)
1932 {
1933 	DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
1934 		(int) RESET_GET_BOARD_ID(val),
1935 		(int) RESET_GET_BOARD_REV(val));
1936 	if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
1937 		printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
1938 		    "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
1939 		return -ENODEV;
1940 	}
1941 	if (revp != NULL)
1942 		*revp = RESET_GET_BOARD_REV(val);
1943 	return 0;
1944 }
1945 
1946 /* -------------------- PCI INITIALIZATION/SHUTDOWN: */
1947 
1948 static int __devinit lanai_pci_start(struct lanai_dev *lanai)
1949 {
1950 	struct pci_dev *pci = lanai->pci;
1951 	int result;
1952 	u16 w;
1953 
1954 	if (pci_enable_device(pci) != 0) {
1955 		printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
1956 		    "PCI device", lanai->number);
1957 		return -ENXIO;
1958 	}
1959 	pci_set_master(pci);
1960 	if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1961 		printk(KERN_WARNING DEV_LABEL
1962 		    "(itf %d): No suitable DMA available.\n", lanai->number);
1963 		return -EBUSY;
1964 	}
1965 	if (pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1966 		printk(KERN_WARNING DEV_LABEL
1967 		    "(itf %d): No suitable DMA available.\n", lanai->number);
1968 		return -EBUSY;
1969 	}
1970 	result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
1971 	if (result != PCIBIOS_SUCCESSFUL) {
1972 		printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
1973 		    "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result);
1974 		return -EINVAL;
1975 	}
1976 	result = check_board_id_and_rev("PCI", w, NULL);
1977 	if (result != 0)
1978 		return result;
1979 	/* Set latency timer to zero as per lanai docs */
1980 	result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
1981 	if (result != PCIBIOS_SUCCESSFUL) {
1982 		printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
1983 		    "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1984 		return -EINVAL;
1985 	}
1986 	pcistatus_check(lanai, 1);
1987 	pcistatus_check(lanai, 0);
1988 	return 0;
1989 }
1990 
1991 /* -------------------- VPI/VCI ALLOCATION: */
1992 
1993 /*
1994  * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
1995  * get a CBRZERO interrupt), and we can use it only if noone is receiving
1996  * AAL0 traffic (since they will use the same queue) - according to the
1997  * docs we shouldn't even use it for AAL0 traffic
1998  */
1999 static inline int vci0_is_ok(struct lanai_dev *lanai,
2000 	const struct atm_qos *qos)
2001 {
2002 	if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
2003 		return 0;
2004 	if (qos->rxtp.traffic_class != ATM_NONE) {
2005 		if (lanai->naal0 != 0)
2006 			return 0;
2007 		lanai->conf2 |= CONFIG2_VCI0_NORMAL;
2008 		conf2_write_if_powerup(lanai);
2009 	}
2010 	return 1;
2011 }
2012 
2013 /* return true if vci is currently unused, or if requested qos is
2014  * compatible
2015  */
2016 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
2017 	const struct atm_vcc *atmvcc)
2018 {
2019 	const struct atm_qos *qos = &atmvcc->qos;
2020 	const struct lanai_vcc *lvcc = lanai->vccs[vci];
2021 	if (vci == 0 && !vci0_is_ok(lanai, qos))
2022 		return 0;
2023 	if (unlikely(lvcc != NULL)) {
2024 		if (qos->rxtp.traffic_class != ATM_NONE &&
2025 		    lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
2026 			return 0;
2027 		if (qos->txtp.traffic_class != ATM_NONE &&
2028 		    lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
2029 			return 0;
2030 		if (qos->txtp.traffic_class == ATM_CBR &&
2031 		    lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2032 			return 0;
2033 	}
2034 	if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2035 	    qos->rxtp.traffic_class != ATM_NONE) {
2036 		const struct lanai_vcc *vci0 = lanai->vccs[0];
2037 		if (vci0 != NULL && vci0->rx.atmvcc != NULL)
2038 			return 0;
2039 		lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2040 		conf2_write_if_powerup(lanai);
2041 	}
2042 	return 1;
2043 }
2044 
2045 static int lanai_normalize_ci(struct lanai_dev *lanai,
2046 	const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
2047 {
2048 	switch (*vpip) {
2049 		case ATM_VPI_ANY:
2050 			*vpip = 0;
2051 			/* FALLTHROUGH */
2052 		case 0:
2053 			break;
2054 		default:
2055 			return -EADDRINUSE;
2056 	}
2057 	switch (*vcip) {
2058 		case ATM_VCI_ANY:
2059 			for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2060 			    (*vcip)++)
2061 				if (vci_is_ok(lanai, *vcip, atmvcc))
2062 					return 0;
2063 			return -EADDRINUSE;
2064 		default:
2065 			if (*vcip >= lanai->num_vci || *vcip < 0 ||
2066 			    !vci_is_ok(lanai, *vcip, atmvcc))
2067 				return -EADDRINUSE;
2068 	}
2069 	return 0;
2070 }
2071 
2072 /* -------------------- MANAGE CBR: */
2073 
2074 /*
2075  * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2076  * Note that storing a number greater than 2046.0 will result in
2077  * incorrect shaping
2078  */
2079 #define CBRICG_FRAC_BITS	(4)
2080 #define CBRICG_MAX		(2046 << CBRICG_FRAC_BITS)
2081 
2082 /*
2083  * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
2084  * where MAXPCR is (according to the docs) 25600000/(54*8),
2085  * which is equal to (3125<<9)/27.
2086  *
2087  * Solving for ICG, we get:
2088  *    ICG = MAXPCR/PCR - 1
2089  *    ICG = (3125<<9)/(27*PCR) - 1
2090  *    ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
2091  *
2092  * The end result is supposed to be a fixed-point number with FRAC_BITS
2093  * bits of a fractional part, so we keep everything in the numerator
2094  * shifted by that much as we compute
2095  *
2096  */
2097 static int pcr_to_cbricg(const struct atm_qos *qos)
2098 {
2099 	int rounddown = 0;	/* 1 = Round PCR down, i.e. round ICG _up_ */
2100 	int x, icg, pcr = atm_pcr_goal(&qos->txtp);
2101 	if (pcr == 0)		/* Use maximum bandwidth */
2102 		return 0;
2103 	if (pcr < 0) {
2104 		rounddown = 1;
2105 		pcr = -pcr;
2106 	}
2107 	x = pcr * 27;
2108 	icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
2109 	if (rounddown)
2110 		icg += x - 1;
2111 	icg /= x;
2112 	if (icg > CBRICG_MAX)
2113 		icg = CBRICG_MAX;
2114 	DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
2115 	    pcr, rounddown ? 'Y' : 'N', icg);
2116 	return icg;
2117 }
2118 
2119 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2120 {
2121 	reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2122 	reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2123 	lanai->conf2 |= CONFIG2_CBR_ENABLE;
2124 	conf2_write(lanai);
2125 }
2126 
2127 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2128 {
2129 	lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2130 	conf2_write(lanai);
2131 }
2132 
2133 /* -------------------- OPERATIONS: */
2134 
2135 /* setup a newly detected device */
2136 static int __devinit lanai_dev_open(struct atm_dev *atmdev)
2137 {
2138 	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2139 	unsigned long raw_base;
2140 	int result;
2141 
2142 	DPRINTK("In lanai_dev_open()\n");
2143 	/* Basic device fields */
2144 	lanai->number = atmdev->number;
2145 	lanai->num_vci = NUM_VCI;
2146 	bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2147 	bitmap_zero(lanai->transmit_ready, NUM_VCI);
2148 	lanai->naal0 = 0;
2149 #ifdef USE_POWERDOWN
2150 	lanai->nbound = 0;
2151 #endif
2152 	lanai->cbrvcc = NULL;
2153 	memset(&lanai->stats, 0, sizeof lanai->stats);
2154 	spin_lock_init(&lanai->endtxlock);
2155 	spin_lock_init(&lanai->servicelock);
2156 	atmdev->ci_range.vpi_bits = 0;
2157 	atmdev->ci_range.vci_bits = 0;
2158 	while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2159 		atmdev->ci_range.vci_bits++;
2160 	atmdev->link_rate = ATM_25_PCR;
2161 
2162 	/* 3.2: PCI initialization */
2163 	if ((result = lanai_pci_start(lanai)) != 0)
2164 		goto error;
2165 	raw_base = lanai->pci->resource[0].start;
2166 	lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2167 	if (lanai->base == NULL) {
2168 		printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
2169 		goto error_pci;
2170 	}
2171 	/* 3.3: Reset lanai and PHY */
2172 	reset_board(lanai);
2173 	lanai->conf1 = reg_read(lanai, Config1_Reg);
2174 	lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2175 	    CONFIG1_MASK_LEDMODE);
2176 	lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2177 	reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2178 	udelay(1000);
2179 	conf1_write(lanai);
2180 
2181 	/*
2182 	 * 3.4: Turn on endian mode for big-endian hardware
2183 	 *   We don't actually want to do this - the actual bit fields
2184 	 *   in the endian register are not documented anywhere.
2185 	 *   Instead we do the bit-flipping ourselves on big-endian
2186 	 *   hardware.
2187 	 *
2188 	 * 3.5: get the board ID/rev by reading the reset register
2189 	 */
2190 	result = check_board_id_and_rev("register",
2191 	    reg_read(lanai, Reset_Reg), &lanai->board_rev);
2192 	if (result != 0)
2193 		goto error_unmap;
2194 
2195 	/* 3.6: read EEPROM */
2196 	if ((result = eeprom_read(lanai)) != 0)
2197 		goto error_unmap;
2198 	if ((result = eeprom_validate(lanai)) != 0)
2199 		goto error_unmap;
2200 
2201 	/* 3.7: re-reset PHY, do loopback tests, setup PHY */
2202 	reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2203 	udelay(1000);
2204 	conf1_write(lanai);
2205 	/* TODO - loopback tests */
2206 	lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2207 	conf1_write(lanai);
2208 
2209 	/* 3.8/3.9: test and initialize card SRAM */
2210 	if ((result = sram_test_and_clear(lanai)) != 0)
2211 		goto error_unmap;
2212 
2213 	/* 3.10: initialize lanai registers */
2214 	lanai->conf1 |= CONFIG1_DMA_ENABLE;
2215 	conf1_write(lanai);
2216 	if ((result = service_buffer_allocate(lanai)) != 0)
2217 		goto error_unmap;
2218 	if ((result = vcc_table_allocate(lanai)) != 0)
2219 		goto error_service;
2220 	lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2221 	    CONFIG2_HEC_DROP |	/* ??? */ CONFIG2_PTI7_MODE;
2222 	conf2_write(lanai);
2223 	reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2224 	reg_write(lanai, 0, CBR_ICG_Reg);	/* CBR defaults to no limit */
2225 	if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2226 	    DEV_LABEL, lanai)) != 0) {
2227 		printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
2228 		goto error_vcctable;
2229 	}
2230 	mb();				/* Make sure that all that made it */
2231 	intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2232 	/* 3.11: initialize loop mode (i.e. turn looping off) */
2233 	lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2234 	    CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
2235 	    CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
2236 	conf1_write(lanai);
2237 	lanai->status = reg_read(lanai, Status_Reg);
2238 	/* We're now done initializing this card */
2239 #ifdef USE_POWERDOWN
2240 	lanai->conf1 |= CONFIG1_POWERDOWN;
2241 	conf1_write(lanai);
2242 #endif
2243 	memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2244 	lanai_timed_poll_start(lanai);
2245 	printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
2246 	    "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
2247 	    (int) lanai->pci->revision, (unsigned long) lanai->base,
2248 	    lanai->pci->irq,
2249 	    atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
2250 	    atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
2251 	printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
2252 	    "board_rev=%d\n", lanai->number,
2253 	    lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2254 	    (unsigned int) lanai->serialno, lanai->board_rev);
2255 	return 0;
2256 
2257     error_vcctable:
2258 	vcc_table_deallocate(lanai);
2259     error_service:
2260 	service_buffer_deallocate(lanai);
2261     error_unmap:
2262 	reset_board(lanai);
2263 #ifdef USE_POWERDOWN
2264 	lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2265 	conf1_write(lanai);
2266 #endif
2267 	iounmap(lanai->base);
2268     error_pci:
2269 	pci_disable_device(lanai->pci);
2270     error:
2271 	return result;
2272 }
2273 
2274 /* called when device is being shutdown, and all vcc's are gone - higher
2275  * levels will deallocate the atm device for us
2276  */
2277 static void lanai_dev_close(struct atm_dev *atmdev)
2278 {
2279 	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2280 	printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
2281 	    lanai->number);
2282 	lanai_timed_poll_stop(lanai);
2283 #ifdef USE_POWERDOWN
2284 	lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2285 	conf1_write(lanai);
2286 #endif
2287 	intr_disable(lanai, INT_ALL);
2288 	free_irq(lanai->pci->irq, lanai);
2289 	reset_board(lanai);
2290 #ifdef USE_POWERDOWN
2291 	lanai->conf1 |= CONFIG1_POWERDOWN;
2292 	conf1_write(lanai);
2293 #endif
2294 	pci_disable_device(lanai->pci);
2295 	vcc_table_deallocate(lanai);
2296 	service_buffer_deallocate(lanai);
2297 	iounmap(lanai->base);
2298 	kfree(lanai);
2299 }
2300 
2301 /* close a vcc */
2302 static void lanai_close(struct atm_vcc *atmvcc)
2303 {
2304 	struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2305 	struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2306 	if (lvcc == NULL)
2307 		return;
2308 	clear_bit(ATM_VF_READY, &atmvcc->flags);
2309 	clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
2310 	if (lvcc->rx.atmvcc == atmvcc) {
2311 		lanai_shutdown_rx_vci(lvcc);
2312 		if (atmvcc->qos.aal == ATM_AAL0) {
2313 			if (--lanai->naal0 <= 0)
2314 				aal0_buffer_free(lanai);
2315 		} else
2316 			lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2317 		lvcc->rx.atmvcc = NULL;
2318 	}
2319 	if (lvcc->tx.atmvcc == atmvcc) {
2320 		if (atmvcc == lanai->cbrvcc) {
2321 			if (lvcc->vbase != NULL)
2322 				lanai_cbr_shutdown(lanai);
2323 			lanai->cbrvcc = NULL;
2324 		}
2325 		lanai_shutdown_tx_vci(lanai, lvcc);
2326 		lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2327 		lvcc->tx.atmvcc = NULL;
2328 	}
2329 	if (--lvcc->nref == 0) {
2330 		host_vcc_unbind(lanai, lvcc);
2331 		kfree(lvcc);
2332 	}
2333 	atmvcc->dev_data = NULL;
2334 	clear_bit(ATM_VF_ADDR, &atmvcc->flags);
2335 }
2336 
2337 /* open a vcc on the card to vpi/vci */
2338 static int lanai_open(struct atm_vcc *atmvcc)
2339 {
2340 	struct lanai_dev *lanai;
2341 	struct lanai_vcc *lvcc;
2342 	int result = 0;
2343 	int vci = atmvcc->vci;
2344 	short vpi = atmvcc->vpi;
2345 	/* we don't support partial open - it's not really useful anyway */
2346 	if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
2347 	    (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
2348 		return -EINVAL;
2349 	lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2350 	result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2351 	if (unlikely(result != 0))
2352 		goto out;
2353 	set_bit(ATM_VF_ADDR, &atmvcc->flags);
2354 	if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
2355 		return -EINVAL;
2356 	DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2357 	    (int) vpi, vci);
2358 	lvcc = lanai->vccs[vci];
2359 	if (lvcc == NULL) {
2360 		lvcc = new_lanai_vcc();
2361 		if (unlikely(lvcc == NULL))
2362 			return -ENOMEM;
2363 		atmvcc->dev_data = lvcc;
2364 	}
2365 	lvcc->nref++;
2366 	if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
2367 		APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
2368 		    vci);
2369 		if (atmvcc->qos.aal == ATM_AAL0) {
2370 			if (lanai->naal0 == 0)
2371 				result = aal0_buffer_allocate(lanai);
2372 		} else
2373 			result = lanai_setup_rx_vci_aal5(
2374 			    lanai, lvcc, &atmvcc->qos);
2375 		if (unlikely(result != 0))
2376 			goto out_free;
2377 		lvcc->rx.atmvcc = atmvcc;
2378 		lvcc->stats.rx_nomem = 0;
2379 		lvcc->stats.x.aal5.rx_badlen = 0;
2380 		lvcc->stats.x.aal5.service_trash = 0;
2381 		lvcc->stats.x.aal5.service_stream = 0;
2382 		lvcc->stats.x.aal5.service_rxcrc = 0;
2383 		if (atmvcc->qos.aal == ATM_AAL0)
2384 			lanai->naal0++;
2385 	}
2386 	if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
2387 		APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
2388 		    vci);
2389 		result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2390 		if (unlikely(result != 0))
2391 			goto out_free;
2392 		lvcc->tx.atmvcc = atmvcc;
2393 		if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
2394 			APRINTK(lanai->cbrvcc == NULL,
2395 			    "cbrvcc!=NULL, vci=%d\n", vci);
2396 			lanai->cbrvcc = atmvcc;
2397 		}
2398 	}
2399 	host_vcc_bind(lanai, lvcc, vci);
2400 	/*
2401 	 * Make sure everything made it to RAM before we tell the card about
2402 	 * the VCC
2403 	 */
2404 	wmb();
2405 	if (atmvcc == lvcc->rx.atmvcc)
2406 		host_vcc_start_rx(lvcc);
2407 	if (atmvcc == lvcc->tx.atmvcc) {
2408 		host_vcc_start_tx(lvcc);
2409 		if (lanai->cbrvcc == atmvcc)
2410 			lanai_cbr_setup(lanai);
2411 	}
2412 	set_bit(ATM_VF_READY, &atmvcc->flags);
2413 	return 0;
2414     out_free:
2415 	lanai_close(atmvcc);
2416     out:
2417 	return result;
2418 }
2419 
2420 static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
2421 {
2422 	struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2423 	struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2424 	unsigned long flags;
2425 	if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
2426 	      lvcc->tx.atmvcc != atmvcc))
2427 		goto einval;
2428 #ifdef DEBUG
2429 	if (unlikely(skb == NULL)) {
2430 		DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
2431 		goto einval;
2432 	}
2433 	if (unlikely(lanai == NULL)) {
2434 		DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2435 		goto einval;
2436 	}
2437 #endif
2438 	ATM_SKB(skb)->vcc = atmvcc;
2439 	switch (atmvcc->qos.aal) {
2440 		case ATM_AAL5:
2441 			read_lock_irqsave(&vcc_sklist_lock, flags);
2442 			vcc_tx_aal5(lanai, lvcc, skb);
2443 			read_unlock_irqrestore(&vcc_sklist_lock, flags);
2444 			return 0;
2445 		case ATM_AAL0:
2446 			if (unlikely(skb->len != ATM_CELL_SIZE-1))
2447 				goto einval;
2448   /* NOTE - this next line is technically invalid - we haven't unshared skb */
2449 			cpu_to_be32s((u32 *) skb->data);
2450 			read_lock_irqsave(&vcc_sklist_lock, flags);
2451 			vcc_tx_aal0(lanai, lvcc, skb);
2452 			read_unlock_irqrestore(&vcc_sklist_lock, flags);
2453 			return 0;
2454 	}
2455 	DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
2456 	    atmvcc->vci);
2457     einval:
2458 	lanai_free_skb(atmvcc, skb);
2459 	return -EINVAL;
2460 }
2461 
2462 static int lanai_change_qos(struct atm_vcc *atmvcc,
2463 	/*const*/ struct atm_qos *qos, int flags)
2464 {
2465 	return -EBUSY;		/* TODO: need to write this */
2466 }
2467 
2468 #ifndef CONFIG_PROC_FS
2469 #define lanai_proc_read NULL
2470 #else
2471 static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
2472 {
2473 	struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2474 	loff_t left = *pos;
2475 	struct lanai_vcc *lvcc;
2476 	if (left-- == 0)
2477 		return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
2478 		    "serial=%u, magic=0x%08X, num_vci=%d\n",
2479 		    atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2480 		    (unsigned int) lanai->serialno,
2481 		    (unsigned int) lanai->magicno, lanai->num_vci);
2482 	if (left-- == 0)
2483 		return sprintf(page, "revision: board=%d, pci_if=%d\n",
2484 		    lanai->board_rev, (int) lanai->pci->revision);
2485 	if (left-- == 0)
2486 		return sprintf(page, "EEPROM ESI: "
2487 		    "%02X:%02X:%02X:%02X:%02X:%02X\n",
2488 		    lanai->eeprom[EEPROM_MAC + 0],
2489 		    lanai->eeprom[EEPROM_MAC + 1],
2490 		    lanai->eeprom[EEPROM_MAC + 2],
2491 		    lanai->eeprom[EEPROM_MAC + 3],
2492 		    lanai->eeprom[EEPROM_MAC + 4],
2493 		    lanai->eeprom[EEPROM_MAC + 5]);
2494 	if (left-- == 0)
2495 		return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
2496 		    "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2497 		    (lanai->status & STATUS_LOCD) ? 1 : 0,
2498 		    (lanai->status & STATUS_LED) ? 1 : 0,
2499 		    (lanai->status & STATUS_GPIN) ? 1 : 0);
2500 	if (left-- == 0)
2501 		return sprintf(page, "global buffer sizes: service=%Zu, "
2502 		    "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2503 		    lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2504 	if (left-- == 0) {
2505 		get_statistics(lanai);
2506 		return sprintf(page, "cells in error: overflow=%u, "
2507 		    "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
2508 		    lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2509 		    lanai->stats.hec_err, lanai->stats.atm_ovfl);
2510 	}
2511 	if (left-- == 0)
2512 		return sprintf(page, "PCI errors: parity_detect=%u, "
2513 		    "master_abort=%u, master_target_abort=%u,\n",
2514 		    lanai->stats.pcierr_parity_detect,
2515 		    lanai->stats.pcierr_serr_set,
2516 		    lanai->stats.pcierr_m_target_abort);
2517 	if (left-- == 0)
2518 		return sprintf(page, "            slave_target_abort=%u, "
2519 		    "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2520 		    lanai->stats.pcierr_master_parity);
2521 	if (left-- == 0)
2522 		return sprintf(page, "                     no_tx=%u, "
2523 		    "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2524 		    lanai->stats.service_notx,
2525 		    lanai->stats.service_rxnotaal5);
2526 	if (left-- == 0)
2527 		return sprintf(page, "resets: dma=%u, card=%u\n",
2528 		    lanai->stats.dma_reenable, lanai->stats.card_reset);
2529 	/* At this point, "left" should be the VCI we're looking for */
2530 	read_lock(&vcc_sklist_lock);
2531 	for (; ; left++) {
2532 		if (left >= NUM_VCI) {
2533 			left = 0;
2534 			goto out;
2535 		}
2536 		if ((lvcc = lanai->vccs[left]) != NULL)
2537 			break;
2538 		(*pos)++;
2539 	}
2540 	/* Note that we re-use "left" here since we're done with it */
2541 	left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u",  (vci_t) left,
2542 	    lvcc->nref, lvcc->stats.rx_nomem);
2543 	if (lvcc->rx.atmvcc != NULL) {
2544 		left += sprintf(&page[left], ",\n          rx_AAL=%d",
2545 		    lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
2546 		if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
2547 			left += sprintf(&page[left], ", rx_buf_size=%Zu, "
2548 			    "rx_bad_len=%u,\n          rx_service_trash=%u, "
2549 			    "rx_service_stream=%u, rx_bad_crc=%u",
2550 			    lanai_buf_size(&lvcc->rx.buf),
2551 			    lvcc->stats.x.aal5.rx_badlen,
2552 			    lvcc->stats.x.aal5.service_trash,
2553 			    lvcc->stats.x.aal5.service_stream,
2554 			    lvcc->stats.x.aal5.service_rxcrc);
2555 	}
2556 	if (lvcc->tx.atmvcc != NULL)
2557 		left += sprintf(&page[left], ",\n          tx_AAL=%d, "
2558 		    "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c",
2559 		    lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
2560 		    lanai_buf_size(&lvcc->tx.buf),
2561 		    lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2562 		    vcc_is_backlogged(lvcc) ? 'Y' : 'N');
2563 	page[left++] = '\n';
2564 	page[left] = '\0';
2565     out:
2566 	read_unlock(&vcc_sklist_lock);
2567 	return left;
2568 }
2569 #endif /* CONFIG_PROC_FS */
2570 
2571 /* -------------------- HOOKS: */
2572 
2573 static const struct atmdev_ops ops = {
2574 	.dev_close	= lanai_dev_close,
2575 	.open		= lanai_open,
2576 	.close		= lanai_close,
2577 	.getsockopt	= NULL,
2578 	.setsockopt	= NULL,
2579 	.send		= lanai_send,
2580 	.phy_put	= NULL,
2581 	.phy_get	= NULL,
2582 	.change_qos	= lanai_change_qos,
2583 	.proc_read	= lanai_proc_read,
2584 	.owner		= THIS_MODULE
2585 };
2586 
2587 /* initialize one probed card */
2588 static int __devinit lanai_init_one(struct pci_dev *pci,
2589 				    const struct pci_device_id *ident)
2590 {
2591 	struct lanai_dev *lanai;
2592 	struct atm_dev *atmdev;
2593 	int result;
2594 
2595 	lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
2596 	if (lanai == NULL) {
2597 		printk(KERN_ERR DEV_LABEL
2598 		       ": couldn't allocate dev_data structure!\n");
2599 		return -ENOMEM;
2600 	}
2601 
2602 	atmdev = atm_dev_register(DEV_LABEL, &ops, -1, NULL);
2603 	if (atmdev == NULL) {
2604 		printk(KERN_ERR DEV_LABEL
2605 		    ": couldn't register atm device!\n");
2606 		kfree(lanai);
2607 		return -EBUSY;
2608 	}
2609 
2610 	atmdev->dev_data = lanai;
2611 	lanai->pci = pci;
2612 	lanai->type = (enum lanai_type) ident->device;
2613 
2614 	result = lanai_dev_open(atmdev);
2615 	if (result != 0) {
2616 		DPRINTK("lanai_start() failed, err=%d\n", -result);
2617 		atm_dev_deregister(atmdev);
2618 		kfree(lanai);
2619 	}
2620 	return result;
2621 }
2622 
2623 static struct pci_device_id lanai_pci_tbl[] = {
2624 	{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
2625 	{ PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
2626 	{ 0, }	/* terminal entry */
2627 };
2628 MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
2629 
2630 static struct pci_driver lanai_driver = {
2631 	.name     = DEV_LABEL,
2632 	.id_table = lanai_pci_tbl,
2633 	.probe    = lanai_init_one,
2634 };
2635 
2636 static int __init lanai_module_init(void)
2637 {
2638 	int x;
2639 
2640 	x = pci_register_driver(&lanai_driver);
2641 	if (x != 0)
2642 		printk(KERN_ERR DEV_LABEL ": no adapter found\n");
2643 	return x;
2644 }
2645 
2646 static void __exit lanai_module_exit(void)
2647 {
2648 	/* We'll only get called when all the interfaces are already
2649 	 * gone, so there isn't much to do
2650 	 */
2651 	DPRINTK("cleanup_module()\n");
2652 	pci_unregister_driver(&lanai_driver);
2653 }
2654 
2655 module_init(lanai_module_init);
2656 module_exit(lanai_module_exit);
2657 
2658 MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
2659 MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
2660 MODULE_LICENSE("GPL");
2661