1 /******************************************************************* 2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $" 3 * 4 * $Author: ecd $ 5 * $Date: 2001/11/11 08:13:54 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32 static char const rcsid[] = 33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"; 34 35 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/poison.h> 39 #include <linux/skbuff.h> 40 #include <linux/kernel.h> 41 #include <linux/vmalloc.h> 42 #include <linux/netdevice.h> 43 #include <linux/atmdev.h> 44 #include <linux/atm.h> 45 #include <linux/delay.h> 46 #include <linux/init.h> 47 #include <linux/bitops.h> 48 #include <linux/wait.h> 49 #include <linux/jiffies.h> 50 #include <linux/mutex.h> 51 52 #include <asm/io.h> 53 #include <asm/uaccess.h> 54 #include <asm/atomic.h> 55 #include <asm/byteorder.h> 56 57 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 58 #include "suni.h" 59 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 60 61 62 #include "idt77252.h" 63 #include "idt77252_tables.h" 64 65 static unsigned int vpibits = 1; 66 67 68 #define ATM_IDT77252_SEND_IDLE 1 69 70 71 /* 72 * Debug HACKs. 73 */ 74 #define DEBUG_MODULE 1 75 #undef HAVE_EEPROM /* does not work, yet. */ 76 77 #ifdef CONFIG_ATM_IDT77252_DEBUG 78 static unsigned long debug = DBG_GENERAL; 79 #endif 80 81 82 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 83 84 85 /* 86 * SCQ Handling. 87 */ 88 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 89 static void free_scq(struct idt77252_dev *, struct scq_info *); 90 static int queue_skb(struct idt77252_dev *, struct vc_map *, 91 struct sk_buff *, int oam); 92 static void drain_scq(struct idt77252_dev *, struct vc_map *); 93 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 94 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 95 96 /* 97 * FBQ Handling. 98 */ 99 static int push_rx_skb(struct idt77252_dev *, 100 struct sk_buff *, int queue); 101 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 102 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 103 static void recycle_rx_pool_skb(struct idt77252_dev *, 104 struct rx_pool *); 105 static void add_rx_skb(struct idt77252_dev *, int queue, 106 unsigned int size, unsigned int count); 107 108 /* 109 * RSQ Handling. 110 */ 111 static int init_rsq(struct idt77252_dev *); 112 static void deinit_rsq(struct idt77252_dev *); 113 static void idt77252_rx(struct idt77252_dev *); 114 115 /* 116 * TSQ handling. 117 */ 118 static int init_tsq(struct idt77252_dev *); 119 static void deinit_tsq(struct idt77252_dev *); 120 static void idt77252_tx(struct idt77252_dev *); 121 122 123 /* 124 * ATM Interface. 125 */ 126 static void idt77252_dev_close(struct atm_dev *dev); 127 static int idt77252_open(struct atm_vcc *vcc); 128 static void idt77252_close(struct atm_vcc *vcc); 129 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 130 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 131 int flags); 132 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 133 unsigned long addr); 134 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 135 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 136 int flags); 137 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 138 char *page); 139 static void idt77252_softint(struct work_struct *work); 140 141 142 static struct atmdev_ops idt77252_ops = 143 { 144 .dev_close = idt77252_dev_close, 145 .open = idt77252_open, 146 .close = idt77252_close, 147 .send = idt77252_send, 148 .send_oam = idt77252_send_oam, 149 .phy_put = idt77252_phy_put, 150 .phy_get = idt77252_phy_get, 151 .change_qos = idt77252_change_qos, 152 .proc_read = idt77252_proc_read, 153 .owner = THIS_MODULE 154 }; 155 156 static struct idt77252_dev *idt77252_chain = NULL; 157 static unsigned int idt77252_sram_write_errors = 0; 158 159 /*****************************************************************************/ 160 /* */ 161 /* I/O and Utility Bus */ 162 /* */ 163 /*****************************************************************************/ 164 165 static void 166 waitfor_idle(struct idt77252_dev *card) 167 { 168 u32 stat; 169 170 stat = readl(SAR_REG_STAT); 171 while (stat & SAR_STAT_CMDBZ) 172 stat = readl(SAR_REG_STAT); 173 } 174 175 static u32 176 read_sram(struct idt77252_dev *card, unsigned long addr) 177 { 178 unsigned long flags; 179 u32 value; 180 181 spin_lock_irqsave(&card->cmd_lock, flags); 182 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 183 waitfor_idle(card); 184 value = readl(SAR_REG_DR0); 185 spin_unlock_irqrestore(&card->cmd_lock, flags); 186 return value; 187 } 188 189 static void 190 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 191 { 192 unsigned long flags; 193 194 if ((idt77252_sram_write_errors == 0) && 195 (((addr > card->tst[0] + card->tst_size - 2) && 196 (addr < card->tst[0] + card->tst_size)) || 197 ((addr > card->tst[1] + card->tst_size - 2) && 198 (addr < card->tst[1] + card->tst_size)))) { 199 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 200 card->name, addr, value); 201 } 202 203 spin_lock_irqsave(&card->cmd_lock, flags); 204 writel(value, SAR_REG_DR0); 205 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 206 waitfor_idle(card); 207 spin_unlock_irqrestore(&card->cmd_lock, flags); 208 } 209 210 static u8 211 read_utility(void *dev, unsigned long ubus_addr) 212 { 213 struct idt77252_dev *card = dev; 214 unsigned long flags; 215 u8 value; 216 217 if (!card) { 218 printk("Error: No such device.\n"); 219 return -1; 220 } 221 222 spin_lock_irqsave(&card->cmd_lock, flags); 223 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 224 waitfor_idle(card); 225 value = readl(SAR_REG_DR0); 226 spin_unlock_irqrestore(&card->cmd_lock, flags); 227 return value; 228 } 229 230 static void 231 write_utility(void *dev, unsigned long ubus_addr, u8 value) 232 { 233 struct idt77252_dev *card = dev; 234 unsigned long flags; 235 236 if (!card) { 237 printk("Error: No such device.\n"); 238 return; 239 } 240 241 spin_lock_irqsave(&card->cmd_lock, flags); 242 writel((u32) value, SAR_REG_DR0); 243 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 244 waitfor_idle(card); 245 spin_unlock_irqrestore(&card->cmd_lock, flags); 246 } 247 248 #ifdef HAVE_EEPROM 249 static u32 rdsrtab[] = 250 { 251 SAR_GP_EECS | SAR_GP_EESCLK, 252 0, 253 SAR_GP_EESCLK, /* 0 */ 254 0, 255 SAR_GP_EESCLK, /* 0 */ 256 0, 257 SAR_GP_EESCLK, /* 0 */ 258 0, 259 SAR_GP_EESCLK, /* 0 */ 260 0, 261 SAR_GP_EESCLK, /* 0 */ 262 SAR_GP_EEDO, 263 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 264 0, 265 SAR_GP_EESCLK, /* 0 */ 266 SAR_GP_EEDO, 267 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 268 }; 269 270 static u32 wrentab[] = 271 { 272 SAR_GP_EECS | SAR_GP_EESCLK, 273 0, 274 SAR_GP_EESCLK, /* 0 */ 275 0, 276 SAR_GP_EESCLK, /* 0 */ 277 0, 278 SAR_GP_EESCLK, /* 0 */ 279 0, 280 SAR_GP_EESCLK, /* 0 */ 281 SAR_GP_EEDO, 282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 283 SAR_GP_EEDO, 284 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 285 0, 286 SAR_GP_EESCLK, /* 0 */ 287 0, 288 SAR_GP_EESCLK /* 0 */ 289 }; 290 291 static u32 rdtab[] = 292 { 293 SAR_GP_EECS | SAR_GP_EESCLK, 294 0, 295 SAR_GP_EESCLK, /* 0 */ 296 0, 297 SAR_GP_EESCLK, /* 0 */ 298 0, 299 SAR_GP_EESCLK, /* 0 */ 300 0, 301 SAR_GP_EESCLK, /* 0 */ 302 0, 303 SAR_GP_EESCLK, /* 0 */ 304 0, 305 SAR_GP_EESCLK, /* 0 */ 306 SAR_GP_EEDO, 307 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 308 SAR_GP_EEDO, 309 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 310 }; 311 312 static u32 wrtab[] = 313 { 314 SAR_GP_EECS | SAR_GP_EESCLK, 315 0, 316 SAR_GP_EESCLK, /* 0 */ 317 0, 318 SAR_GP_EESCLK, /* 0 */ 319 0, 320 SAR_GP_EESCLK, /* 0 */ 321 0, 322 SAR_GP_EESCLK, /* 0 */ 323 0, 324 SAR_GP_EESCLK, /* 0 */ 325 0, 326 SAR_GP_EESCLK, /* 0 */ 327 SAR_GP_EEDO, 328 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 329 0, 330 SAR_GP_EESCLK /* 0 */ 331 }; 332 333 static u32 clktab[] = 334 { 335 0, 336 SAR_GP_EESCLK, 337 0, 338 SAR_GP_EESCLK, 339 0, 340 SAR_GP_EESCLK, 341 0, 342 SAR_GP_EESCLK, 343 0, 344 SAR_GP_EESCLK, 345 0, 346 SAR_GP_EESCLK, 347 0, 348 SAR_GP_EESCLK, 349 0, 350 SAR_GP_EESCLK, 351 0 352 }; 353 354 static u32 355 idt77252_read_gp(struct idt77252_dev *card) 356 { 357 u32 gp; 358 359 gp = readl(SAR_REG_GP); 360 #if 0 361 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 362 #endif 363 return gp; 364 } 365 366 static void 367 idt77252_write_gp(struct idt77252_dev *card, u32 value) 368 { 369 unsigned long flags; 370 371 #if 0 372 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 373 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 374 value & SAR_GP_EEDO ? "1" : "0"); 375 #endif 376 377 spin_lock_irqsave(&card->cmd_lock, flags); 378 waitfor_idle(card); 379 writel(value, SAR_REG_GP); 380 spin_unlock_irqrestore(&card->cmd_lock, flags); 381 } 382 383 static u8 384 idt77252_eeprom_read_status(struct idt77252_dev *card) 385 { 386 u8 byte; 387 u32 gp; 388 int i, j; 389 390 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 391 392 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 393 idt77252_write_gp(card, gp | rdsrtab[i]); 394 udelay(5); 395 } 396 idt77252_write_gp(card, gp | SAR_GP_EECS); 397 udelay(5); 398 399 byte = 0; 400 for (i = 0, j = 0; i < 8; i++) { 401 byte <<= 1; 402 403 idt77252_write_gp(card, gp | clktab[j++]); 404 udelay(5); 405 406 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 407 408 idt77252_write_gp(card, gp | clktab[j++]); 409 udelay(5); 410 } 411 idt77252_write_gp(card, gp | SAR_GP_EECS); 412 udelay(5); 413 414 return byte; 415 } 416 417 static u8 418 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 419 { 420 u8 byte; 421 u32 gp; 422 int i, j; 423 424 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 425 426 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 427 idt77252_write_gp(card, gp | rdtab[i]); 428 udelay(5); 429 } 430 idt77252_write_gp(card, gp | SAR_GP_EECS); 431 udelay(5); 432 433 for (i = 0, j = 0; i < 8; i++) { 434 idt77252_write_gp(card, gp | clktab[j++] | 435 (offset & 1 ? SAR_GP_EEDO : 0)); 436 udelay(5); 437 438 idt77252_write_gp(card, gp | clktab[j++] | 439 (offset & 1 ? SAR_GP_EEDO : 0)); 440 udelay(5); 441 442 offset >>= 1; 443 } 444 idt77252_write_gp(card, gp | SAR_GP_EECS); 445 udelay(5); 446 447 byte = 0; 448 for (i = 0, j = 0; i < 8; i++) { 449 byte <<= 1; 450 451 idt77252_write_gp(card, gp | clktab[j++]); 452 udelay(5); 453 454 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 455 456 idt77252_write_gp(card, gp | clktab[j++]); 457 udelay(5); 458 } 459 idt77252_write_gp(card, gp | SAR_GP_EECS); 460 udelay(5); 461 462 return byte; 463 } 464 465 static void 466 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 467 { 468 u32 gp; 469 int i, j; 470 471 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 472 473 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 474 idt77252_write_gp(card, gp | wrentab[i]); 475 udelay(5); 476 } 477 idt77252_write_gp(card, gp | SAR_GP_EECS); 478 udelay(5); 479 480 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 481 idt77252_write_gp(card, gp | wrtab[i]); 482 udelay(5); 483 } 484 idt77252_write_gp(card, gp | SAR_GP_EECS); 485 udelay(5); 486 487 for (i = 0, j = 0; i < 8; i++) { 488 idt77252_write_gp(card, gp | clktab[j++] | 489 (offset & 1 ? SAR_GP_EEDO : 0)); 490 udelay(5); 491 492 idt77252_write_gp(card, gp | clktab[j++] | 493 (offset & 1 ? SAR_GP_EEDO : 0)); 494 udelay(5); 495 496 offset >>= 1; 497 } 498 idt77252_write_gp(card, gp | SAR_GP_EECS); 499 udelay(5); 500 501 for (i = 0, j = 0; i < 8; i++) { 502 idt77252_write_gp(card, gp | clktab[j++] | 503 (data & 1 ? SAR_GP_EEDO : 0)); 504 udelay(5); 505 506 idt77252_write_gp(card, gp | clktab[j++] | 507 (data & 1 ? SAR_GP_EEDO : 0)); 508 udelay(5); 509 510 data >>= 1; 511 } 512 idt77252_write_gp(card, gp | SAR_GP_EECS); 513 udelay(5); 514 } 515 516 static void 517 idt77252_eeprom_init(struct idt77252_dev *card) 518 { 519 u32 gp; 520 521 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 522 523 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 524 udelay(5); 525 idt77252_write_gp(card, gp | SAR_GP_EECS); 526 udelay(5); 527 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 528 udelay(5); 529 idt77252_write_gp(card, gp | SAR_GP_EECS); 530 udelay(5); 531 } 532 #endif /* HAVE_EEPROM */ 533 534 535 #ifdef CONFIG_ATM_IDT77252_DEBUG 536 static void 537 dump_tct(struct idt77252_dev *card, int index) 538 { 539 unsigned long tct; 540 int i; 541 542 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 543 544 printk("%s: TCT %x:", card->name, index); 545 for (i = 0; i < 8; i++) { 546 printk(" %08x", read_sram(card, tct + i)); 547 } 548 printk("\n"); 549 } 550 551 static void 552 idt77252_tx_dump(struct idt77252_dev *card) 553 { 554 struct atm_vcc *vcc; 555 struct vc_map *vc; 556 int i; 557 558 printk("%s\n", __func__); 559 for (i = 0; i < card->tct_size; i++) { 560 vc = card->vcs[i]; 561 if (!vc) 562 continue; 563 564 vcc = NULL; 565 if (vc->rx_vcc) 566 vcc = vc->rx_vcc; 567 else if (vc->tx_vcc) 568 vcc = vc->tx_vcc; 569 570 if (!vcc) 571 continue; 572 573 printk("%s: Connection %d:\n", card->name, vc->index); 574 dump_tct(card, vc->index); 575 } 576 } 577 #endif 578 579 580 /*****************************************************************************/ 581 /* */ 582 /* SCQ Handling */ 583 /* */ 584 /*****************************************************************************/ 585 586 static int 587 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 588 { 589 struct sb_pool *pool = &card->sbpool[queue]; 590 int index; 591 592 index = pool->index; 593 while (pool->skb[index]) { 594 index = (index + 1) & FBQ_MASK; 595 if (index == pool->index) 596 return -ENOBUFS; 597 } 598 599 pool->skb[index] = skb; 600 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 601 602 pool->index = (index + 1) & FBQ_MASK; 603 return 0; 604 } 605 606 static void 607 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 608 { 609 unsigned int queue, index; 610 u32 handle; 611 612 handle = IDT77252_PRV_POOL(skb); 613 614 queue = POOL_QUEUE(handle); 615 if (queue > 3) 616 return; 617 618 index = POOL_INDEX(handle); 619 if (index > FBQ_SIZE - 1) 620 return; 621 622 card->sbpool[queue].skb[index] = NULL; 623 } 624 625 static struct sk_buff * 626 sb_pool_skb(struct idt77252_dev *card, u32 handle) 627 { 628 unsigned int queue, index; 629 630 queue = POOL_QUEUE(handle); 631 if (queue > 3) 632 return NULL; 633 634 index = POOL_INDEX(handle); 635 if (index > FBQ_SIZE - 1) 636 return NULL; 637 638 return card->sbpool[queue].skb[index]; 639 } 640 641 static struct scq_info * 642 alloc_scq(struct idt77252_dev *card, int class) 643 { 644 struct scq_info *scq; 645 646 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 647 if (!scq) 648 return NULL; 649 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 650 &scq->paddr); 651 if (scq->base == NULL) { 652 kfree(scq); 653 return NULL; 654 } 655 memset(scq->base, 0, SCQ_SIZE); 656 657 scq->next = scq->base; 658 scq->last = scq->base + (SCQ_ENTRIES - 1); 659 atomic_set(&scq->used, 0); 660 661 spin_lock_init(&scq->lock); 662 spin_lock_init(&scq->skblock); 663 664 skb_queue_head_init(&scq->transmit); 665 skb_queue_head_init(&scq->pending); 666 667 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 668 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 669 670 return scq; 671 } 672 673 static void 674 free_scq(struct idt77252_dev *card, struct scq_info *scq) 675 { 676 struct sk_buff *skb; 677 struct atm_vcc *vcc; 678 679 pci_free_consistent(card->pcidev, SCQ_SIZE, 680 scq->base, scq->paddr); 681 682 while ((skb = skb_dequeue(&scq->transmit))) { 683 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 684 skb->len, PCI_DMA_TODEVICE); 685 686 vcc = ATM_SKB(skb)->vcc; 687 if (vcc->pop) 688 vcc->pop(vcc, skb); 689 else 690 dev_kfree_skb(skb); 691 } 692 693 while ((skb = skb_dequeue(&scq->pending))) { 694 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 695 skb->len, PCI_DMA_TODEVICE); 696 697 vcc = ATM_SKB(skb)->vcc; 698 if (vcc->pop) 699 vcc->pop(vcc, skb); 700 else 701 dev_kfree_skb(skb); 702 } 703 704 kfree(scq); 705 } 706 707 708 static int 709 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 710 { 711 struct scq_info *scq = vc->scq; 712 unsigned long flags; 713 struct scqe *tbd; 714 int entries; 715 716 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 717 718 atomic_inc(&scq->used); 719 entries = atomic_read(&scq->used); 720 if (entries > (SCQ_ENTRIES - 1)) { 721 atomic_dec(&scq->used); 722 goto out; 723 } 724 725 skb_queue_tail(&scq->transmit, skb); 726 727 spin_lock_irqsave(&vc->lock, flags); 728 if (vc->estimator) { 729 struct atm_vcc *vcc = vc->tx_vcc; 730 struct sock *sk = sk_atm(vcc); 731 732 vc->estimator->cells += (skb->len + 47) / 48; 733 if (atomic_read(&sk->sk_wmem_alloc) > 734 (sk->sk_sndbuf >> 1)) { 735 u32 cps = vc->estimator->maxcps; 736 737 vc->estimator->cps = cps; 738 vc->estimator->avcps = cps << 5; 739 if (vc->lacr < vc->init_er) { 740 vc->lacr = vc->init_er; 741 writel(TCMDQ_LACR | (vc->lacr << 16) | 742 vc->index, SAR_REG_TCMDQ); 743 } 744 } 745 } 746 spin_unlock_irqrestore(&vc->lock, flags); 747 748 tbd = &IDT77252_PRV_TBD(skb); 749 750 spin_lock_irqsave(&scq->lock, flags); 751 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 752 SAR_TBD_TSIF | SAR_TBD_GTSI); 753 scq->next->word_2 = cpu_to_le32(tbd->word_2); 754 scq->next->word_3 = cpu_to_le32(tbd->word_3); 755 scq->next->word_4 = cpu_to_le32(tbd->word_4); 756 757 if (scq->next == scq->last) 758 scq->next = scq->base; 759 else 760 scq->next++; 761 762 write_sram(card, scq->scd, 763 scq->paddr + 764 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 765 spin_unlock_irqrestore(&scq->lock, flags); 766 767 scq->trans_start = jiffies; 768 769 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 770 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 771 SAR_REG_TCMDQ); 772 } 773 774 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 775 776 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 777 card->name, atomic_read(&scq->used), 778 read_sram(card, scq->scd + 1), scq->next); 779 780 return 0; 781 782 out: 783 if (time_after(jiffies, scq->trans_start + HZ)) { 784 printk("%s: Error pushing TBD for %d.%d\n", 785 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 786 #ifdef CONFIG_ATM_IDT77252_DEBUG 787 idt77252_tx_dump(card); 788 #endif 789 scq->trans_start = jiffies; 790 } 791 792 return -ENOBUFS; 793 } 794 795 796 static void 797 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 798 { 799 struct scq_info *scq = vc->scq; 800 struct sk_buff *skb; 801 struct atm_vcc *vcc; 802 803 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 804 card->name, atomic_read(&scq->used), scq->next); 805 806 skb = skb_dequeue(&scq->transmit); 807 if (skb) { 808 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 809 810 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 811 skb->len, PCI_DMA_TODEVICE); 812 813 vcc = ATM_SKB(skb)->vcc; 814 815 if (vcc->pop) 816 vcc->pop(vcc, skb); 817 else 818 dev_kfree_skb(skb); 819 820 atomic_inc(&vcc->stats->tx); 821 } 822 823 atomic_dec(&scq->used); 824 825 spin_lock(&scq->skblock); 826 while ((skb = skb_dequeue(&scq->pending))) { 827 if (push_on_scq(card, vc, skb)) { 828 skb_queue_head(&vc->scq->pending, skb); 829 break; 830 } 831 } 832 spin_unlock(&scq->skblock); 833 } 834 835 static int 836 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 837 struct sk_buff *skb, int oam) 838 { 839 struct atm_vcc *vcc; 840 struct scqe *tbd; 841 unsigned long flags; 842 int error; 843 int aal; 844 845 if (skb->len == 0) { 846 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 847 return -EINVAL; 848 } 849 850 TXPRINTK("%s: Sending %d bytes of data.\n", 851 card->name, skb->len); 852 853 tbd = &IDT77252_PRV_TBD(skb); 854 vcc = ATM_SKB(skb)->vcc; 855 856 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 857 skb->len, PCI_DMA_TODEVICE); 858 859 error = -EINVAL; 860 861 if (oam) { 862 if (skb->len != 52) 863 goto errout; 864 865 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 866 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 867 tbd->word_3 = 0x00000000; 868 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 869 (skb->data[2] << 8) | (skb->data[3] << 0); 870 871 if (test_bit(VCF_RSV, &vc->flags)) 872 vc = card->vcs[0]; 873 874 goto done; 875 } 876 877 if (test_bit(VCF_RSV, &vc->flags)) { 878 printk("%s: Trying to transmit on reserved VC\n", card->name); 879 goto errout; 880 } 881 882 aal = vcc->qos.aal; 883 884 switch (aal) { 885 case ATM_AAL0: 886 case ATM_AAL34: 887 if (skb->len > 52) 888 goto errout; 889 890 if (aal == ATM_AAL0) 891 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 892 ATM_CELL_PAYLOAD; 893 else 894 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 895 ATM_CELL_PAYLOAD; 896 897 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 898 tbd->word_3 = 0x00000000; 899 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 900 (skb->data[2] << 8) | (skb->data[3] << 0); 901 break; 902 903 case ATM_AAL5: 904 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 905 tbd->word_2 = IDT77252_PRV_PADDR(skb); 906 tbd->word_3 = skb->len; 907 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 908 (vcc->vci << SAR_TBD_VCI_SHIFT); 909 break; 910 911 case ATM_AAL1: 912 case ATM_AAL2: 913 default: 914 printk("%s: Traffic type not supported.\n", card->name); 915 error = -EPROTONOSUPPORT; 916 goto errout; 917 } 918 919 done: 920 spin_lock_irqsave(&vc->scq->skblock, flags); 921 skb_queue_tail(&vc->scq->pending, skb); 922 923 while ((skb = skb_dequeue(&vc->scq->pending))) { 924 if (push_on_scq(card, vc, skb)) { 925 skb_queue_head(&vc->scq->pending, skb); 926 break; 927 } 928 } 929 spin_unlock_irqrestore(&vc->scq->skblock, flags); 930 931 return 0; 932 933 errout: 934 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 935 skb->len, PCI_DMA_TODEVICE); 936 return error; 937 } 938 939 static unsigned long 940 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 941 { 942 int i; 943 944 for (i = 0; i < card->scd_size; i++) { 945 if (!card->scd2vc[i]) { 946 card->scd2vc[i] = vc; 947 vc->scd_index = i; 948 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 949 } 950 } 951 return 0; 952 } 953 954 static void 955 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 956 { 957 write_sram(card, scq->scd, scq->paddr); 958 write_sram(card, scq->scd + 1, 0x00000000); 959 write_sram(card, scq->scd + 2, 0xffffffff); 960 write_sram(card, scq->scd + 3, 0x00000000); 961 } 962 963 static void 964 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 965 { 966 return; 967 } 968 969 /*****************************************************************************/ 970 /* */ 971 /* RSQ Handling */ 972 /* */ 973 /*****************************************************************************/ 974 975 static int 976 init_rsq(struct idt77252_dev *card) 977 { 978 struct rsq_entry *rsqe; 979 980 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 981 &card->rsq.paddr); 982 if (card->rsq.base == NULL) { 983 printk("%s: can't allocate RSQ.\n", card->name); 984 return -1; 985 } 986 memset(card->rsq.base, 0, RSQSIZE); 987 988 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 989 card->rsq.next = card->rsq.last; 990 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 991 rsqe->word_4 = 0; 992 993 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 994 SAR_REG_RSQH); 995 writel(card->rsq.paddr, SAR_REG_RSQB); 996 997 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 998 (unsigned long) card->rsq.base, 999 readl(SAR_REG_RSQB)); 1000 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 1001 card->name, 1002 readl(SAR_REG_RSQH), 1003 readl(SAR_REG_RSQB), 1004 readl(SAR_REG_RSQT)); 1005 1006 return 0; 1007 } 1008 1009 static void 1010 deinit_rsq(struct idt77252_dev *card) 1011 { 1012 pci_free_consistent(card->pcidev, RSQSIZE, 1013 card->rsq.base, card->rsq.paddr); 1014 } 1015 1016 static void 1017 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1018 { 1019 struct atm_vcc *vcc; 1020 struct sk_buff *skb; 1021 struct rx_pool *rpp; 1022 struct vc_map *vc; 1023 u32 header, vpi, vci; 1024 u32 stat; 1025 int i; 1026 1027 stat = le32_to_cpu(rsqe->word_4); 1028 1029 if (stat & SAR_RSQE_IDLE) { 1030 RXPRINTK("%s: message about inactive connection.\n", 1031 card->name); 1032 return; 1033 } 1034 1035 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1036 if (skb == NULL) { 1037 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1038 card->name, __func__, 1039 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1040 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1041 return; 1042 } 1043 1044 header = le32_to_cpu(rsqe->word_1); 1045 vpi = (header >> 16) & 0x00ff; 1046 vci = (header >> 0) & 0xffff; 1047 1048 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1049 card->name, vpi, vci, skb, skb->data); 1050 1051 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1052 printk("%s: SDU received for out-of-range vc %u.%u\n", 1053 card->name, vpi, vci); 1054 recycle_rx_skb(card, skb); 1055 return; 1056 } 1057 1058 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1059 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1060 printk("%s: SDU received on non RX vc %u.%u\n", 1061 card->name, vpi, vci); 1062 recycle_rx_skb(card, skb); 1063 return; 1064 } 1065 1066 vcc = vc->rx_vcc; 1067 1068 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1069 skb_end_pointer(skb) - skb->data, 1070 PCI_DMA_FROMDEVICE); 1071 1072 if ((vcc->qos.aal == ATM_AAL0) || 1073 (vcc->qos.aal == ATM_AAL34)) { 1074 struct sk_buff *sb; 1075 unsigned char *cell; 1076 u32 aal0; 1077 1078 cell = skb->data; 1079 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1080 if ((sb = dev_alloc_skb(64)) == NULL) { 1081 printk("%s: Can't allocate buffers for aal0.\n", 1082 card->name); 1083 atomic_add(i, &vcc->stats->rx_drop); 1084 break; 1085 } 1086 if (!atm_charge(vcc, sb->truesize)) { 1087 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1088 card->name); 1089 atomic_add(i - 1, &vcc->stats->rx_drop); 1090 dev_kfree_skb(sb); 1091 break; 1092 } 1093 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1094 (vci << ATM_HDR_VCI_SHIFT); 1095 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1096 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1097 1098 *((u32 *) sb->data) = aal0; 1099 skb_put(sb, sizeof(u32)); 1100 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1101 cell, ATM_CELL_PAYLOAD); 1102 1103 ATM_SKB(sb)->vcc = vcc; 1104 __net_timestamp(sb); 1105 vcc->push(vcc, sb); 1106 atomic_inc(&vcc->stats->rx); 1107 1108 cell += ATM_CELL_PAYLOAD; 1109 } 1110 1111 recycle_rx_skb(card, skb); 1112 return; 1113 } 1114 if (vcc->qos.aal != ATM_AAL5) { 1115 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1116 card->name, vcc->qos.aal); 1117 recycle_rx_skb(card, skb); 1118 return; 1119 } 1120 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1121 1122 rpp = &vc->rcv.rx_pool; 1123 1124 rpp->len += skb->len; 1125 if (!rpp->count++) 1126 rpp->first = skb; 1127 *rpp->last = skb; 1128 rpp->last = &skb->next; 1129 1130 if (stat & SAR_RSQE_EPDU) { 1131 unsigned char *l1l2; 1132 unsigned int len; 1133 1134 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1135 1136 len = (l1l2[0] << 8) | l1l2[1]; 1137 len = len ? len : 0x10000; 1138 1139 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1140 1141 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1142 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1143 "(CDC: %08x)\n", 1144 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1145 recycle_rx_pool_skb(card, rpp); 1146 atomic_inc(&vcc->stats->rx_err); 1147 return; 1148 } 1149 if (stat & SAR_RSQE_CRC) { 1150 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1151 recycle_rx_pool_skb(card, rpp); 1152 atomic_inc(&vcc->stats->rx_err); 1153 return; 1154 } 1155 if (rpp->count > 1) { 1156 struct sk_buff *sb; 1157 1158 skb = dev_alloc_skb(rpp->len); 1159 if (!skb) { 1160 RXPRINTK("%s: Can't alloc RX skb.\n", 1161 card->name); 1162 recycle_rx_pool_skb(card, rpp); 1163 atomic_inc(&vcc->stats->rx_err); 1164 return; 1165 } 1166 if (!atm_charge(vcc, skb->truesize)) { 1167 recycle_rx_pool_skb(card, rpp); 1168 dev_kfree_skb(skb); 1169 return; 1170 } 1171 sb = rpp->first; 1172 for (i = 0; i < rpp->count; i++) { 1173 memcpy(skb_put(skb, sb->len), 1174 sb->data, sb->len); 1175 sb = sb->next; 1176 } 1177 1178 recycle_rx_pool_skb(card, rpp); 1179 1180 skb_trim(skb, len); 1181 ATM_SKB(skb)->vcc = vcc; 1182 __net_timestamp(skb); 1183 1184 vcc->push(vcc, skb); 1185 atomic_inc(&vcc->stats->rx); 1186 1187 return; 1188 } 1189 1190 skb->next = NULL; 1191 flush_rx_pool(card, rpp); 1192 1193 if (!atm_charge(vcc, skb->truesize)) { 1194 recycle_rx_skb(card, skb); 1195 return; 1196 } 1197 1198 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1199 skb_end_pointer(skb) - skb->data, 1200 PCI_DMA_FROMDEVICE); 1201 sb_pool_remove(card, skb); 1202 1203 skb_trim(skb, len); 1204 ATM_SKB(skb)->vcc = vcc; 1205 __net_timestamp(skb); 1206 1207 vcc->push(vcc, skb); 1208 atomic_inc(&vcc->stats->rx); 1209 1210 if (skb->truesize > SAR_FB_SIZE_3) 1211 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1212 else if (skb->truesize > SAR_FB_SIZE_2) 1213 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1214 else if (skb->truesize > SAR_FB_SIZE_1) 1215 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1216 else 1217 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1218 return; 1219 } 1220 } 1221 1222 static void 1223 idt77252_rx(struct idt77252_dev *card) 1224 { 1225 struct rsq_entry *rsqe; 1226 1227 if (card->rsq.next == card->rsq.last) 1228 rsqe = card->rsq.base; 1229 else 1230 rsqe = card->rsq.next + 1; 1231 1232 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1233 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1234 return; 1235 } 1236 1237 do { 1238 dequeue_rx(card, rsqe); 1239 rsqe->word_4 = 0; 1240 card->rsq.next = rsqe; 1241 if (card->rsq.next == card->rsq.last) 1242 rsqe = card->rsq.base; 1243 else 1244 rsqe = card->rsq.next + 1; 1245 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1246 1247 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1248 SAR_REG_RSQH); 1249 } 1250 1251 static void 1252 idt77252_rx_raw(struct idt77252_dev *card) 1253 { 1254 struct sk_buff *queue; 1255 u32 head, tail; 1256 struct atm_vcc *vcc; 1257 struct vc_map *vc; 1258 struct sk_buff *sb; 1259 1260 if (card->raw_cell_head == NULL) { 1261 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1262 card->raw_cell_head = sb_pool_skb(card, handle); 1263 } 1264 1265 queue = card->raw_cell_head; 1266 if (!queue) 1267 return; 1268 1269 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1270 tail = readl(SAR_REG_RAWCT); 1271 1272 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1273 skb_end_pointer(queue) - queue->head - 16, 1274 PCI_DMA_FROMDEVICE); 1275 1276 while (head != tail) { 1277 unsigned int vpi, vci, pti; 1278 u32 header; 1279 1280 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1281 1282 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1283 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1284 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1285 1286 #ifdef CONFIG_ATM_IDT77252_DEBUG 1287 if (debug & DBG_RAW_CELL) { 1288 int i; 1289 1290 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1291 card->name, (header >> 28) & 0x000f, 1292 (header >> 20) & 0x00ff, 1293 (header >> 4) & 0xffff, 1294 (header >> 1) & 0x0007, 1295 (header >> 0) & 0x0001); 1296 for (i = 16; i < 64; i++) 1297 printk(" %02x", queue->data[i]); 1298 printk("\n"); 1299 } 1300 #endif 1301 1302 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1303 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1304 card->name, vpi, vci); 1305 goto drop; 1306 } 1307 1308 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1309 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1310 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1311 card->name, vpi, vci); 1312 goto drop; 1313 } 1314 1315 vcc = vc->rx_vcc; 1316 1317 if (vcc->qos.aal != ATM_AAL0) { 1318 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1319 card->name, vpi, vci); 1320 atomic_inc(&vcc->stats->rx_drop); 1321 goto drop; 1322 } 1323 1324 if ((sb = dev_alloc_skb(64)) == NULL) { 1325 printk("%s: Can't allocate buffers for AAL0.\n", 1326 card->name); 1327 atomic_inc(&vcc->stats->rx_err); 1328 goto drop; 1329 } 1330 1331 if (!atm_charge(vcc, sb->truesize)) { 1332 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1333 card->name); 1334 dev_kfree_skb(sb); 1335 goto drop; 1336 } 1337 1338 *((u32 *) sb->data) = header; 1339 skb_put(sb, sizeof(u32)); 1340 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1341 ATM_CELL_PAYLOAD); 1342 1343 ATM_SKB(sb)->vcc = vcc; 1344 __net_timestamp(sb); 1345 vcc->push(vcc, sb); 1346 atomic_inc(&vcc->stats->rx); 1347 1348 drop: 1349 skb_pull(queue, 64); 1350 1351 head = IDT77252_PRV_PADDR(queue) 1352 + (queue->data - queue->head - 16); 1353 1354 if (queue->len < 128) { 1355 struct sk_buff *next; 1356 u32 handle; 1357 1358 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1359 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1360 1361 next = sb_pool_skb(card, handle); 1362 recycle_rx_skb(card, queue); 1363 1364 if (next) { 1365 card->raw_cell_head = next; 1366 queue = card->raw_cell_head; 1367 pci_dma_sync_single_for_cpu(card->pcidev, 1368 IDT77252_PRV_PADDR(queue), 1369 (skb_end_pointer(queue) - 1370 queue->data), 1371 PCI_DMA_FROMDEVICE); 1372 } else { 1373 card->raw_cell_head = NULL; 1374 printk("%s: raw cell queue overrun\n", 1375 card->name); 1376 break; 1377 } 1378 } 1379 } 1380 } 1381 1382 1383 /*****************************************************************************/ 1384 /* */ 1385 /* TSQ Handling */ 1386 /* */ 1387 /*****************************************************************************/ 1388 1389 static int 1390 init_tsq(struct idt77252_dev *card) 1391 { 1392 struct tsq_entry *tsqe; 1393 1394 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1395 &card->tsq.paddr); 1396 if (card->tsq.base == NULL) { 1397 printk("%s: can't allocate TSQ.\n", card->name); 1398 return -1; 1399 } 1400 memset(card->tsq.base, 0, TSQSIZE); 1401 1402 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1403 card->tsq.next = card->tsq.last; 1404 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1405 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1406 1407 writel(card->tsq.paddr, SAR_REG_TSQB); 1408 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1409 SAR_REG_TSQH); 1410 1411 return 0; 1412 } 1413 1414 static void 1415 deinit_tsq(struct idt77252_dev *card) 1416 { 1417 pci_free_consistent(card->pcidev, TSQSIZE, 1418 card->tsq.base, card->tsq.paddr); 1419 } 1420 1421 static void 1422 idt77252_tx(struct idt77252_dev *card) 1423 { 1424 struct tsq_entry *tsqe; 1425 unsigned int vpi, vci; 1426 struct vc_map *vc; 1427 u32 conn, stat; 1428 1429 if (card->tsq.next == card->tsq.last) 1430 tsqe = card->tsq.base; 1431 else 1432 tsqe = card->tsq.next + 1; 1433 1434 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1435 card->tsq.base, card->tsq.next, card->tsq.last); 1436 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1437 readl(SAR_REG_TSQB), 1438 readl(SAR_REG_TSQT), 1439 readl(SAR_REG_TSQH)); 1440 1441 stat = le32_to_cpu(tsqe->word_2); 1442 1443 if (stat & SAR_TSQE_INVALID) 1444 return; 1445 1446 do { 1447 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1448 le32_to_cpu(tsqe->word_1), 1449 le32_to_cpu(tsqe->word_2)); 1450 1451 switch (stat & SAR_TSQE_TYPE) { 1452 case SAR_TSQE_TYPE_TIMER: 1453 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1454 break; 1455 1456 case SAR_TSQE_TYPE_IDLE: 1457 1458 conn = le32_to_cpu(tsqe->word_1); 1459 1460 if (SAR_TSQE_TAG(stat) == 0x10) { 1461 #ifdef NOTDEF 1462 printk("%s: Connection %d halted.\n", 1463 card->name, 1464 le32_to_cpu(tsqe->word_1) & 0x1fff); 1465 #endif 1466 break; 1467 } 1468 1469 vc = card->vcs[conn & 0x1fff]; 1470 if (!vc) { 1471 printk("%s: could not find VC from conn %d\n", 1472 card->name, conn & 0x1fff); 1473 break; 1474 } 1475 1476 printk("%s: Connection %d IDLE.\n", 1477 card->name, vc->index); 1478 1479 set_bit(VCF_IDLE, &vc->flags); 1480 break; 1481 1482 case SAR_TSQE_TYPE_TSR: 1483 1484 conn = le32_to_cpu(tsqe->word_1); 1485 1486 vc = card->vcs[conn & 0x1fff]; 1487 if (!vc) { 1488 printk("%s: no VC at index %d\n", 1489 card->name, 1490 le32_to_cpu(tsqe->word_1) & 0x1fff); 1491 break; 1492 } 1493 1494 drain_scq(card, vc); 1495 break; 1496 1497 case SAR_TSQE_TYPE_TBD_COMP: 1498 1499 conn = le32_to_cpu(tsqe->word_1); 1500 1501 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1502 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1503 1504 if (vpi >= (1 << card->vpibits) || 1505 vci >= (1 << card->vcibits)) { 1506 printk("%s: TBD complete: " 1507 "out of range VPI.VCI %u.%u\n", 1508 card->name, vpi, vci); 1509 break; 1510 } 1511 1512 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1513 if (!vc) { 1514 printk("%s: TBD complete: " 1515 "no VC at VPI.VCI %u.%u\n", 1516 card->name, vpi, vci); 1517 break; 1518 } 1519 1520 drain_scq(card, vc); 1521 break; 1522 } 1523 1524 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1525 1526 card->tsq.next = tsqe; 1527 if (card->tsq.next == card->tsq.last) 1528 tsqe = card->tsq.base; 1529 else 1530 tsqe = card->tsq.next + 1; 1531 1532 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1533 card->tsq.base, card->tsq.next, card->tsq.last); 1534 1535 stat = le32_to_cpu(tsqe->word_2); 1536 1537 } while (!(stat & SAR_TSQE_INVALID)); 1538 1539 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1540 SAR_REG_TSQH); 1541 1542 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1543 card->index, readl(SAR_REG_TSQH), 1544 readl(SAR_REG_TSQT), card->tsq.next); 1545 } 1546 1547 1548 static void 1549 tst_timer(unsigned long data) 1550 { 1551 struct idt77252_dev *card = (struct idt77252_dev *)data; 1552 unsigned long base, idle, jump; 1553 unsigned long flags; 1554 u32 pc; 1555 int e; 1556 1557 spin_lock_irqsave(&card->tst_lock, flags); 1558 1559 base = card->tst[card->tst_index]; 1560 idle = card->tst[card->tst_index ^ 1]; 1561 1562 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1563 jump = base + card->tst_size - 2; 1564 1565 pc = readl(SAR_REG_NOW) >> 2; 1566 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1567 mod_timer(&card->tst_timer, jiffies + 1); 1568 goto out; 1569 } 1570 1571 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1572 1573 card->tst_index ^= 1; 1574 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1575 1576 base = card->tst[card->tst_index]; 1577 idle = card->tst[card->tst_index ^ 1]; 1578 1579 for (e = 0; e < card->tst_size - 2; e++) { 1580 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1581 write_sram(card, idle + e, 1582 card->soft_tst[e].tste & TSTE_MASK); 1583 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1584 } 1585 } 1586 } 1587 1588 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1589 1590 for (e = 0; e < card->tst_size - 2; e++) { 1591 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1592 write_sram(card, idle + e, 1593 card->soft_tst[e].tste & TSTE_MASK); 1594 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1595 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1596 } 1597 } 1598 1599 jump = base + card->tst_size - 2; 1600 1601 write_sram(card, jump, TSTE_OPC_NULL); 1602 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1603 1604 mod_timer(&card->tst_timer, jiffies + 1); 1605 } 1606 1607 out: 1608 spin_unlock_irqrestore(&card->tst_lock, flags); 1609 } 1610 1611 static int 1612 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1613 int n, unsigned int opc) 1614 { 1615 unsigned long cl, avail; 1616 unsigned long idle; 1617 int e, r; 1618 u32 data; 1619 1620 avail = card->tst_size - 2; 1621 for (e = 0; e < avail; e++) { 1622 if (card->soft_tst[e].vc == NULL) 1623 break; 1624 } 1625 if (e >= avail) { 1626 printk("%s: No free TST entries found\n", card->name); 1627 return -1; 1628 } 1629 1630 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1631 card->name, vc ? vc->index : -1, e); 1632 1633 r = n; 1634 cl = avail; 1635 data = opc & TSTE_OPC_MASK; 1636 if (vc && (opc != TSTE_OPC_NULL)) 1637 data = opc | vc->index; 1638 1639 idle = card->tst[card->tst_index ^ 1]; 1640 1641 /* 1642 * Fill Soft TST. 1643 */ 1644 while (r > 0) { 1645 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1646 if (vc) 1647 card->soft_tst[e].vc = vc; 1648 else 1649 card->soft_tst[e].vc = (void *)-1; 1650 1651 card->soft_tst[e].tste = data; 1652 if (timer_pending(&card->tst_timer)) 1653 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1654 else { 1655 write_sram(card, idle + e, data); 1656 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1657 } 1658 1659 cl -= card->tst_size; 1660 r--; 1661 } 1662 1663 if (++e == avail) 1664 e = 0; 1665 cl += n; 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int 1672 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1673 { 1674 unsigned long flags; 1675 int res; 1676 1677 spin_lock_irqsave(&card->tst_lock, flags); 1678 1679 res = __fill_tst(card, vc, n, opc); 1680 1681 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1682 if (!timer_pending(&card->tst_timer)) 1683 mod_timer(&card->tst_timer, jiffies + 1); 1684 1685 spin_unlock_irqrestore(&card->tst_lock, flags); 1686 return res; 1687 } 1688 1689 static int 1690 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1691 { 1692 unsigned long idle; 1693 int e; 1694 1695 idle = card->tst[card->tst_index ^ 1]; 1696 1697 for (e = 0; e < card->tst_size - 2; e++) { 1698 if (card->soft_tst[e].vc == vc) { 1699 card->soft_tst[e].vc = NULL; 1700 1701 card->soft_tst[e].tste = TSTE_OPC_VAR; 1702 if (timer_pending(&card->tst_timer)) 1703 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1704 else { 1705 write_sram(card, idle + e, TSTE_OPC_VAR); 1706 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1707 } 1708 } 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int 1715 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1716 { 1717 unsigned long flags; 1718 int res; 1719 1720 spin_lock_irqsave(&card->tst_lock, flags); 1721 1722 res = __clear_tst(card, vc); 1723 1724 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1725 if (!timer_pending(&card->tst_timer)) 1726 mod_timer(&card->tst_timer, jiffies + 1); 1727 1728 spin_unlock_irqrestore(&card->tst_lock, flags); 1729 return res; 1730 } 1731 1732 static int 1733 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1734 int n, unsigned int opc) 1735 { 1736 unsigned long flags; 1737 int res; 1738 1739 spin_lock_irqsave(&card->tst_lock, flags); 1740 1741 __clear_tst(card, vc); 1742 res = __fill_tst(card, vc, n, opc); 1743 1744 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1745 if (!timer_pending(&card->tst_timer)) 1746 mod_timer(&card->tst_timer, jiffies + 1); 1747 1748 spin_unlock_irqrestore(&card->tst_lock, flags); 1749 return res; 1750 } 1751 1752 1753 static int 1754 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1755 { 1756 unsigned long tct; 1757 1758 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1759 1760 switch (vc->class) { 1761 case SCHED_CBR: 1762 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1763 card->name, tct, vc->scq->scd); 1764 1765 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1766 write_sram(card, tct + 1, 0); 1767 write_sram(card, tct + 2, 0); 1768 write_sram(card, tct + 3, 0); 1769 write_sram(card, tct + 4, 0); 1770 write_sram(card, tct + 5, 0); 1771 write_sram(card, tct + 6, 0); 1772 write_sram(card, tct + 7, 0); 1773 break; 1774 1775 case SCHED_UBR: 1776 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1777 card->name, tct, vc->scq->scd); 1778 1779 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1780 write_sram(card, tct + 1, 0); 1781 write_sram(card, tct + 2, TCT_TSIF); 1782 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1783 write_sram(card, tct + 4, 0); 1784 write_sram(card, tct + 5, vc->init_er); 1785 write_sram(card, tct + 6, 0); 1786 write_sram(card, tct + 7, TCT_FLAG_UBR); 1787 break; 1788 1789 case SCHED_VBR: 1790 case SCHED_ABR: 1791 default: 1792 return -ENOSYS; 1793 } 1794 1795 return 0; 1796 } 1797 1798 /*****************************************************************************/ 1799 /* */ 1800 /* FBQ Handling */ 1801 /* */ 1802 /*****************************************************************************/ 1803 1804 static __inline__ int 1805 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1806 { 1807 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1808 } 1809 1810 static __inline__ int 1811 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1812 { 1813 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1814 } 1815 1816 static int 1817 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1818 { 1819 unsigned long flags; 1820 u32 handle; 1821 u32 addr; 1822 1823 skb->data = skb->head; 1824 skb_reset_tail_pointer(skb); 1825 skb->len = 0; 1826 1827 skb_reserve(skb, 16); 1828 1829 switch (queue) { 1830 case 0: 1831 skb_put(skb, SAR_FB_SIZE_0); 1832 break; 1833 case 1: 1834 skb_put(skb, SAR_FB_SIZE_1); 1835 break; 1836 case 2: 1837 skb_put(skb, SAR_FB_SIZE_2); 1838 break; 1839 case 3: 1840 skb_put(skb, SAR_FB_SIZE_3); 1841 break; 1842 default: 1843 return -1; 1844 } 1845 1846 if (idt77252_fbq_full(card, queue)) 1847 return -1; 1848 1849 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1850 1851 handle = IDT77252_PRV_POOL(skb); 1852 addr = IDT77252_PRV_PADDR(skb); 1853 1854 spin_lock_irqsave(&card->cmd_lock, flags); 1855 writel(handle, card->fbq[queue]); 1856 writel(addr, card->fbq[queue]); 1857 spin_unlock_irqrestore(&card->cmd_lock, flags); 1858 1859 return 0; 1860 } 1861 1862 static void 1863 add_rx_skb(struct idt77252_dev *card, int queue, 1864 unsigned int size, unsigned int count) 1865 { 1866 struct sk_buff *skb; 1867 dma_addr_t paddr; 1868 u32 handle; 1869 1870 while (count--) { 1871 skb = dev_alloc_skb(size); 1872 if (!skb) 1873 return; 1874 1875 if (sb_pool_add(card, skb, queue)) { 1876 printk("%s: SB POOL full\n", __func__); 1877 goto outfree; 1878 } 1879 1880 paddr = pci_map_single(card->pcidev, skb->data, 1881 skb_end_pointer(skb) - skb->data, 1882 PCI_DMA_FROMDEVICE); 1883 IDT77252_PRV_PADDR(skb) = paddr; 1884 1885 if (push_rx_skb(card, skb, queue)) { 1886 printk("%s: FB QUEUE full\n", __func__); 1887 goto outunmap; 1888 } 1889 } 1890 1891 return; 1892 1893 outunmap: 1894 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1895 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1896 1897 handle = IDT77252_PRV_POOL(skb); 1898 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1899 1900 outfree: 1901 dev_kfree_skb(skb); 1902 } 1903 1904 1905 static void 1906 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1907 { 1908 u32 handle = IDT77252_PRV_POOL(skb); 1909 int err; 1910 1911 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1912 skb_end_pointer(skb) - skb->data, 1913 PCI_DMA_FROMDEVICE); 1914 1915 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1916 if (err) { 1917 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1918 skb_end_pointer(skb) - skb->data, 1919 PCI_DMA_FROMDEVICE); 1920 sb_pool_remove(card, skb); 1921 dev_kfree_skb(skb); 1922 } 1923 } 1924 1925 static void 1926 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1927 { 1928 rpp->len = 0; 1929 rpp->count = 0; 1930 rpp->first = NULL; 1931 rpp->last = &rpp->first; 1932 } 1933 1934 static void 1935 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1936 { 1937 struct sk_buff *skb, *next; 1938 int i; 1939 1940 skb = rpp->first; 1941 for (i = 0; i < rpp->count; i++) { 1942 next = skb->next; 1943 skb->next = NULL; 1944 recycle_rx_skb(card, skb); 1945 skb = next; 1946 } 1947 flush_rx_pool(card, rpp); 1948 } 1949 1950 /*****************************************************************************/ 1951 /* */ 1952 /* ATM Interface */ 1953 /* */ 1954 /*****************************************************************************/ 1955 1956 static void 1957 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1958 { 1959 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1960 } 1961 1962 static unsigned char 1963 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1964 { 1965 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1966 } 1967 1968 static inline int 1969 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1970 { 1971 struct atm_dev *dev = vcc->dev; 1972 struct idt77252_dev *card = dev->dev_data; 1973 struct vc_map *vc = vcc->dev_data; 1974 int err; 1975 1976 if (vc == NULL) { 1977 printk("%s: NULL connection in send().\n", card->name); 1978 atomic_inc(&vcc->stats->tx_err); 1979 dev_kfree_skb(skb); 1980 return -EINVAL; 1981 } 1982 if (!test_bit(VCF_TX, &vc->flags)) { 1983 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1984 atomic_inc(&vcc->stats->tx_err); 1985 dev_kfree_skb(skb); 1986 return -EINVAL; 1987 } 1988 1989 switch (vcc->qos.aal) { 1990 case ATM_AAL0: 1991 case ATM_AAL1: 1992 case ATM_AAL5: 1993 break; 1994 default: 1995 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1996 atomic_inc(&vcc->stats->tx_err); 1997 dev_kfree_skb(skb); 1998 return -EINVAL; 1999 } 2000 2001 if (skb_shinfo(skb)->nr_frags != 0) { 2002 printk("%s: No scatter-gather yet.\n", card->name); 2003 atomic_inc(&vcc->stats->tx_err); 2004 dev_kfree_skb(skb); 2005 return -EINVAL; 2006 } 2007 ATM_SKB(skb)->vcc = vcc; 2008 2009 err = queue_skb(card, vc, skb, oam); 2010 if (err) { 2011 atomic_inc(&vcc->stats->tx_err); 2012 dev_kfree_skb(skb); 2013 return err; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2020 { 2021 return idt77252_send_skb(vcc, skb, 0); 2022 } 2023 2024 static int 2025 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2026 { 2027 struct atm_dev *dev = vcc->dev; 2028 struct idt77252_dev *card = dev->dev_data; 2029 struct sk_buff *skb; 2030 2031 skb = dev_alloc_skb(64); 2032 if (!skb) { 2033 printk("%s: Out of memory in send_oam().\n", card->name); 2034 atomic_inc(&vcc->stats->tx_err); 2035 return -ENOMEM; 2036 } 2037 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2038 2039 memcpy(skb_put(skb, 52), cell, 52); 2040 2041 return idt77252_send_skb(vcc, skb, 1); 2042 } 2043 2044 static __inline__ unsigned int 2045 idt77252_fls(unsigned int x) 2046 { 2047 int r = 1; 2048 2049 if (x == 0) 2050 return 0; 2051 if (x & 0xffff0000) { 2052 x >>= 16; 2053 r += 16; 2054 } 2055 if (x & 0xff00) { 2056 x >>= 8; 2057 r += 8; 2058 } 2059 if (x & 0xf0) { 2060 x >>= 4; 2061 r += 4; 2062 } 2063 if (x & 0xc) { 2064 x >>= 2; 2065 r += 2; 2066 } 2067 if (x & 0x2) 2068 r += 1; 2069 return r; 2070 } 2071 2072 static u16 2073 idt77252_int_to_atmfp(unsigned int rate) 2074 { 2075 u16 m, e; 2076 2077 if (rate == 0) 2078 return 0; 2079 e = idt77252_fls(rate) - 1; 2080 if (e < 9) 2081 m = (rate - (1 << e)) << (9 - e); 2082 else if (e == 9) 2083 m = (rate - (1 << e)); 2084 else /* e > 9 */ 2085 m = (rate - (1 << e)) >> (e - 9); 2086 return 0x4000 | (e << 9) | m; 2087 } 2088 2089 static u8 2090 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2091 { 2092 u16 afp; 2093 2094 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2095 if (pcr < 0) 2096 return rate_to_log[(afp >> 5) & 0x1ff]; 2097 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2098 } 2099 2100 static void 2101 idt77252_est_timer(unsigned long data) 2102 { 2103 struct vc_map *vc = (struct vc_map *)data; 2104 struct idt77252_dev *card = vc->card; 2105 struct rate_estimator *est; 2106 unsigned long flags; 2107 u32 rate, cps; 2108 u64 ncells; 2109 u8 lacr; 2110 2111 spin_lock_irqsave(&vc->lock, flags); 2112 est = vc->estimator; 2113 if (!est) 2114 goto out; 2115 2116 ncells = est->cells; 2117 2118 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2119 est->last_cells = ncells; 2120 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2121 est->cps = (est->avcps + 0x1f) >> 5; 2122 2123 cps = est->cps; 2124 if (cps < (est->maxcps >> 4)) 2125 cps = est->maxcps >> 4; 2126 2127 lacr = idt77252_rate_logindex(card, cps); 2128 if (lacr > vc->max_er) 2129 lacr = vc->max_er; 2130 2131 if (lacr != vc->lacr) { 2132 vc->lacr = lacr; 2133 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2134 } 2135 2136 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2137 add_timer(&est->timer); 2138 2139 out: 2140 spin_unlock_irqrestore(&vc->lock, flags); 2141 } 2142 2143 static struct rate_estimator * 2144 idt77252_init_est(struct vc_map *vc, int pcr) 2145 { 2146 struct rate_estimator *est; 2147 2148 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2149 if (!est) 2150 return NULL; 2151 est->maxcps = pcr < 0 ? -pcr : pcr; 2152 est->cps = est->maxcps; 2153 est->avcps = est->cps << 5; 2154 2155 est->interval = 2; /* XXX: make this configurable */ 2156 est->ewma_log = 2; /* XXX: make this configurable */ 2157 init_timer(&est->timer); 2158 est->timer.data = (unsigned long)vc; 2159 est->timer.function = idt77252_est_timer; 2160 2161 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2162 add_timer(&est->timer); 2163 2164 return est; 2165 } 2166 2167 static int 2168 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2169 struct atm_vcc *vcc, struct atm_qos *qos) 2170 { 2171 int tst_free, tst_used, tst_entries; 2172 unsigned long tmpl, modl; 2173 int tcr, tcra; 2174 2175 if ((qos->txtp.max_pcr == 0) && 2176 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2177 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2178 card->name); 2179 return -EINVAL; 2180 } 2181 2182 tst_used = 0; 2183 tst_free = card->tst_free; 2184 if (test_bit(VCF_TX, &vc->flags)) 2185 tst_used = vc->ntste; 2186 tst_free += tst_used; 2187 2188 tcr = atm_pcr_goal(&qos->txtp); 2189 tcra = tcr >= 0 ? tcr : -tcr; 2190 2191 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2192 2193 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2194 modl = tmpl % (unsigned long)card->utopia_pcr; 2195 2196 tst_entries = (int) (tmpl / card->utopia_pcr); 2197 if (tcr > 0) { 2198 if (modl > 0) 2199 tst_entries++; 2200 } else if (tcr == 0) { 2201 tst_entries = tst_free - SAR_TST_RESERVED; 2202 if (tst_entries <= 0) { 2203 printk("%s: no CBR bandwidth free.\n", card->name); 2204 return -ENOSR; 2205 } 2206 } 2207 2208 if (tst_entries == 0) { 2209 printk("%s: selected CBR bandwidth < granularity.\n", 2210 card->name); 2211 return -EINVAL; 2212 } 2213 2214 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2215 printk("%s: not enough CBR bandwidth free.\n", card->name); 2216 return -ENOSR; 2217 } 2218 2219 vc->ntste = tst_entries; 2220 2221 card->tst_free = tst_free - tst_entries; 2222 if (test_bit(VCF_TX, &vc->flags)) { 2223 if (tst_used == tst_entries) 2224 return 0; 2225 2226 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2227 card->name, tst_used, tst_entries); 2228 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2229 return 0; 2230 } 2231 2232 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2233 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2234 return 0; 2235 } 2236 2237 static int 2238 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2239 struct atm_vcc *vcc, struct atm_qos *qos) 2240 { 2241 unsigned long flags; 2242 int tcr; 2243 2244 spin_lock_irqsave(&vc->lock, flags); 2245 if (vc->estimator) { 2246 del_timer(&vc->estimator->timer); 2247 kfree(vc->estimator); 2248 vc->estimator = NULL; 2249 } 2250 spin_unlock_irqrestore(&vc->lock, flags); 2251 2252 tcr = atm_pcr_goal(&qos->txtp); 2253 if (tcr == 0) 2254 tcr = card->link_pcr; 2255 2256 vc->estimator = idt77252_init_est(vc, tcr); 2257 2258 vc->class = SCHED_UBR; 2259 vc->init_er = idt77252_rate_logindex(card, tcr); 2260 vc->lacr = vc->init_er; 2261 if (tcr < 0) 2262 vc->max_er = vc->init_er; 2263 else 2264 vc->max_er = 0xff; 2265 2266 return 0; 2267 } 2268 2269 static int 2270 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2271 struct atm_vcc *vcc, struct atm_qos *qos) 2272 { 2273 int error; 2274 2275 if (test_bit(VCF_TX, &vc->flags)) 2276 return -EBUSY; 2277 2278 switch (qos->txtp.traffic_class) { 2279 case ATM_CBR: 2280 vc->class = SCHED_CBR; 2281 break; 2282 2283 case ATM_UBR: 2284 vc->class = SCHED_UBR; 2285 break; 2286 2287 case ATM_VBR: 2288 case ATM_ABR: 2289 default: 2290 return -EPROTONOSUPPORT; 2291 } 2292 2293 vc->scq = alloc_scq(card, vc->class); 2294 if (!vc->scq) { 2295 printk("%s: can't get SCQ.\n", card->name); 2296 return -ENOMEM; 2297 } 2298 2299 vc->scq->scd = get_free_scd(card, vc); 2300 if (vc->scq->scd == 0) { 2301 printk("%s: no SCD available.\n", card->name); 2302 free_scq(card, vc->scq); 2303 return -ENOMEM; 2304 } 2305 2306 fill_scd(card, vc->scq, vc->class); 2307 2308 if (set_tct(card, vc)) { 2309 printk("%s: class %d not supported.\n", 2310 card->name, qos->txtp.traffic_class); 2311 2312 card->scd2vc[vc->scd_index] = NULL; 2313 free_scq(card, vc->scq); 2314 return -EPROTONOSUPPORT; 2315 } 2316 2317 switch (vc->class) { 2318 case SCHED_CBR: 2319 error = idt77252_init_cbr(card, vc, vcc, qos); 2320 if (error) { 2321 card->scd2vc[vc->scd_index] = NULL; 2322 free_scq(card, vc->scq); 2323 return error; 2324 } 2325 2326 clear_bit(VCF_IDLE, &vc->flags); 2327 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2328 break; 2329 2330 case SCHED_UBR: 2331 error = idt77252_init_ubr(card, vc, vcc, qos); 2332 if (error) { 2333 card->scd2vc[vc->scd_index] = NULL; 2334 free_scq(card, vc->scq); 2335 return error; 2336 } 2337 2338 set_bit(VCF_IDLE, &vc->flags); 2339 break; 2340 } 2341 2342 vc->tx_vcc = vcc; 2343 set_bit(VCF_TX, &vc->flags); 2344 return 0; 2345 } 2346 2347 static int 2348 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2349 struct atm_vcc *vcc, struct atm_qos *qos) 2350 { 2351 unsigned long flags; 2352 unsigned long addr; 2353 u32 rcte = 0; 2354 2355 if (test_bit(VCF_RX, &vc->flags)) 2356 return -EBUSY; 2357 2358 vc->rx_vcc = vcc; 2359 set_bit(VCF_RX, &vc->flags); 2360 2361 if ((vcc->vci == 3) || (vcc->vci == 4)) 2362 return 0; 2363 2364 flush_rx_pool(card, &vc->rcv.rx_pool); 2365 2366 rcte |= SAR_RCTE_CONNECTOPEN; 2367 rcte |= SAR_RCTE_RAWCELLINTEN; 2368 2369 switch (qos->aal) { 2370 case ATM_AAL0: 2371 rcte |= SAR_RCTE_RCQ; 2372 break; 2373 case ATM_AAL1: 2374 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2375 break; 2376 case ATM_AAL34: 2377 rcte |= SAR_RCTE_AAL34; 2378 break; 2379 case ATM_AAL5: 2380 rcte |= SAR_RCTE_AAL5; 2381 break; 2382 default: 2383 rcte |= SAR_RCTE_RCQ; 2384 break; 2385 } 2386 2387 if (qos->aal != ATM_AAL5) 2388 rcte |= SAR_RCTE_FBP_1; 2389 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2390 rcte |= SAR_RCTE_FBP_3; 2391 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2392 rcte |= SAR_RCTE_FBP_2; 2393 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2394 rcte |= SAR_RCTE_FBP_1; 2395 else 2396 rcte |= SAR_RCTE_FBP_01; 2397 2398 addr = card->rct_base + (vc->index << 2); 2399 2400 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2401 write_sram(card, addr, rcte); 2402 2403 spin_lock_irqsave(&card->cmd_lock, flags); 2404 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2405 waitfor_idle(card); 2406 spin_unlock_irqrestore(&card->cmd_lock, flags); 2407 2408 return 0; 2409 } 2410 2411 static int 2412 idt77252_open(struct atm_vcc *vcc) 2413 { 2414 struct atm_dev *dev = vcc->dev; 2415 struct idt77252_dev *card = dev->dev_data; 2416 struct vc_map *vc; 2417 unsigned int index; 2418 unsigned int inuse; 2419 int error; 2420 int vci = vcc->vci; 2421 short vpi = vcc->vpi; 2422 2423 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2424 return 0; 2425 2426 if (vpi >= (1 << card->vpibits)) { 2427 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2428 return -EINVAL; 2429 } 2430 2431 if (vci >= (1 << card->vcibits)) { 2432 printk("%s: unsupported VCI: %d\n", card->name, vci); 2433 return -EINVAL; 2434 } 2435 2436 set_bit(ATM_VF_ADDR, &vcc->flags); 2437 2438 mutex_lock(&card->mutex); 2439 2440 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2441 2442 switch (vcc->qos.aal) { 2443 case ATM_AAL0: 2444 case ATM_AAL1: 2445 case ATM_AAL5: 2446 break; 2447 default: 2448 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2449 mutex_unlock(&card->mutex); 2450 return -EPROTONOSUPPORT; 2451 } 2452 2453 index = VPCI2VC(card, vpi, vci); 2454 if (!card->vcs[index]) { 2455 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2456 if (!card->vcs[index]) { 2457 printk("%s: can't alloc vc in open()\n", card->name); 2458 mutex_unlock(&card->mutex); 2459 return -ENOMEM; 2460 } 2461 card->vcs[index]->card = card; 2462 card->vcs[index]->index = index; 2463 2464 spin_lock_init(&card->vcs[index]->lock); 2465 } 2466 vc = card->vcs[index]; 2467 2468 vcc->dev_data = vc; 2469 2470 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2471 card->name, vc->index, vcc->vpi, vcc->vci, 2472 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2473 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2474 vcc->qos.rxtp.max_sdu); 2475 2476 inuse = 0; 2477 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2478 test_bit(VCF_TX, &vc->flags)) 2479 inuse = 1; 2480 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2481 test_bit(VCF_RX, &vc->flags)) 2482 inuse += 2; 2483 2484 if (inuse) { 2485 printk("%s: %s vci already in use.\n", card->name, 2486 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2487 mutex_unlock(&card->mutex); 2488 return -EADDRINUSE; 2489 } 2490 2491 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2492 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2493 if (error) { 2494 mutex_unlock(&card->mutex); 2495 return error; 2496 } 2497 } 2498 2499 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2500 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2501 if (error) { 2502 mutex_unlock(&card->mutex); 2503 return error; 2504 } 2505 } 2506 2507 set_bit(ATM_VF_READY, &vcc->flags); 2508 2509 mutex_unlock(&card->mutex); 2510 return 0; 2511 } 2512 2513 static void 2514 idt77252_close(struct atm_vcc *vcc) 2515 { 2516 struct atm_dev *dev = vcc->dev; 2517 struct idt77252_dev *card = dev->dev_data; 2518 struct vc_map *vc = vcc->dev_data; 2519 unsigned long flags; 2520 unsigned long addr; 2521 unsigned long timeout; 2522 2523 mutex_lock(&card->mutex); 2524 2525 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2526 card->name, vc->index, vcc->vpi, vcc->vci); 2527 2528 clear_bit(ATM_VF_READY, &vcc->flags); 2529 2530 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2531 2532 spin_lock_irqsave(&vc->lock, flags); 2533 clear_bit(VCF_RX, &vc->flags); 2534 vc->rx_vcc = NULL; 2535 spin_unlock_irqrestore(&vc->lock, flags); 2536 2537 if ((vcc->vci == 3) || (vcc->vci == 4)) 2538 goto done; 2539 2540 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2541 2542 spin_lock_irqsave(&card->cmd_lock, flags); 2543 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2544 waitfor_idle(card); 2545 spin_unlock_irqrestore(&card->cmd_lock, flags); 2546 2547 if (vc->rcv.rx_pool.count) { 2548 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2549 card->name); 2550 2551 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2552 } 2553 } 2554 2555 done: 2556 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2557 2558 spin_lock_irqsave(&vc->lock, flags); 2559 clear_bit(VCF_TX, &vc->flags); 2560 clear_bit(VCF_IDLE, &vc->flags); 2561 clear_bit(VCF_RSV, &vc->flags); 2562 vc->tx_vcc = NULL; 2563 2564 if (vc->estimator) { 2565 del_timer(&vc->estimator->timer); 2566 kfree(vc->estimator); 2567 vc->estimator = NULL; 2568 } 2569 spin_unlock_irqrestore(&vc->lock, flags); 2570 2571 timeout = 5 * 1000; 2572 while (atomic_read(&vc->scq->used) > 0) { 2573 timeout = msleep_interruptible(timeout); 2574 if (!timeout) 2575 break; 2576 } 2577 if (!timeout) 2578 printk("%s: SCQ drain timeout: %u used\n", 2579 card->name, atomic_read(&vc->scq->used)); 2580 2581 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2582 clear_scd(card, vc->scq, vc->class); 2583 2584 if (vc->class == SCHED_CBR) { 2585 clear_tst(card, vc); 2586 card->tst_free += vc->ntste; 2587 vc->ntste = 0; 2588 } 2589 2590 card->scd2vc[vc->scd_index] = NULL; 2591 free_scq(card, vc->scq); 2592 } 2593 2594 mutex_unlock(&card->mutex); 2595 } 2596 2597 static int 2598 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2599 { 2600 struct atm_dev *dev = vcc->dev; 2601 struct idt77252_dev *card = dev->dev_data; 2602 struct vc_map *vc = vcc->dev_data; 2603 int error = 0; 2604 2605 mutex_lock(&card->mutex); 2606 2607 if (qos->txtp.traffic_class != ATM_NONE) { 2608 if (!test_bit(VCF_TX, &vc->flags)) { 2609 error = idt77252_init_tx(card, vc, vcc, qos); 2610 if (error) 2611 goto out; 2612 } else { 2613 switch (qos->txtp.traffic_class) { 2614 case ATM_CBR: 2615 error = idt77252_init_cbr(card, vc, vcc, qos); 2616 if (error) 2617 goto out; 2618 break; 2619 2620 case ATM_UBR: 2621 error = idt77252_init_ubr(card, vc, vcc, qos); 2622 if (error) 2623 goto out; 2624 2625 if (!test_bit(VCF_IDLE, &vc->flags)) { 2626 writel(TCMDQ_LACR | (vc->lacr << 16) | 2627 vc->index, SAR_REG_TCMDQ); 2628 } 2629 break; 2630 2631 case ATM_VBR: 2632 case ATM_ABR: 2633 error = -EOPNOTSUPP; 2634 goto out; 2635 } 2636 } 2637 } 2638 2639 if ((qos->rxtp.traffic_class != ATM_NONE) && 2640 !test_bit(VCF_RX, &vc->flags)) { 2641 error = idt77252_init_rx(card, vc, vcc, qos); 2642 if (error) 2643 goto out; 2644 } 2645 2646 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2647 2648 set_bit(ATM_VF_HASQOS, &vcc->flags); 2649 2650 out: 2651 mutex_unlock(&card->mutex); 2652 return error; 2653 } 2654 2655 static int 2656 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2657 { 2658 struct idt77252_dev *card = dev->dev_data; 2659 int i, left; 2660 2661 left = (int) *pos; 2662 if (!left--) 2663 return sprintf(page, "IDT77252 Interrupts:\n"); 2664 if (!left--) 2665 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2666 if (!left--) 2667 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2668 if (!left--) 2669 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2670 if (!left--) 2671 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2672 if (!left--) 2673 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2674 if (!left--) 2675 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2676 if (!left--) 2677 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2678 if (!left--) 2679 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2680 if (!left--) 2681 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2682 if (!left--) 2683 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2684 if (!left--) 2685 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2686 if (!left--) 2687 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2688 if (!left--) 2689 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2690 if (!left--) 2691 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2692 2693 for (i = 0; i < card->tct_size; i++) { 2694 unsigned long tct; 2695 struct atm_vcc *vcc; 2696 struct vc_map *vc; 2697 char *p; 2698 2699 vc = card->vcs[i]; 2700 if (!vc) 2701 continue; 2702 2703 vcc = NULL; 2704 if (vc->tx_vcc) 2705 vcc = vc->tx_vcc; 2706 if (!vcc) 2707 continue; 2708 if (left--) 2709 continue; 2710 2711 p = page; 2712 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2713 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2714 2715 for (i = 0; i < 8; i++) 2716 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2717 p += sprintf(p, "\n"); 2718 return p - page; 2719 } 2720 return 0; 2721 } 2722 2723 /*****************************************************************************/ 2724 /* */ 2725 /* Interrupt handler */ 2726 /* */ 2727 /*****************************************************************************/ 2728 2729 static void 2730 idt77252_collect_stat(struct idt77252_dev *card) 2731 { 2732 u32 cdc, vpec, icc; 2733 2734 cdc = readl(SAR_REG_CDC); 2735 vpec = readl(SAR_REG_VPEC); 2736 icc = readl(SAR_REG_ICC); 2737 2738 #ifdef NOTDEF 2739 printk("%s:", card->name); 2740 2741 if (cdc & 0x7f0000) { 2742 char *s = ""; 2743 2744 printk(" ["); 2745 if (cdc & (1 << 22)) { 2746 printk("%sRM ID", s); 2747 s = " | "; 2748 } 2749 if (cdc & (1 << 21)) { 2750 printk("%sCON TAB", s); 2751 s = " | "; 2752 } 2753 if (cdc & (1 << 20)) { 2754 printk("%sNO FB", s); 2755 s = " | "; 2756 } 2757 if (cdc & (1 << 19)) { 2758 printk("%sOAM CRC", s); 2759 s = " | "; 2760 } 2761 if (cdc & (1 << 18)) { 2762 printk("%sRM CRC", s); 2763 s = " | "; 2764 } 2765 if (cdc & (1 << 17)) { 2766 printk("%sRM FIFO", s); 2767 s = " | "; 2768 } 2769 if (cdc & (1 << 16)) { 2770 printk("%sRX FIFO", s); 2771 s = " | "; 2772 } 2773 printk("]"); 2774 } 2775 2776 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2777 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2778 #endif 2779 } 2780 2781 static irqreturn_t 2782 idt77252_interrupt(int irq, void *dev_id) 2783 { 2784 struct idt77252_dev *card = dev_id; 2785 u32 stat; 2786 2787 stat = readl(SAR_REG_STAT) & 0xffff; 2788 if (!stat) /* no interrupt for us */ 2789 return IRQ_NONE; 2790 2791 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2792 printk("%s: Re-entering irq_handler()\n", card->name); 2793 goto out; 2794 } 2795 2796 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2797 2798 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2799 INTPRINTK("%s: TSIF\n", card->name); 2800 card->irqstat[15]++; 2801 idt77252_tx(card); 2802 } 2803 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2804 INTPRINTK("%s: TXICP\n", card->name); 2805 card->irqstat[14]++; 2806 #ifdef CONFIG_ATM_IDT77252_DEBUG 2807 idt77252_tx_dump(card); 2808 #endif 2809 } 2810 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2811 INTPRINTK("%s: TSQF\n", card->name); 2812 card->irqstat[12]++; 2813 idt77252_tx(card); 2814 } 2815 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2816 INTPRINTK("%s: TMROF\n", card->name); 2817 card->irqstat[11]++; 2818 idt77252_collect_stat(card); 2819 } 2820 2821 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2822 INTPRINTK("%s: EPDU\n", card->name); 2823 card->irqstat[5]++; 2824 idt77252_rx(card); 2825 } 2826 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2827 INTPRINTK("%s: RSQAF\n", card->name); 2828 card->irqstat[1]++; 2829 idt77252_rx(card); 2830 } 2831 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2832 INTPRINTK("%s: RSQF\n", card->name); 2833 card->irqstat[6]++; 2834 idt77252_rx(card); 2835 } 2836 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2837 INTPRINTK("%s: RAWCF\n", card->name); 2838 card->irqstat[4]++; 2839 idt77252_rx_raw(card); 2840 } 2841 2842 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2843 INTPRINTK("%s: PHYI", card->name); 2844 card->irqstat[10]++; 2845 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2846 card->atmdev->phy->interrupt(card->atmdev); 2847 } 2848 2849 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2850 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2851 2852 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2853 2854 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2855 2856 if (stat & SAR_STAT_FBQ0A) 2857 card->irqstat[2]++; 2858 if (stat & SAR_STAT_FBQ1A) 2859 card->irqstat[3]++; 2860 if (stat & SAR_STAT_FBQ2A) 2861 card->irqstat[7]++; 2862 if (stat & SAR_STAT_FBQ3A) 2863 card->irqstat[8]++; 2864 2865 schedule_work(&card->tqueue); 2866 } 2867 2868 out: 2869 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2870 return IRQ_HANDLED; 2871 } 2872 2873 static void 2874 idt77252_softint(struct work_struct *work) 2875 { 2876 struct idt77252_dev *card = 2877 container_of(work, struct idt77252_dev, tqueue); 2878 u32 stat; 2879 int done; 2880 2881 for (done = 1; ; done = 1) { 2882 stat = readl(SAR_REG_STAT) >> 16; 2883 2884 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2885 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2886 done = 0; 2887 } 2888 2889 stat >>= 4; 2890 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2891 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2892 done = 0; 2893 } 2894 2895 stat >>= 4; 2896 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2897 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2898 done = 0; 2899 } 2900 2901 stat >>= 4; 2902 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2903 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2904 done = 0; 2905 } 2906 2907 if (done) 2908 break; 2909 } 2910 2911 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2912 } 2913 2914 2915 static int 2916 open_card_oam(struct idt77252_dev *card) 2917 { 2918 unsigned long flags; 2919 unsigned long addr; 2920 struct vc_map *vc; 2921 int vpi, vci; 2922 int index; 2923 u32 rcte; 2924 2925 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2926 for (vci = 3; vci < 5; vci++) { 2927 index = VPCI2VC(card, vpi, vci); 2928 2929 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2930 if (!vc) { 2931 printk("%s: can't alloc vc\n", card->name); 2932 return -ENOMEM; 2933 } 2934 vc->index = index; 2935 card->vcs[index] = vc; 2936 2937 flush_rx_pool(card, &vc->rcv.rx_pool); 2938 2939 rcte = SAR_RCTE_CONNECTOPEN | 2940 SAR_RCTE_RAWCELLINTEN | 2941 SAR_RCTE_RCQ | 2942 SAR_RCTE_FBP_1; 2943 2944 addr = card->rct_base + (vc->index << 2); 2945 write_sram(card, addr, rcte); 2946 2947 spin_lock_irqsave(&card->cmd_lock, flags); 2948 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2949 SAR_REG_CMD); 2950 waitfor_idle(card); 2951 spin_unlock_irqrestore(&card->cmd_lock, flags); 2952 } 2953 } 2954 2955 return 0; 2956 } 2957 2958 static void 2959 close_card_oam(struct idt77252_dev *card) 2960 { 2961 unsigned long flags; 2962 unsigned long addr; 2963 struct vc_map *vc; 2964 int vpi, vci; 2965 int index; 2966 2967 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2968 for (vci = 3; vci < 5; vci++) { 2969 index = VPCI2VC(card, vpi, vci); 2970 vc = card->vcs[index]; 2971 2972 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2973 2974 spin_lock_irqsave(&card->cmd_lock, flags); 2975 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2976 SAR_REG_CMD); 2977 waitfor_idle(card); 2978 spin_unlock_irqrestore(&card->cmd_lock, flags); 2979 2980 if (vc->rcv.rx_pool.count) { 2981 DPRINTK("%s: closing a VC " 2982 "with pending rx buffers.\n", 2983 card->name); 2984 2985 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2986 } 2987 } 2988 } 2989 } 2990 2991 static int 2992 open_card_ubr0(struct idt77252_dev *card) 2993 { 2994 struct vc_map *vc; 2995 2996 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2997 if (!vc) { 2998 printk("%s: can't alloc vc\n", card->name); 2999 return -ENOMEM; 3000 } 3001 card->vcs[0] = vc; 3002 vc->class = SCHED_UBR0; 3003 3004 vc->scq = alloc_scq(card, vc->class); 3005 if (!vc->scq) { 3006 printk("%s: can't get SCQ.\n", card->name); 3007 return -ENOMEM; 3008 } 3009 3010 card->scd2vc[0] = vc; 3011 vc->scd_index = 0; 3012 vc->scq->scd = card->scd_base; 3013 3014 fill_scd(card, vc->scq, vc->class); 3015 3016 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3017 write_sram(card, card->tct_base + 1, 0); 3018 write_sram(card, card->tct_base + 2, 0); 3019 write_sram(card, card->tct_base + 3, 0); 3020 write_sram(card, card->tct_base + 4, 0); 3021 write_sram(card, card->tct_base + 5, 0); 3022 write_sram(card, card->tct_base + 6, 0); 3023 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3024 3025 clear_bit(VCF_IDLE, &vc->flags); 3026 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3027 return 0; 3028 } 3029 3030 static int 3031 idt77252_dev_open(struct idt77252_dev *card) 3032 { 3033 u32 conf; 3034 3035 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3036 printk("%s: SAR not yet initialized.\n", card->name); 3037 return -1; 3038 } 3039 3040 conf = SAR_CFG_RXPTH| /* enable receive path */ 3041 SAR_RX_DELAY | /* interrupt on complete PDU */ 3042 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3043 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3044 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3045 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3046 SAR_CFG_TXEN | /* transmit operation enable */ 3047 SAR_CFG_TXINT | /* interrupt on transmit status */ 3048 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3049 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3050 SAR_CFG_PHYIE /* enable PHY interrupts */ 3051 ; 3052 3053 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 3054 /* Test RAW cell receive. */ 3055 conf |= SAR_CFG_VPECA; 3056 #endif 3057 3058 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3059 3060 if (open_card_oam(card)) { 3061 printk("%s: Error initializing OAM.\n", card->name); 3062 return -1; 3063 } 3064 3065 if (open_card_ubr0(card)) { 3066 printk("%s: Error initializing UBR0.\n", card->name); 3067 return -1; 3068 } 3069 3070 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3071 return 0; 3072 } 3073 3074 static void idt77252_dev_close(struct atm_dev *dev) 3075 { 3076 struct idt77252_dev *card = dev->dev_data; 3077 u32 conf; 3078 3079 close_card_oam(card); 3080 3081 conf = SAR_CFG_RXPTH | /* enable receive path */ 3082 SAR_RX_DELAY | /* interrupt on complete PDU */ 3083 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3084 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3085 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3086 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3087 SAR_CFG_TXEN | /* transmit operation enable */ 3088 SAR_CFG_TXINT | /* interrupt on transmit status */ 3089 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3090 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3091 ; 3092 3093 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3094 3095 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3096 } 3097 3098 3099 /*****************************************************************************/ 3100 /* */ 3101 /* Initialisation and Deinitialization of IDT77252 */ 3102 /* */ 3103 /*****************************************************************************/ 3104 3105 3106 static void 3107 deinit_card(struct idt77252_dev *card) 3108 { 3109 struct sk_buff *skb; 3110 int i, j; 3111 3112 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3113 printk("%s: SAR not yet initialized.\n", card->name); 3114 return; 3115 } 3116 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3117 3118 writel(0, SAR_REG_CFG); 3119 3120 if (card->atmdev) 3121 atm_dev_deregister(card->atmdev); 3122 3123 for (i = 0; i < 4; i++) { 3124 for (j = 0; j < FBQ_SIZE; j++) { 3125 skb = card->sbpool[i].skb[j]; 3126 if (skb) { 3127 pci_unmap_single(card->pcidev, 3128 IDT77252_PRV_PADDR(skb), 3129 (skb_end_pointer(skb) - 3130 skb->data), 3131 PCI_DMA_FROMDEVICE); 3132 card->sbpool[i].skb[j] = NULL; 3133 dev_kfree_skb(skb); 3134 } 3135 } 3136 } 3137 3138 vfree(card->soft_tst); 3139 3140 vfree(card->scd2vc); 3141 3142 vfree(card->vcs); 3143 3144 if (card->raw_cell_hnd) { 3145 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3146 card->raw_cell_hnd, card->raw_cell_paddr); 3147 } 3148 3149 if (card->rsq.base) { 3150 DIPRINTK("%s: Release RSQ ...\n", card->name); 3151 deinit_rsq(card); 3152 } 3153 3154 if (card->tsq.base) { 3155 DIPRINTK("%s: Release TSQ ...\n", card->name); 3156 deinit_tsq(card); 3157 } 3158 3159 DIPRINTK("idt77252: Release IRQ.\n"); 3160 free_irq(card->pcidev->irq, card); 3161 3162 for (i = 0; i < 4; i++) { 3163 if (card->fbq[i]) 3164 iounmap(card->fbq[i]); 3165 } 3166 3167 if (card->membase) 3168 iounmap(card->membase); 3169 3170 clear_bit(IDT77252_BIT_INIT, &card->flags); 3171 DIPRINTK("%s: Card deinitialized.\n", card->name); 3172 } 3173 3174 3175 static int __devinit 3176 init_sram(struct idt77252_dev *card) 3177 { 3178 int i; 3179 3180 for (i = 0; i < card->sramsize; i += 4) 3181 write_sram(card, (i >> 2), 0); 3182 3183 /* set SRAM layout for THIS card */ 3184 if (card->sramsize == (512 * 1024)) { 3185 card->tct_base = SAR_SRAM_TCT_128_BASE; 3186 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3187 / SAR_SRAM_TCT_SIZE; 3188 card->rct_base = SAR_SRAM_RCT_128_BASE; 3189 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3190 / SAR_SRAM_RCT_SIZE; 3191 card->rt_base = SAR_SRAM_RT_128_BASE; 3192 card->scd_base = SAR_SRAM_SCD_128_BASE; 3193 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3194 / SAR_SRAM_SCD_SIZE; 3195 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3196 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3197 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3198 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3199 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3200 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3201 card->fifo_size = SAR_RXFD_SIZE_32K; 3202 } else { 3203 card->tct_base = SAR_SRAM_TCT_32_BASE; 3204 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3205 / SAR_SRAM_TCT_SIZE; 3206 card->rct_base = SAR_SRAM_RCT_32_BASE; 3207 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3208 / SAR_SRAM_RCT_SIZE; 3209 card->rt_base = SAR_SRAM_RT_32_BASE; 3210 card->scd_base = SAR_SRAM_SCD_32_BASE; 3211 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3212 / SAR_SRAM_SCD_SIZE; 3213 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3214 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3215 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3216 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3217 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3218 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3219 card->fifo_size = SAR_RXFD_SIZE_4K; 3220 } 3221 3222 /* Initialize TCT */ 3223 for (i = 0; i < card->tct_size; i++) { 3224 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3225 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3232 } 3233 3234 /* Initialize RCT */ 3235 for (i = 0; i < card->rct_size; i++) { 3236 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3237 (u32) SAR_RCTE_RAWCELLINTEN); 3238 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3239 (u32) 0); 3240 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3241 (u32) 0); 3242 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3243 (u32) 0xffffffff); 3244 } 3245 3246 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3247 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3248 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3249 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3250 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3251 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3252 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3253 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3254 3255 /* Initialize rate table */ 3256 for (i = 0; i < 256; i++) { 3257 write_sram(card, card->rt_base + i, log_to_rate[i]); 3258 } 3259 3260 for (i = 0; i < 128; i++) { 3261 unsigned int tmp; 3262 3263 tmp = rate_to_log[(i << 2) + 0] << 0; 3264 tmp |= rate_to_log[(i << 2) + 1] << 8; 3265 tmp |= rate_to_log[(i << 2) + 2] << 16; 3266 tmp |= rate_to_log[(i << 2) + 3] << 24; 3267 write_sram(card, card->rt_base + 256 + i, tmp); 3268 } 3269 3270 #if 0 /* Fill RDF and AIR tables. */ 3271 for (i = 0; i < 128; i++) { 3272 unsigned int tmp; 3273 3274 tmp = RDF[0][(i << 1) + 0] << 16; 3275 tmp |= RDF[0][(i << 1) + 1] << 0; 3276 write_sram(card, card->rt_base + 512 + i, tmp); 3277 } 3278 3279 for (i = 0; i < 128; i++) { 3280 unsigned int tmp; 3281 3282 tmp = AIR[0][(i << 1) + 0] << 16; 3283 tmp |= AIR[0][(i << 1) + 1] << 0; 3284 write_sram(card, card->rt_base + 640 + i, tmp); 3285 } 3286 #endif 3287 3288 IPRINTK("%s: initialize rate table ...\n", card->name); 3289 writel(card->rt_base << 2, SAR_REG_RTBL); 3290 3291 /* Initialize TSTs */ 3292 IPRINTK("%s: initialize TST ...\n", card->name); 3293 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3294 3295 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3296 write_sram(card, i, TSTE_OPC_VAR); 3297 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3298 idt77252_sram_write_errors = 1; 3299 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3300 idt77252_sram_write_errors = 0; 3301 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3302 write_sram(card, i, TSTE_OPC_VAR); 3303 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3304 idt77252_sram_write_errors = 1; 3305 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3306 idt77252_sram_write_errors = 0; 3307 3308 card->tst_index = 0; 3309 writel(card->tst[0] << 2, SAR_REG_TSTB); 3310 3311 /* Initialize ABRSTD and Receive FIFO */ 3312 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3313 writel(card->abrst_size | (card->abrst_base << 2), 3314 SAR_REG_ABRSTD); 3315 3316 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3317 writel(card->fifo_size | (card->fifo_base << 2), 3318 SAR_REG_RXFD); 3319 3320 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3321 return 0; 3322 } 3323 3324 static int __devinit 3325 init_card(struct atm_dev *dev) 3326 { 3327 struct idt77252_dev *card = dev->dev_data; 3328 struct pci_dev *pcidev = card->pcidev; 3329 unsigned long tmpl, modl; 3330 unsigned int linkrate, rsvdcr; 3331 unsigned int tst_entries; 3332 struct net_device *tmp; 3333 char tname[10]; 3334 3335 u32 size; 3336 u_char pci_byte; 3337 u32 conf; 3338 int i, k; 3339 3340 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3341 printk("Error: SAR already initialized.\n"); 3342 return -1; 3343 } 3344 3345 /*****************************************************************/ 3346 /* P C I C O N F I G U R A T I O N */ 3347 /*****************************************************************/ 3348 3349 /* Set PCI Retry-Timeout and TRDY timeout */ 3350 IPRINTK("%s: Checking PCI retries.\n", card->name); 3351 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3352 printk("%s: can't read PCI retry timeout.\n", card->name); 3353 deinit_card(card); 3354 return -1; 3355 } 3356 if (pci_byte != 0) { 3357 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3358 card->name, pci_byte); 3359 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3360 printk("%s: can't set PCI retry timeout.\n", 3361 card->name); 3362 deinit_card(card); 3363 return -1; 3364 } 3365 } 3366 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3367 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3368 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3369 deinit_card(card); 3370 return -1; 3371 } 3372 if (pci_byte != 0) { 3373 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3374 card->name, pci_byte); 3375 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3376 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3377 deinit_card(card); 3378 return -1; 3379 } 3380 } 3381 /* Reset Timer register */ 3382 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3383 printk("%s: resetting timer overflow.\n", card->name); 3384 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3385 } 3386 IPRINTK("%s: Request IRQ ... ", card->name); 3387 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3388 card->name, card) != 0) { 3389 printk("%s: can't allocate IRQ.\n", card->name); 3390 deinit_card(card); 3391 return -1; 3392 } 3393 IPRINTK("got %d.\n", pcidev->irq); 3394 3395 /*****************************************************************/ 3396 /* C H E C K A N D I N I T S R A M */ 3397 /*****************************************************************/ 3398 3399 IPRINTK("%s: Initializing SRAM\n", card->name); 3400 3401 /* preset size of connecton table, so that init_sram() knows about it */ 3402 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3403 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3404 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3405 #ifndef ATM_IDT77252_SEND_IDLE 3406 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3407 #endif 3408 0; 3409 3410 if (card->sramsize == (512 * 1024)) 3411 conf |= SAR_CFG_CNTBL_1k; 3412 else 3413 conf |= SAR_CFG_CNTBL_512; 3414 3415 switch (vpibits) { 3416 case 0: 3417 conf |= SAR_CFG_VPVCS_0; 3418 break; 3419 default: 3420 case 1: 3421 conf |= SAR_CFG_VPVCS_1; 3422 break; 3423 case 2: 3424 conf |= SAR_CFG_VPVCS_2; 3425 break; 3426 case 8: 3427 conf |= SAR_CFG_VPVCS_8; 3428 break; 3429 } 3430 3431 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3432 3433 if (init_sram(card) < 0) 3434 return -1; 3435 3436 /********************************************************************/ 3437 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3438 /********************************************************************/ 3439 /* Initialize TSQ */ 3440 if (0 != init_tsq(card)) { 3441 deinit_card(card); 3442 return -1; 3443 } 3444 /* Initialize RSQ */ 3445 if (0 != init_rsq(card)) { 3446 deinit_card(card); 3447 return -1; 3448 } 3449 3450 card->vpibits = vpibits; 3451 if (card->sramsize == (512 * 1024)) { 3452 card->vcibits = 10 - card->vpibits; 3453 } else { 3454 card->vcibits = 9 - card->vpibits; 3455 } 3456 3457 card->vcimask = 0; 3458 for (k = 0, i = 1; k < card->vcibits; k++) { 3459 card->vcimask |= i; 3460 i <<= 1; 3461 } 3462 3463 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3464 writel(0, SAR_REG_VPM); 3465 3466 /* Little Endian Order */ 3467 writel(0, SAR_REG_GP); 3468 3469 /* Initialize RAW Cell Handle Register */ 3470 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3471 &card->raw_cell_paddr); 3472 if (!card->raw_cell_hnd) { 3473 printk("%s: memory allocation failure.\n", card->name); 3474 deinit_card(card); 3475 return -1; 3476 } 3477 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3478 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3479 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3480 card->raw_cell_hnd); 3481 3482 size = sizeof(struct vc_map *) * card->tct_size; 3483 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3484 if (NULL == (card->vcs = vmalloc(size))) { 3485 printk("%s: memory allocation failure.\n", card->name); 3486 deinit_card(card); 3487 return -1; 3488 } 3489 memset(card->vcs, 0, size); 3490 3491 size = sizeof(struct vc_map *) * card->scd_size; 3492 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3493 card->name, size); 3494 if (NULL == (card->scd2vc = vmalloc(size))) { 3495 printk("%s: memory allocation failure.\n", card->name); 3496 deinit_card(card); 3497 return -1; 3498 } 3499 memset(card->scd2vc, 0, size); 3500 3501 size = sizeof(struct tst_info) * (card->tst_size - 2); 3502 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3503 card->name, size); 3504 if (NULL == (card->soft_tst = vmalloc(size))) { 3505 printk("%s: memory allocation failure.\n", card->name); 3506 deinit_card(card); 3507 return -1; 3508 } 3509 for (i = 0; i < card->tst_size - 2; i++) { 3510 card->soft_tst[i].tste = TSTE_OPC_VAR; 3511 card->soft_tst[i].vc = NULL; 3512 } 3513 3514 if (dev->phy == NULL) { 3515 printk("%s: No LT device defined.\n", card->name); 3516 deinit_card(card); 3517 return -1; 3518 } 3519 if (dev->phy->ioctl == NULL) { 3520 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3521 deinit_card(card); 3522 return -1; 3523 } 3524 3525 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3526 /* 3527 * this is a jhs hack to get around special functionality in the 3528 * phy driver for the atecom hardware; the functionality doesn't 3529 * exist in the linux atm suni driver 3530 * 3531 * it isn't the right way to do things, but as the guy from NIST 3532 * said, talking about their measurement of the fine structure 3533 * constant, "it's good enough for government work." 3534 */ 3535 linkrate = 149760000; 3536 #endif 3537 3538 card->link_pcr = (linkrate / 8 / 53); 3539 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3540 card->name, linkrate, card->link_pcr); 3541 3542 #ifdef ATM_IDT77252_SEND_IDLE 3543 card->utopia_pcr = card->link_pcr; 3544 #else 3545 card->utopia_pcr = (160000000 / 8 / 54); 3546 #endif 3547 3548 rsvdcr = 0; 3549 if (card->utopia_pcr > card->link_pcr) 3550 rsvdcr = card->utopia_pcr - card->link_pcr; 3551 3552 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3553 modl = tmpl % (unsigned long)card->utopia_pcr; 3554 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3555 if (modl) 3556 tst_entries++; 3557 card->tst_free -= tst_entries; 3558 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3559 3560 #ifdef HAVE_EEPROM 3561 idt77252_eeprom_init(card); 3562 printk("%s: EEPROM: %02x:", card->name, 3563 idt77252_eeprom_read_status(card)); 3564 3565 for (i = 0; i < 0x80; i++) { 3566 printk(" %02x", 3567 idt77252_eeprom_read_byte(card, i) 3568 ); 3569 } 3570 printk("\n"); 3571 #endif /* HAVE_EEPROM */ 3572 3573 /* 3574 * XXX: <hack> 3575 */ 3576 sprintf(tname, "eth%d", card->index); 3577 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3578 if (tmp) { 3579 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3580 3581 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3582 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3583 card->atmdev->esi[2], card->atmdev->esi[3], 3584 card->atmdev->esi[4], card->atmdev->esi[5]); 3585 } 3586 /* 3587 * XXX: </hack> 3588 */ 3589 3590 /* Set Maximum Deficit Count for now. */ 3591 writel(0xffff, SAR_REG_MDFCT); 3592 3593 set_bit(IDT77252_BIT_INIT, &card->flags); 3594 3595 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3596 return 0; 3597 } 3598 3599 3600 /*****************************************************************************/ 3601 /* */ 3602 /* Probing of IDT77252 ABR SAR */ 3603 /* */ 3604 /*****************************************************************************/ 3605 3606 3607 static int __devinit 3608 idt77252_preset(struct idt77252_dev *card) 3609 { 3610 u16 pci_command; 3611 3612 /*****************************************************************/ 3613 /* P C I C O N F I G U R A T I O N */ 3614 /*****************************************************************/ 3615 3616 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3617 card->name); 3618 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3619 printk("%s: can't read PCI_COMMAND.\n", card->name); 3620 deinit_card(card); 3621 return -1; 3622 } 3623 if (!(pci_command & PCI_COMMAND_IO)) { 3624 printk("%s: PCI_COMMAND: %04x (???)\n", 3625 card->name, pci_command); 3626 deinit_card(card); 3627 return (-1); 3628 } 3629 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3630 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3631 printk("%s: can't write PCI_COMMAND.\n", card->name); 3632 deinit_card(card); 3633 return -1; 3634 } 3635 /*****************************************************************/ 3636 /* G E N E R I C R E S E T */ 3637 /*****************************************************************/ 3638 3639 /* Software reset */ 3640 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3641 mdelay(1); 3642 writel(0, SAR_REG_CFG); 3643 3644 IPRINTK("%s: Software resetted.\n", card->name); 3645 return 0; 3646 } 3647 3648 3649 static unsigned long __devinit 3650 probe_sram(struct idt77252_dev *card) 3651 { 3652 u32 data, addr; 3653 3654 writel(0, SAR_REG_DR0); 3655 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3656 3657 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3658 writel(ATM_POISON, SAR_REG_DR0); 3659 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3660 3661 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3662 data = readl(SAR_REG_DR0); 3663 3664 if (data != 0) 3665 break; 3666 } 3667 3668 return addr * sizeof(u32); 3669 } 3670 3671 static int __devinit 3672 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3673 { 3674 static struct idt77252_dev **last = &idt77252_chain; 3675 static int index = 0; 3676 3677 unsigned long membase, srambase; 3678 struct idt77252_dev *card; 3679 struct atm_dev *dev; 3680 int i, err; 3681 3682 3683 if ((err = pci_enable_device(pcidev))) { 3684 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3685 return err; 3686 } 3687 3688 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3689 if (!card) { 3690 printk("idt77252-%d: can't allocate private data\n", index); 3691 err = -ENOMEM; 3692 goto err_out_disable_pdev; 3693 } 3694 card->revision = pcidev->revision; 3695 card->index = index; 3696 card->pcidev = pcidev; 3697 sprintf(card->name, "idt77252-%d", card->index); 3698 3699 INIT_WORK(&card->tqueue, idt77252_softint); 3700 3701 membase = pci_resource_start(pcidev, 1); 3702 srambase = pci_resource_start(pcidev, 2); 3703 3704 mutex_init(&card->mutex); 3705 spin_lock_init(&card->cmd_lock); 3706 spin_lock_init(&card->tst_lock); 3707 3708 init_timer(&card->tst_timer); 3709 card->tst_timer.data = (unsigned long)card; 3710 card->tst_timer.function = tst_timer; 3711 3712 /* Do the I/O remapping... */ 3713 card->membase = ioremap(membase, 1024); 3714 if (!card->membase) { 3715 printk("%s: can't ioremap() membase\n", card->name); 3716 err = -EIO; 3717 goto err_out_free_card; 3718 } 3719 3720 if (idt77252_preset(card)) { 3721 printk("%s: preset failed\n", card->name); 3722 err = -EIO; 3723 goto err_out_iounmap; 3724 } 3725 3726 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3727 if (!dev) { 3728 printk("%s: can't register atm device\n", card->name); 3729 err = -EIO; 3730 goto err_out_iounmap; 3731 } 3732 dev->dev_data = card; 3733 card->atmdev = dev; 3734 3735 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3736 suni_init(dev); 3737 if (!dev->phy) { 3738 printk("%s: can't init SUNI\n", card->name); 3739 err = -EIO; 3740 goto err_out_deinit_card; 3741 } 3742 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3743 3744 card->sramsize = probe_sram(card); 3745 3746 for (i = 0; i < 4; i++) { 3747 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3748 if (!card->fbq[i]) { 3749 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3750 err = -EIO; 3751 goto err_out_deinit_card; 3752 } 3753 } 3754 3755 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3756 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3757 'A' + card->revision - 1 : '?', membase, srambase, 3758 card->sramsize / 1024); 3759 3760 if (init_card(dev)) { 3761 printk("%s: init_card failed\n", card->name); 3762 err = -EIO; 3763 goto err_out_deinit_card; 3764 } 3765 3766 dev->ci_range.vpi_bits = card->vpibits; 3767 dev->ci_range.vci_bits = card->vcibits; 3768 dev->link_rate = card->link_pcr; 3769 3770 if (dev->phy->start) 3771 dev->phy->start(dev); 3772 3773 if (idt77252_dev_open(card)) { 3774 printk("%s: dev_open failed\n", card->name); 3775 err = -EIO; 3776 goto err_out_stop; 3777 } 3778 3779 *last = card; 3780 last = &card->next; 3781 index++; 3782 3783 return 0; 3784 3785 err_out_stop: 3786 if (dev->phy->stop) 3787 dev->phy->stop(dev); 3788 3789 err_out_deinit_card: 3790 deinit_card(card); 3791 3792 err_out_iounmap: 3793 iounmap(card->membase); 3794 3795 err_out_free_card: 3796 kfree(card); 3797 3798 err_out_disable_pdev: 3799 pci_disable_device(pcidev); 3800 return err; 3801 } 3802 3803 static struct pci_device_id idt77252_pci_tbl[] = 3804 { 3805 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3807 { 0, } 3808 }; 3809 3810 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3811 3812 static struct pci_driver idt77252_driver = { 3813 .name = "idt77252", 3814 .id_table = idt77252_pci_tbl, 3815 .probe = idt77252_init_one, 3816 }; 3817 3818 static int __init idt77252_init(void) 3819 { 3820 struct sk_buff *skb; 3821 3822 printk("%s: at %p\n", __func__, idt77252_init); 3823 3824 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3825 sizeof(struct idt77252_skb_prv)) { 3826 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3827 __func__, (unsigned long) sizeof(skb->cb), 3828 (unsigned long) sizeof(struct atm_skb_data) + 3829 sizeof(struct idt77252_skb_prv)); 3830 return -EIO; 3831 } 3832 3833 return pci_register_driver(&idt77252_driver); 3834 } 3835 3836 static void __exit idt77252_exit(void) 3837 { 3838 struct idt77252_dev *card; 3839 struct atm_dev *dev; 3840 3841 pci_unregister_driver(&idt77252_driver); 3842 3843 while (idt77252_chain) { 3844 card = idt77252_chain; 3845 dev = card->atmdev; 3846 idt77252_chain = card->next; 3847 3848 if (dev->phy->stop) 3849 dev->phy->stop(dev); 3850 deinit_card(card); 3851 pci_disable_device(card->pcidev); 3852 kfree(card); 3853 } 3854 3855 DIPRINTK("idt77252: finished cleanup-module().\n"); 3856 } 3857 3858 module_init(idt77252_init); 3859 module_exit(idt77252_exit); 3860 3861 MODULE_LICENSE("GPL"); 3862 3863 module_param(vpibits, uint, 0); 3864 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3865 #ifdef CONFIG_ATM_IDT77252_DEBUG 3866 module_param(debug, ulong, 0644); 3867 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3868 #endif 3869 3870 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3871 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3872