1 /******************************************************************* 2 * 3 * Copyright (c) 2000 ATecoM GmbH 4 * 5 * The author may be reached at ecd@atecom.com. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 *******************************************************************/ 28 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/poison.h> 32 #include <linux/skbuff.h> 33 #include <linux/kernel.h> 34 #include <linux/vmalloc.h> 35 #include <linux/netdevice.h> 36 #include <linux/atmdev.h> 37 #include <linux/atm.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/bitops.h> 41 #include <linux/wait.h> 42 #include <linux/jiffies.h> 43 #include <linux/mutex.h> 44 #include <linux/slab.h> 45 46 #include <asm/io.h> 47 #include <asm/uaccess.h> 48 #include <asm/atomic.h> 49 #include <asm/byteorder.h> 50 51 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 52 #include "suni.h" 53 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 54 55 56 #include "idt77252.h" 57 #include "idt77252_tables.h" 58 59 static unsigned int vpibits = 1; 60 61 62 #define ATM_IDT77252_SEND_IDLE 1 63 64 65 /* 66 * Debug HACKs. 67 */ 68 #define DEBUG_MODULE 1 69 #undef HAVE_EEPROM /* does not work, yet. */ 70 71 #ifdef CONFIG_ATM_IDT77252_DEBUG 72 static unsigned long debug = DBG_GENERAL; 73 #endif 74 75 76 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 77 78 79 /* 80 * SCQ Handling. 81 */ 82 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 83 static void free_scq(struct idt77252_dev *, struct scq_info *); 84 static int queue_skb(struct idt77252_dev *, struct vc_map *, 85 struct sk_buff *, int oam); 86 static void drain_scq(struct idt77252_dev *, struct vc_map *); 87 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 88 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 89 90 /* 91 * FBQ Handling. 92 */ 93 static int push_rx_skb(struct idt77252_dev *, 94 struct sk_buff *, int queue); 95 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 96 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 97 static void recycle_rx_pool_skb(struct idt77252_dev *, 98 struct rx_pool *); 99 static void add_rx_skb(struct idt77252_dev *, int queue, 100 unsigned int size, unsigned int count); 101 102 /* 103 * RSQ Handling. 104 */ 105 static int init_rsq(struct idt77252_dev *); 106 static void deinit_rsq(struct idt77252_dev *); 107 static void idt77252_rx(struct idt77252_dev *); 108 109 /* 110 * TSQ handling. 111 */ 112 static int init_tsq(struct idt77252_dev *); 113 static void deinit_tsq(struct idt77252_dev *); 114 static void idt77252_tx(struct idt77252_dev *); 115 116 117 /* 118 * ATM Interface. 119 */ 120 static void idt77252_dev_close(struct atm_dev *dev); 121 static int idt77252_open(struct atm_vcc *vcc); 122 static void idt77252_close(struct atm_vcc *vcc); 123 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 124 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 125 int flags); 126 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 127 unsigned long addr); 128 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 129 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 130 int flags); 131 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 132 char *page); 133 static void idt77252_softint(struct work_struct *work); 134 135 136 static struct atmdev_ops idt77252_ops = 137 { 138 .dev_close = idt77252_dev_close, 139 .open = idt77252_open, 140 .close = idt77252_close, 141 .send = idt77252_send, 142 .send_oam = idt77252_send_oam, 143 .phy_put = idt77252_phy_put, 144 .phy_get = idt77252_phy_get, 145 .change_qos = idt77252_change_qos, 146 .proc_read = idt77252_proc_read, 147 .owner = THIS_MODULE 148 }; 149 150 static struct idt77252_dev *idt77252_chain = NULL; 151 static unsigned int idt77252_sram_write_errors = 0; 152 153 /*****************************************************************************/ 154 /* */ 155 /* I/O and Utility Bus */ 156 /* */ 157 /*****************************************************************************/ 158 159 static void 160 waitfor_idle(struct idt77252_dev *card) 161 { 162 u32 stat; 163 164 stat = readl(SAR_REG_STAT); 165 while (stat & SAR_STAT_CMDBZ) 166 stat = readl(SAR_REG_STAT); 167 } 168 169 static u32 170 read_sram(struct idt77252_dev *card, unsigned long addr) 171 { 172 unsigned long flags; 173 u32 value; 174 175 spin_lock_irqsave(&card->cmd_lock, flags); 176 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 177 waitfor_idle(card); 178 value = readl(SAR_REG_DR0); 179 spin_unlock_irqrestore(&card->cmd_lock, flags); 180 return value; 181 } 182 183 static void 184 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 185 { 186 unsigned long flags; 187 188 if ((idt77252_sram_write_errors == 0) && 189 (((addr > card->tst[0] + card->tst_size - 2) && 190 (addr < card->tst[0] + card->tst_size)) || 191 ((addr > card->tst[1] + card->tst_size - 2) && 192 (addr < card->tst[1] + card->tst_size)))) { 193 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 194 card->name, addr, value); 195 } 196 197 spin_lock_irqsave(&card->cmd_lock, flags); 198 writel(value, SAR_REG_DR0); 199 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 200 waitfor_idle(card); 201 spin_unlock_irqrestore(&card->cmd_lock, flags); 202 } 203 204 static u8 205 read_utility(void *dev, unsigned long ubus_addr) 206 { 207 struct idt77252_dev *card = dev; 208 unsigned long flags; 209 u8 value; 210 211 if (!card) { 212 printk("Error: No such device.\n"); 213 return -1; 214 } 215 216 spin_lock_irqsave(&card->cmd_lock, flags); 217 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 218 waitfor_idle(card); 219 value = readl(SAR_REG_DR0); 220 spin_unlock_irqrestore(&card->cmd_lock, flags); 221 return value; 222 } 223 224 static void 225 write_utility(void *dev, unsigned long ubus_addr, u8 value) 226 { 227 struct idt77252_dev *card = dev; 228 unsigned long flags; 229 230 if (!card) { 231 printk("Error: No such device.\n"); 232 return; 233 } 234 235 spin_lock_irqsave(&card->cmd_lock, flags); 236 writel((u32) value, SAR_REG_DR0); 237 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 238 waitfor_idle(card); 239 spin_unlock_irqrestore(&card->cmd_lock, flags); 240 } 241 242 #ifdef HAVE_EEPROM 243 static u32 rdsrtab[] = 244 { 245 SAR_GP_EECS | SAR_GP_EESCLK, 246 0, 247 SAR_GP_EESCLK, /* 0 */ 248 0, 249 SAR_GP_EESCLK, /* 0 */ 250 0, 251 SAR_GP_EESCLK, /* 0 */ 252 0, 253 SAR_GP_EESCLK, /* 0 */ 254 0, 255 SAR_GP_EESCLK, /* 0 */ 256 SAR_GP_EEDO, 257 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 258 0, 259 SAR_GP_EESCLK, /* 0 */ 260 SAR_GP_EEDO, 261 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 262 }; 263 264 static u32 wrentab[] = 265 { 266 SAR_GP_EECS | SAR_GP_EESCLK, 267 0, 268 SAR_GP_EESCLK, /* 0 */ 269 0, 270 SAR_GP_EESCLK, /* 0 */ 271 0, 272 SAR_GP_EESCLK, /* 0 */ 273 0, 274 SAR_GP_EESCLK, /* 0 */ 275 SAR_GP_EEDO, 276 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 277 SAR_GP_EEDO, 278 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 279 0, 280 SAR_GP_EESCLK, /* 0 */ 281 0, 282 SAR_GP_EESCLK /* 0 */ 283 }; 284 285 static u32 rdtab[] = 286 { 287 SAR_GP_EECS | SAR_GP_EESCLK, 288 0, 289 SAR_GP_EESCLK, /* 0 */ 290 0, 291 SAR_GP_EESCLK, /* 0 */ 292 0, 293 SAR_GP_EESCLK, /* 0 */ 294 0, 295 SAR_GP_EESCLK, /* 0 */ 296 0, 297 SAR_GP_EESCLK, /* 0 */ 298 0, 299 SAR_GP_EESCLK, /* 0 */ 300 SAR_GP_EEDO, 301 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 302 SAR_GP_EEDO, 303 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 304 }; 305 306 static u32 wrtab[] = 307 { 308 SAR_GP_EECS | SAR_GP_EESCLK, 309 0, 310 SAR_GP_EESCLK, /* 0 */ 311 0, 312 SAR_GP_EESCLK, /* 0 */ 313 0, 314 SAR_GP_EESCLK, /* 0 */ 315 0, 316 SAR_GP_EESCLK, /* 0 */ 317 0, 318 SAR_GP_EESCLK, /* 0 */ 319 0, 320 SAR_GP_EESCLK, /* 0 */ 321 SAR_GP_EEDO, 322 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 323 0, 324 SAR_GP_EESCLK /* 0 */ 325 }; 326 327 static u32 clktab[] = 328 { 329 0, 330 SAR_GP_EESCLK, 331 0, 332 SAR_GP_EESCLK, 333 0, 334 SAR_GP_EESCLK, 335 0, 336 SAR_GP_EESCLK, 337 0, 338 SAR_GP_EESCLK, 339 0, 340 SAR_GP_EESCLK, 341 0, 342 SAR_GP_EESCLK, 343 0, 344 SAR_GP_EESCLK, 345 0 346 }; 347 348 static u32 349 idt77252_read_gp(struct idt77252_dev *card) 350 { 351 u32 gp; 352 353 gp = readl(SAR_REG_GP); 354 #if 0 355 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 356 #endif 357 return gp; 358 } 359 360 static void 361 idt77252_write_gp(struct idt77252_dev *card, u32 value) 362 { 363 unsigned long flags; 364 365 #if 0 366 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 367 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 368 value & SAR_GP_EEDO ? "1" : "0"); 369 #endif 370 371 spin_lock_irqsave(&card->cmd_lock, flags); 372 waitfor_idle(card); 373 writel(value, SAR_REG_GP); 374 spin_unlock_irqrestore(&card->cmd_lock, flags); 375 } 376 377 static u8 378 idt77252_eeprom_read_status(struct idt77252_dev *card) 379 { 380 u8 byte; 381 u32 gp; 382 int i, j; 383 384 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 385 386 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 387 idt77252_write_gp(card, gp | rdsrtab[i]); 388 udelay(5); 389 } 390 idt77252_write_gp(card, gp | SAR_GP_EECS); 391 udelay(5); 392 393 byte = 0; 394 for (i = 0, j = 0; i < 8; i++) { 395 byte <<= 1; 396 397 idt77252_write_gp(card, gp | clktab[j++]); 398 udelay(5); 399 400 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 401 402 idt77252_write_gp(card, gp | clktab[j++]); 403 udelay(5); 404 } 405 idt77252_write_gp(card, gp | SAR_GP_EECS); 406 udelay(5); 407 408 return byte; 409 } 410 411 static u8 412 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 413 { 414 u8 byte; 415 u32 gp; 416 int i, j; 417 418 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 419 420 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 421 idt77252_write_gp(card, gp | rdtab[i]); 422 udelay(5); 423 } 424 idt77252_write_gp(card, gp | SAR_GP_EECS); 425 udelay(5); 426 427 for (i = 0, j = 0; i < 8; i++) { 428 idt77252_write_gp(card, gp | clktab[j++] | 429 (offset & 1 ? SAR_GP_EEDO : 0)); 430 udelay(5); 431 432 idt77252_write_gp(card, gp | clktab[j++] | 433 (offset & 1 ? SAR_GP_EEDO : 0)); 434 udelay(5); 435 436 offset >>= 1; 437 } 438 idt77252_write_gp(card, gp | SAR_GP_EECS); 439 udelay(5); 440 441 byte = 0; 442 for (i = 0, j = 0; i < 8; i++) { 443 byte <<= 1; 444 445 idt77252_write_gp(card, gp | clktab[j++]); 446 udelay(5); 447 448 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 449 450 idt77252_write_gp(card, gp | clktab[j++]); 451 udelay(5); 452 } 453 idt77252_write_gp(card, gp | SAR_GP_EECS); 454 udelay(5); 455 456 return byte; 457 } 458 459 static void 460 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 461 { 462 u32 gp; 463 int i, j; 464 465 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 466 467 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 468 idt77252_write_gp(card, gp | wrentab[i]); 469 udelay(5); 470 } 471 idt77252_write_gp(card, gp | SAR_GP_EECS); 472 udelay(5); 473 474 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 475 idt77252_write_gp(card, gp | wrtab[i]); 476 udelay(5); 477 } 478 idt77252_write_gp(card, gp | SAR_GP_EECS); 479 udelay(5); 480 481 for (i = 0, j = 0; i < 8; i++) { 482 idt77252_write_gp(card, gp | clktab[j++] | 483 (offset & 1 ? SAR_GP_EEDO : 0)); 484 udelay(5); 485 486 idt77252_write_gp(card, gp | clktab[j++] | 487 (offset & 1 ? SAR_GP_EEDO : 0)); 488 udelay(5); 489 490 offset >>= 1; 491 } 492 idt77252_write_gp(card, gp | SAR_GP_EECS); 493 udelay(5); 494 495 for (i = 0, j = 0; i < 8; i++) { 496 idt77252_write_gp(card, gp | clktab[j++] | 497 (data & 1 ? SAR_GP_EEDO : 0)); 498 udelay(5); 499 500 idt77252_write_gp(card, gp | clktab[j++] | 501 (data & 1 ? SAR_GP_EEDO : 0)); 502 udelay(5); 503 504 data >>= 1; 505 } 506 idt77252_write_gp(card, gp | SAR_GP_EECS); 507 udelay(5); 508 } 509 510 static void 511 idt77252_eeprom_init(struct idt77252_dev *card) 512 { 513 u32 gp; 514 515 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 516 517 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 518 udelay(5); 519 idt77252_write_gp(card, gp | SAR_GP_EECS); 520 udelay(5); 521 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 522 udelay(5); 523 idt77252_write_gp(card, gp | SAR_GP_EECS); 524 udelay(5); 525 } 526 #endif /* HAVE_EEPROM */ 527 528 529 #ifdef CONFIG_ATM_IDT77252_DEBUG 530 static void 531 dump_tct(struct idt77252_dev *card, int index) 532 { 533 unsigned long tct; 534 int i; 535 536 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 537 538 printk("%s: TCT %x:", card->name, index); 539 for (i = 0; i < 8; i++) { 540 printk(" %08x", read_sram(card, tct + i)); 541 } 542 printk("\n"); 543 } 544 545 static void 546 idt77252_tx_dump(struct idt77252_dev *card) 547 { 548 struct atm_vcc *vcc; 549 struct vc_map *vc; 550 int i; 551 552 printk("%s\n", __func__); 553 for (i = 0; i < card->tct_size; i++) { 554 vc = card->vcs[i]; 555 if (!vc) 556 continue; 557 558 vcc = NULL; 559 if (vc->rx_vcc) 560 vcc = vc->rx_vcc; 561 else if (vc->tx_vcc) 562 vcc = vc->tx_vcc; 563 564 if (!vcc) 565 continue; 566 567 printk("%s: Connection %d:\n", card->name, vc->index); 568 dump_tct(card, vc->index); 569 } 570 } 571 #endif 572 573 574 /*****************************************************************************/ 575 /* */ 576 /* SCQ Handling */ 577 /* */ 578 /*****************************************************************************/ 579 580 static int 581 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 582 { 583 struct sb_pool *pool = &card->sbpool[queue]; 584 int index; 585 586 index = pool->index; 587 while (pool->skb[index]) { 588 index = (index + 1) & FBQ_MASK; 589 if (index == pool->index) 590 return -ENOBUFS; 591 } 592 593 pool->skb[index] = skb; 594 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 595 596 pool->index = (index + 1) & FBQ_MASK; 597 return 0; 598 } 599 600 static void 601 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 602 { 603 unsigned int queue, index; 604 u32 handle; 605 606 handle = IDT77252_PRV_POOL(skb); 607 608 queue = POOL_QUEUE(handle); 609 if (queue > 3) 610 return; 611 612 index = POOL_INDEX(handle); 613 if (index > FBQ_SIZE - 1) 614 return; 615 616 card->sbpool[queue].skb[index] = NULL; 617 } 618 619 static struct sk_buff * 620 sb_pool_skb(struct idt77252_dev *card, u32 handle) 621 { 622 unsigned int queue, index; 623 624 queue = POOL_QUEUE(handle); 625 if (queue > 3) 626 return NULL; 627 628 index = POOL_INDEX(handle); 629 if (index > FBQ_SIZE - 1) 630 return NULL; 631 632 return card->sbpool[queue].skb[index]; 633 } 634 635 static struct scq_info * 636 alloc_scq(struct idt77252_dev *card, int class) 637 { 638 struct scq_info *scq; 639 640 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 641 if (!scq) 642 return NULL; 643 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 644 &scq->paddr); 645 if (scq->base == NULL) { 646 kfree(scq); 647 return NULL; 648 } 649 memset(scq->base, 0, SCQ_SIZE); 650 651 scq->next = scq->base; 652 scq->last = scq->base + (SCQ_ENTRIES - 1); 653 atomic_set(&scq->used, 0); 654 655 spin_lock_init(&scq->lock); 656 spin_lock_init(&scq->skblock); 657 658 skb_queue_head_init(&scq->transmit); 659 skb_queue_head_init(&scq->pending); 660 661 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 662 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 663 664 return scq; 665 } 666 667 static void 668 free_scq(struct idt77252_dev *card, struct scq_info *scq) 669 { 670 struct sk_buff *skb; 671 struct atm_vcc *vcc; 672 673 pci_free_consistent(card->pcidev, SCQ_SIZE, 674 scq->base, scq->paddr); 675 676 while ((skb = skb_dequeue(&scq->transmit))) { 677 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 678 skb->len, PCI_DMA_TODEVICE); 679 680 vcc = ATM_SKB(skb)->vcc; 681 if (vcc->pop) 682 vcc->pop(vcc, skb); 683 else 684 dev_kfree_skb(skb); 685 } 686 687 while ((skb = skb_dequeue(&scq->pending))) { 688 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 689 skb->len, PCI_DMA_TODEVICE); 690 691 vcc = ATM_SKB(skb)->vcc; 692 if (vcc->pop) 693 vcc->pop(vcc, skb); 694 else 695 dev_kfree_skb(skb); 696 } 697 698 kfree(scq); 699 } 700 701 702 static int 703 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 704 { 705 struct scq_info *scq = vc->scq; 706 unsigned long flags; 707 struct scqe *tbd; 708 int entries; 709 710 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 711 712 atomic_inc(&scq->used); 713 entries = atomic_read(&scq->used); 714 if (entries > (SCQ_ENTRIES - 1)) { 715 atomic_dec(&scq->used); 716 goto out; 717 } 718 719 skb_queue_tail(&scq->transmit, skb); 720 721 spin_lock_irqsave(&vc->lock, flags); 722 if (vc->estimator) { 723 struct atm_vcc *vcc = vc->tx_vcc; 724 struct sock *sk = sk_atm(vcc); 725 726 vc->estimator->cells += (skb->len + 47) / 48; 727 if (atomic_read(&sk->sk_wmem_alloc) > 728 (sk->sk_sndbuf >> 1)) { 729 u32 cps = vc->estimator->maxcps; 730 731 vc->estimator->cps = cps; 732 vc->estimator->avcps = cps << 5; 733 if (vc->lacr < vc->init_er) { 734 vc->lacr = vc->init_er; 735 writel(TCMDQ_LACR | (vc->lacr << 16) | 736 vc->index, SAR_REG_TCMDQ); 737 } 738 } 739 } 740 spin_unlock_irqrestore(&vc->lock, flags); 741 742 tbd = &IDT77252_PRV_TBD(skb); 743 744 spin_lock_irqsave(&scq->lock, flags); 745 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 746 SAR_TBD_TSIF | SAR_TBD_GTSI); 747 scq->next->word_2 = cpu_to_le32(tbd->word_2); 748 scq->next->word_3 = cpu_to_le32(tbd->word_3); 749 scq->next->word_4 = cpu_to_le32(tbd->word_4); 750 751 if (scq->next == scq->last) 752 scq->next = scq->base; 753 else 754 scq->next++; 755 756 write_sram(card, scq->scd, 757 scq->paddr + 758 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 759 spin_unlock_irqrestore(&scq->lock, flags); 760 761 scq->trans_start = jiffies; 762 763 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 764 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 765 SAR_REG_TCMDQ); 766 } 767 768 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 769 770 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 771 card->name, atomic_read(&scq->used), 772 read_sram(card, scq->scd + 1), scq->next); 773 774 return 0; 775 776 out: 777 if (time_after(jiffies, scq->trans_start + HZ)) { 778 printk("%s: Error pushing TBD for %d.%d\n", 779 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 780 #ifdef CONFIG_ATM_IDT77252_DEBUG 781 idt77252_tx_dump(card); 782 #endif 783 scq->trans_start = jiffies; 784 } 785 786 return -ENOBUFS; 787 } 788 789 790 static void 791 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 792 { 793 struct scq_info *scq = vc->scq; 794 struct sk_buff *skb; 795 struct atm_vcc *vcc; 796 797 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 798 card->name, atomic_read(&scq->used), scq->next); 799 800 skb = skb_dequeue(&scq->transmit); 801 if (skb) { 802 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 803 804 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 805 skb->len, PCI_DMA_TODEVICE); 806 807 vcc = ATM_SKB(skb)->vcc; 808 809 if (vcc->pop) 810 vcc->pop(vcc, skb); 811 else 812 dev_kfree_skb(skb); 813 814 atomic_inc(&vcc->stats->tx); 815 } 816 817 atomic_dec(&scq->used); 818 819 spin_lock(&scq->skblock); 820 while ((skb = skb_dequeue(&scq->pending))) { 821 if (push_on_scq(card, vc, skb)) { 822 skb_queue_head(&vc->scq->pending, skb); 823 break; 824 } 825 } 826 spin_unlock(&scq->skblock); 827 } 828 829 static int 830 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 831 struct sk_buff *skb, int oam) 832 { 833 struct atm_vcc *vcc; 834 struct scqe *tbd; 835 unsigned long flags; 836 int error; 837 int aal; 838 839 if (skb->len == 0) { 840 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 841 return -EINVAL; 842 } 843 844 TXPRINTK("%s: Sending %d bytes of data.\n", 845 card->name, skb->len); 846 847 tbd = &IDT77252_PRV_TBD(skb); 848 vcc = ATM_SKB(skb)->vcc; 849 850 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 851 skb->len, PCI_DMA_TODEVICE); 852 853 error = -EINVAL; 854 855 if (oam) { 856 if (skb->len != 52) 857 goto errout; 858 859 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 860 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 861 tbd->word_3 = 0x00000000; 862 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 863 (skb->data[2] << 8) | (skb->data[3] << 0); 864 865 if (test_bit(VCF_RSV, &vc->flags)) 866 vc = card->vcs[0]; 867 868 goto done; 869 } 870 871 if (test_bit(VCF_RSV, &vc->flags)) { 872 printk("%s: Trying to transmit on reserved VC\n", card->name); 873 goto errout; 874 } 875 876 aal = vcc->qos.aal; 877 878 switch (aal) { 879 case ATM_AAL0: 880 case ATM_AAL34: 881 if (skb->len > 52) 882 goto errout; 883 884 if (aal == ATM_AAL0) 885 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 886 ATM_CELL_PAYLOAD; 887 else 888 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 889 ATM_CELL_PAYLOAD; 890 891 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 892 tbd->word_3 = 0x00000000; 893 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 894 (skb->data[2] << 8) | (skb->data[3] << 0); 895 break; 896 897 case ATM_AAL5: 898 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 899 tbd->word_2 = IDT77252_PRV_PADDR(skb); 900 tbd->word_3 = skb->len; 901 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 902 (vcc->vci << SAR_TBD_VCI_SHIFT); 903 break; 904 905 case ATM_AAL1: 906 case ATM_AAL2: 907 default: 908 printk("%s: Traffic type not supported.\n", card->name); 909 error = -EPROTONOSUPPORT; 910 goto errout; 911 } 912 913 done: 914 spin_lock_irqsave(&vc->scq->skblock, flags); 915 skb_queue_tail(&vc->scq->pending, skb); 916 917 while ((skb = skb_dequeue(&vc->scq->pending))) { 918 if (push_on_scq(card, vc, skb)) { 919 skb_queue_head(&vc->scq->pending, skb); 920 break; 921 } 922 } 923 spin_unlock_irqrestore(&vc->scq->skblock, flags); 924 925 return 0; 926 927 errout: 928 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 929 skb->len, PCI_DMA_TODEVICE); 930 return error; 931 } 932 933 static unsigned long 934 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 935 { 936 int i; 937 938 for (i = 0; i < card->scd_size; i++) { 939 if (!card->scd2vc[i]) { 940 card->scd2vc[i] = vc; 941 vc->scd_index = i; 942 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 943 } 944 } 945 return 0; 946 } 947 948 static void 949 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 950 { 951 write_sram(card, scq->scd, scq->paddr); 952 write_sram(card, scq->scd + 1, 0x00000000); 953 write_sram(card, scq->scd + 2, 0xffffffff); 954 write_sram(card, scq->scd + 3, 0x00000000); 955 } 956 957 static void 958 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 959 { 960 return; 961 } 962 963 /*****************************************************************************/ 964 /* */ 965 /* RSQ Handling */ 966 /* */ 967 /*****************************************************************************/ 968 969 static int 970 init_rsq(struct idt77252_dev *card) 971 { 972 struct rsq_entry *rsqe; 973 974 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 975 &card->rsq.paddr); 976 if (card->rsq.base == NULL) { 977 printk("%s: can't allocate RSQ.\n", card->name); 978 return -1; 979 } 980 memset(card->rsq.base, 0, RSQSIZE); 981 982 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 983 card->rsq.next = card->rsq.last; 984 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 985 rsqe->word_4 = 0; 986 987 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 988 SAR_REG_RSQH); 989 writel(card->rsq.paddr, SAR_REG_RSQB); 990 991 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 992 (unsigned long) card->rsq.base, 993 readl(SAR_REG_RSQB)); 994 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 995 card->name, 996 readl(SAR_REG_RSQH), 997 readl(SAR_REG_RSQB), 998 readl(SAR_REG_RSQT)); 999 1000 return 0; 1001 } 1002 1003 static void 1004 deinit_rsq(struct idt77252_dev *card) 1005 { 1006 pci_free_consistent(card->pcidev, RSQSIZE, 1007 card->rsq.base, card->rsq.paddr); 1008 } 1009 1010 static void 1011 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1012 { 1013 struct atm_vcc *vcc; 1014 struct sk_buff *skb; 1015 struct rx_pool *rpp; 1016 struct vc_map *vc; 1017 u32 header, vpi, vci; 1018 u32 stat; 1019 int i; 1020 1021 stat = le32_to_cpu(rsqe->word_4); 1022 1023 if (stat & SAR_RSQE_IDLE) { 1024 RXPRINTK("%s: message about inactive connection.\n", 1025 card->name); 1026 return; 1027 } 1028 1029 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1030 if (skb == NULL) { 1031 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1032 card->name, __func__, 1033 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1034 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1035 return; 1036 } 1037 1038 header = le32_to_cpu(rsqe->word_1); 1039 vpi = (header >> 16) & 0x00ff; 1040 vci = (header >> 0) & 0xffff; 1041 1042 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1043 card->name, vpi, vci, skb, skb->data); 1044 1045 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1046 printk("%s: SDU received for out-of-range vc %u.%u\n", 1047 card->name, vpi, vci); 1048 recycle_rx_skb(card, skb); 1049 return; 1050 } 1051 1052 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1053 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1054 printk("%s: SDU received on non RX vc %u.%u\n", 1055 card->name, vpi, vci); 1056 recycle_rx_skb(card, skb); 1057 return; 1058 } 1059 1060 vcc = vc->rx_vcc; 1061 1062 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1063 skb_end_pointer(skb) - skb->data, 1064 PCI_DMA_FROMDEVICE); 1065 1066 if ((vcc->qos.aal == ATM_AAL0) || 1067 (vcc->qos.aal == ATM_AAL34)) { 1068 struct sk_buff *sb; 1069 unsigned char *cell; 1070 u32 aal0; 1071 1072 cell = skb->data; 1073 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1074 if ((sb = dev_alloc_skb(64)) == NULL) { 1075 printk("%s: Can't allocate buffers for aal0.\n", 1076 card->name); 1077 atomic_add(i, &vcc->stats->rx_drop); 1078 break; 1079 } 1080 if (!atm_charge(vcc, sb->truesize)) { 1081 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1082 card->name); 1083 atomic_add(i - 1, &vcc->stats->rx_drop); 1084 dev_kfree_skb(sb); 1085 break; 1086 } 1087 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1088 (vci << ATM_HDR_VCI_SHIFT); 1089 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1090 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1091 1092 *((u32 *) sb->data) = aal0; 1093 skb_put(sb, sizeof(u32)); 1094 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1095 cell, ATM_CELL_PAYLOAD); 1096 1097 ATM_SKB(sb)->vcc = vcc; 1098 __net_timestamp(sb); 1099 vcc->push(vcc, sb); 1100 atomic_inc(&vcc->stats->rx); 1101 1102 cell += ATM_CELL_PAYLOAD; 1103 } 1104 1105 recycle_rx_skb(card, skb); 1106 return; 1107 } 1108 if (vcc->qos.aal != ATM_AAL5) { 1109 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1110 card->name, vcc->qos.aal); 1111 recycle_rx_skb(card, skb); 1112 return; 1113 } 1114 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1115 1116 rpp = &vc->rcv.rx_pool; 1117 1118 __skb_queue_tail(&rpp->queue, skb); 1119 rpp->len += skb->len; 1120 1121 if (stat & SAR_RSQE_EPDU) { 1122 unsigned char *l1l2; 1123 unsigned int len; 1124 1125 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1126 1127 len = (l1l2[0] << 8) | l1l2[1]; 1128 len = len ? len : 0x10000; 1129 1130 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1131 1132 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1133 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1134 "(CDC: %08x)\n", 1135 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1136 recycle_rx_pool_skb(card, rpp); 1137 atomic_inc(&vcc->stats->rx_err); 1138 return; 1139 } 1140 if (stat & SAR_RSQE_CRC) { 1141 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1142 recycle_rx_pool_skb(card, rpp); 1143 atomic_inc(&vcc->stats->rx_err); 1144 return; 1145 } 1146 if (skb_queue_len(&rpp->queue) > 1) { 1147 struct sk_buff *sb; 1148 1149 skb = dev_alloc_skb(rpp->len); 1150 if (!skb) { 1151 RXPRINTK("%s: Can't alloc RX skb.\n", 1152 card->name); 1153 recycle_rx_pool_skb(card, rpp); 1154 atomic_inc(&vcc->stats->rx_err); 1155 return; 1156 } 1157 if (!atm_charge(vcc, skb->truesize)) { 1158 recycle_rx_pool_skb(card, rpp); 1159 dev_kfree_skb(skb); 1160 return; 1161 } 1162 skb_queue_walk(&rpp->queue, sb) 1163 memcpy(skb_put(skb, sb->len), 1164 sb->data, sb->len); 1165 1166 recycle_rx_pool_skb(card, rpp); 1167 1168 skb_trim(skb, len); 1169 ATM_SKB(skb)->vcc = vcc; 1170 __net_timestamp(skb); 1171 1172 vcc->push(vcc, skb); 1173 atomic_inc(&vcc->stats->rx); 1174 1175 return; 1176 } 1177 1178 flush_rx_pool(card, rpp); 1179 1180 if (!atm_charge(vcc, skb->truesize)) { 1181 recycle_rx_skb(card, skb); 1182 return; 1183 } 1184 1185 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1186 skb_end_pointer(skb) - skb->data, 1187 PCI_DMA_FROMDEVICE); 1188 sb_pool_remove(card, skb); 1189 1190 skb_trim(skb, len); 1191 ATM_SKB(skb)->vcc = vcc; 1192 __net_timestamp(skb); 1193 1194 vcc->push(vcc, skb); 1195 atomic_inc(&vcc->stats->rx); 1196 1197 if (skb->truesize > SAR_FB_SIZE_3) 1198 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1199 else if (skb->truesize > SAR_FB_SIZE_2) 1200 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1201 else if (skb->truesize > SAR_FB_SIZE_1) 1202 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1203 else 1204 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1205 return; 1206 } 1207 } 1208 1209 static void 1210 idt77252_rx(struct idt77252_dev *card) 1211 { 1212 struct rsq_entry *rsqe; 1213 1214 if (card->rsq.next == card->rsq.last) 1215 rsqe = card->rsq.base; 1216 else 1217 rsqe = card->rsq.next + 1; 1218 1219 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1220 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1221 return; 1222 } 1223 1224 do { 1225 dequeue_rx(card, rsqe); 1226 rsqe->word_4 = 0; 1227 card->rsq.next = rsqe; 1228 if (card->rsq.next == card->rsq.last) 1229 rsqe = card->rsq.base; 1230 else 1231 rsqe = card->rsq.next + 1; 1232 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1233 1234 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1235 SAR_REG_RSQH); 1236 } 1237 1238 static void 1239 idt77252_rx_raw(struct idt77252_dev *card) 1240 { 1241 struct sk_buff *queue; 1242 u32 head, tail; 1243 struct atm_vcc *vcc; 1244 struct vc_map *vc; 1245 struct sk_buff *sb; 1246 1247 if (card->raw_cell_head == NULL) { 1248 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1249 card->raw_cell_head = sb_pool_skb(card, handle); 1250 } 1251 1252 queue = card->raw_cell_head; 1253 if (!queue) 1254 return; 1255 1256 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1257 tail = readl(SAR_REG_RAWCT); 1258 1259 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1260 skb_end_pointer(queue) - queue->head - 16, 1261 PCI_DMA_FROMDEVICE); 1262 1263 while (head != tail) { 1264 unsigned int vpi, vci; 1265 u32 header; 1266 1267 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1268 1269 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1270 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1271 1272 #ifdef CONFIG_ATM_IDT77252_DEBUG 1273 if (debug & DBG_RAW_CELL) { 1274 int i; 1275 1276 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1277 card->name, (header >> 28) & 0x000f, 1278 (header >> 20) & 0x00ff, 1279 (header >> 4) & 0xffff, 1280 (header >> 1) & 0x0007, 1281 (header >> 0) & 0x0001); 1282 for (i = 16; i < 64; i++) 1283 printk(" %02x", queue->data[i]); 1284 printk("\n"); 1285 } 1286 #endif 1287 1288 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1289 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1290 card->name, vpi, vci); 1291 goto drop; 1292 } 1293 1294 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1295 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1296 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1297 card->name, vpi, vci); 1298 goto drop; 1299 } 1300 1301 vcc = vc->rx_vcc; 1302 1303 if (vcc->qos.aal != ATM_AAL0) { 1304 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1305 card->name, vpi, vci); 1306 atomic_inc(&vcc->stats->rx_drop); 1307 goto drop; 1308 } 1309 1310 if ((sb = dev_alloc_skb(64)) == NULL) { 1311 printk("%s: Can't allocate buffers for AAL0.\n", 1312 card->name); 1313 atomic_inc(&vcc->stats->rx_err); 1314 goto drop; 1315 } 1316 1317 if (!atm_charge(vcc, sb->truesize)) { 1318 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1319 card->name); 1320 dev_kfree_skb(sb); 1321 goto drop; 1322 } 1323 1324 *((u32 *) sb->data) = header; 1325 skb_put(sb, sizeof(u32)); 1326 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1327 ATM_CELL_PAYLOAD); 1328 1329 ATM_SKB(sb)->vcc = vcc; 1330 __net_timestamp(sb); 1331 vcc->push(vcc, sb); 1332 atomic_inc(&vcc->stats->rx); 1333 1334 drop: 1335 skb_pull(queue, 64); 1336 1337 head = IDT77252_PRV_PADDR(queue) 1338 + (queue->data - queue->head - 16); 1339 1340 if (queue->len < 128) { 1341 struct sk_buff *next; 1342 u32 handle; 1343 1344 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1345 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1346 1347 next = sb_pool_skb(card, handle); 1348 recycle_rx_skb(card, queue); 1349 1350 if (next) { 1351 card->raw_cell_head = next; 1352 queue = card->raw_cell_head; 1353 pci_dma_sync_single_for_cpu(card->pcidev, 1354 IDT77252_PRV_PADDR(queue), 1355 (skb_end_pointer(queue) - 1356 queue->data), 1357 PCI_DMA_FROMDEVICE); 1358 } else { 1359 card->raw_cell_head = NULL; 1360 printk("%s: raw cell queue overrun\n", 1361 card->name); 1362 break; 1363 } 1364 } 1365 } 1366 } 1367 1368 1369 /*****************************************************************************/ 1370 /* */ 1371 /* TSQ Handling */ 1372 /* */ 1373 /*****************************************************************************/ 1374 1375 static int 1376 init_tsq(struct idt77252_dev *card) 1377 { 1378 struct tsq_entry *tsqe; 1379 1380 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1381 &card->tsq.paddr); 1382 if (card->tsq.base == NULL) { 1383 printk("%s: can't allocate TSQ.\n", card->name); 1384 return -1; 1385 } 1386 memset(card->tsq.base, 0, TSQSIZE); 1387 1388 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1389 card->tsq.next = card->tsq.last; 1390 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1391 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1392 1393 writel(card->tsq.paddr, SAR_REG_TSQB); 1394 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1395 SAR_REG_TSQH); 1396 1397 return 0; 1398 } 1399 1400 static void 1401 deinit_tsq(struct idt77252_dev *card) 1402 { 1403 pci_free_consistent(card->pcidev, TSQSIZE, 1404 card->tsq.base, card->tsq.paddr); 1405 } 1406 1407 static void 1408 idt77252_tx(struct idt77252_dev *card) 1409 { 1410 struct tsq_entry *tsqe; 1411 unsigned int vpi, vci; 1412 struct vc_map *vc; 1413 u32 conn, stat; 1414 1415 if (card->tsq.next == card->tsq.last) 1416 tsqe = card->tsq.base; 1417 else 1418 tsqe = card->tsq.next + 1; 1419 1420 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1421 card->tsq.base, card->tsq.next, card->tsq.last); 1422 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1423 readl(SAR_REG_TSQB), 1424 readl(SAR_REG_TSQT), 1425 readl(SAR_REG_TSQH)); 1426 1427 stat = le32_to_cpu(tsqe->word_2); 1428 1429 if (stat & SAR_TSQE_INVALID) 1430 return; 1431 1432 do { 1433 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1434 le32_to_cpu(tsqe->word_1), 1435 le32_to_cpu(tsqe->word_2)); 1436 1437 switch (stat & SAR_TSQE_TYPE) { 1438 case SAR_TSQE_TYPE_TIMER: 1439 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1440 break; 1441 1442 case SAR_TSQE_TYPE_IDLE: 1443 1444 conn = le32_to_cpu(tsqe->word_1); 1445 1446 if (SAR_TSQE_TAG(stat) == 0x10) { 1447 #ifdef NOTDEF 1448 printk("%s: Connection %d halted.\n", 1449 card->name, 1450 le32_to_cpu(tsqe->word_1) & 0x1fff); 1451 #endif 1452 break; 1453 } 1454 1455 vc = card->vcs[conn & 0x1fff]; 1456 if (!vc) { 1457 printk("%s: could not find VC from conn %d\n", 1458 card->name, conn & 0x1fff); 1459 break; 1460 } 1461 1462 printk("%s: Connection %d IDLE.\n", 1463 card->name, vc->index); 1464 1465 set_bit(VCF_IDLE, &vc->flags); 1466 break; 1467 1468 case SAR_TSQE_TYPE_TSR: 1469 1470 conn = le32_to_cpu(tsqe->word_1); 1471 1472 vc = card->vcs[conn & 0x1fff]; 1473 if (!vc) { 1474 printk("%s: no VC at index %d\n", 1475 card->name, 1476 le32_to_cpu(tsqe->word_1) & 0x1fff); 1477 break; 1478 } 1479 1480 drain_scq(card, vc); 1481 break; 1482 1483 case SAR_TSQE_TYPE_TBD_COMP: 1484 1485 conn = le32_to_cpu(tsqe->word_1); 1486 1487 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1488 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1489 1490 if (vpi >= (1 << card->vpibits) || 1491 vci >= (1 << card->vcibits)) { 1492 printk("%s: TBD complete: " 1493 "out of range VPI.VCI %u.%u\n", 1494 card->name, vpi, vci); 1495 break; 1496 } 1497 1498 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1499 if (!vc) { 1500 printk("%s: TBD complete: " 1501 "no VC at VPI.VCI %u.%u\n", 1502 card->name, vpi, vci); 1503 break; 1504 } 1505 1506 drain_scq(card, vc); 1507 break; 1508 } 1509 1510 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1511 1512 card->tsq.next = tsqe; 1513 if (card->tsq.next == card->tsq.last) 1514 tsqe = card->tsq.base; 1515 else 1516 tsqe = card->tsq.next + 1; 1517 1518 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1519 card->tsq.base, card->tsq.next, card->tsq.last); 1520 1521 stat = le32_to_cpu(tsqe->word_2); 1522 1523 } while (!(stat & SAR_TSQE_INVALID)); 1524 1525 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1526 SAR_REG_TSQH); 1527 1528 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1529 card->index, readl(SAR_REG_TSQH), 1530 readl(SAR_REG_TSQT), card->tsq.next); 1531 } 1532 1533 1534 static void 1535 tst_timer(unsigned long data) 1536 { 1537 struct idt77252_dev *card = (struct idt77252_dev *)data; 1538 unsigned long base, idle, jump; 1539 unsigned long flags; 1540 u32 pc; 1541 int e; 1542 1543 spin_lock_irqsave(&card->tst_lock, flags); 1544 1545 base = card->tst[card->tst_index]; 1546 idle = card->tst[card->tst_index ^ 1]; 1547 1548 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1549 jump = base + card->tst_size - 2; 1550 1551 pc = readl(SAR_REG_NOW) >> 2; 1552 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1553 mod_timer(&card->tst_timer, jiffies + 1); 1554 goto out; 1555 } 1556 1557 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1558 1559 card->tst_index ^= 1; 1560 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1561 1562 base = card->tst[card->tst_index]; 1563 idle = card->tst[card->tst_index ^ 1]; 1564 1565 for (e = 0; e < card->tst_size - 2; e++) { 1566 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1567 write_sram(card, idle + e, 1568 card->soft_tst[e].tste & TSTE_MASK); 1569 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1570 } 1571 } 1572 } 1573 1574 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1575 1576 for (e = 0; e < card->tst_size - 2; e++) { 1577 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1578 write_sram(card, idle + e, 1579 card->soft_tst[e].tste & TSTE_MASK); 1580 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1581 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1582 } 1583 } 1584 1585 jump = base + card->tst_size - 2; 1586 1587 write_sram(card, jump, TSTE_OPC_NULL); 1588 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1589 1590 mod_timer(&card->tst_timer, jiffies + 1); 1591 } 1592 1593 out: 1594 spin_unlock_irqrestore(&card->tst_lock, flags); 1595 } 1596 1597 static int 1598 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1599 int n, unsigned int opc) 1600 { 1601 unsigned long cl, avail; 1602 unsigned long idle; 1603 int e, r; 1604 u32 data; 1605 1606 avail = card->tst_size - 2; 1607 for (e = 0; e < avail; e++) { 1608 if (card->soft_tst[e].vc == NULL) 1609 break; 1610 } 1611 if (e >= avail) { 1612 printk("%s: No free TST entries found\n", card->name); 1613 return -1; 1614 } 1615 1616 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1617 card->name, vc ? vc->index : -1, e); 1618 1619 r = n; 1620 cl = avail; 1621 data = opc & TSTE_OPC_MASK; 1622 if (vc && (opc != TSTE_OPC_NULL)) 1623 data = opc | vc->index; 1624 1625 idle = card->tst[card->tst_index ^ 1]; 1626 1627 /* 1628 * Fill Soft TST. 1629 */ 1630 while (r > 0) { 1631 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1632 if (vc) 1633 card->soft_tst[e].vc = vc; 1634 else 1635 card->soft_tst[e].vc = (void *)-1; 1636 1637 card->soft_tst[e].tste = data; 1638 if (timer_pending(&card->tst_timer)) 1639 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1640 else { 1641 write_sram(card, idle + e, data); 1642 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1643 } 1644 1645 cl -= card->tst_size; 1646 r--; 1647 } 1648 1649 if (++e == avail) 1650 e = 0; 1651 cl += n; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int 1658 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1659 { 1660 unsigned long flags; 1661 int res; 1662 1663 spin_lock_irqsave(&card->tst_lock, flags); 1664 1665 res = __fill_tst(card, vc, n, opc); 1666 1667 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1668 if (!timer_pending(&card->tst_timer)) 1669 mod_timer(&card->tst_timer, jiffies + 1); 1670 1671 spin_unlock_irqrestore(&card->tst_lock, flags); 1672 return res; 1673 } 1674 1675 static int 1676 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1677 { 1678 unsigned long idle; 1679 int e; 1680 1681 idle = card->tst[card->tst_index ^ 1]; 1682 1683 for (e = 0; e < card->tst_size - 2; e++) { 1684 if (card->soft_tst[e].vc == vc) { 1685 card->soft_tst[e].vc = NULL; 1686 1687 card->soft_tst[e].tste = TSTE_OPC_VAR; 1688 if (timer_pending(&card->tst_timer)) 1689 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1690 else { 1691 write_sram(card, idle + e, TSTE_OPC_VAR); 1692 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1693 } 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int 1701 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1702 { 1703 unsigned long flags; 1704 int res; 1705 1706 spin_lock_irqsave(&card->tst_lock, flags); 1707 1708 res = __clear_tst(card, vc); 1709 1710 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1711 if (!timer_pending(&card->tst_timer)) 1712 mod_timer(&card->tst_timer, jiffies + 1); 1713 1714 spin_unlock_irqrestore(&card->tst_lock, flags); 1715 return res; 1716 } 1717 1718 static int 1719 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1720 int n, unsigned int opc) 1721 { 1722 unsigned long flags; 1723 int res; 1724 1725 spin_lock_irqsave(&card->tst_lock, flags); 1726 1727 __clear_tst(card, vc); 1728 res = __fill_tst(card, vc, n, opc); 1729 1730 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1731 if (!timer_pending(&card->tst_timer)) 1732 mod_timer(&card->tst_timer, jiffies + 1); 1733 1734 spin_unlock_irqrestore(&card->tst_lock, flags); 1735 return res; 1736 } 1737 1738 1739 static int 1740 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1741 { 1742 unsigned long tct; 1743 1744 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1745 1746 switch (vc->class) { 1747 case SCHED_CBR: 1748 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1749 card->name, tct, vc->scq->scd); 1750 1751 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1752 write_sram(card, tct + 1, 0); 1753 write_sram(card, tct + 2, 0); 1754 write_sram(card, tct + 3, 0); 1755 write_sram(card, tct + 4, 0); 1756 write_sram(card, tct + 5, 0); 1757 write_sram(card, tct + 6, 0); 1758 write_sram(card, tct + 7, 0); 1759 break; 1760 1761 case SCHED_UBR: 1762 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1763 card->name, tct, vc->scq->scd); 1764 1765 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1766 write_sram(card, tct + 1, 0); 1767 write_sram(card, tct + 2, TCT_TSIF); 1768 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1769 write_sram(card, tct + 4, 0); 1770 write_sram(card, tct + 5, vc->init_er); 1771 write_sram(card, tct + 6, 0); 1772 write_sram(card, tct + 7, TCT_FLAG_UBR); 1773 break; 1774 1775 case SCHED_VBR: 1776 case SCHED_ABR: 1777 default: 1778 return -ENOSYS; 1779 } 1780 1781 return 0; 1782 } 1783 1784 /*****************************************************************************/ 1785 /* */ 1786 /* FBQ Handling */ 1787 /* */ 1788 /*****************************************************************************/ 1789 1790 static __inline__ int 1791 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1792 { 1793 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1794 } 1795 1796 static __inline__ int 1797 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1798 { 1799 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1800 } 1801 1802 static int 1803 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1804 { 1805 unsigned long flags; 1806 u32 handle; 1807 u32 addr; 1808 1809 skb->data = skb->head; 1810 skb_reset_tail_pointer(skb); 1811 skb->len = 0; 1812 1813 skb_reserve(skb, 16); 1814 1815 switch (queue) { 1816 case 0: 1817 skb_put(skb, SAR_FB_SIZE_0); 1818 break; 1819 case 1: 1820 skb_put(skb, SAR_FB_SIZE_1); 1821 break; 1822 case 2: 1823 skb_put(skb, SAR_FB_SIZE_2); 1824 break; 1825 case 3: 1826 skb_put(skb, SAR_FB_SIZE_3); 1827 break; 1828 default: 1829 return -1; 1830 } 1831 1832 if (idt77252_fbq_full(card, queue)) 1833 return -1; 1834 1835 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1836 1837 handle = IDT77252_PRV_POOL(skb); 1838 addr = IDT77252_PRV_PADDR(skb); 1839 1840 spin_lock_irqsave(&card->cmd_lock, flags); 1841 writel(handle, card->fbq[queue]); 1842 writel(addr, card->fbq[queue]); 1843 spin_unlock_irqrestore(&card->cmd_lock, flags); 1844 1845 return 0; 1846 } 1847 1848 static void 1849 add_rx_skb(struct idt77252_dev *card, int queue, 1850 unsigned int size, unsigned int count) 1851 { 1852 struct sk_buff *skb; 1853 dma_addr_t paddr; 1854 u32 handle; 1855 1856 while (count--) { 1857 skb = dev_alloc_skb(size); 1858 if (!skb) 1859 return; 1860 1861 if (sb_pool_add(card, skb, queue)) { 1862 printk("%s: SB POOL full\n", __func__); 1863 goto outfree; 1864 } 1865 1866 paddr = pci_map_single(card->pcidev, skb->data, 1867 skb_end_pointer(skb) - skb->data, 1868 PCI_DMA_FROMDEVICE); 1869 IDT77252_PRV_PADDR(skb) = paddr; 1870 1871 if (push_rx_skb(card, skb, queue)) { 1872 printk("%s: FB QUEUE full\n", __func__); 1873 goto outunmap; 1874 } 1875 } 1876 1877 return; 1878 1879 outunmap: 1880 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1881 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1882 1883 handle = IDT77252_PRV_POOL(skb); 1884 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1885 1886 outfree: 1887 dev_kfree_skb(skb); 1888 } 1889 1890 1891 static void 1892 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1893 { 1894 u32 handle = IDT77252_PRV_POOL(skb); 1895 int err; 1896 1897 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1898 skb_end_pointer(skb) - skb->data, 1899 PCI_DMA_FROMDEVICE); 1900 1901 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1902 if (err) { 1903 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1904 skb_end_pointer(skb) - skb->data, 1905 PCI_DMA_FROMDEVICE); 1906 sb_pool_remove(card, skb); 1907 dev_kfree_skb(skb); 1908 } 1909 } 1910 1911 static void 1912 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1913 { 1914 skb_queue_head_init(&rpp->queue); 1915 rpp->len = 0; 1916 } 1917 1918 static void 1919 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1920 { 1921 struct sk_buff *skb, *tmp; 1922 1923 skb_queue_walk_safe(&rpp->queue, skb, tmp) 1924 recycle_rx_skb(card, skb); 1925 1926 flush_rx_pool(card, rpp); 1927 } 1928 1929 /*****************************************************************************/ 1930 /* */ 1931 /* ATM Interface */ 1932 /* */ 1933 /*****************************************************************************/ 1934 1935 static void 1936 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1937 { 1938 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1939 } 1940 1941 static unsigned char 1942 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1943 { 1944 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1945 } 1946 1947 static inline int 1948 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1949 { 1950 struct atm_dev *dev = vcc->dev; 1951 struct idt77252_dev *card = dev->dev_data; 1952 struct vc_map *vc = vcc->dev_data; 1953 int err; 1954 1955 if (vc == NULL) { 1956 printk("%s: NULL connection in send().\n", card->name); 1957 atomic_inc(&vcc->stats->tx_err); 1958 dev_kfree_skb(skb); 1959 return -EINVAL; 1960 } 1961 if (!test_bit(VCF_TX, &vc->flags)) { 1962 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1963 atomic_inc(&vcc->stats->tx_err); 1964 dev_kfree_skb(skb); 1965 return -EINVAL; 1966 } 1967 1968 switch (vcc->qos.aal) { 1969 case ATM_AAL0: 1970 case ATM_AAL1: 1971 case ATM_AAL5: 1972 break; 1973 default: 1974 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1975 atomic_inc(&vcc->stats->tx_err); 1976 dev_kfree_skb(skb); 1977 return -EINVAL; 1978 } 1979 1980 if (skb_shinfo(skb)->nr_frags != 0) { 1981 printk("%s: No scatter-gather yet.\n", card->name); 1982 atomic_inc(&vcc->stats->tx_err); 1983 dev_kfree_skb(skb); 1984 return -EINVAL; 1985 } 1986 ATM_SKB(skb)->vcc = vcc; 1987 1988 err = queue_skb(card, vc, skb, oam); 1989 if (err) { 1990 atomic_inc(&vcc->stats->tx_err); 1991 dev_kfree_skb(skb); 1992 return err; 1993 } 1994 1995 return 0; 1996 } 1997 1998 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 1999 { 2000 return idt77252_send_skb(vcc, skb, 0); 2001 } 2002 2003 static int 2004 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2005 { 2006 struct atm_dev *dev = vcc->dev; 2007 struct idt77252_dev *card = dev->dev_data; 2008 struct sk_buff *skb; 2009 2010 skb = dev_alloc_skb(64); 2011 if (!skb) { 2012 printk("%s: Out of memory in send_oam().\n", card->name); 2013 atomic_inc(&vcc->stats->tx_err); 2014 return -ENOMEM; 2015 } 2016 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2017 2018 memcpy(skb_put(skb, 52), cell, 52); 2019 2020 return idt77252_send_skb(vcc, skb, 1); 2021 } 2022 2023 static __inline__ unsigned int 2024 idt77252_fls(unsigned int x) 2025 { 2026 int r = 1; 2027 2028 if (x == 0) 2029 return 0; 2030 if (x & 0xffff0000) { 2031 x >>= 16; 2032 r += 16; 2033 } 2034 if (x & 0xff00) { 2035 x >>= 8; 2036 r += 8; 2037 } 2038 if (x & 0xf0) { 2039 x >>= 4; 2040 r += 4; 2041 } 2042 if (x & 0xc) { 2043 x >>= 2; 2044 r += 2; 2045 } 2046 if (x & 0x2) 2047 r += 1; 2048 return r; 2049 } 2050 2051 static u16 2052 idt77252_int_to_atmfp(unsigned int rate) 2053 { 2054 u16 m, e; 2055 2056 if (rate == 0) 2057 return 0; 2058 e = idt77252_fls(rate) - 1; 2059 if (e < 9) 2060 m = (rate - (1 << e)) << (9 - e); 2061 else if (e == 9) 2062 m = (rate - (1 << e)); 2063 else /* e > 9 */ 2064 m = (rate - (1 << e)) >> (e - 9); 2065 return 0x4000 | (e << 9) | m; 2066 } 2067 2068 static u8 2069 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2070 { 2071 u16 afp; 2072 2073 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2074 if (pcr < 0) 2075 return rate_to_log[(afp >> 5) & 0x1ff]; 2076 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2077 } 2078 2079 static void 2080 idt77252_est_timer(unsigned long data) 2081 { 2082 struct vc_map *vc = (struct vc_map *)data; 2083 struct idt77252_dev *card = vc->card; 2084 struct rate_estimator *est; 2085 unsigned long flags; 2086 u32 rate, cps; 2087 u64 ncells; 2088 u8 lacr; 2089 2090 spin_lock_irqsave(&vc->lock, flags); 2091 est = vc->estimator; 2092 if (!est) 2093 goto out; 2094 2095 ncells = est->cells; 2096 2097 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2098 est->last_cells = ncells; 2099 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2100 est->cps = (est->avcps + 0x1f) >> 5; 2101 2102 cps = est->cps; 2103 if (cps < (est->maxcps >> 4)) 2104 cps = est->maxcps >> 4; 2105 2106 lacr = idt77252_rate_logindex(card, cps); 2107 if (lacr > vc->max_er) 2108 lacr = vc->max_er; 2109 2110 if (lacr != vc->lacr) { 2111 vc->lacr = lacr; 2112 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2113 } 2114 2115 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2116 add_timer(&est->timer); 2117 2118 out: 2119 spin_unlock_irqrestore(&vc->lock, flags); 2120 } 2121 2122 static struct rate_estimator * 2123 idt77252_init_est(struct vc_map *vc, int pcr) 2124 { 2125 struct rate_estimator *est; 2126 2127 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2128 if (!est) 2129 return NULL; 2130 est->maxcps = pcr < 0 ? -pcr : pcr; 2131 est->cps = est->maxcps; 2132 est->avcps = est->cps << 5; 2133 2134 est->interval = 2; /* XXX: make this configurable */ 2135 est->ewma_log = 2; /* XXX: make this configurable */ 2136 init_timer(&est->timer); 2137 est->timer.data = (unsigned long)vc; 2138 est->timer.function = idt77252_est_timer; 2139 2140 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2141 add_timer(&est->timer); 2142 2143 return est; 2144 } 2145 2146 static int 2147 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2148 struct atm_vcc *vcc, struct atm_qos *qos) 2149 { 2150 int tst_free, tst_used, tst_entries; 2151 unsigned long tmpl, modl; 2152 int tcr, tcra; 2153 2154 if ((qos->txtp.max_pcr == 0) && 2155 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2156 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2157 card->name); 2158 return -EINVAL; 2159 } 2160 2161 tst_used = 0; 2162 tst_free = card->tst_free; 2163 if (test_bit(VCF_TX, &vc->flags)) 2164 tst_used = vc->ntste; 2165 tst_free += tst_used; 2166 2167 tcr = atm_pcr_goal(&qos->txtp); 2168 tcra = tcr >= 0 ? tcr : -tcr; 2169 2170 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2171 2172 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2173 modl = tmpl % (unsigned long)card->utopia_pcr; 2174 2175 tst_entries = (int) (tmpl / card->utopia_pcr); 2176 if (tcr > 0) { 2177 if (modl > 0) 2178 tst_entries++; 2179 } else if (tcr == 0) { 2180 tst_entries = tst_free - SAR_TST_RESERVED; 2181 if (tst_entries <= 0) { 2182 printk("%s: no CBR bandwidth free.\n", card->name); 2183 return -ENOSR; 2184 } 2185 } 2186 2187 if (tst_entries == 0) { 2188 printk("%s: selected CBR bandwidth < granularity.\n", 2189 card->name); 2190 return -EINVAL; 2191 } 2192 2193 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2194 printk("%s: not enough CBR bandwidth free.\n", card->name); 2195 return -ENOSR; 2196 } 2197 2198 vc->ntste = tst_entries; 2199 2200 card->tst_free = tst_free - tst_entries; 2201 if (test_bit(VCF_TX, &vc->flags)) { 2202 if (tst_used == tst_entries) 2203 return 0; 2204 2205 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2206 card->name, tst_used, tst_entries); 2207 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2208 return 0; 2209 } 2210 2211 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2212 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2213 return 0; 2214 } 2215 2216 static int 2217 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2218 struct atm_vcc *vcc, struct atm_qos *qos) 2219 { 2220 unsigned long flags; 2221 int tcr; 2222 2223 spin_lock_irqsave(&vc->lock, flags); 2224 if (vc->estimator) { 2225 del_timer(&vc->estimator->timer); 2226 kfree(vc->estimator); 2227 vc->estimator = NULL; 2228 } 2229 spin_unlock_irqrestore(&vc->lock, flags); 2230 2231 tcr = atm_pcr_goal(&qos->txtp); 2232 if (tcr == 0) 2233 tcr = card->link_pcr; 2234 2235 vc->estimator = idt77252_init_est(vc, tcr); 2236 2237 vc->class = SCHED_UBR; 2238 vc->init_er = idt77252_rate_logindex(card, tcr); 2239 vc->lacr = vc->init_er; 2240 if (tcr < 0) 2241 vc->max_er = vc->init_er; 2242 else 2243 vc->max_er = 0xff; 2244 2245 return 0; 2246 } 2247 2248 static int 2249 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2250 struct atm_vcc *vcc, struct atm_qos *qos) 2251 { 2252 int error; 2253 2254 if (test_bit(VCF_TX, &vc->flags)) 2255 return -EBUSY; 2256 2257 switch (qos->txtp.traffic_class) { 2258 case ATM_CBR: 2259 vc->class = SCHED_CBR; 2260 break; 2261 2262 case ATM_UBR: 2263 vc->class = SCHED_UBR; 2264 break; 2265 2266 case ATM_VBR: 2267 case ATM_ABR: 2268 default: 2269 return -EPROTONOSUPPORT; 2270 } 2271 2272 vc->scq = alloc_scq(card, vc->class); 2273 if (!vc->scq) { 2274 printk("%s: can't get SCQ.\n", card->name); 2275 return -ENOMEM; 2276 } 2277 2278 vc->scq->scd = get_free_scd(card, vc); 2279 if (vc->scq->scd == 0) { 2280 printk("%s: no SCD available.\n", card->name); 2281 free_scq(card, vc->scq); 2282 return -ENOMEM; 2283 } 2284 2285 fill_scd(card, vc->scq, vc->class); 2286 2287 if (set_tct(card, vc)) { 2288 printk("%s: class %d not supported.\n", 2289 card->name, qos->txtp.traffic_class); 2290 2291 card->scd2vc[vc->scd_index] = NULL; 2292 free_scq(card, vc->scq); 2293 return -EPROTONOSUPPORT; 2294 } 2295 2296 switch (vc->class) { 2297 case SCHED_CBR: 2298 error = idt77252_init_cbr(card, vc, vcc, qos); 2299 if (error) { 2300 card->scd2vc[vc->scd_index] = NULL; 2301 free_scq(card, vc->scq); 2302 return error; 2303 } 2304 2305 clear_bit(VCF_IDLE, &vc->flags); 2306 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2307 break; 2308 2309 case SCHED_UBR: 2310 error = idt77252_init_ubr(card, vc, vcc, qos); 2311 if (error) { 2312 card->scd2vc[vc->scd_index] = NULL; 2313 free_scq(card, vc->scq); 2314 return error; 2315 } 2316 2317 set_bit(VCF_IDLE, &vc->flags); 2318 break; 2319 } 2320 2321 vc->tx_vcc = vcc; 2322 set_bit(VCF_TX, &vc->flags); 2323 return 0; 2324 } 2325 2326 static int 2327 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2328 struct atm_vcc *vcc, struct atm_qos *qos) 2329 { 2330 unsigned long flags; 2331 unsigned long addr; 2332 u32 rcte = 0; 2333 2334 if (test_bit(VCF_RX, &vc->flags)) 2335 return -EBUSY; 2336 2337 vc->rx_vcc = vcc; 2338 set_bit(VCF_RX, &vc->flags); 2339 2340 if ((vcc->vci == 3) || (vcc->vci == 4)) 2341 return 0; 2342 2343 flush_rx_pool(card, &vc->rcv.rx_pool); 2344 2345 rcte |= SAR_RCTE_CONNECTOPEN; 2346 rcte |= SAR_RCTE_RAWCELLINTEN; 2347 2348 switch (qos->aal) { 2349 case ATM_AAL0: 2350 rcte |= SAR_RCTE_RCQ; 2351 break; 2352 case ATM_AAL1: 2353 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2354 break; 2355 case ATM_AAL34: 2356 rcte |= SAR_RCTE_AAL34; 2357 break; 2358 case ATM_AAL5: 2359 rcte |= SAR_RCTE_AAL5; 2360 break; 2361 default: 2362 rcte |= SAR_RCTE_RCQ; 2363 break; 2364 } 2365 2366 if (qos->aal != ATM_AAL5) 2367 rcte |= SAR_RCTE_FBP_1; 2368 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2369 rcte |= SAR_RCTE_FBP_3; 2370 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2371 rcte |= SAR_RCTE_FBP_2; 2372 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2373 rcte |= SAR_RCTE_FBP_1; 2374 else 2375 rcte |= SAR_RCTE_FBP_01; 2376 2377 addr = card->rct_base + (vc->index << 2); 2378 2379 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2380 write_sram(card, addr, rcte); 2381 2382 spin_lock_irqsave(&card->cmd_lock, flags); 2383 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2384 waitfor_idle(card); 2385 spin_unlock_irqrestore(&card->cmd_lock, flags); 2386 2387 return 0; 2388 } 2389 2390 static int 2391 idt77252_open(struct atm_vcc *vcc) 2392 { 2393 struct atm_dev *dev = vcc->dev; 2394 struct idt77252_dev *card = dev->dev_data; 2395 struct vc_map *vc; 2396 unsigned int index; 2397 unsigned int inuse; 2398 int error; 2399 int vci = vcc->vci; 2400 short vpi = vcc->vpi; 2401 2402 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2403 return 0; 2404 2405 if (vpi >= (1 << card->vpibits)) { 2406 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2407 return -EINVAL; 2408 } 2409 2410 if (vci >= (1 << card->vcibits)) { 2411 printk("%s: unsupported VCI: %d\n", card->name, vci); 2412 return -EINVAL; 2413 } 2414 2415 set_bit(ATM_VF_ADDR, &vcc->flags); 2416 2417 mutex_lock(&card->mutex); 2418 2419 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2420 2421 switch (vcc->qos.aal) { 2422 case ATM_AAL0: 2423 case ATM_AAL1: 2424 case ATM_AAL5: 2425 break; 2426 default: 2427 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2428 mutex_unlock(&card->mutex); 2429 return -EPROTONOSUPPORT; 2430 } 2431 2432 index = VPCI2VC(card, vpi, vci); 2433 if (!card->vcs[index]) { 2434 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2435 if (!card->vcs[index]) { 2436 printk("%s: can't alloc vc in open()\n", card->name); 2437 mutex_unlock(&card->mutex); 2438 return -ENOMEM; 2439 } 2440 card->vcs[index]->card = card; 2441 card->vcs[index]->index = index; 2442 2443 spin_lock_init(&card->vcs[index]->lock); 2444 } 2445 vc = card->vcs[index]; 2446 2447 vcc->dev_data = vc; 2448 2449 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2450 card->name, vc->index, vcc->vpi, vcc->vci, 2451 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2452 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2453 vcc->qos.rxtp.max_sdu); 2454 2455 inuse = 0; 2456 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2457 test_bit(VCF_TX, &vc->flags)) 2458 inuse = 1; 2459 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2460 test_bit(VCF_RX, &vc->flags)) 2461 inuse += 2; 2462 2463 if (inuse) { 2464 printk("%s: %s vci already in use.\n", card->name, 2465 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2466 mutex_unlock(&card->mutex); 2467 return -EADDRINUSE; 2468 } 2469 2470 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2471 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2472 if (error) { 2473 mutex_unlock(&card->mutex); 2474 return error; 2475 } 2476 } 2477 2478 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2479 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2480 if (error) { 2481 mutex_unlock(&card->mutex); 2482 return error; 2483 } 2484 } 2485 2486 set_bit(ATM_VF_READY, &vcc->flags); 2487 2488 mutex_unlock(&card->mutex); 2489 return 0; 2490 } 2491 2492 static void 2493 idt77252_close(struct atm_vcc *vcc) 2494 { 2495 struct atm_dev *dev = vcc->dev; 2496 struct idt77252_dev *card = dev->dev_data; 2497 struct vc_map *vc = vcc->dev_data; 2498 unsigned long flags; 2499 unsigned long addr; 2500 unsigned long timeout; 2501 2502 mutex_lock(&card->mutex); 2503 2504 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2505 card->name, vc->index, vcc->vpi, vcc->vci); 2506 2507 clear_bit(ATM_VF_READY, &vcc->flags); 2508 2509 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2510 2511 spin_lock_irqsave(&vc->lock, flags); 2512 clear_bit(VCF_RX, &vc->flags); 2513 vc->rx_vcc = NULL; 2514 spin_unlock_irqrestore(&vc->lock, flags); 2515 2516 if ((vcc->vci == 3) || (vcc->vci == 4)) 2517 goto done; 2518 2519 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2520 2521 spin_lock_irqsave(&card->cmd_lock, flags); 2522 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2523 waitfor_idle(card); 2524 spin_unlock_irqrestore(&card->cmd_lock, flags); 2525 2526 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2527 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2528 card->name); 2529 2530 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2531 } 2532 } 2533 2534 done: 2535 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2536 2537 spin_lock_irqsave(&vc->lock, flags); 2538 clear_bit(VCF_TX, &vc->flags); 2539 clear_bit(VCF_IDLE, &vc->flags); 2540 clear_bit(VCF_RSV, &vc->flags); 2541 vc->tx_vcc = NULL; 2542 2543 if (vc->estimator) { 2544 del_timer(&vc->estimator->timer); 2545 kfree(vc->estimator); 2546 vc->estimator = NULL; 2547 } 2548 spin_unlock_irqrestore(&vc->lock, flags); 2549 2550 timeout = 5 * 1000; 2551 while (atomic_read(&vc->scq->used) > 0) { 2552 timeout = msleep_interruptible(timeout); 2553 if (!timeout) 2554 break; 2555 } 2556 if (!timeout) 2557 printk("%s: SCQ drain timeout: %u used\n", 2558 card->name, atomic_read(&vc->scq->used)); 2559 2560 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2561 clear_scd(card, vc->scq, vc->class); 2562 2563 if (vc->class == SCHED_CBR) { 2564 clear_tst(card, vc); 2565 card->tst_free += vc->ntste; 2566 vc->ntste = 0; 2567 } 2568 2569 card->scd2vc[vc->scd_index] = NULL; 2570 free_scq(card, vc->scq); 2571 } 2572 2573 mutex_unlock(&card->mutex); 2574 } 2575 2576 static int 2577 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2578 { 2579 struct atm_dev *dev = vcc->dev; 2580 struct idt77252_dev *card = dev->dev_data; 2581 struct vc_map *vc = vcc->dev_data; 2582 int error = 0; 2583 2584 mutex_lock(&card->mutex); 2585 2586 if (qos->txtp.traffic_class != ATM_NONE) { 2587 if (!test_bit(VCF_TX, &vc->flags)) { 2588 error = idt77252_init_tx(card, vc, vcc, qos); 2589 if (error) 2590 goto out; 2591 } else { 2592 switch (qos->txtp.traffic_class) { 2593 case ATM_CBR: 2594 error = idt77252_init_cbr(card, vc, vcc, qos); 2595 if (error) 2596 goto out; 2597 break; 2598 2599 case ATM_UBR: 2600 error = idt77252_init_ubr(card, vc, vcc, qos); 2601 if (error) 2602 goto out; 2603 2604 if (!test_bit(VCF_IDLE, &vc->flags)) { 2605 writel(TCMDQ_LACR | (vc->lacr << 16) | 2606 vc->index, SAR_REG_TCMDQ); 2607 } 2608 break; 2609 2610 case ATM_VBR: 2611 case ATM_ABR: 2612 error = -EOPNOTSUPP; 2613 goto out; 2614 } 2615 } 2616 } 2617 2618 if ((qos->rxtp.traffic_class != ATM_NONE) && 2619 !test_bit(VCF_RX, &vc->flags)) { 2620 error = idt77252_init_rx(card, vc, vcc, qos); 2621 if (error) 2622 goto out; 2623 } 2624 2625 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2626 2627 set_bit(ATM_VF_HASQOS, &vcc->flags); 2628 2629 out: 2630 mutex_unlock(&card->mutex); 2631 return error; 2632 } 2633 2634 static int 2635 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2636 { 2637 struct idt77252_dev *card = dev->dev_data; 2638 int i, left; 2639 2640 left = (int) *pos; 2641 if (!left--) 2642 return sprintf(page, "IDT77252 Interrupts:\n"); 2643 if (!left--) 2644 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2645 if (!left--) 2646 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2647 if (!left--) 2648 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2649 if (!left--) 2650 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2651 if (!left--) 2652 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2653 if (!left--) 2654 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2655 if (!left--) 2656 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2657 if (!left--) 2658 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2659 if (!left--) 2660 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2661 if (!left--) 2662 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2663 if (!left--) 2664 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2665 if (!left--) 2666 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2667 if (!left--) 2668 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2669 if (!left--) 2670 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2671 2672 for (i = 0; i < card->tct_size; i++) { 2673 unsigned long tct; 2674 struct atm_vcc *vcc; 2675 struct vc_map *vc; 2676 char *p; 2677 2678 vc = card->vcs[i]; 2679 if (!vc) 2680 continue; 2681 2682 vcc = NULL; 2683 if (vc->tx_vcc) 2684 vcc = vc->tx_vcc; 2685 if (!vcc) 2686 continue; 2687 if (left--) 2688 continue; 2689 2690 p = page; 2691 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2692 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2693 2694 for (i = 0; i < 8; i++) 2695 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2696 p += sprintf(p, "\n"); 2697 return p - page; 2698 } 2699 return 0; 2700 } 2701 2702 /*****************************************************************************/ 2703 /* */ 2704 /* Interrupt handler */ 2705 /* */ 2706 /*****************************************************************************/ 2707 2708 static void 2709 idt77252_collect_stat(struct idt77252_dev *card) 2710 { 2711 (void) readl(SAR_REG_CDC); 2712 (void) readl(SAR_REG_VPEC); 2713 (void) readl(SAR_REG_ICC); 2714 2715 } 2716 2717 static irqreturn_t 2718 idt77252_interrupt(int irq, void *dev_id) 2719 { 2720 struct idt77252_dev *card = dev_id; 2721 u32 stat; 2722 2723 stat = readl(SAR_REG_STAT) & 0xffff; 2724 if (!stat) /* no interrupt for us */ 2725 return IRQ_NONE; 2726 2727 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2728 printk("%s: Re-entering irq_handler()\n", card->name); 2729 goto out; 2730 } 2731 2732 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2733 2734 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2735 INTPRINTK("%s: TSIF\n", card->name); 2736 card->irqstat[15]++; 2737 idt77252_tx(card); 2738 } 2739 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2740 INTPRINTK("%s: TXICP\n", card->name); 2741 card->irqstat[14]++; 2742 #ifdef CONFIG_ATM_IDT77252_DEBUG 2743 idt77252_tx_dump(card); 2744 #endif 2745 } 2746 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2747 INTPRINTK("%s: TSQF\n", card->name); 2748 card->irqstat[12]++; 2749 idt77252_tx(card); 2750 } 2751 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2752 INTPRINTK("%s: TMROF\n", card->name); 2753 card->irqstat[11]++; 2754 idt77252_collect_stat(card); 2755 } 2756 2757 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2758 INTPRINTK("%s: EPDU\n", card->name); 2759 card->irqstat[5]++; 2760 idt77252_rx(card); 2761 } 2762 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2763 INTPRINTK("%s: RSQAF\n", card->name); 2764 card->irqstat[1]++; 2765 idt77252_rx(card); 2766 } 2767 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2768 INTPRINTK("%s: RSQF\n", card->name); 2769 card->irqstat[6]++; 2770 idt77252_rx(card); 2771 } 2772 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2773 INTPRINTK("%s: RAWCF\n", card->name); 2774 card->irqstat[4]++; 2775 idt77252_rx_raw(card); 2776 } 2777 2778 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2779 INTPRINTK("%s: PHYI", card->name); 2780 card->irqstat[10]++; 2781 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2782 card->atmdev->phy->interrupt(card->atmdev); 2783 } 2784 2785 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2786 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2787 2788 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2789 2790 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2791 2792 if (stat & SAR_STAT_FBQ0A) 2793 card->irqstat[2]++; 2794 if (stat & SAR_STAT_FBQ1A) 2795 card->irqstat[3]++; 2796 if (stat & SAR_STAT_FBQ2A) 2797 card->irqstat[7]++; 2798 if (stat & SAR_STAT_FBQ3A) 2799 card->irqstat[8]++; 2800 2801 schedule_work(&card->tqueue); 2802 } 2803 2804 out: 2805 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2806 return IRQ_HANDLED; 2807 } 2808 2809 static void 2810 idt77252_softint(struct work_struct *work) 2811 { 2812 struct idt77252_dev *card = 2813 container_of(work, struct idt77252_dev, tqueue); 2814 u32 stat; 2815 int done; 2816 2817 for (done = 1; ; done = 1) { 2818 stat = readl(SAR_REG_STAT) >> 16; 2819 2820 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2821 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2822 done = 0; 2823 } 2824 2825 stat >>= 4; 2826 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2827 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2828 done = 0; 2829 } 2830 2831 stat >>= 4; 2832 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2833 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2834 done = 0; 2835 } 2836 2837 stat >>= 4; 2838 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2839 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2840 done = 0; 2841 } 2842 2843 if (done) 2844 break; 2845 } 2846 2847 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2848 } 2849 2850 2851 static int 2852 open_card_oam(struct idt77252_dev *card) 2853 { 2854 unsigned long flags; 2855 unsigned long addr; 2856 struct vc_map *vc; 2857 int vpi, vci; 2858 int index; 2859 u32 rcte; 2860 2861 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2862 for (vci = 3; vci < 5; vci++) { 2863 index = VPCI2VC(card, vpi, vci); 2864 2865 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2866 if (!vc) { 2867 printk("%s: can't alloc vc\n", card->name); 2868 return -ENOMEM; 2869 } 2870 vc->index = index; 2871 card->vcs[index] = vc; 2872 2873 flush_rx_pool(card, &vc->rcv.rx_pool); 2874 2875 rcte = SAR_RCTE_CONNECTOPEN | 2876 SAR_RCTE_RAWCELLINTEN | 2877 SAR_RCTE_RCQ | 2878 SAR_RCTE_FBP_1; 2879 2880 addr = card->rct_base + (vc->index << 2); 2881 write_sram(card, addr, rcte); 2882 2883 spin_lock_irqsave(&card->cmd_lock, flags); 2884 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2885 SAR_REG_CMD); 2886 waitfor_idle(card); 2887 spin_unlock_irqrestore(&card->cmd_lock, flags); 2888 } 2889 } 2890 2891 return 0; 2892 } 2893 2894 static void 2895 close_card_oam(struct idt77252_dev *card) 2896 { 2897 unsigned long flags; 2898 unsigned long addr; 2899 struct vc_map *vc; 2900 int vpi, vci; 2901 int index; 2902 2903 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2904 for (vci = 3; vci < 5; vci++) { 2905 index = VPCI2VC(card, vpi, vci); 2906 vc = card->vcs[index]; 2907 2908 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2909 2910 spin_lock_irqsave(&card->cmd_lock, flags); 2911 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2912 SAR_REG_CMD); 2913 waitfor_idle(card); 2914 spin_unlock_irqrestore(&card->cmd_lock, flags); 2915 2916 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2917 DPRINTK("%s: closing a VC " 2918 "with pending rx buffers.\n", 2919 card->name); 2920 2921 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2922 } 2923 } 2924 } 2925 } 2926 2927 static int 2928 open_card_ubr0(struct idt77252_dev *card) 2929 { 2930 struct vc_map *vc; 2931 2932 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2933 if (!vc) { 2934 printk("%s: can't alloc vc\n", card->name); 2935 return -ENOMEM; 2936 } 2937 card->vcs[0] = vc; 2938 vc->class = SCHED_UBR0; 2939 2940 vc->scq = alloc_scq(card, vc->class); 2941 if (!vc->scq) { 2942 printk("%s: can't get SCQ.\n", card->name); 2943 return -ENOMEM; 2944 } 2945 2946 card->scd2vc[0] = vc; 2947 vc->scd_index = 0; 2948 vc->scq->scd = card->scd_base; 2949 2950 fill_scd(card, vc->scq, vc->class); 2951 2952 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 2953 write_sram(card, card->tct_base + 1, 0); 2954 write_sram(card, card->tct_base + 2, 0); 2955 write_sram(card, card->tct_base + 3, 0); 2956 write_sram(card, card->tct_base + 4, 0); 2957 write_sram(card, card->tct_base + 5, 0); 2958 write_sram(card, card->tct_base + 6, 0); 2959 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 2960 2961 clear_bit(VCF_IDLE, &vc->flags); 2962 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 2963 return 0; 2964 } 2965 2966 static int 2967 idt77252_dev_open(struct idt77252_dev *card) 2968 { 2969 u32 conf; 2970 2971 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 2972 printk("%s: SAR not yet initialized.\n", card->name); 2973 return -1; 2974 } 2975 2976 conf = SAR_CFG_RXPTH| /* enable receive path */ 2977 SAR_RX_DELAY | /* interrupt on complete PDU */ 2978 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 2979 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 2980 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 2981 SAR_CFG_FBIE | /* interrupt on low free buffers */ 2982 SAR_CFG_TXEN | /* transmit operation enable */ 2983 SAR_CFG_TXINT | /* interrupt on transmit status */ 2984 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 2985 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 2986 SAR_CFG_PHYIE /* enable PHY interrupts */ 2987 ; 2988 2989 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 2990 /* Test RAW cell receive. */ 2991 conf |= SAR_CFG_VPECA; 2992 #endif 2993 2994 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 2995 2996 if (open_card_oam(card)) { 2997 printk("%s: Error initializing OAM.\n", card->name); 2998 return -1; 2999 } 3000 3001 if (open_card_ubr0(card)) { 3002 printk("%s: Error initializing UBR0.\n", card->name); 3003 return -1; 3004 } 3005 3006 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3007 return 0; 3008 } 3009 3010 static void idt77252_dev_close(struct atm_dev *dev) 3011 { 3012 struct idt77252_dev *card = dev->dev_data; 3013 u32 conf; 3014 3015 close_card_oam(card); 3016 3017 conf = SAR_CFG_RXPTH | /* enable receive path */ 3018 SAR_RX_DELAY | /* interrupt on complete PDU */ 3019 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3020 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3021 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3022 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3023 SAR_CFG_TXEN | /* transmit operation enable */ 3024 SAR_CFG_TXINT | /* interrupt on transmit status */ 3025 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3026 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3027 ; 3028 3029 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3030 3031 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3032 } 3033 3034 3035 /*****************************************************************************/ 3036 /* */ 3037 /* Initialisation and Deinitialization of IDT77252 */ 3038 /* */ 3039 /*****************************************************************************/ 3040 3041 3042 static void 3043 deinit_card(struct idt77252_dev *card) 3044 { 3045 struct sk_buff *skb; 3046 int i, j; 3047 3048 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3049 printk("%s: SAR not yet initialized.\n", card->name); 3050 return; 3051 } 3052 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3053 3054 writel(0, SAR_REG_CFG); 3055 3056 if (card->atmdev) 3057 atm_dev_deregister(card->atmdev); 3058 3059 for (i = 0; i < 4; i++) { 3060 for (j = 0; j < FBQ_SIZE; j++) { 3061 skb = card->sbpool[i].skb[j]; 3062 if (skb) { 3063 pci_unmap_single(card->pcidev, 3064 IDT77252_PRV_PADDR(skb), 3065 (skb_end_pointer(skb) - 3066 skb->data), 3067 PCI_DMA_FROMDEVICE); 3068 card->sbpool[i].skb[j] = NULL; 3069 dev_kfree_skb(skb); 3070 } 3071 } 3072 } 3073 3074 vfree(card->soft_tst); 3075 3076 vfree(card->scd2vc); 3077 3078 vfree(card->vcs); 3079 3080 if (card->raw_cell_hnd) { 3081 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3082 card->raw_cell_hnd, card->raw_cell_paddr); 3083 } 3084 3085 if (card->rsq.base) { 3086 DIPRINTK("%s: Release RSQ ...\n", card->name); 3087 deinit_rsq(card); 3088 } 3089 3090 if (card->tsq.base) { 3091 DIPRINTK("%s: Release TSQ ...\n", card->name); 3092 deinit_tsq(card); 3093 } 3094 3095 DIPRINTK("idt77252: Release IRQ.\n"); 3096 free_irq(card->pcidev->irq, card); 3097 3098 for (i = 0; i < 4; i++) { 3099 if (card->fbq[i]) 3100 iounmap(card->fbq[i]); 3101 } 3102 3103 if (card->membase) 3104 iounmap(card->membase); 3105 3106 clear_bit(IDT77252_BIT_INIT, &card->flags); 3107 DIPRINTK("%s: Card deinitialized.\n", card->name); 3108 } 3109 3110 3111 static void __devinit 3112 init_sram(struct idt77252_dev *card) 3113 { 3114 int i; 3115 3116 for (i = 0; i < card->sramsize; i += 4) 3117 write_sram(card, (i >> 2), 0); 3118 3119 /* set SRAM layout for THIS card */ 3120 if (card->sramsize == (512 * 1024)) { 3121 card->tct_base = SAR_SRAM_TCT_128_BASE; 3122 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3123 / SAR_SRAM_TCT_SIZE; 3124 card->rct_base = SAR_SRAM_RCT_128_BASE; 3125 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3126 / SAR_SRAM_RCT_SIZE; 3127 card->rt_base = SAR_SRAM_RT_128_BASE; 3128 card->scd_base = SAR_SRAM_SCD_128_BASE; 3129 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3130 / SAR_SRAM_SCD_SIZE; 3131 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3132 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3133 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3134 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3135 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3136 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3137 card->fifo_size = SAR_RXFD_SIZE_32K; 3138 } else { 3139 card->tct_base = SAR_SRAM_TCT_32_BASE; 3140 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3141 / SAR_SRAM_TCT_SIZE; 3142 card->rct_base = SAR_SRAM_RCT_32_BASE; 3143 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3144 / SAR_SRAM_RCT_SIZE; 3145 card->rt_base = SAR_SRAM_RT_32_BASE; 3146 card->scd_base = SAR_SRAM_SCD_32_BASE; 3147 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3148 / SAR_SRAM_SCD_SIZE; 3149 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3150 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3151 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3152 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3153 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3154 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3155 card->fifo_size = SAR_RXFD_SIZE_4K; 3156 } 3157 3158 /* Initialize TCT */ 3159 for (i = 0; i < card->tct_size; i++) { 3160 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3161 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3162 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3163 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3164 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3165 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3166 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3167 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3168 } 3169 3170 /* Initialize RCT */ 3171 for (i = 0; i < card->rct_size; i++) { 3172 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3173 (u32) SAR_RCTE_RAWCELLINTEN); 3174 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3175 (u32) 0); 3176 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3177 (u32) 0); 3178 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3179 (u32) 0xffffffff); 3180 } 3181 3182 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3183 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3184 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3185 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3186 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3187 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3188 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3189 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3190 3191 /* Initialize rate table */ 3192 for (i = 0; i < 256; i++) { 3193 write_sram(card, card->rt_base + i, log_to_rate[i]); 3194 } 3195 3196 for (i = 0; i < 128; i++) { 3197 unsigned int tmp; 3198 3199 tmp = rate_to_log[(i << 2) + 0] << 0; 3200 tmp |= rate_to_log[(i << 2) + 1] << 8; 3201 tmp |= rate_to_log[(i << 2) + 2] << 16; 3202 tmp |= rate_to_log[(i << 2) + 3] << 24; 3203 write_sram(card, card->rt_base + 256 + i, tmp); 3204 } 3205 3206 #if 0 /* Fill RDF and AIR tables. */ 3207 for (i = 0; i < 128; i++) { 3208 unsigned int tmp; 3209 3210 tmp = RDF[0][(i << 1) + 0] << 16; 3211 tmp |= RDF[0][(i << 1) + 1] << 0; 3212 write_sram(card, card->rt_base + 512 + i, tmp); 3213 } 3214 3215 for (i = 0; i < 128; i++) { 3216 unsigned int tmp; 3217 3218 tmp = AIR[0][(i << 1) + 0] << 16; 3219 tmp |= AIR[0][(i << 1) + 1] << 0; 3220 write_sram(card, card->rt_base + 640 + i, tmp); 3221 } 3222 #endif 3223 3224 IPRINTK("%s: initialize rate table ...\n", card->name); 3225 writel(card->rt_base << 2, SAR_REG_RTBL); 3226 3227 /* Initialize TSTs */ 3228 IPRINTK("%s: initialize TST ...\n", card->name); 3229 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3230 3231 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3232 write_sram(card, i, TSTE_OPC_VAR); 3233 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3234 idt77252_sram_write_errors = 1; 3235 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3236 idt77252_sram_write_errors = 0; 3237 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3238 write_sram(card, i, TSTE_OPC_VAR); 3239 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3240 idt77252_sram_write_errors = 1; 3241 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3242 idt77252_sram_write_errors = 0; 3243 3244 card->tst_index = 0; 3245 writel(card->tst[0] << 2, SAR_REG_TSTB); 3246 3247 /* Initialize ABRSTD and Receive FIFO */ 3248 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3249 writel(card->abrst_size | (card->abrst_base << 2), 3250 SAR_REG_ABRSTD); 3251 3252 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3253 writel(card->fifo_size | (card->fifo_base << 2), 3254 SAR_REG_RXFD); 3255 3256 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3257 } 3258 3259 static int __devinit 3260 init_card(struct atm_dev *dev) 3261 { 3262 struct idt77252_dev *card = dev->dev_data; 3263 struct pci_dev *pcidev = card->pcidev; 3264 unsigned long tmpl, modl; 3265 unsigned int linkrate, rsvdcr; 3266 unsigned int tst_entries; 3267 struct net_device *tmp; 3268 char tname[10]; 3269 3270 u32 size; 3271 u_char pci_byte; 3272 u32 conf; 3273 int i, k; 3274 3275 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3276 printk("Error: SAR already initialized.\n"); 3277 return -1; 3278 } 3279 3280 /*****************************************************************/ 3281 /* P C I C O N F I G U R A T I O N */ 3282 /*****************************************************************/ 3283 3284 /* Set PCI Retry-Timeout and TRDY timeout */ 3285 IPRINTK("%s: Checking PCI retries.\n", card->name); 3286 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3287 printk("%s: can't read PCI retry timeout.\n", card->name); 3288 deinit_card(card); 3289 return -1; 3290 } 3291 if (pci_byte != 0) { 3292 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3293 card->name, pci_byte); 3294 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3295 printk("%s: can't set PCI retry timeout.\n", 3296 card->name); 3297 deinit_card(card); 3298 return -1; 3299 } 3300 } 3301 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3302 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3303 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3304 deinit_card(card); 3305 return -1; 3306 } 3307 if (pci_byte != 0) { 3308 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3309 card->name, pci_byte); 3310 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3311 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3312 deinit_card(card); 3313 return -1; 3314 } 3315 } 3316 /* Reset Timer register */ 3317 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3318 printk("%s: resetting timer overflow.\n", card->name); 3319 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3320 } 3321 IPRINTK("%s: Request IRQ ... ", card->name); 3322 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED, 3323 card->name, card) != 0) { 3324 printk("%s: can't allocate IRQ.\n", card->name); 3325 deinit_card(card); 3326 return -1; 3327 } 3328 IPRINTK("got %d.\n", pcidev->irq); 3329 3330 /*****************************************************************/ 3331 /* C H E C K A N D I N I T S R A M */ 3332 /*****************************************************************/ 3333 3334 IPRINTK("%s: Initializing SRAM\n", card->name); 3335 3336 /* preset size of connecton table, so that init_sram() knows about it */ 3337 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3338 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3339 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3340 #ifndef ATM_IDT77252_SEND_IDLE 3341 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3342 #endif 3343 0; 3344 3345 if (card->sramsize == (512 * 1024)) 3346 conf |= SAR_CFG_CNTBL_1k; 3347 else 3348 conf |= SAR_CFG_CNTBL_512; 3349 3350 switch (vpibits) { 3351 case 0: 3352 conf |= SAR_CFG_VPVCS_0; 3353 break; 3354 default: 3355 case 1: 3356 conf |= SAR_CFG_VPVCS_1; 3357 break; 3358 case 2: 3359 conf |= SAR_CFG_VPVCS_2; 3360 break; 3361 case 8: 3362 conf |= SAR_CFG_VPVCS_8; 3363 break; 3364 } 3365 3366 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3367 3368 init_sram(card); 3369 3370 /********************************************************************/ 3371 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3372 /********************************************************************/ 3373 /* Initialize TSQ */ 3374 if (0 != init_tsq(card)) { 3375 deinit_card(card); 3376 return -1; 3377 } 3378 /* Initialize RSQ */ 3379 if (0 != init_rsq(card)) { 3380 deinit_card(card); 3381 return -1; 3382 } 3383 3384 card->vpibits = vpibits; 3385 if (card->sramsize == (512 * 1024)) { 3386 card->vcibits = 10 - card->vpibits; 3387 } else { 3388 card->vcibits = 9 - card->vpibits; 3389 } 3390 3391 card->vcimask = 0; 3392 for (k = 0, i = 1; k < card->vcibits; k++) { 3393 card->vcimask |= i; 3394 i <<= 1; 3395 } 3396 3397 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3398 writel(0, SAR_REG_VPM); 3399 3400 /* Little Endian Order */ 3401 writel(0, SAR_REG_GP); 3402 3403 /* Initialize RAW Cell Handle Register */ 3404 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3405 &card->raw_cell_paddr); 3406 if (!card->raw_cell_hnd) { 3407 printk("%s: memory allocation failure.\n", card->name); 3408 deinit_card(card); 3409 return -1; 3410 } 3411 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3412 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3413 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3414 card->raw_cell_hnd); 3415 3416 size = sizeof(struct vc_map *) * card->tct_size; 3417 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3418 if (NULL == (card->vcs = vmalloc(size))) { 3419 printk("%s: memory allocation failure.\n", card->name); 3420 deinit_card(card); 3421 return -1; 3422 } 3423 memset(card->vcs, 0, size); 3424 3425 size = sizeof(struct vc_map *) * card->scd_size; 3426 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3427 card->name, size); 3428 if (NULL == (card->scd2vc = vmalloc(size))) { 3429 printk("%s: memory allocation failure.\n", card->name); 3430 deinit_card(card); 3431 return -1; 3432 } 3433 memset(card->scd2vc, 0, size); 3434 3435 size = sizeof(struct tst_info) * (card->tst_size - 2); 3436 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3437 card->name, size); 3438 if (NULL == (card->soft_tst = vmalloc(size))) { 3439 printk("%s: memory allocation failure.\n", card->name); 3440 deinit_card(card); 3441 return -1; 3442 } 3443 for (i = 0; i < card->tst_size - 2; i++) { 3444 card->soft_tst[i].tste = TSTE_OPC_VAR; 3445 card->soft_tst[i].vc = NULL; 3446 } 3447 3448 if (dev->phy == NULL) { 3449 printk("%s: No LT device defined.\n", card->name); 3450 deinit_card(card); 3451 return -1; 3452 } 3453 if (dev->phy->ioctl == NULL) { 3454 printk("%s: LT had no IOCTL function defined.\n", card->name); 3455 deinit_card(card); 3456 return -1; 3457 } 3458 3459 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3460 /* 3461 * this is a jhs hack to get around special functionality in the 3462 * phy driver for the atecom hardware; the functionality doesn't 3463 * exist in the linux atm suni driver 3464 * 3465 * it isn't the right way to do things, but as the guy from NIST 3466 * said, talking about their measurement of the fine structure 3467 * constant, "it's good enough for government work." 3468 */ 3469 linkrate = 149760000; 3470 #endif 3471 3472 card->link_pcr = (linkrate / 8 / 53); 3473 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3474 card->name, linkrate, card->link_pcr); 3475 3476 #ifdef ATM_IDT77252_SEND_IDLE 3477 card->utopia_pcr = card->link_pcr; 3478 #else 3479 card->utopia_pcr = (160000000 / 8 / 54); 3480 #endif 3481 3482 rsvdcr = 0; 3483 if (card->utopia_pcr > card->link_pcr) 3484 rsvdcr = card->utopia_pcr - card->link_pcr; 3485 3486 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3487 modl = tmpl % (unsigned long)card->utopia_pcr; 3488 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3489 if (modl) 3490 tst_entries++; 3491 card->tst_free -= tst_entries; 3492 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3493 3494 #ifdef HAVE_EEPROM 3495 idt77252_eeprom_init(card); 3496 printk("%s: EEPROM: %02x:", card->name, 3497 idt77252_eeprom_read_status(card)); 3498 3499 for (i = 0; i < 0x80; i++) { 3500 printk(" %02x", 3501 idt77252_eeprom_read_byte(card, i) 3502 ); 3503 } 3504 printk("\n"); 3505 #endif /* HAVE_EEPROM */ 3506 3507 /* 3508 * XXX: <hack> 3509 */ 3510 sprintf(tname, "eth%d", card->index); 3511 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3512 if (tmp) { 3513 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3514 3515 printk("%s: ESI %pM\n", card->name, card->atmdev->esi); 3516 } 3517 /* 3518 * XXX: </hack> 3519 */ 3520 3521 /* Set Maximum Deficit Count for now. */ 3522 writel(0xffff, SAR_REG_MDFCT); 3523 3524 set_bit(IDT77252_BIT_INIT, &card->flags); 3525 3526 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3527 return 0; 3528 } 3529 3530 3531 /*****************************************************************************/ 3532 /* */ 3533 /* Probing of IDT77252 ABR SAR */ 3534 /* */ 3535 /*****************************************************************************/ 3536 3537 3538 static int __devinit 3539 idt77252_preset(struct idt77252_dev *card) 3540 { 3541 u16 pci_command; 3542 3543 /*****************************************************************/ 3544 /* P C I C O N F I G U R A T I O N */ 3545 /*****************************************************************/ 3546 3547 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3548 card->name); 3549 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3550 printk("%s: can't read PCI_COMMAND.\n", card->name); 3551 deinit_card(card); 3552 return -1; 3553 } 3554 if (!(pci_command & PCI_COMMAND_IO)) { 3555 printk("%s: PCI_COMMAND: %04x (???)\n", 3556 card->name, pci_command); 3557 deinit_card(card); 3558 return (-1); 3559 } 3560 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3561 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3562 printk("%s: can't write PCI_COMMAND.\n", card->name); 3563 deinit_card(card); 3564 return -1; 3565 } 3566 /*****************************************************************/ 3567 /* G E N E R I C R E S E T */ 3568 /*****************************************************************/ 3569 3570 /* Software reset */ 3571 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3572 mdelay(1); 3573 writel(0, SAR_REG_CFG); 3574 3575 IPRINTK("%s: Software resetted.\n", card->name); 3576 return 0; 3577 } 3578 3579 3580 static unsigned long __devinit 3581 probe_sram(struct idt77252_dev *card) 3582 { 3583 u32 data, addr; 3584 3585 writel(0, SAR_REG_DR0); 3586 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3587 3588 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3589 writel(ATM_POISON, SAR_REG_DR0); 3590 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3591 3592 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3593 data = readl(SAR_REG_DR0); 3594 3595 if (data != 0) 3596 break; 3597 } 3598 3599 return addr * sizeof(u32); 3600 } 3601 3602 static int __devinit 3603 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3604 { 3605 static struct idt77252_dev **last = &idt77252_chain; 3606 static int index = 0; 3607 3608 unsigned long membase, srambase; 3609 struct idt77252_dev *card; 3610 struct atm_dev *dev; 3611 int i, err; 3612 3613 3614 if ((err = pci_enable_device(pcidev))) { 3615 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3616 return err; 3617 } 3618 3619 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3620 if (!card) { 3621 printk("idt77252-%d: can't allocate private data\n", index); 3622 err = -ENOMEM; 3623 goto err_out_disable_pdev; 3624 } 3625 card->revision = pcidev->revision; 3626 card->index = index; 3627 card->pcidev = pcidev; 3628 sprintf(card->name, "idt77252-%d", card->index); 3629 3630 INIT_WORK(&card->tqueue, idt77252_softint); 3631 3632 membase = pci_resource_start(pcidev, 1); 3633 srambase = pci_resource_start(pcidev, 2); 3634 3635 mutex_init(&card->mutex); 3636 spin_lock_init(&card->cmd_lock); 3637 spin_lock_init(&card->tst_lock); 3638 3639 init_timer(&card->tst_timer); 3640 card->tst_timer.data = (unsigned long)card; 3641 card->tst_timer.function = tst_timer; 3642 3643 /* Do the I/O remapping... */ 3644 card->membase = ioremap(membase, 1024); 3645 if (!card->membase) { 3646 printk("%s: can't ioremap() membase\n", card->name); 3647 err = -EIO; 3648 goto err_out_free_card; 3649 } 3650 3651 if (idt77252_preset(card)) { 3652 printk("%s: preset failed\n", card->name); 3653 err = -EIO; 3654 goto err_out_iounmap; 3655 } 3656 3657 dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1, 3658 NULL); 3659 if (!dev) { 3660 printk("%s: can't register atm device\n", card->name); 3661 err = -EIO; 3662 goto err_out_iounmap; 3663 } 3664 dev->dev_data = card; 3665 card->atmdev = dev; 3666 3667 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3668 suni_init(dev); 3669 if (!dev->phy) { 3670 printk("%s: can't init SUNI\n", card->name); 3671 err = -EIO; 3672 goto err_out_deinit_card; 3673 } 3674 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3675 3676 card->sramsize = probe_sram(card); 3677 3678 for (i = 0; i < 4; i++) { 3679 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3680 if (!card->fbq[i]) { 3681 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3682 err = -EIO; 3683 goto err_out_deinit_card; 3684 } 3685 } 3686 3687 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3688 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3689 'A' + card->revision - 1 : '?', membase, srambase, 3690 card->sramsize / 1024); 3691 3692 if (init_card(dev)) { 3693 printk("%s: init_card failed\n", card->name); 3694 err = -EIO; 3695 goto err_out_deinit_card; 3696 } 3697 3698 dev->ci_range.vpi_bits = card->vpibits; 3699 dev->ci_range.vci_bits = card->vcibits; 3700 dev->link_rate = card->link_pcr; 3701 3702 if (dev->phy->start) 3703 dev->phy->start(dev); 3704 3705 if (idt77252_dev_open(card)) { 3706 printk("%s: dev_open failed\n", card->name); 3707 err = -EIO; 3708 goto err_out_stop; 3709 } 3710 3711 *last = card; 3712 last = &card->next; 3713 index++; 3714 3715 return 0; 3716 3717 err_out_stop: 3718 if (dev->phy->stop) 3719 dev->phy->stop(dev); 3720 3721 err_out_deinit_card: 3722 deinit_card(card); 3723 3724 err_out_iounmap: 3725 iounmap(card->membase); 3726 3727 err_out_free_card: 3728 kfree(card); 3729 3730 err_out_disable_pdev: 3731 pci_disable_device(pcidev); 3732 return err; 3733 } 3734 3735 static struct pci_device_id idt77252_pci_tbl[] = 3736 { 3737 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 }, 3738 { 0, } 3739 }; 3740 3741 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3742 3743 static struct pci_driver idt77252_driver = { 3744 .name = "idt77252", 3745 .id_table = idt77252_pci_tbl, 3746 .probe = idt77252_init_one, 3747 }; 3748 3749 static int __init idt77252_init(void) 3750 { 3751 struct sk_buff *skb; 3752 3753 printk("%s: at %p\n", __func__, idt77252_init); 3754 3755 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3756 sizeof(struct idt77252_skb_prv)) { 3757 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3758 __func__, (unsigned long) sizeof(skb->cb), 3759 (unsigned long) sizeof(struct atm_skb_data) + 3760 sizeof(struct idt77252_skb_prv)); 3761 return -EIO; 3762 } 3763 3764 return pci_register_driver(&idt77252_driver); 3765 } 3766 3767 static void __exit idt77252_exit(void) 3768 { 3769 struct idt77252_dev *card; 3770 struct atm_dev *dev; 3771 3772 pci_unregister_driver(&idt77252_driver); 3773 3774 while (idt77252_chain) { 3775 card = idt77252_chain; 3776 dev = card->atmdev; 3777 idt77252_chain = card->next; 3778 3779 if (dev->phy->stop) 3780 dev->phy->stop(dev); 3781 deinit_card(card); 3782 pci_disable_device(card->pcidev); 3783 kfree(card); 3784 } 3785 3786 DIPRINTK("idt77252: finished cleanup-module().\n"); 3787 } 3788 3789 module_init(idt77252_init); 3790 module_exit(idt77252_exit); 3791 3792 MODULE_LICENSE("GPL"); 3793 3794 module_param(vpibits, uint, 0); 3795 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3796 #ifdef CONFIG_ATM_IDT77252_DEBUG 3797 module_param(debug, ulong, 0644); 3798 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3799 #endif 3800 3801 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3802 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3803