1 /******************************************************************* 2 * 3 * Copyright (c) 2000 ATecoM GmbH 4 * 5 * The author may be reached at ecd@atecom.com. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 *******************************************************************/ 28 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/poison.h> 32 #include <linux/skbuff.h> 33 #include <linux/kernel.h> 34 #include <linux/vmalloc.h> 35 #include <linux/netdevice.h> 36 #include <linux/atmdev.h> 37 #include <linux/atm.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/bitops.h> 41 #include <linux/wait.h> 42 #include <linux/jiffies.h> 43 #include <linux/mutex.h> 44 45 #include <asm/io.h> 46 #include <asm/uaccess.h> 47 #include <asm/atomic.h> 48 #include <asm/byteorder.h> 49 50 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 51 #include "suni.h" 52 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 53 54 55 #include "idt77252.h" 56 #include "idt77252_tables.h" 57 58 static unsigned int vpibits = 1; 59 60 61 #define ATM_IDT77252_SEND_IDLE 1 62 63 64 /* 65 * Debug HACKs. 66 */ 67 #define DEBUG_MODULE 1 68 #undef HAVE_EEPROM /* does not work, yet. */ 69 70 #ifdef CONFIG_ATM_IDT77252_DEBUG 71 static unsigned long debug = DBG_GENERAL; 72 #endif 73 74 75 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 76 77 78 /* 79 * SCQ Handling. 80 */ 81 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 82 static void free_scq(struct idt77252_dev *, struct scq_info *); 83 static int queue_skb(struct idt77252_dev *, struct vc_map *, 84 struct sk_buff *, int oam); 85 static void drain_scq(struct idt77252_dev *, struct vc_map *); 86 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 87 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 88 89 /* 90 * FBQ Handling. 91 */ 92 static int push_rx_skb(struct idt77252_dev *, 93 struct sk_buff *, int queue); 94 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 95 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 96 static void recycle_rx_pool_skb(struct idt77252_dev *, 97 struct rx_pool *); 98 static void add_rx_skb(struct idt77252_dev *, int queue, 99 unsigned int size, unsigned int count); 100 101 /* 102 * RSQ Handling. 103 */ 104 static int init_rsq(struct idt77252_dev *); 105 static void deinit_rsq(struct idt77252_dev *); 106 static void idt77252_rx(struct idt77252_dev *); 107 108 /* 109 * TSQ handling. 110 */ 111 static int init_tsq(struct idt77252_dev *); 112 static void deinit_tsq(struct idt77252_dev *); 113 static void idt77252_tx(struct idt77252_dev *); 114 115 116 /* 117 * ATM Interface. 118 */ 119 static void idt77252_dev_close(struct atm_dev *dev); 120 static int idt77252_open(struct atm_vcc *vcc); 121 static void idt77252_close(struct atm_vcc *vcc); 122 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 123 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 124 int flags); 125 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 126 unsigned long addr); 127 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 128 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 129 int flags); 130 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 131 char *page); 132 static void idt77252_softint(struct work_struct *work); 133 134 135 static struct atmdev_ops idt77252_ops = 136 { 137 .dev_close = idt77252_dev_close, 138 .open = idt77252_open, 139 .close = idt77252_close, 140 .send = idt77252_send, 141 .send_oam = idt77252_send_oam, 142 .phy_put = idt77252_phy_put, 143 .phy_get = idt77252_phy_get, 144 .change_qos = idt77252_change_qos, 145 .proc_read = idt77252_proc_read, 146 .owner = THIS_MODULE 147 }; 148 149 static struct idt77252_dev *idt77252_chain = NULL; 150 static unsigned int idt77252_sram_write_errors = 0; 151 152 /*****************************************************************************/ 153 /* */ 154 /* I/O and Utility Bus */ 155 /* */ 156 /*****************************************************************************/ 157 158 static void 159 waitfor_idle(struct idt77252_dev *card) 160 { 161 u32 stat; 162 163 stat = readl(SAR_REG_STAT); 164 while (stat & SAR_STAT_CMDBZ) 165 stat = readl(SAR_REG_STAT); 166 } 167 168 static u32 169 read_sram(struct idt77252_dev *card, unsigned long addr) 170 { 171 unsigned long flags; 172 u32 value; 173 174 spin_lock_irqsave(&card->cmd_lock, flags); 175 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 176 waitfor_idle(card); 177 value = readl(SAR_REG_DR0); 178 spin_unlock_irqrestore(&card->cmd_lock, flags); 179 return value; 180 } 181 182 static void 183 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 184 { 185 unsigned long flags; 186 187 if ((idt77252_sram_write_errors == 0) && 188 (((addr > card->tst[0] + card->tst_size - 2) && 189 (addr < card->tst[0] + card->tst_size)) || 190 ((addr > card->tst[1] + card->tst_size - 2) && 191 (addr < card->tst[1] + card->tst_size)))) { 192 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 193 card->name, addr, value); 194 } 195 196 spin_lock_irqsave(&card->cmd_lock, flags); 197 writel(value, SAR_REG_DR0); 198 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 199 waitfor_idle(card); 200 spin_unlock_irqrestore(&card->cmd_lock, flags); 201 } 202 203 static u8 204 read_utility(void *dev, unsigned long ubus_addr) 205 { 206 struct idt77252_dev *card = dev; 207 unsigned long flags; 208 u8 value; 209 210 if (!card) { 211 printk("Error: No such device.\n"); 212 return -1; 213 } 214 215 spin_lock_irqsave(&card->cmd_lock, flags); 216 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 217 waitfor_idle(card); 218 value = readl(SAR_REG_DR0); 219 spin_unlock_irqrestore(&card->cmd_lock, flags); 220 return value; 221 } 222 223 static void 224 write_utility(void *dev, unsigned long ubus_addr, u8 value) 225 { 226 struct idt77252_dev *card = dev; 227 unsigned long flags; 228 229 if (!card) { 230 printk("Error: No such device.\n"); 231 return; 232 } 233 234 spin_lock_irqsave(&card->cmd_lock, flags); 235 writel((u32) value, SAR_REG_DR0); 236 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 237 waitfor_idle(card); 238 spin_unlock_irqrestore(&card->cmd_lock, flags); 239 } 240 241 #ifdef HAVE_EEPROM 242 static u32 rdsrtab[] = 243 { 244 SAR_GP_EECS | SAR_GP_EESCLK, 245 0, 246 SAR_GP_EESCLK, /* 0 */ 247 0, 248 SAR_GP_EESCLK, /* 0 */ 249 0, 250 SAR_GP_EESCLK, /* 0 */ 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 SAR_GP_EEDO, 256 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 257 0, 258 SAR_GP_EESCLK, /* 0 */ 259 SAR_GP_EEDO, 260 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 261 }; 262 263 static u32 wrentab[] = 264 { 265 SAR_GP_EECS | SAR_GP_EESCLK, 266 0, 267 SAR_GP_EESCLK, /* 0 */ 268 0, 269 SAR_GP_EESCLK, /* 0 */ 270 0, 271 SAR_GP_EESCLK, /* 0 */ 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 SAR_GP_EEDO, 275 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 276 SAR_GP_EEDO, 277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 278 0, 279 SAR_GP_EESCLK, /* 0 */ 280 0, 281 SAR_GP_EESCLK /* 0 */ 282 }; 283 284 static u32 rdtab[] = 285 { 286 SAR_GP_EECS | SAR_GP_EESCLK, 287 0, 288 SAR_GP_EESCLK, /* 0 */ 289 0, 290 SAR_GP_EESCLK, /* 0 */ 291 0, 292 SAR_GP_EESCLK, /* 0 */ 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 SAR_GP_EEDO, 300 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 301 SAR_GP_EEDO, 302 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 303 }; 304 305 static u32 wrtab[] = 306 { 307 SAR_GP_EECS | SAR_GP_EESCLK, 308 0, 309 SAR_GP_EESCLK, /* 0 */ 310 0, 311 SAR_GP_EESCLK, /* 0 */ 312 0, 313 SAR_GP_EESCLK, /* 0 */ 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 SAR_GP_EEDO, 321 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 322 0, 323 SAR_GP_EESCLK /* 0 */ 324 }; 325 326 static u32 clktab[] = 327 { 328 0, 329 SAR_GP_EESCLK, 330 0, 331 SAR_GP_EESCLK, 332 0, 333 SAR_GP_EESCLK, 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0 345 }; 346 347 static u32 348 idt77252_read_gp(struct idt77252_dev *card) 349 { 350 u32 gp; 351 352 gp = readl(SAR_REG_GP); 353 #if 0 354 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 355 #endif 356 return gp; 357 } 358 359 static void 360 idt77252_write_gp(struct idt77252_dev *card, u32 value) 361 { 362 unsigned long flags; 363 364 #if 0 365 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 366 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 367 value & SAR_GP_EEDO ? "1" : "0"); 368 #endif 369 370 spin_lock_irqsave(&card->cmd_lock, flags); 371 waitfor_idle(card); 372 writel(value, SAR_REG_GP); 373 spin_unlock_irqrestore(&card->cmd_lock, flags); 374 } 375 376 static u8 377 idt77252_eeprom_read_status(struct idt77252_dev *card) 378 { 379 u8 byte; 380 u32 gp; 381 int i, j; 382 383 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 384 385 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 386 idt77252_write_gp(card, gp | rdsrtab[i]); 387 udelay(5); 388 } 389 idt77252_write_gp(card, gp | SAR_GP_EECS); 390 udelay(5); 391 392 byte = 0; 393 for (i = 0, j = 0; i < 8; i++) { 394 byte <<= 1; 395 396 idt77252_write_gp(card, gp | clktab[j++]); 397 udelay(5); 398 399 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 400 401 idt77252_write_gp(card, gp | clktab[j++]); 402 udelay(5); 403 } 404 idt77252_write_gp(card, gp | SAR_GP_EECS); 405 udelay(5); 406 407 return byte; 408 } 409 410 static u8 411 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 412 { 413 u8 byte; 414 u32 gp; 415 int i, j; 416 417 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 418 419 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 420 idt77252_write_gp(card, gp | rdtab[i]); 421 udelay(5); 422 } 423 idt77252_write_gp(card, gp | SAR_GP_EECS); 424 udelay(5); 425 426 for (i = 0, j = 0; i < 8; i++) { 427 idt77252_write_gp(card, gp | clktab[j++] | 428 (offset & 1 ? SAR_GP_EEDO : 0)); 429 udelay(5); 430 431 idt77252_write_gp(card, gp | clktab[j++] | 432 (offset & 1 ? SAR_GP_EEDO : 0)); 433 udelay(5); 434 435 offset >>= 1; 436 } 437 idt77252_write_gp(card, gp | SAR_GP_EECS); 438 udelay(5); 439 440 byte = 0; 441 for (i = 0, j = 0; i < 8; i++) { 442 byte <<= 1; 443 444 idt77252_write_gp(card, gp | clktab[j++]); 445 udelay(5); 446 447 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 448 449 idt77252_write_gp(card, gp | clktab[j++]); 450 udelay(5); 451 } 452 idt77252_write_gp(card, gp | SAR_GP_EECS); 453 udelay(5); 454 455 return byte; 456 } 457 458 static void 459 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 460 { 461 u32 gp; 462 int i, j; 463 464 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 465 466 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 467 idt77252_write_gp(card, gp | wrentab[i]); 468 udelay(5); 469 } 470 idt77252_write_gp(card, gp | SAR_GP_EECS); 471 udelay(5); 472 473 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 474 idt77252_write_gp(card, gp | wrtab[i]); 475 udelay(5); 476 } 477 idt77252_write_gp(card, gp | SAR_GP_EECS); 478 udelay(5); 479 480 for (i = 0, j = 0; i < 8; i++) { 481 idt77252_write_gp(card, gp | clktab[j++] | 482 (offset & 1 ? SAR_GP_EEDO : 0)); 483 udelay(5); 484 485 idt77252_write_gp(card, gp | clktab[j++] | 486 (offset & 1 ? SAR_GP_EEDO : 0)); 487 udelay(5); 488 489 offset >>= 1; 490 } 491 idt77252_write_gp(card, gp | SAR_GP_EECS); 492 udelay(5); 493 494 for (i = 0, j = 0; i < 8; i++) { 495 idt77252_write_gp(card, gp | clktab[j++] | 496 (data & 1 ? SAR_GP_EEDO : 0)); 497 udelay(5); 498 499 idt77252_write_gp(card, gp | clktab[j++] | 500 (data & 1 ? SAR_GP_EEDO : 0)); 501 udelay(5); 502 503 data >>= 1; 504 } 505 idt77252_write_gp(card, gp | SAR_GP_EECS); 506 udelay(5); 507 } 508 509 static void 510 idt77252_eeprom_init(struct idt77252_dev *card) 511 { 512 u32 gp; 513 514 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 515 516 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 517 udelay(5); 518 idt77252_write_gp(card, gp | SAR_GP_EECS); 519 udelay(5); 520 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 521 udelay(5); 522 idt77252_write_gp(card, gp | SAR_GP_EECS); 523 udelay(5); 524 } 525 #endif /* HAVE_EEPROM */ 526 527 528 #ifdef CONFIG_ATM_IDT77252_DEBUG 529 static void 530 dump_tct(struct idt77252_dev *card, int index) 531 { 532 unsigned long tct; 533 int i; 534 535 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 536 537 printk("%s: TCT %x:", card->name, index); 538 for (i = 0; i < 8; i++) { 539 printk(" %08x", read_sram(card, tct + i)); 540 } 541 printk("\n"); 542 } 543 544 static void 545 idt77252_tx_dump(struct idt77252_dev *card) 546 { 547 struct atm_vcc *vcc; 548 struct vc_map *vc; 549 int i; 550 551 printk("%s\n", __func__); 552 for (i = 0; i < card->tct_size; i++) { 553 vc = card->vcs[i]; 554 if (!vc) 555 continue; 556 557 vcc = NULL; 558 if (vc->rx_vcc) 559 vcc = vc->rx_vcc; 560 else if (vc->tx_vcc) 561 vcc = vc->tx_vcc; 562 563 if (!vcc) 564 continue; 565 566 printk("%s: Connection %d:\n", card->name, vc->index); 567 dump_tct(card, vc->index); 568 } 569 } 570 #endif 571 572 573 /*****************************************************************************/ 574 /* */ 575 /* SCQ Handling */ 576 /* */ 577 /*****************************************************************************/ 578 579 static int 580 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 581 { 582 struct sb_pool *pool = &card->sbpool[queue]; 583 int index; 584 585 index = pool->index; 586 while (pool->skb[index]) { 587 index = (index + 1) & FBQ_MASK; 588 if (index == pool->index) 589 return -ENOBUFS; 590 } 591 592 pool->skb[index] = skb; 593 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 594 595 pool->index = (index + 1) & FBQ_MASK; 596 return 0; 597 } 598 599 static void 600 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 601 { 602 unsigned int queue, index; 603 u32 handle; 604 605 handle = IDT77252_PRV_POOL(skb); 606 607 queue = POOL_QUEUE(handle); 608 if (queue > 3) 609 return; 610 611 index = POOL_INDEX(handle); 612 if (index > FBQ_SIZE - 1) 613 return; 614 615 card->sbpool[queue].skb[index] = NULL; 616 } 617 618 static struct sk_buff * 619 sb_pool_skb(struct idt77252_dev *card, u32 handle) 620 { 621 unsigned int queue, index; 622 623 queue = POOL_QUEUE(handle); 624 if (queue > 3) 625 return NULL; 626 627 index = POOL_INDEX(handle); 628 if (index > FBQ_SIZE - 1) 629 return NULL; 630 631 return card->sbpool[queue].skb[index]; 632 } 633 634 static struct scq_info * 635 alloc_scq(struct idt77252_dev *card, int class) 636 { 637 struct scq_info *scq; 638 639 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 640 if (!scq) 641 return NULL; 642 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 643 &scq->paddr); 644 if (scq->base == NULL) { 645 kfree(scq); 646 return NULL; 647 } 648 memset(scq->base, 0, SCQ_SIZE); 649 650 scq->next = scq->base; 651 scq->last = scq->base + (SCQ_ENTRIES - 1); 652 atomic_set(&scq->used, 0); 653 654 spin_lock_init(&scq->lock); 655 spin_lock_init(&scq->skblock); 656 657 skb_queue_head_init(&scq->transmit); 658 skb_queue_head_init(&scq->pending); 659 660 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 661 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 662 663 return scq; 664 } 665 666 static void 667 free_scq(struct idt77252_dev *card, struct scq_info *scq) 668 { 669 struct sk_buff *skb; 670 struct atm_vcc *vcc; 671 672 pci_free_consistent(card->pcidev, SCQ_SIZE, 673 scq->base, scq->paddr); 674 675 while ((skb = skb_dequeue(&scq->transmit))) { 676 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 677 skb->len, PCI_DMA_TODEVICE); 678 679 vcc = ATM_SKB(skb)->vcc; 680 if (vcc->pop) 681 vcc->pop(vcc, skb); 682 else 683 dev_kfree_skb(skb); 684 } 685 686 while ((skb = skb_dequeue(&scq->pending))) { 687 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 688 skb->len, PCI_DMA_TODEVICE); 689 690 vcc = ATM_SKB(skb)->vcc; 691 if (vcc->pop) 692 vcc->pop(vcc, skb); 693 else 694 dev_kfree_skb(skb); 695 } 696 697 kfree(scq); 698 } 699 700 701 static int 702 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 703 { 704 struct scq_info *scq = vc->scq; 705 unsigned long flags; 706 struct scqe *tbd; 707 int entries; 708 709 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 710 711 atomic_inc(&scq->used); 712 entries = atomic_read(&scq->used); 713 if (entries > (SCQ_ENTRIES - 1)) { 714 atomic_dec(&scq->used); 715 goto out; 716 } 717 718 skb_queue_tail(&scq->transmit, skb); 719 720 spin_lock_irqsave(&vc->lock, flags); 721 if (vc->estimator) { 722 struct atm_vcc *vcc = vc->tx_vcc; 723 struct sock *sk = sk_atm(vcc); 724 725 vc->estimator->cells += (skb->len + 47) / 48; 726 if (atomic_read(&sk->sk_wmem_alloc) > 727 (sk->sk_sndbuf >> 1)) { 728 u32 cps = vc->estimator->maxcps; 729 730 vc->estimator->cps = cps; 731 vc->estimator->avcps = cps << 5; 732 if (vc->lacr < vc->init_er) { 733 vc->lacr = vc->init_er; 734 writel(TCMDQ_LACR | (vc->lacr << 16) | 735 vc->index, SAR_REG_TCMDQ); 736 } 737 } 738 } 739 spin_unlock_irqrestore(&vc->lock, flags); 740 741 tbd = &IDT77252_PRV_TBD(skb); 742 743 spin_lock_irqsave(&scq->lock, flags); 744 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 745 SAR_TBD_TSIF | SAR_TBD_GTSI); 746 scq->next->word_2 = cpu_to_le32(tbd->word_2); 747 scq->next->word_3 = cpu_to_le32(tbd->word_3); 748 scq->next->word_4 = cpu_to_le32(tbd->word_4); 749 750 if (scq->next == scq->last) 751 scq->next = scq->base; 752 else 753 scq->next++; 754 755 write_sram(card, scq->scd, 756 scq->paddr + 757 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 758 spin_unlock_irqrestore(&scq->lock, flags); 759 760 scq->trans_start = jiffies; 761 762 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 763 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 764 SAR_REG_TCMDQ); 765 } 766 767 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 768 769 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 770 card->name, atomic_read(&scq->used), 771 read_sram(card, scq->scd + 1), scq->next); 772 773 return 0; 774 775 out: 776 if (time_after(jiffies, scq->trans_start + HZ)) { 777 printk("%s: Error pushing TBD for %d.%d\n", 778 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 779 #ifdef CONFIG_ATM_IDT77252_DEBUG 780 idt77252_tx_dump(card); 781 #endif 782 scq->trans_start = jiffies; 783 } 784 785 return -ENOBUFS; 786 } 787 788 789 static void 790 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 791 { 792 struct scq_info *scq = vc->scq; 793 struct sk_buff *skb; 794 struct atm_vcc *vcc; 795 796 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 797 card->name, atomic_read(&scq->used), scq->next); 798 799 skb = skb_dequeue(&scq->transmit); 800 if (skb) { 801 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 802 803 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 804 skb->len, PCI_DMA_TODEVICE); 805 806 vcc = ATM_SKB(skb)->vcc; 807 808 if (vcc->pop) 809 vcc->pop(vcc, skb); 810 else 811 dev_kfree_skb(skb); 812 813 atomic_inc(&vcc->stats->tx); 814 } 815 816 atomic_dec(&scq->used); 817 818 spin_lock(&scq->skblock); 819 while ((skb = skb_dequeue(&scq->pending))) { 820 if (push_on_scq(card, vc, skb)) { 821 skb_queue_head(&vc->scq->pending, skb); 822 break; 823 } 824 } 825 spin_unlock(&scq->skblock); 826 } 827 828 static int 829 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 830 struct sk_buff *skb, int oam) 831 { 832 struct atm_vcc *vcc; 833 struct scqe *tbd; 834 unsigned long flags; 835 int error; 836 int aal; 837 838 if (skb->len == 0) { 839 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 840 return -EINVAL; 841 } 842 843 TXPRINTK("%s: Sending %d bytes of data.\n", 844 card->name, skb->len); 845 846 tbd = &IDT77252_PRV_TBD(skb); 847 vcc = ATM_SKB(skb)->vcc; 848 849 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 850 skb->len, PCI_DMA_TODEVICE); 851 852 error = -EINVAL; 853 854 if (oam) { 855 if (skb->len != 52) 856 goto errout; 857 858 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 859 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 860 tbd->word_3 = 0x00000000; 861 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 862 (skb->data[2] << 8) | (skb->data[3] << 0); 863 864 if (test_bit(VCF_RSV, &vc->flags)) 865 vc = card->vcs[0]; 866 867 goto done; 868 } 869 870 if (test_bit(VCF_RSV, &vc->flags)) { 871 printk("%s: Trying to transmit on reserved VC\n", card->name); 872 goto errout; 873 } 874 875 aal = vcc->qos.aal; 876 877 switch (aal) { 878 case ATM_AAL0: 879 case ATM_AAL34: 880 if (skb->len > 52) 881 goto errout; 882 883 if (aal == ATM_AAL0) 884 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 885 ATM_CELL_PAYLOAD; 886 else 887 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 888 ATM_CELL_PAYLOAD; 889 890 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 891 tbd->word_3 = 0x00000000; 892 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 893 (skb->data[2] << 8) | (skb->data[3] << 0); 894 break; 895 896 case ATM_AAL5: 897 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 898 tbd->word_2 = IDT77252_PRV_PADDR(skb); 899 tbd->word_3 = skb->len; 900 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 901 (vcc->vci << SAR_TBD_VCI_SHIFT); 902 break; 903 904 case ATM_AAL1: 905 case ATM_AAL2: 906 default: 907 printk("%s: Traffic type not supported.\n", card->name); 908 error = -EPROTONOSUPPORT; 909 goto errout; 910 } 911 912 done: 913 spin_lock_irqsave(&vc->scq->skblock, flags); 914 skb_queue_tail(&vc->scq->pending, skb); 915 916 while ((skb = skb_dequeue(&vc->scq->pending))) { 917 if (push_on_scq(card, vc, skb)) { 918 skb_queue_head(&vc->scq->pending, skb); 919 break; 920 } 921 } 922 spin_unlock_irqrestore(&vc->scq->skblock, flags); 923 924 return 0; 925 926 errout: 927 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 928 skb->len, PCI_DMA_TODEVICE); 929 return error; 930 } 931 932 static unsigned long 933 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 934 { 935 int i; 936 937 for (i = 0; i < card->scd_size; i++) { 938 if (!card->scd2vc[i]) { 939 card->scd2vc[i] = vc; 940 vc->scd_index = i; 941 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 942 } 943 } 944 return 0; 945 } 946 947 static void 948 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 949 { 950 write_sram(card, scq->scd, scq->paddr); 951 write_sram(card, scq->scd + 1, 0x00000000); 952 write_sram(card, scq->scd + 2, 0xffffffff); 953 write_sram(card, scq->scd + 3, 0x00000000); 954 } 955 956 static void 957 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 958 { 959 return; 960 } 961 962 /*****************************************************************************/ 963 /* */ 964 /* RSQ Handling */ 965 /* */ 966 /*****************************************************************************/ 967 968 static int 969 init_rsq(struct idt77252_dev *card) 970 { 971 struct rsq_entry *rsqe; 972 973 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 974 &card->rsq.paddr); 975 if (card->rsq.base == NULL) { 976 printk("%s: can't allocate RSQ.\n", card->name); 977 return -1; 978 } 979 memset(card->rsq.base, 0, RSQSIZE); 980 981 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 982 card->rsq.next = card->rsq.last; 983 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 984 rsqe->word_4 = 0; 985 986 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 987 SAR_REG_RSQH); 988 writel(card->rsq.paddr, SAR_REG_RSQB); 989 990 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 991 (unsigned long) card->rsq.base, 992 readl(SAR_REG_RSQB)); 993 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 994 card->name, 995 readl(SAR_REG_RSQH), 996 readl(SAR_REG_RSQB), 997 readl(SAR_REG_RSQT)); 998 999 return 0; 1000 } 1001 1002 static void 1003 deinit_rsq(struct idt77252_dev *card) 1004 { 1005 pci_free_consistent(card->pcidev, RSQSIZE, 1006 card->rsq.base, card->rsq.paddr); 1007 } 1008 1009 static void 1010 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1011 { 1012 struct atm_vcc *vcc; 1013 struct sk_buff *skb; 1014 struct rx_pool *rpp; 1015 struct vc_map *vc; 1016 u32 header, vpi, vci; 1017 u32 stat; 1018 int i; 1019 1020 stat = le32_to_cpu(rsqe->word_4); 1021 1022 if (stat & SAR_RSQE_IDLE) { 1023 RXPRINTK("%s: message about inactive connection.\n", 1024 card->name); 1025 return; 1026 } 1027 1028 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1029 if (skb == NULL) { 1030 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1031 card->name, __func__, 1032 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1033 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1034 return; 1035 } 1036 1037 header = le32_to_cpu(rsqe->word_1); 1038 vpi = (header >> 16) & 0x00ff; 1039 vci = (header >> 0) & 0xffff; 1040 1041 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1042 card->name, vpi, vci, skb, skb->data); 1043 1044 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1045 printk("%s: SDU received for out-of-range vc %u.%u\n", 1046 card->name, vpi, vci); 1047 recycle_rx_skb(card, skb); 1048 return; 1049 } 1050 1051 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1052 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1053 printk("%s: SDU received on non RX vc %u.%u\n", 1054 card->name, vpi, vci); 1055 recycle_rx_skb(card, skb); 1056 return; 1057 } 1058 1059 vcc = vc->rx_vcc; 1060 1061 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1062 skb_end_pointer(skb) - skb->data, 1063 PCI_DMA_FROMDEVICE); 1064 1065 if ((vcc->qos.aal == ATM_AAL0) || 1066 (vcc->qos.aal == ATM_AAL34)) { 1067 struct sk_buff *sb; 1068 unsigned char *cell; 1069 u32 aal0; 1070 1071 cell = skb->data; 1072 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1073 if ((sb = dev_alloc_skb(64)) == NULL) { 1074 printk("%s: Can't allocate buffers for aal0.\n", 1075 card->name); 1076 atomic_add(i, &vcc->stats->rx_drop); 1077 break; 1078 } 1079 if (!atm_charge(vcc, sb->truesize)) { 1080 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1081 card->name); 1082 atomic_add(i - 1, &vcc->stats->rx_drop); 1083 dev_kfree_skb(sb); 1084 break; 1085 } 1086 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1087 (vci << ATM_HDR_VCI_SHIFT); 1088 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1089 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1090 1091 *((u32 *) sb->data) = aal0; 1092 skb_put(sb, sizeof(u32)); 1093 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1094 cell, ATM_CELL_PAYLOAD); 1095 1096 ATM_SKB(sb)->vcc = vcc; 1097 __net_timestamp(sb); 1098 vcc->push(vcc, sb); 1099 atomic_inc(&vcc->stats->rx); 1100 1101 cell += ATM_CELL_PAYLOAD; 1102 } 1103 1104 recycle_rx_skb(card, skb); 1105 return; 1106 } 1107 if (vcc->qos.aal != ATM_AAL5) { 1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1109 card->name, vcc->qos.aal); 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1114 1115 rpp = &vc->rcv.rx_pool; 1116 1117 __skb_queue_tail(&rpp->queue, skb); 1118 rpp->len += skb->len; 1119 1120 if (stat & SAR_RSQE_EPDU) { 1121 unsigned char *l1l2; 1122 unsigned int len; 1123 1124 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1125 1126 len = (l1l2[0] << 8) | l1l2[1]; 1127 len = len ? len : 0x10000; 1128 1129 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1130 1131 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1132 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1133 "(CDC: %08x)\n", 1134 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1135 recycle_rx_pool_skb(card, rpp); 1136 atomic_inc(&vcc->stats->rx_err); 1137 return; 1138 } 1139 if (stat & SAR_RSQE_CRC) { 1140 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1141 recycle_rx_pool_skb(card, rpp); 1142 atomic_inc(&vcc->stats->rx_err); 1143 return; 1144 } 1145 if (skb_queue_len(&rpp->queue) > 1) { 1146 struct sk_buff *sb; 1147 1148 skb = dev_alloc_skb(rpp->len); 1149 if (!skb) { 1150 RXPRINTK("%s: Can't alloc RX skb.\n", 1151 card->name); 1152 recycle_rx_pool_skb(card, rpp); 1153 atomic_inc(&vcc->stats->rx_err); 1154 return; 1155 } 1156 if (!atm_charge(vcc, skb->truesize)) { 1157 recycle_rx_pool_skb(card, rpp); 1158 dev_kfree_skb(skb); 1159 return; 1160 } 1161 skb_queue_walk(&rpp->queue, sb) 1162 memcpy(skb_put(skb, sb->len), 1163 sb->data, sb->len); 1164 1165 recycle_rx_pool_skb(card, rpp); 1166 1167 skb_trim(skb, len); 1168 ATM_SKB(skb)->vcc = vcc; 1169 __net_timestamp(skb); 1170 1171 vcc->push(vcc, skb); 1172 atomic_inc(&vcc->stats->rx); 1173 1174 return; 1175 } 1176 1177 flush_rx_pool(card, rpp); 1178 1179 if (!atm_charge(vcc, skb->truesize)) { 1180 recycle_rx_skb(card, skb); 1181 return; 1182 } 1183 1184 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1185 skb_end_pointer(skb) - skb->data, 1186 PCI_DMA_FROMDEVICE); 1187 sb_pool_remove(card, skb); 1188 1189 skb_trim(skb, len); 1190 ATM_SKB(skb)->vcc = vcc; 1191 __net_timestamp(skb); 1192 1193 vcc->push(vcc, skb); 1194 atomic_inc(&vcc->stats->rx); 1195 1196 if (skb->truesize > SAR_FB_SIZE_3) 1197 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1198 else if (skb->truesize > SAR_FB_SIZE_2) 1199 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1200 else if (skb->truesize > SAR_FB_SIZE_1) 1201 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1202 else 1203 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1204 return; 1205 } 1206 } 1207 1208 static void 1209 idt77252_rx(struct idt77252_dev *card) 1210 { 1211 struct rsq_entry *rsqe; 1212 1213 if (card->rsq.next == card->rsq.last) 1214 rsqe = card->rsq.base; 1215 else 1216 rsqe = card->rsq.next + 1; 1217 1218 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1219 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1220 return; 1221 } 1222 1223 do { 1224 dequeue_rx(card, rsqe); 1225 rsqe->word_4 = 0; 1226 card->rsq.next = rsqe; 1227 if (card->rsq.next == card->rsq.last) 1228 rsqe = card->rsq.base; 1229 else 1230 rsqe = card->rsq.next + 1; 1231 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1232 1233 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1234 SAR_REG_RSQH); 1235 } 1236 1237 static void 1238 idt77252_rx_raw(struct idt77252_dev *card) 1239 { 1240 struct sk_buff *queue; 1241 u32 head, tail; 1242 struct atm_vcc *vcc; 1243 struct vc_map *vc; 1244 struct sk_buff *sb; 1245 1246 if (card->raw_cell_head == NULL) { 1247 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1248 card->raw_cell_head = sb_pool_skb(card, handle); 1249 } 1250 1251 queue = card->raw_cell_head; 1252 if (!queue) 1253 return; 1254 1255 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1256 tail = readl(SAR_REG_RAWCT); 1257 1258 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1259 skb_end_pointer(queue) - queue->head - 16, 1260 PCI_DMA_FROMDEVICE); 1261 1262 while (head != tail) { 1263 unsigned int vpi, vci, pti; 1264 u32 header; 1265 1266 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1267 1268 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1269 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1270 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1271 1272 #ifdef CONFIG_ATM_IDT77252_DEBUG 1273 if (debug & DBG_RAW_CELL) { 1274 int i; 1275 1276 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1277 card->name, (header >> 28) & 0x000f, 1278 (header >> 20) & 0x00ff, 1279 (header >> 4) & 0xffff, 1280 (header >> 1) & 0x0007, 1281 (header >> 0) & 0x0001); 1282 for (i = 16; i < 64; i++) 1283 printk(" %02x", queue->data[i]); 1284 printk("\n"); 1285 } 1286 #endif 1287 1288 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1289 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1290 card->name, vpi, vci); 1291 goto drop; 1292 } 1293 1294 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1295 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1296 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1297 card->name, vpi, vci); 1298 goto drop; 1299 } 1300 1301 vcc = vc->rx_vcc; 1302 1303 if (vcc->qos.aal != ATM_AAL0) { 1304 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1305 card->name, vpi, vci); 1306 atomic_inc(&vcc->stats->rx_drop); 1307 goto drop; 1308 } 1309 1310 if ((sb = dev_alloc_skb(64)) == NULL) { 1311 printk("%s: Can't allocate buffers for AAL0.\n", 1312 card->name); 1313 atomic_inc(&vcc->stats->rx_err); 1314 goto drop; 1315 } 1316 1317 if (!atm_charge(vcc, sb->truesize)) { 1318 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1319 card->name); 1320 dev_kfree_skb(sb); 1321 goto drop; 1322 } 1323 1324 *((u32 *) sb->data) = header; 1325 skb_put(sb, sizeof(u32)); 1326 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1327 ATM_CELL_PAYLOAD); 1328 1329 ATM_SKB(sb)->vcc = vcc; 1330 __net_timestamp(sb); 1331 vcc->push(vcc, sb); 1332 atomic_inc(&vcc->stats->rx); 1333 1334 drop: 1335 skb_pull(queue, 64); 1336 1337 head = IDT77252_PRV_PADDR(queue) 1338 + (queue->data - queue->head - 16); 1339 1340 if (queue->len < 128) { 1341 struct sk_buff *next; 1342 u32 handle; 1343 1344 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1345 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1346 1347 next = sb_pool_skb(card, handle); 1348 recycle_rx_skb(card, queue); 1349 1350 if (next) { 1351 card->raw_cell_head = next; 1352 queue = card->raw_cell_head; 1353 pci_dma_sync_single_for_cpu(card->pcidev, 1354 IDT77252_PRV_PADDR(queue), 1355 (skb_end_pointer(queue) - 1356 queue->data), 1357 PCI_DMA_FROMDEVICE); 1358 } else { 1359 card->raw_cell_head = NULL; 1360 printk("%s: raw cell queue overrun\n", 1361 card->name); 1362 break; 1363 } 1364 } 1365 } 1366 } 1367 1368 1369 /*****************************************************************************/ 1370 /* */ 1371 /* TSQ Handling */ 1372 /* */ 1373 /*****************************************************************************/ 1374 1375 static int 1376 init_tsq(struct idt77252_dev *card) 1377 { 1378 struct tsq_entry *tsqe; 1379 1380 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1381 &card->tsq.paddr); 1382 if (card->tsq.base == NULL) { 1383 printk("%s: can't allocate TSQ.\n", card->name); 1384 return -1; 1385 } 1386 memset(card->tsq.base, 0, TSQSIZE); 1387 1388 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1389 card->tsq.next = card->tsq.last; 1390 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1391 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1392 1393 writel(card->tsq.paddr, SAR_REG_TSQB); 1394 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1395 SAR_REG_TSQH); 1396 1397 return 0; 1398 } 1399 1400 static void 1401 deinit_tsq(struct idt77252_dev *card) 1402 { 1403 pci_free_consistent(card->pcidev, TSQSIZE, 1404 card->tsq.base, card->tsq.paddr); 1405 } 1406 1407 static void 1408 idt77252_tx(struct idt77252_dev *card) 1409 { 1410 struct tsq_entry *tsqe; 1411 unsigned int vpi, vci; 1412 struct vc_map *vc; 1413 u32 conn, stat; 1414 1415 if (card->tsq.next == card->tsq.last) 1416 tsqe = card->tsq.base; 1417 else 1418 tsqe = card->tsq.next + 1; 1419 1420 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1421 card->tsq.base, card->tsq.next, card->tsq.last); 1422 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1423 readl(SAR_REG_TSQB), 1424 readl(SAR_REG_TSQT), 1425 readl(SAR_REG_TSQH)); 1426 1427 stat = le32_to_cpu(tsqe->word_2); 1428 1429 if (stat & SAR_TSQE_INVALID) 1430 return; 1431 1432 do { 1433 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1434 le32_to_cpu(tsqe->word_1), 1435 le32_to_cpu(tsqe->word_2)); 1436 1437 switch (stat & SAR_TSQE_TYPE) { 1438 case SAR_TSQE_TYPE_TIMER: 1439 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1440 break; 1441 1442 case SAR_TSQE_TYPE_IDLE: 1443 1444 conn = le32_to_cpu(tsqe->word_1); 1445 1446 if (SAR_TSQE_TAG(stat) == 0x10) { 1447 #ifdef NOTDEF 1448 printk("%s: Connection %d halted.\n", 1449 card->name, 1450 le32_to_cpu(tsqe->word_1) & 0x1fff); 1451 #endif 1452 break; 1453 } 1454 1455 vc = card->vcs[conn & 0x1fff]; 1456 if (!vc) { 1457 printk("%s: could not find VC from conn %d\n", 1458 card->name, conn & 0x1fff); 1459 break; 1460 } 1461 1462 printk("%s: Connection %d IDLE.\n", 1463 card->name, vc->index); 1464 1465 set_bit(VCF_IDLE, &vc->flags); 1466 break; 1467 1468 case SAR_TSQE_TYPE_TSR: 1469 1470 conn = le32_to_cpu(tsqe->word_1); 1471 1472 vc = card->vcs[conn & 0x1fff]; 1473 if (!vc) { 1474 printk("%s: no VC at index %d\n", 1475 card->name, 1476 le32_to_cpu(tsqe->word_1) & 0x1fff); 1477 break; 1478 } 1479 1480 drain_scq(card, vc); 1481 break; 1482 1483 case SAR_TSQE_TYPE_TBD_COMP: 1484 1485 conn = le32_to_cpu(tsqe->word_1); 1486 1487 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1488 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1489 1490 if (vpi >= (1 << card->vpibits) || 1491 vci >= (1 << card->vcibits)) { 1492 printk("%s: TBD complete: " 1493 "out of range VPI.VCI %u.%u\n", 1494 card->name, vpi, vci); 1495 break; 1496 } 1497 1498 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1499 if (!vc) { 1500 printk("%s: TBD complete: " 1501 "no VC at VPI.VCI %u.%u\n", 1502 card->name, vpi, vci); 1503 break; 1504 } 1505 1506 drain_scq(card, vc); 1507 break; 1508 } 1509 1510 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1511 1512 card->tsq.next = tsqe; 1513 if (card->tsq.next == card->tsq.last) 1514 tsqe = card->tsq.base; 1515 else 1516 tsqe = card->tsq.next + 1; 1517 1518 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1519 card->tsq.base, card->tsq.next, card->tsq.last); 1520 1521 stat = le32_to_cpu(tsqe->word_2); 1522 1523 } while (!(stat & SAR_TSQE_INVALID)); 1524 1525 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1526 SAR_REG_TSQH); 1527 1528 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1529 card->index, readl(SAR_REG_TSQH), 1530 readl(SAR_REG_TSQT), card->tsq.next); 1531 } 1532 1533 1534 static void 1535 tst_timer(unsigned long data) 1536 { 1537 struct idt77252_dev *card = (struct idt77252_dev *)data; 1538 unsigned long base, idle, jump; 1539 unsigned long flags; 1540 u32 pc; 1541 int e; 1542 1543 spin_lock_irqsave(&card->tst_lock, flags); 1544 1545 base = card->tst[card->tst_index]; 1546 idle = card->tst[card->tst_index ^ 1]; 1547 1548 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1549 jump = base + card->tst_size - 2; 1550 1551 pc = readl(SAR_REG_NOW) >> 2; 1552 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1553 mod_timer(&card->tst_timer, jiffies + 1); 1554 goto out; 1555 } 1556 1557 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1558 1559 card->tst_index ^= 1; 1560 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1561 1562 base = card->tst[card->tst_index]; 1563 idle = card->tst[card->tst_index ^ 1]; 1564 1565 for (e = 0; e < card->tst_size - 2; e++) { 1566 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1567 write_sram(card, idle + e, 1568 card->soft_tst[e].tste & TSTE_MASK); 1569 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1570 } 1571 } 1572 } 1573 1574 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1575 1576 for (e = 0; e < card->tst_size - 2; e++) { 1577 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1578 write_sram(card, idle + e, 1579 card->soft_tst[e].tste & TSTE_MASK); 1580 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1581 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1582 } 1583 } 1584 1585 jump = base + card->tst_size - 2; 1586 1587 write_sram(card, jump, TSTE_OPC_NULL); 1588 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1589 1590 mod_timer(&card->tst_timer, jiffies + 1); 1591 } 1592 1593 out: 1594 spin_unlock_irqrestore(&card->tst_lock, flags); 1595 } 1596 1597 static int 1598 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1599 int n, unsigned int opc) 1600 { 1601 unsigned long cl, avail; 1602 unsigned long idle; 1603 int e, r; 1604 u32 data; 1605 1606 avail = card->tst_size - 2; 1607 for (e = 0; e < avail; e++) { 1608 if (card->soft_tst[e].vc == NULL) 1609 break; 1610 } 1611 if (e >= avail) { 1612 printk("%s: No free TST entries found\n", card->name); 1613 return -1; 1614 } 1615 1616 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1617 card->name, vc ? vc->index : -1, e); 1618 1619 r = n; 1620 cl = avail; 1621 data = opc & TSTE_OPC_MASK; 1622 if (vc && (opc != TSTE_OPC_NULL)) 1623 data = opc | vc->index; 1624 1625 idle = card->tst[card->tst_index ^ 1]; 1626 1627 /* 1628 * Fill Soft TST. 1629 */ 1630 while (r > 0) { 1631 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1632 if (vc) 1633 card->soft_tst[e].vc = vc; 1634 else 1635 card->soft_tst[e].vc = (void *)-1; 1636 1637 card->soft_tst[e].tste = data; 1638 if (timer_pending(&card->tst_timer)) 1639 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1640 else { 1641 write_sram(card, idle + e, data); 1642 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1643 } 1644 1645 cl -= card->tst_size; 1646 r--; 1647 } 1648 1649 if (++e == avail) 1650 e = 0; 1651 cl += n; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int 1658 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1659 { 1660 unsigned long flags; 1661 int res; 1662 1663 spin_lock_irqsave(&card->tst_lock, flags); 1664 1665 res = __fill_tst(card, vc, n, opc); 1666 1667 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1668 if (!timer_pending(&card->tst_timer)) 1669 mod_timer(&card->tst_timer, jiffies + 1); 1670 1671 spin_unlock_irqrestore(&card->tst_lock, flags); 1672 return res; 1673 } 1674 1675 static int 1676 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1677 { 1678 unsigned long idle; 1679 int e; 1680 1681 idle = card->tst[card->tst_index ^ 1]; 1682 1683 for (e = 0; e < card->tst_size - 2; e++) { 1684 if (card->soft_tst[e].vc == vc) { 1685 card->soft_tst[e].vc = NULL; 1686 1687 card->soft_tst[e].tste = TSTE_OPC_VAR; 1688 if (timer_pending(&card->tst_timer)) 1689 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1690 else { 1691 write_sram(card, idle + e, TSTE_OPC_VAR); 1692 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1693 } 1694 } 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int 1701 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1702 { 1703 unsigned long flags; 1704 int res; 1705 1706 spin_lock_irqsave(&card->tst_lock, flags); 1707 1708 res = __clear_tst(card, vc); 1709 1710 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1711 if (!timer_pending(&card->tst_timer)) 1712 mod_timer(&card->tst_timer, jiffies + 1); 1713 1714 spin_unlock_irqrestore(&card->tst_lock, flags); 1715 return res; 1716 } 1717 1718 static int 1719 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1720 int n, unsigned int opc) 1721 { 1722 unsigned long flags; 1723 int res; 1724 1725 spin_lock_irqsave(&card->tst_lock, flags); 1726 1727 __clear_tst(card, vc); 1728 res = __fill_tst(card, vc, n, opc); 1729 1730 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1731 if (!timer_pending(&card->tst_timer)) 1732 mod_timer(&card->tst_timer, jiffies + 1); 1733 1734 spin_unlock_irqrestore(&card->tst_lock, flags); 1735 return res; 1736 } 1737 1738 1739 static int 1740 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1741 { 1742 unsigned long tct; 1743 1744 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1745 1746 switch (vc->class) { 1747 case SCHED_CBR: 1748 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1749 card->name, tct, vc->scq->scd); 1750 1751 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1752 write_sram(card, tct + 1, 0); 1753 write_sram(card, tct + 2, 0); 1754 write_sram(card, tct + 3, 0); 1755 write_sram(card, tct + 4, 0); 1756 write_sram(card, tct + 5, 0); 1757 write_sram(card, tct + 6, 0); 1758 write_sram(card, tct + 7, 0); 1759 break; 1760 1761 case SCHED_UBR: 1762 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1763 card->name, tct, vc->scq->scd); 1764 1765 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1766 write_sram(card, tct + 1, 0); 1767 write_sram(card, tct + 2, TCT_TSIF); 1768 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1769 write_sram(card, tct + 4, 0); 1770 write_sram(card, tct + 5, vc->init_er); 1771 write_sram(card, tct + 6, 0); 1772 write_sram(card, tct + 7, TCT_FLAG_UBR); 1773 break; 1774 1775 case SCHED_VBR: 1776 case SCHED_ABR: 1777 default: 1778 return -ENOSYS; 1779 } 1780 1781 return 0; 1782 } 1783 1784 /*****************************************************************************/ 1785 /* */ 1786 /* FBQ Handling */ 1787 /* */ 1788 /*****************************************************************************/ 1789 1790 static __inline__ int 1791 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1792 { 1793 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1794 } 1795 1796 static __inline__ int 1797 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1798 { 1799 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1800 } 1801 1802 static int 1803 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1804 { 1805 unsigned long flags; 1806 u32 handle; 1807 u32 addr; 1808 1809 skb->data = skb->head; 1810 skb_reset_tail_pointer(skb); 1811 skb->len = 0; 1812 1813 skb_reserve(skb, 16); 1814 1815 switch (queue) { 1816 case 0: 1817 skb_put(skb, SAR_FB_SIZE_0); 1818 break; 1819 case 1: 1820 skb_put(skb, SAR_FB_SIZE_1); 1821 break; 1822 case 2: 1823 skb_put(skb, SAR_FB_SIZE_2); 1824 break; 1825 case 3: 1826 skb_put(skb, SAR_FB_SIZE_3); 1827 break; 1828 default: 1829 return -1; 1830 } 1831 1832 if (idt77252_fbq_full(card, queue)) 1833 return -1; 1834 1835 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1836 1837 handle = IDT77252_PRV_POOL(skb); 1838 addr = IDT77252_PRV_PADDR(skb); 1839 1840 spin_lock_irqsave(&card->cmd_lock, flags); 1841 writel(handle, card->fbq[queue]); 1842 writel(addr, card->fbq[queue]); 1843 spin_unlock_irqrestore(&card->cmd_lock, flags); 1844 1845 return 0; 1846 } 1847 1848 static void 1849 add_rx_skb(struct idt77252_dev *card, int queue, 1850 unsigned int size, unsigned int count) 1851 { 1852 struct sk_buff *skb; 1853 dma_addr_t paddr; 1854 u32 handle; 1855 1856 while (count--) { 1857 skb = dev_alloc_skb(size); 1858 if (!skb) 1859 return; 1860 1861 if (sb_pool_add(card, skb, queue)) { 1862 printk("%s: SB POOL full\n", __func__); 1863 goto outfree; 1864 } 1865 1866 paddr = pci_map_single(card->pcidev, skb->data, 1867 skb_end_pointer(skb) - skb->data, 1868 PCI_DMA_FROMDEVICE); 1869 IDT77252_PRV_PADDR(skb) = paddr; 1870 1871 if (push_rx_skb(card, skb, queue)) { 1872 printk("%s: FB QUEUE full\n", __func__); 1873 goto outunmap; 1874 } 1875 } 1876 1877 return; 1878 1879 outunmap: 1880 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1881 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1882 1883 handle = IDT77252_PRV_POOL(skb); 1884 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1885 1886 outfree: 1887 dev_kfree_skb(skb); 1888 } 1889 1890 1891 static void 1892 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1893 { 1894 u32 handle = IDT77252_PRV_POOL(skb); 1895 int err; 1896 1897 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1898 skb_end_pointer(skb) - skb->data, 1899 PCI_DMA_FROMDEVICE); 1900 1901 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1902 if (err) { 1903 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1904 skb_end_pointer(skb) - skb->data, 1905 PCI_DMA_FROMDEVICE); 1906 sb_pool_remove(card, skb); 1907 dev_kfree_skb(skb); 1908 } 1909 } 1910 1911 static void 1912 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1913 { 1914 skb_queue_head_init(&rpp->queue); 1915 rpp->len = 0; 1916 } 1917 1918 static void 1919 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1920 { 1921 struct sk_buff *skb, *tmp; 1922 1923 skb_queue_walk_safe(&rpp->queue, skb, tmp) 1924 recycle_rx_skb(card, skb); 1925 1926 flush_rx_pool(card, rpp); 1927 } 1928 1929 /*****************************************************************************/ 1930 /* */ 1931 /* ATM Interface */ 1932 /* */ 1933 /*****************************************************************************/ 1934 1935 static void 1936 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1937 { 1938 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1939 } 1940 1941 static unsigned char 1942 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1943 { 1944 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1945 } 1946 1947 static inline int 1948 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1949 { 1950 struct atm_dev *dev = vcc->dev; 1951 struct idt77252_dev *card = dev->dev_data; 1952 struct vc_map *vc = vcc->dev_data; 1953 int err; 1954 1955 if (vc == NULL) { 1956 printk("%s: NULL connection in send().\n", card->name); 1957 atomic_inc(&vcc->stats->tx_err); 1958 dev_kfree_skb(skb); 1959 return -EINVAL; 1960 } 1961 if (!test_bit(VCF_TX, &vc->flags)) { 1962 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1963 atomic_inc(&vcc->stats->tx_err); 1964 dev_kfree_skb(skb); 1965 return -EINVAL; 1966 } 1967 1968 switch (vcc->qos.aal) { 1969 case ATM_AAL0: 1970 case ATM_AAL1: 1971 case ATM_AAL5: 1972 break; 1973 default: 1974 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1975 atomic_inc(&vcc->stats->tx_err); 1976 dev_kfree_skb(skb); 1977 return -EINVAL; 1978 } 1979 1980 if (skb_shinfo(skb)->nr_frags != 0) { 1981 printk("%s: No scatter-gather yet.\n", card->name); 1982 atomic_inc(&vcc->stats->tx_err); 1983 dev_kfree_skb(skb); 1984 return -EINVAL; 1985 } 1986 ATM_SKB(skb)->vcc = vcc; 1987 1988 err = queue_skb(card, vc, skb, oam); 1989 if (err) { 1990 atomic_inc(&vcc->stats->tx_err); 1991 dev_kfree_skb(skb); 1992 return err; 1993 } 1994 1995 return 0; 1996 } 1997 1998 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 1999 { 2000 return idt77252_send_skb(vcc, skb, 0); 2001 } 2002 2003 static int 2004 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2005 { 2006 struct atm_dev *dev = vcc->dev; 2007 struct idt77252_dev *card = dev->dev_data; 2008 struct sk_buff *skb; 2009 2010 skb = dev_alloc_skb(64); 2011 if (!skb) { 2012 printk("%s: Out of memory in send_oam().\n", card->name); 2013 atomic_inc(&vcc->stats->tx_err); 2014 return -ENOMEM; 2015 } 2016 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2017 2018 memcpy(skb_put(skb, 52), cell, 52); 2019 2020 return idt77252_send_skb(vcc, skb, 1); 2021 } 2022 2023 static __inline__ unsigned int 2024 idt77252_fls(unsigned int x) 2025 { 2026 int r = 1; 2027 2028 if (x == 0) 2029 return 0; 2030 if (x & 0xffff0000) { 2031 x >>= 16; 2032 r += 16; 2033 } 2034 if (x & 0xff00) { 2035 x >>= 8; 2036 r += 8; 2037 } 2038 if (x & 0xf0) { 2039 x >>= 4; 2040 r += 4; 2041 } 2042 if (x & 0xc) { 2043 x >>= 2; 2044 r += 2; 2045 } 2046 if (x & 0x2) 2047 r += 1; 2048 return r; 2049 } 2050 2051 static u16 2052 idt77252_int_to_atmfp(unsigned int rate) 2053 { 2054 u16 m, e; 2055 2056 if (rate == 0) 2057 return 0; 2058 e = idt77252_fls(rate) - 1; 2059 if (e < 9) 2060 m = (rate - (1 << e)) << (9 - e); 2061 else if (e == 9) 2062 m = (rate - (1 << e)); 2063 else /* e > 9 */ 2064 m = (rate - (1 << e)) >> (e - 9); 2065 return 0x4000 | (e << 9) | m; 2066 } 2067 2068 static u8 2069 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2070 { 2071 u16 afp; 2072 2073 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2074 if (pcr < 0) 2075 return rate_to_log[(afp >> 5) & 0x1ff]; 2076 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2077 } 2078 2079 static void 2080 idt77252_est_timer(unsigned long data) 2081 { 2082 struct vc_map *vc = (struct vc_map *)data; 2083 struct idt77252_dev *card = vc->card; 2084 struct rate_estimator *est; 2085 unsigned long flags; 2086 u32 rate, cps; 2087 u64 ncells; 2088 u8 lacr; 2089 2090 spin_lock_irqsave(&vc->lock, flags); 2091 est = vc->estimator; 2092 if (!est) 2093 goto out; 2094 2095 ncells = est->cells; 2096 2097 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2098 est->last_cells = ncells; 2099 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2100 est->cps = (est->avcps + 0x1f) >> 5; 2101 2102 cps = est->cps; 2103 if (cps < (est->maxcps >> 4)) 2104 cps = est->maxcps >> 4; 2105 2106 lacr = idt77252_rate_logindex(card, cps); 2107 if (lacr > vc->max_er) 2108 lacr = vc->max_er; 2109 2110 if (lacr != vc->lacr) { 2111 vc->lacr = lacr; 2112 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2113 } 2114 2115 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2116 add_timer(&est->timer); 2117 2118 out: 2119 spin_unlock_irqrestore(&vc->lock, flags); 2120 } 2121 2122 static struct rate_estimator * 2123 idt77252_init_est(struct vc_map *vc, int pcr) 2124 { 2125 struct rate_estimator *est; 2126 2127 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2128 if (!est) 2129 return NULL; 2130 est->maxcps = pcr < 0 ? -pcr : pcr; 2131 est->cps = est->maxcps; 2132 est->avcps = est->cps << 5; 2133 2134 est->interval = 2; /* XXX: make this configurable */ 2135 est->ewma_log = 2; /* XXX: make this configurable */ 2136 init_timer(&est->timer); 2137 est->timer.data = (unsigned long)vc; 2138 est->timer.function = idt77252_est_timer; 2139 2140 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2141 add_timer(&est->timer); 2142 2143 return est; 2144 } 2145 2146 static int 2147 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2148 struct atm_vcc *vcc, struct atm_qos *qos) 2149 { 2150 int tst_free, tst_used, tst_entries; 2151 unsigned long tmpl, modl; 2152 int tcr, tcra; 2153 2154 if ((qos->txtp.max_pcr == 0) && 2155 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2156 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2157 card->name); 2158 return -EINVAL; 2159 } 2160 2161 tst_used = 0; 2162 tst_free = card->tst_free; 2163 if (test_bit(VCF_TX, &vc->flags)) 2164 tst_used = vc->ntste; 2165 tst_free += tst_used; 2166 2167 tcr = atm_pcr_goal(&qos->txtp); 2168 tcra = tcr >= 0 ? tcr : -tcr; 2169 2170 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2171 2172 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2173 modl = tmpl % (unsigned long)card->utopia_pcr; 2174 2175 tst_entries = (int) (tmpl / card->utopia_pcr); 2176 if (tcr > 0) { 2177 if (modl > 0) 2178 tst_entries++; 2179 } else if (tcr == 0) { 2180 tst_entries = tst_free - SAR_TST_RESERVED; 2181 if (tst_entries <= 0) { 2182 printk("%s: no CBR bandwidth free.\n", card->name); 2183 return -ENOSR; 2184 } 2185 } 2186 2187 if (tst_entries == 0) { 2188 printk("%s: selected CBR bandwidth < granularity.\n", 2189 card->name); 2190 return -EINVAL; 2191 } 2192 2193 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2194 printk("%s: not enough CBR bandwidth free.\n", card->name); 2195 return -ENOSR; 2196 } 2197 2198 vc->ntste = tst_entries; 2199 2200 card->tst_free = tst_free - tst_entries; 2201 if (test_bit(VCF_TX, &vc->flags)) { 2202 if (tst_used == tst_entries) 2203 return 0; 2204 2205 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2206 card->name, tst_used, tst_entries); 2207 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2208 return 0; 2209 } 2210 2211 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2212 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2213 return 0; 2214 } 2215 2216 static int 2217 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2218 struct atm_vcc *vcc, struct atm_qos *qos) 2219 { 2220 unsigned long flags; 2221 int tcr; 2222 2223 spin_lock_irqsave(&vc->lock, flags); 2224 if (vc->estimator) { 2225 del_timer(&vc->estimator->timer); 2226 kfree(vc->estimator); 2227 vc->estimator = NULL; 2228 } 2229 spin_unlock_irqrestore(&vc->lock, flags); 2230 2231 tcr = atm_pcr_goal(&qos->txtp); 2232 if (tcr == 0) 2233 tcr = card->link_pcr; 2234 2235 vc->estimator = idt77252_init_est(vc, tcr); 2236 2237 vc->class = SCHED_UBR; 2238 vc->init_er = idt77252_rate_logindex(card, tcr); 2239 vc->lacr = vc->init_er; 2240 if (tcr < 0) 2241 vc->max_er = vc->init_er; 2242 else 2243 vc->max_er = 0xff; 2244 2245 return 0; 2246 } 2247 2248 static int 2249 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2250 struct atm_vcc *vcc, struct atm_qos *qos) 2251 { 2252 int error; 2253 2254 if (test_bit(VCF_TX, &vc->flags)) 2255 return -EBUSY; 2256 2257 switch (qos->txtp.traffic_class) { 2258 case ATM_CBR: 2259 vc->class = SCHED_CBR; 2260 break; 2261 2262 case ATM_UBR: 2263 vc->class = SCHED_UBR; 2264 break; 2265 2266 case ATM_VBR: 2267 case ATM_ABR: 2268 default: 2269 return -EPROTONOSUPPORT; 2270 } 2271 2272 vc->scq = alloc_scq(card, vc->class); 2273 if (!vc->scq) { 2274 printk("%s: can't get SCQ.\n", card->name); 2275 return -ENOMEM; 2276 } 2277 2278 vc->scq->scd = get_free_scd(card, vc); 2279 if (vc->scq->scd == 0) { 2280 printk("%s: no SCD available.\n", card->name); 2281 free_scq(card, vc->scq); 2282 return -ENOMEM; 2283 } 2284 2285 fill_scd(card, vc->scq, vc->class); 2286 2287 if (set_tct(card, vc)) { 2288 printk("%s: class %d not supported.\n", 2289 card->name, qos->txtp.traffic_class); 2290 2291 card->scd2vc[vc->scd_index] = NULL; 2292 free_scq(card, vc->scq); 2293 return -EPROTONOSUPPORT; 2294 } 2295 2296 switch (vc->class) { 2297 case SCHED_CBR: 2298 error = idt77252_init_cbr(card, vc, vcc, qos); 2299 if (error) { 2300 card->scd2vc[vc->scd_index] = NULL; 2301 free_scq(card, vc->scq); 2302 return error; 2303 } 2304 2305 clear_bit(VCF_IDLE, &vc->flags); 2306 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2307 break; 2308 2309 case SCHED_UBR: 2310 error = idt77252_init_ubr(card, vc, vcc, qos); 2311 if (error) { 2312 card->scd2vc[vc->scd_index] = NULL; 2313 free_scq(card, vc->scq); 2314 return error; 2315 } 2316 2317 set_bit(VCF_IDLE, &vc->flags); 2318 break; 2319 } 2320 2321 vc->tx_vcc = vcc; 2322 set_bit(VCF_TX, &vc->flags); 2323 return 0; 2324 } 2325 2326 static int 2327 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2328 struct atm_vcc *vcc, struct atm_qos *qos) 2329 { 2330 unsigned long flags; 2331 unsigned long addr; 2332 u32 rcte = 0; 2333 2334 if (test_bit(VCF_RX, &vc->flags)) 2335 return -EBUSY; 2336 2337 vc->rx_vcc = vcc; 2338 set_bit(VCF_RX, &vc->flags); 2339 2340 if ((vcc->vci == 3) || (vcc->vci == 4)) 2341 return 0; 2342 2343 flush_rx_pool(card, &vc->rcv.rx_pool); 2344 2345 rcte |= SAR_RCTE_CONNECTOPEN; 2346 rcte |= SAR_RCTE_RAWCELLINTEN; 2347 2348 switch (qos->aal) { 2349 case ATM_AAL0: 2350 rcte |= SAR_RCTE_RCQ; 2351 break; 2352 case ATM_AAL1: 2353 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2354 break; 2355 case ATM_AAL34: 2356 rcte |= SAR_RCTE_AAL34; 2357 break; 2358 case ATM_AAL5: 2359 rcte |= SAR_RCTE_AAL5; 2360 break; 2361 default: 2362 rcte |= SAR_RCTE_RCQ; 2363 break; 2364 } 2365 2366 if (qos->aal != ATM_AAL5) 2367 rcte |= SAR_RCTE_FBP_1; 2368 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2369 rcte |= SAR_RCTE_FBP_3; 2370 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2371 rcte |= SAR_RCTE_FBP_2; 2372 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2373 rcte |= SAR_RCTE_FBP_1; 2374 else 2375 rcte |= SAR_RCTE_FBP_01; 2376 2377 addr = card->rct_base + (vc->index << 2); 2378 2379 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2380 write_sram(card, addr, rcte); 2381 2382 spin_lock_irqsave(&card->cmd_lock, flags); 2383 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2384 waitfor_idle(card); 2385 spin_unlock_irqrestore(&card->cmd_lock, flags); 2386 2387 return 0; 2388 } 2389 2390 static int 2391 idt77252_open(struct atm_vcc *vcc) 2392 { 2393 struct atm_dev *dev = vcc->dev; 2394 struct idt77252_dev *card = dev->dev_data; 2395 struct vc_map *vc; 2396 unsigned int index; 2397 unsigned int inuse; 2398 int error; 2399 int vci = vcc->vci; 2400 short vpi = vcc->vpi; 2401 2402 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2403 return 0; 2404 2405 if (vpi >= (1 << card->vpibits)) { 2406 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2407 return -EINVAL; 2408 } 2409 2410 if (vci >= (1 << card->vcibits)) { 2411 printk("%s: unsupported VCI: %d\n", card->name, vci); 2412 return -EINVAL; 2413 } 2414 2415 set_bit(ATM_VF_ADDR, &vcc->flags); 2416 2417 mutex_lock(&card->mutex); 2418 2419 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2420 2421 switch (vcc->qos.aal) { 2422 case ATM_AAL0: 2423 case ATM_AAL1: 2424 case ATM_AAL5: 2425 break; 2426 default: 2427 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2428 mutex_unlock(&card->mutex); 2429 return -EPROTONOSUPPORT; 2430 } 2431 2432 index = VPCI2VC(card, vpi, vci); 2433 if (!card->vcs[index]) { 2434 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2435 if (!card->vcs[index]) { 2436 printk("%s: can't alloc vc in open()\n", card->name); 2437 mutex_unlock(&card->mutex); 2438 return -ENOMEM; 2439 } 2440 card->vcs[index]->card = card; 2441 card->vcs[index]->index = index; 2442 2443 spin_lock_init(&card->vcs[index]->lock); 2444 } 2445 vc = card->vcs[index]; 2446 2447 vcc->dev_data = vc; 2448 2449 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2450 card->name, vc->index, vcc->vpi, vcc->vci, 2451 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2452 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2453 vcc->qos.rxtp.max_sdu); 2454 2455 inuse = 0; 2456 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2457 test_bit(VCF_TX, &vc->flags)) 2458 inuse = 1; 2459 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2460 test_bit(VCF_RX, &vc->flags)) 2461 inuse += 2; 2462 2463 if (inuse) { 2464 printk("%s: %s vci already in use.\n", card->name, 2465 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2466 mutex_unlock(&card->mutex); 2467 return -EADDRINUSE; 2468 } 2469 2470 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2471 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2472 if (error) { 2473 mutex_unlock(&card->mutex); 2474 return error; 2475 } 2476 } 2477 2478 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2479 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2480 if (error) { 2481 mutex_unlock(&card->mutex); 2482 return error; 2483 } 2484 } 2485 2486 set_bit(ATM_VF_READY, &vcc->flags); 2487 2488 mutex_unlock(&card->mutex); 2489 return 0; 2490 } 2491 2492 static void 2493 idt77252_close(struct atm_vcc *vcc) 2494 { 2495 struct atm_dev *dev = vcc->dev; 2496 struct idt77252_dev *card = dev->dev_data; 2497 struct vc_map *vc = vcc->dev_data; 2498 unsigned long flags; 2499 unsigned long addr; 2500 unsigned long timeout; 2501 2502 mutex_lock(&card->mutex); 2503 2504 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2505 card->name, vc->index, vcc->vpi, vcc->vci); 2506 2507 clear_bit(ATM_VF_READY, &vcc->flags); 2508 2509 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2510 2511 spin_lock_irqsave(&vc->lock, flags); 2512 clear_bit(VCF_RX, &vc->flags); 2513 vc->rx_vcc = NULL; 2514 spin_unlock_irqrestore(&vc->lock, flags); 2515 2516 if ((vcc->vci == 3) || (vcc->vci == 4)) 2517 goto done; 2518 2519 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2520 2521 spin_lock_irqsave(&card->cmd_lock, flags); 2522 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2523 waitfor_idle(card); 2524 spin_unlock_irqrestore(&card->cmd_lock, flags); 2525 2526 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2527 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2528 card->name); 2529 2530 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2531 } 2532 } 2533 2534 done: 2535 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2536 2537 spin_lock_irqsave(&vc->lock, flags); 2538 clear_bit(VCF_TX, &vc->flags); 2539 clear_bit(VCF_IDLE, &vc->flags); 2540 clear_bit(VCF_RSV, &vc->flags); 2541 vc->tx_vcc = NULL; 2542 2543 if (vc->estimator) { 2544 del_timer(&vc->estimator->timer); 2545 kfree(vc->estimator); 2546 vc->estimator = NULL; 2547 } 2548 spin_unlock_irqrestore(&vc->lock, flags); 2549 2550 timeout = 5 * 1000; 2551 while (atomic_read(&vc->scq->used) > 0) { 2552 timeout = msleep_interruptible(timeout); 2553 if (!timeout) 2554 break; 2555 } 2556 if (!timeout) 2557 printk("%s: SCQ drain timeout: %u used\n", 2558 card->name, atomic_read(&vc->scq->used)); 2559 2560 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2561 clear_scd(card, vc->scq, vc->class); 2562 2563 if (vc->class == SCHED_CBR) { 2564 clear_tst(card, vc); 2565 card->tst_free += vc->ntste; 2566 vc->ntste = 0; 2567 } 2568 2569 card->scd2vc[vc->scd_index] = NULL; 2570 free_scq(card, vc->scq); 2571 } 2572 2573 mutex_unlock(&card->mutex); 2574 } 2575 2576 static int 2577 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2578 { 2579 struct atm_dev *dev = vcc->dev; 2580 struct idt77252_dev *card = dev->dev_data; 2581 struct vc_map *vc = vcc->dev_data; 2582 int error = 0; 2583 2584 mutex_lock(&card->mutex); 2585 2586 if (qos->txtp.traffic_class != ATM_NONE) { 2587 if (!test_bit(VCF_TX, &vc->flags)) { 2588 error = idt77252_init_tx(card, vc, vcc, qos); 2589 if (error) 2590 goto out; 2591 } else { 2592 switch (qos->txtp.traffic_class) { 2593 case ATM_CBR: 2594 error = idt77252_init_cbr(card, vc, vcc, qos); 2595 if (error) 2596 goto out; 2597 break; 2598 2599 case ATM_UBR: 2600 error = idt77252_init_ubr(card, vc, vcc, qos); 2601 if (error) 2602 goto out; 2603 2604 if (!test_bit(VCF_IDLE, &vc->flags)) { 2605 writel(TCMDQ_LACR | (vc->lacr << 16) | 2606 vc->index, SAR_REG_TCMDQ); 2607 } 2608 break; 2609 2610 case ATM_VBR: 2611 case ATM_ABR: 2612 error = -EOPNOTSUPP; 2613 goto out; 2614 } 2615 } 2616 } 2617 2618 if ((qos->rxtp.traffic_class != ATM_NONE) && 2619 !test_bit(VCF_RX, &vc->flags)) { 2620 error = idt77252_init_rx(card, vc, vcc, qos); 2621 if (error) 2622 goto out; 2623 } 2624 2625 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2626 2627 set_bit(ATM_VF_HASQOS, &vcc->flags); 2628 2629 out: 2630 mutex_unlock(&card->mutex); 2631 return error; 2632 } 2633 2634 static int 2635 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2636 { 2637 struct idt77252_dev *card = dev->dev_data; 2638 int i, left; 2639 2640 left = (int) *pos; 2641 if (!left--) 2642 return sprintf(page, "IDT77252 Interrupts:\n"); 2643 if (!left--) 2644 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2645 if (!left--) 2646 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2647 if (!left--) 2648 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2649 if (!left--) 2650 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2651 if (!left--) 2652 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2653 if (!left--) 2654 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2655 if (!left--) 2656 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2657 if (!left--) 2658 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2659 if (!left--) 2660 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2661 if (!left--) 2662 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2663 if (!left--) 2664 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2665 if (!left--) 2666 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2667 if (!left--) 2668 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2669 if (!left--) 2670 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2671 2672 for (i = 0; i < card->tct_size; i++) { 2673 unsigned long tct; 2674 struct atm_vcc *vcc; 2675 struct vc_map *vc; 2676 char *p; 2677 2678 vc = card->vcs[i]; 2679 if (!vc) 2680 continue; 2681 2682 vcc = NULL; 2683 if (vc->tx_vcc) 2684 vcc = vc->tx_vcc; 2685 if (!vcc) 2686 continue; 2687 if (left--) 2688 continue; 2689 2690 p = page; 2691 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2692 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2693 2694 for (i = 0; i < 8; i++) 2695 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2696 p += sprintf(p, "\n"); 2697 return p - page; 2698 } 2699 return 0; 2700 } 2701 2702 /*****************************************************************************/ 2703 /* */ 2704 /* Interrupt handler */ 2705 /* */ 2706 /*****************************************************************************/ 2707 2708 static void 2709 idt77252_collect_stat(struct idt77252_dev *card) 2710 { 2711 u32 cdc, vpec, icc; 2712 2713 cdc = readl(SAR_REG_CDC); 2714 vpec = readl(SAR_REG_VPEC); 2715 icc = readl(SAR_REG_ICC); 2716 2717 #ifdef NOTDEF 2718 printk("%s:", card->name); 2719 2720 if (cdc & 0x7f0000) { 2721 char *s = ""; 2722 2723 printk(" ["); 2724 if (cdc & (1 << 22)) { 2725 printk("%sRM ID", s); 2726 s = " | "; 2727 } 2728 if (cdc & (1 << 21)) { 2729 printk("%sCON TAB", s); 2730 s = " | "; 2731 } 2732 if (cdc & (1 << 20)) { 2733 printk("%sNO FB", s); 2734 s = " | "; 2735 } 2736 if (cdc & (1 << 19)) { 2737 printk("%sOAM CRC", s); 2738 s = " | "; 2739 } 2740 if (cdc & (1 << 18)) { 2741 printk("%sRM CRC", s); 2742 s = " | "; 2743 } 2744 if (cdc & (1 << 17)) { 2745 printk("%sRM FIFO", s); 2746 s = " | "; 2747 } 2748 if (cdc & (1 << 16)) { 2749 printk("%sRX FIFO", s); 2750 s = " | "; 2751 } 2752 printk("]"); 2753 } 2754 2755 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2756 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2757 #endif 2758 } 2759 2760 static irqreturn_t 2761 idt77252_interrupt(int irq, void *dev_id) 2762 { 2763 struct idt77252_dev *card = dev_id; 2764 u32 stat; 2765 2766 stat = readl(SAR_REG_STAT) & 0xffff; 2767 if (!stat) /* no interrupt for us */ 2768 return IRQ_NONE; 2769 2770 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2771 printk("%s: Re-entering irq_handler()\n", card->name); 2772 goto out; 2773 } 2774 2775 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2776 2777 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2778 INTPRINTK("%s: TSIF\n", card->name); 2779 card->irqstat[15]++; 2780 idt77252_tx(card); 2781 } 2782 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2783 INTPRINTK("%s: TXICP\n", card->name); 2784 card->irqstat[14]++; 2785 #ifdef CONFIG_ATM_IDT77252_DEBUG 2786 idt77252_tx_dump(card); 2787 #endif 2788 } 2789 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2790 INTPRINTK("%s: TSQF\n", card->name); 2791 card->irqstat[12]++; 2792 idt77252_tx(card); 2793 } 2794 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2795 INTPRINTK("%s: TMROF\n", card->name); 2796 card->irqstat[11]++; 2797 idt77252_collect_stat(card); 2798 } 2799 2800 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2801 INTPRINTK("%s: EPDU\n", card->name); 2802 card->irqstat[5]++; 2803 idt77252_rx(card); 2804 } 2805 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2806 INTPRINTK("%s: RSQAF\n", card->name); 2807 card->irqstat[1]++; 2808 idt77252_rx(card); 2809 } 2810 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2811 INTPRINTK("%s: RSQF\n", card->name); 2812 card->irqstat[6]++; 2813 idt77252_rx(card); 2814 } 2815 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2816 INTPRINTK("%s: RAWCF\n", card->name); 2817 card->irqstat[4]++; 2818 idt77252_rx_raw(card); 2819 } 2820 2821 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2822 INTPRINTK("%s: PHYI", card->name); 2823 card->irqstat[10]++; 2824 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2825 card->atmdev->phy->interrupt(card->atmdev); 2826 } 2827 2828 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2829 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2830 2831 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2832 2833 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2834 2835 if (stat & SAR_STAT_FBQ0A) 2836 card->irqstat[2]++; 2837 if (stat & SAR_STAT_FBQ1A) 2838 card->irqstat[3]++; 2839 if (stat & SAR_STAT_FBQ2A) 2840 card->irqstat[7]++; 2841 if (stat & SAR_STAT_FBQ3A) 2842 card->irqstat[8]++; 2843 2844 schedule_work(&card->tqueue); 2845 } 2846 2847 out: 2848 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2849 return IRQ_HANDLED; 2850 } 2851 2852 static void 2853 idt77252_softint(struct work_struct *work) 2854 { 2855 struct idt77252_dev *card = 2856 container_of(work, struct idt77252_dev, tqueue); 2857 u32 stat; 2858 int done; 2859 2860 for (done = 1; ; done = 1) { 2861 stat = readl(SAR_REG_STAT) >> 16; 2862 2863 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2864 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2865 done = 0; 2866 } 2867 2868 stat >>= 4; 2869 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2870 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2871 done = 0; 2872 } 2873 2874 stat >>= 4; 2875 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2876 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2877 done = 0; 2878 } 2879 2880 stat >>= 4; 2881 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2882 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2883 done = 0; 2884 } 2885 2886 if (done) 2887 break; 2888 } 2889 2890 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2891 } 2892 2893 2894 static int 2895 open_card_oam(struct idt77252_dev *card) 2896 { 2897 unsigned long flags; 2898 unsigned long addr; 2899 struct vc_map *vc; 2900 int vpi, vci; 2901 int index; 2902 u32 rcte; 2903 2904 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2905 for (vci = 3; vci < 5; vci++) { 2906 index = VPCI2VC(card, vpi, vci); 2907 2908 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2909 if (!vc) { 2910 printk("%s: can't alloc vc\n", card->name); 2911 return -ENOMEM; 2912 } 2913 vc->index = index; 2914 card->vcs[index] = vc; 2915 2916 flush_rx_pool(card, &vc->rcv.rx_pool); 2917 2918 rcte = SAR_RCTE_CONNECTOPEN | 2919 SAR_RCTE_RAWCELLINTEN | 2920 SAR_RCTE_RCQ | 2921 SAR_RCTE_FBP_1; 2922 2923 addr = card->rct_base + (vc->index << 2); 2924 write_sram(card, addr, rcte); 2925 2926 spin_lock_irqsave(&card->cmd_lock, flags); 2927 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2928 SAR_REG_CMD); 2929 waitfor_idle(card); 2930 spin_unlock_irqrestore(&card->cmd_lock, flags); 2931 } 2932 } 2933 2934 return 0; 2935 } 2936 2937 static void 2938 close_card_oam(struct idt77252_dev *card) 2939 { 2940 unsigned long flags; 2941 unsigned long addr; 2942 struct vc_map *vc; 2943 int vpi, vci; 2944 int index; 2945 2946 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2947 for (vci = 3; vci < 5; vci++) { 2948 index = VPCI2VC(card, vpi, vci); 2949 vc = card->vcs[index]; 2950 2951 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2952 2953 spin_lock_irqsave(&card->cmd_lock, flags); 2954 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2955 SAR_REG_CMD); 2956 waitfor_idle(card); 2957 spin_unlock_irqrestore(&card->cmd_lock, flags); 2958 2959 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2960 DPRINTK("%s: closing a VC " 2961 "with pending rx buffers.\n", 2962 card->name); 2963 2964 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2965 } 2966 } 2967 } 2968 } 2969 2970 static int 2971 open_card_ubr0(struct idt77252_dev *card) 2972 { 2973 struct vc_map *vc; 2974 2975 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2976 if (!vc) { 2977 printk("%s: can't alloc vc\n", card->name); 2978 return -ENOMEM; 2979 } 2980 card->vcs[0] = vc; 2981 vc->class = SCHED_UBR0; 2982 2983 vc->scq = alloc_scq(card, vc->class); 2984 if (!vc->scq) { 2985 printk("%s: can't get SCQ.\n", card->name); 2986 return -ENOMEM; 2987 } 2988 2989 card->scd2vc[0] = vc; 2990 vc->scd_index = 0; 2991 vc->scq->scd = card->scd_base; 2992 2993 fill_scd(card, vc->scq, vc->class); 2994 2995 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 2996 write_sram(card, card->tct_base + 1, 0); 2997 write_sram(card, card->tct_base + 2, 0); 2998 write_sram(card, card->tct_base + 3, 0); 2999 write_sram(card, card->tct_base + 4, 0); 3000 write_sram(card, card->tct_base + 5, 0); 3001 write_sram(card, card->tct_base + 6, 0); 3002 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3003 3004 clear_bit(VCF_IDLE, &vc->flags); 3005 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3006 return 0; 3007 } 3008 3009 static int 3010 idt77252_dev_open(struct idt77252_dev *card) 3011 { 3012 u32 conf; 3013 3014 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3015 printk("%s: SAR not yet initialized.\n", card->name); 3016 return -1; 3017 } 3018 3019 conf = SAR_CFG_RXPTH| /* enable receive path */ 3020 SAR_RX_DELAY | /* interrupt on complete PDU */ 3021 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3022 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3023 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3024 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3025 SAR_CFG_TXEN | /* transmit operation enable */ 3026 SAR_CFG_TXINT | /* interrupt on transmit status */ 3027 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3028 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3029 SAR_CFG_PHYIE /* enable PHY interrupts */ 3030 ; 3031 3032 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 3033 /* Test RAW cell receive. */ 3034 conf |= SAR_CFG_VPECA; 3035 #endif 3036 3037 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3038 3039 if (open_card_oam(card)) { 3040 printk("%s: Error initializing OAM.\n", card->name); 3041 return -1; 3042 } 3043 3044 if (open_card_ubr0(card)) { 3045 printk("%s: Error initializing UBR0.\n", card->name); 3046 return -1; 3047 } 3048 3049 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3050 return 0; 3051 } 3052 3053 static void idt77252_dev_close(struct atm_dev *dev) 3054 { 3055 struct idt77252_dev *card = dev->dev_data; 3056 u32 conf; 3057 3058 close_card_oam(card); 3059 3060 conf = SAR_CFG_RXPTH | /* enable receive path */ 3061 SAR_RX_DELAY | /* interrupt on complete PDU */ 3062 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3063 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3064 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3065 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3066 SAR_CFG_TXEN | /* transmit operation enable */ 3067 SAR_CFG_TXINT | /* interrupt on transmit status */ 3068 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3069 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3070 ; 3071 3072 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3073 3074 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3075 } 3076 3077 3078 /*****************************************************************************/ 3079 /* */ 3080 /* Initialisation and Deinitialization of IDT77252 */ 3081 /* */ 3082 /*****************************************************************************/ 3083 3084 3085 static void 3086 deinit_card(struct idt77252_dev *card) 3087 { 3088 struct sk_buff *skb; 3089 int i, j; 3090 3091 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3092 printk("%s: SAR not yet initialized.\n", card->name); 3093 return; 3094 } 3095 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3096 3097 writel(0, SAR_REG_CFG); 3098 3099 if (card->atmdev) 3100 atm_dev_deregister(card->atmdev); 3101 3102 for (i = 0; i < 4; i++) { 3103 for (j = 0; j < FBQ_SIZE; j++) { 3104 skb = card->sbpool[i].skb[j]; 3105 if (skb) { 3106 pci_unmap_single(card->pcidev, 3107 IDT77252_PRV_PADDR(skb), 3108 (skb_end_pointer(skb) - 3109 skb->data), 3110 PCI_DMA_FROMDEVICE); 3111 card->sbpool[i].skb[j] = NULL; 3112 dev_kfree_skb(skb); 3113 } 3114 } 3115 } 3116 3117 vfree(card->soft_tst); 3118 3119 vfree(card->scd2vc); 3120 3121 vfree(card->vcs); 3122 3123 if (card->raw_cell_hnd) { 3124 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3125 card->raw_cell_hnd, card->raw_cell_paddr); 3126 } 3127 3128 if (card->rsq.base) { 3129 DIPRINTK("%s: Release RSQ ...\n", card->name); 3130 deinit_rsq(card); 3131 } 3132 3133 if (card->tsq.base) { 3134 DIPRINTK("%s: Release TSQ ...\n", card->name); 3135 deinit_tsq(card); 3136 } 3137 3138 DIPRINTK("idt77252: Release IRQ.\n"); 3139 free_irq(card->pcidev->irq, card); 3140 3141 for (i = 0; i < 4; i++) { 3142 if (card->fbq[i]) 3143 iounmap(card->fbq[i]); 3144 } 3145 3146 if (card->membase) 3147 iounmap(card->membase); 3148 3149 clear_bit(IDT77252_BIT_INIT, &card->flags); 3150 DIPRINTK("%s: Card deinitialized.\n", card->name); 3151 } 3152 3153 3154 static int __devinit 3155 init_sram(struct idt77252_dev *card) 3156 { 3157 int i; 3158 3159 for (i = 0; i < card->sramsize; i += 4) 3160 write_sram(card, (i >> 2), 0); 3161 3162 /* set SRAM layout for THIS card */ 3163 if (card->sramsize == (512 * 1024)) { 3164 card->tct_base = SAR_SRAM_TCT_128_BASE; 3165 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3166 / SAR_SRAM_TCT_SIZE; 3167 card->rct_base = SAR_SRAM_RCT_128_BASE; 3168 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3169 / SAR_SRAM_RCT_SIZE; 3170 card->rt_base = SAR_SRAM_RT_128_BASE; 3171 card->scd_base = SAR_SRAM_SCD_128_BASE; 3172 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3173 / SAR_SRAM_SCD_SIZE; 3174 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3175 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3176 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3177 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3178 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3179 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3180 card->fifo_size = SAR_RXFD_SIZE_32K; 3181 } else { 3182 card->tct_base = SAR_SRAM_TCT_32_BASE; 3183 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3184 / SAR_SRAM_TCT_SIZE; 3185 card->rct_base = SAR_SRAM_RCT_32_BASE; 3186 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3187 / SAR_SRAM_RCT_SIZE; 3188 card->rt_base = SAR_SRAM_RT_32_BASE; 3189 card->scd_base = SAR_SRAM_SCD_32_BASE; 3190 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3191 / SAR_SRAM_SCD_SIZE; 3192 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3193 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3194 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3195 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3196 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3197 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3198 card->fifo_size = SAR_RXFD_SIZE_4K; 3199 } 3200 3201 /* Initialize TCT */ 3202 for (i = 0; i < card->tct_size; i++) { 3203 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3204 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3205 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3206 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3207 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3208 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3209 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3210 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3211 } 3212 3213 /* Initialize RCT */ 3214 for (i = 0; i < card->rct_size; i++) { 3215 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3216 (u32) SAR_RCTE_RAWCELLINTEN); 3217 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3218 (u32) 0); 3219 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3220 (u32) 0); 3221 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3222 (u32) 0xffffffff); 3223 } 3224 3225 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3226 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3227 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3228 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3229 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3230 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3231 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3232 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3233 3234 /* Initialize rate table */ 3235 for (i = 0; i < 256; i++) { 3236 write_sram(card, card->rt_base + i, log_to_rate[i]); 3237 } 3238 3239 for (i = 0; i < 128; i++) { 3240 unsigned int tmp; 3241 3242 tmp = rate_to_log[(i << 2) + 0] << 0; 3243 tmp |= rate_to_log[(i << 2) + 1] << 8; 3244 tmp |= rate_to_log[(i << 2) + 2] << 16; 3245 tmp |= rate_to_log[(i << 2) + 3] << 24; 3246 write_sram(card, card->rt_base + 256 + i, tmp); 3247 } 3248 3249 #if 0 /* Fill RDF and AIR tables. */ 3250 for (i = 0; i < 128; i++) { 3251 unsigned int tmp; 3252 3253 tmp = RDF[0][(i << 1) + 0] << 16; 3254 tmp |= RDF[0][(i << 1) + 1] << 0; 3255 write_sram(card, card->rt_base + 512 + i, tmp); 3256 } 3257 3258 for (i = 0; i < 128; i++) { 3259 unsigned int tmp; 3260 3261 tmp = AIR[0][(i << 1) + 0] << 16; 3262 tmp |= AIR[0][(i << 1) + 1] << 0; 3263 write_sram(card, card->rt_base + 640 + i, tmp); 3264 } 3265 #endif 3266 3267 IPRINTK("%s: initialize rate table ...\n", card->name); 3268 writel(card->rt_base << 2, SAR_REG_RTBL); 3269 3270 /* Initialize TSTs */ 3271 IPRINTK("%s: initialize TST ...\n", card->name); 3272 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3273 3274 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3275 write_sram(card, i, TSTE_OPC_VAR); 3276 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3277 idt77252_sram_write_errors = 1; 3278 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3279 idt77252_sram_write_errors = 0; 3280 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3281 write_sram(card, i, TSTE_OPC_VAR); 3282 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3283 idt77252_sram_write_errors = 1; 3284 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3285 idt77252_sram_write_errors = 0; 3286 3287 card->tst_index = 0; 3288 writel(card->tst[0] << 2, SAR_REG_TSTB); 3289 3290 /* Initialize ABRSTD and Receive FIFO */ 3291 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3292 writel(card->abrst_size | (card->abrst_base << 2), 3293 SAR_REG_ABRSTD); 3294 3295 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3296 writel(card->fifo_size | (card->fifo_base << 2), 3297 SAR_REG_RXFD); 3298 3299 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3300 return 0; 3301 } 3302 3303 static int __devinit 3304 init_card(struct atm_dev *dev) 3305 { 3306 struct idt77252_dev *card = dev->dev_data; 3307 struct pci_dev *pcidev = card->pcidev; 3308 unsigned long tmpl, modl; 3309 unsigned int linkrate, rsvdcr; 3310 unsigned int tst_entries; 3311 struct net_device *tmp; 3312 char tname[10]; 3313 3314 u32 size; 3315 u_char pci_byte; 3316 u32 conf; 3317 int i, k; 3318 3319 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3320 printk("Error: SAR already initialized.\n"); 3321 return -1; 3322 } 3323 3324 /*****************************************************************/ 3325 /* P C I C O N F I G U R A T I O N */ 3326 /*****************************************************************/ 3327 3328 /* Set PCI Retry-Timeout and TRDY timeout */ 3329 IPRINTK("%s: Checking PCI retries.\n", card->name); 3330 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3331 printk("%s: can't read PCI retry timeout.\n", card->name); 3332 deinit_card(card); 3333 return -1; 3334 } 3335 if (pci_byte != 0) { 3336 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3337 card->name, pci_byte); 3338 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3339 printk("%s: can't set PCI retry timeout.\n", 3340 card->name); 3341 deinit_card(card); 3342 return -1; 3343 } 3344 } 3345 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3346 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3347 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3348 deinit_card(card); 3349 return -1; 3350 } 3351 if (pci_byte != 0) { 3352 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3353 card->name, pci_byte); 3354 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3355 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3356 deinit_card(card); 3357 return -1; 3358 } 3359 } 3360 /* Reset Timer register */ 3361 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3362 printk("%s: resetting timer overflow.\n", card->name); 3363 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3364 } 3365 IPRINTK("%s: Request IRQ ... ", card->name); 3366 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3367 card->name, card) != 0) { 3368 printk("%s: can't allocate IRQ.\n", card->name); 3369 deinit_card(card); 3370 return -1; 3371 } 3372 IPRINTK("got %d.\n", pcidev->irq); 3373 3374 /*****************************************************************/ 3375 /* C H E C K A N D I N I T S R A M */ 3376 /*****************************************************************/ 3377 3378 IPRINTK("%s: Initializing SRAM\n", card->name); 3379 3380 /* preset size of connecton table, so that init_sram() knows about it */ 3381 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3382 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3383 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3384 #ifndef ATM_IDT77252_SEND_IDLE 3385 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3386 #endif 3387 0; 3388 3389 if (card->sramsize == (512 * 1024)) 3390 conf |= SAR_CFG_CNTBL_1k; 3391 else 3392 conf |= SAR_CFG_CNTBL_512; 3393 3394 switch (vpibits) { 3395 case 0: 3396 conf |= SAR_CFG_VPVCS_0; 3397 break; 3398 default: 3399 case 1: 3400 conf |= SAR_CFG_VPVCS_1; 3401 break; 3402 case 2: 3403 conf |= SAR_CFG_VPVCS_2; 3404 break; 3405 case 8: 3406 conf |= SAR_CFG_VPVCS_8; 3407 break; 3408 } 3409 3410 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3411 3412 if (init_sram(card) < 0) 3413 return -1; 3414 3415 /********************************************************************/ 3416 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3417 /********************************************************************/ 3418 /* Initialize TSQ */ 3419 if (0 != init_tsq(card)) { 3420 deinit_card(card); 3421 return -1; 3422 } 3423 /* Initialize RSQ */ 3424 if (0 != init_rsq(card)) { 3425 deinit_card(card); 3426 return -1; 3427 } 3428 3429 card->vpibits = vpibits; 3430 if (card->sramsize == (512 * 1024)) { 3431 card->vcibits = 10 - card->vpibits; 3432 } else { 3433 card->vcibits = 9 - card->vpibits; 3434 } 3435 3436 card->vcimask = 0; 3437 for (k = 0, i = 1; k < card->vcibits; k++) { 3438 card->vcimask |= i; 3439 i <<= 1; 3440 } 3441 3442 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3443 writel(0, SAR_REG_VPM); 3444 3445 /* Little Endian Order */ 3446 writel(0, SAR_REG_GP); 3447 3448 /* Initialize RAW Cell Handle Register */ 3449 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3450 &card->raw_cell_paddr); 3451 if (!card->raw_cell_hnd) { 3452 printk("%s: memory allocation failure.\n", card->name); 3453 deinit_card(card); 3454 return -1; 3455 } 3456 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3457 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3458 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3459 card->raw_cell_hnd); 3460 3461 size = sizeof(struct vc_map *) * card->tct_size; 3462 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3463 if (NULL == (card->vcs = vmalloc(size))) { 3464 printk("%s: memory allocation failure.\n", card->name); 3465 deinit_card(card); 3466 return -1; 3467 } 3468 memset(card->vcs, 0, size); 3469 3470 size = sizeof(struct vc_map *) * card->scd_size; 3471 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3472 card->name, size); 3473 if (NULL == (card->scd2vc = vmalloc(size))) { 3474 printk("%s: memory allocation failure.\n", card->name); 3475 deinit_card(card); 3476 return -1; 3477 } 3478 memset(card->scd2vc, 0, size); 3479 3480 size = sizeof(struct tst_info) * (card->tst_size - 2); 3481 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3482 card->name, size); 3483 if (NULL == (card->soft_tst = vmalloc(size))) { 3484 printk("%s: memory allocation failure.\n", card->name); 3485 deinit_card(card); 3486 return -1; 3487 } 3488 for (i = 0; i < card->tst_size - 2; i++) { 3489 card->soft_tst[i].tste = TSTE_OPC_VAR; 3490 card->soft_tst[i].vc = NULL; 3491 } 3492 3493 if (dev->phy == NULL) { 3494 printk("%s: No LT device defined.\n", card->name); 3495 deinit_card(card); 3496 return -1; 3497 } 3498 if (dev->phy->ioctl == NULL) { 3499 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3500 deinit_card(card); 3501 return -1; 3502 } 3503 3504 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3505 /* 3506 * this is a jhs hack to get around special functionality in the 3507 * phy driver for the atecom hardware; the functionality doesn't 3508 * exist in the linux atm suni driver 3509 * 3510 * it isn't the right way to do things, but as the guy from NIST 3511 * said, talking about their measurement of the fine structure 3512 * constant, "it's good enough for government work." 3513 */ 3514 linkrate = 149760000; 3515 #endif 3516 3517 card->link_pcr = (linkrate / 8 / 53); 3518 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3519 card->name, linkrate, card->link_pcr); 3520 3521 #ifdef ATM_IDT77252_SEND_IDLE 3522 card->utopia_pcr = card->link_pcr; 3523 #else 3524 card->utopia_pcr = (160000000 / 8 / 54); 3525 #endif 3526 3527 rsvdcr = 0; 3528 if (card->utopia_pcr > card->link_pcr) 3529 rsvdcr = card->utopia_pcr - card->link_pcr; 3530 3531 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3532 modl = tmpl % (unsigned long)card->utopia_pcr; 3533 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3534 if (modl) 3535 tst_entries++; 3536 card->tst_free -= tst_entries; 3537 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3538 3539 #ifdef HAVE_EEPROM 3540 idt77252_eeprom_init(card); 3541 printk("%s: EEPROM: %02x:", card->name, 3542 idt77252_eeprom_read_status(card)); 3543 3544 for (i = 0; i < 0x80; i++) { 3545 printk(" %02x", 3546 idt77252_eeprom_read_byte(card, i) 3547 ); 3548 } 3549 printk("\n"); 3550 #endif /* HAVE_EEPROM */ 3551 3552 /* 3553 * XXX: <hack> 3554 */ 3555 sprintf(tname, "eth%d", card->index); 3556 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3557 if (tmp) { 3558 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3559 3560 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3561 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3562 card->atmdev->esi[2], card->atmdev->esi[3], 3563 card->atmdev->esi[4], card->atmdev->esi[5]); 3564 } 3565 /* 3566 * XXX: </hack> 3567 */ 3568 3569 /* Set Maximum Deficit Count for now. */ 3570 writel(0xffff, SAR_REG_MDFCT); 3571 3572 set_bit(IDT77252_BIT_INIT, &card->flags); 3573 3574 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3575 return 0; 3576 } 3577 3578 3579 /*****************************************************************************/ 3580 /* */ 3581 /* Probing of IDT77252 ABR SAR */ 3582 /* */ 3583 /*****************************************************************************/ 3584 3585 3586 static int __devinit 3587 idt77252_preset(struct idt77252_dev *card) 3588 { 3589 u16 pci_command; 3590 3591 /*****************************************************************/ 3592 /* P C I C O N F I G U R A T I O N */ 3593 /*****************************************************************/ 3594 3595 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3596 card->name); 3597 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3598 printk("%s: can't read PCI_COMMAND.\n", card->name); 3599 deinit_card(card); 3600 return -1; 3601 } 3602 if (!(pci_command & PCI_COMMAND_IO)) { 3603 printk("%s: PCI_COMMAND: %04x (???)\n", 3604 card->name, pci_command); 3605 deinit_card(card); 3606 return (-1); 3607 } 3608 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3609 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3610 printk("%s: can't write PCI_COMMAND.\n", card->name); 3611 deinit_card(card); 3612 return -1; 3613 } 3614 /*****************************************************************/ 3615 /* G E N E R I C R E S E T */ 3616 /*****************************************************************/ 3617 3618 /* Software reset */ 3619 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3620 mdelay(1); 3621 writel(0, SAR_REG_CFG); 3622 3623 IPRINTK("%s: Software resetted.\n", card->name); 3624 return 0; 3625 } 3626 3627 3628 static unsigned long __devinit 3629 probe_sram(struct idt77252_dev *card) 3630 { 3631 u32 data, addr; 3632 3633 writel(0, SAR_REG_DR0); 3634 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3635 3636 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3637 writel(ATM_POISON, SAR_REG_DR0); 3638 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3639 3640 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3641 data = readl(SAR_REG_DR0); 3642 3643 if (data != 0) 3644 break; 3645 } 3646 3647 return addr * sizeof(u32); 3648 } 3649 3650 static int __devinit 3651 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3652 { 3653 static struct idt77252_dev **last = &idt77252_chain; 3654 static int index = 0; 3655 3656 unsigned long membase, srambase; 3657 struct idt77252_dev *card; 3658 struct atm_dev *dev; 3659 int i, err; 3660 3661 3662 if ((err = pci_enable_device(pcidev))) { 3663 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3664 return err; 3665 } 3666 3667 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3668 if (!card) { 3669 printk("idt77252-%d: can't allocate private data\n", index); 3670 err = -ENOMEM; 3671 goto err_out_disable_pdev; 3672 } 3673 card->revision = pcidev->revision; 3674 card->index = index; 3675 card->pcidev = pcidev; 3676 sprintf(card->name, "idt77252-%d", card->index); 3677 3678 INIT_WORK(&card->tqueue, idt77252_softint); 3679 3680 membase = pci_resource_start(pcidev, 1); 3681 srambase = pci_resource_start(pcidev, 2); 3682 3683 mutex_init(&card->mutex); 3684 spin_lock_init(&card->cmd_lock); 3685 spin_lock_init(&card->tst_lock); 3686 3687 init_timer(&card->tst_timer); 3688 card->tst_timer.data = (unsigned long)card; 3689 card->tst_timer.function = tst_timer; 3690 3691 /* Do the I/O remapping... */ 3692 card->membase = ioremap(membase, 1024); 3693 if (!card->membase) { 3694 printk("%s: can't ioremap() membase\n", card->name); 3695 err = -EIO; 3696 goto err_out_free_card; 3697 } 3698 3699 if (idt77252_preset(card)) { 3700 printk("%s: preset failed\n", card->name); 3701 err = -EIO; 3702 goto err_out_iounmap; 3703 } 3704 3705 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3706 if (!dev) { 3707 printk("%s: can't register atm device\n", card->name); 3708 err = -EIO; 3709 goto err_out_iounmap; 3710 } 3711 dev->dev_data = card; 3712 card->atmdev = dev; 3713 3714 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3715 suni_init(dev); 3716 if (!dev->phy) { 3717 printk("%s: can't init SUNI\n", card->name); 3718 err = -EIO; 3719 goto err_out_deinit_card; 3720 } 3721 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3722 3723 card->sramsize = probe_sram(card); 3724 3725 for (i = 0; i < 4; i++) { 3726 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3727 if (!card->fbq[i]) { 3728 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3729 err = -EIO; 3730 goto err_out_deinit_card; 3731 } 3732 } 3733 3734 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3735 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3736 'A' + card->revision - 1 : '?', membase, srambase, 3737 card->sramsize / 1024); 3738 3739 if (init_card(dev)) { 3740 printk("%s: init_card failed\n", card->name); 3741 err = -EIO; 3742 goto err_out_deinit_card; 3743 } 3744 3745 dev->ci_range.vpi_bits = card->vpibits; 3746 dev->ci_range.vci_bits = card->vcibits; 3747 dev->link_rate = card->link_pcr; 3748 3749 if (dev->phy->start) 3750 dev->phy->start(dev); 3751 3752 if (idt77252_dev_open(card)) { 3753 printk("%s: dev_open failed\n", card->name); 3754 err = -EIO; 3755 goto err_out_stop; 3756 } 3757 3758 *last = card; 3759 last = &card->next; 3760 index++; 3761 3762 return 0; 3763 3764 err_out_stop: 3765 if (dev->phy->stop) 3766 dev->phy->stop(dev); 3767 3768 err_out_deinit_card: 3769 deinit_card(card); 3770 3771 err_out_iounmap: 3772 iounmap(card->membase); 3773 3774 err_out_free_card: 3775 kfree(card); 3776 3777 err_out_disable_pdev: 3778 pci_disable_device(pcidev); 3779 return err; 3780 } 3781 3782 static struct pci_device_id idt77252_pci_tbl[] = 3783 { 3784 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3786 { 0, } 3787 }; 3788 3789 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3790 3791 static struct pci_driver idt77252_driver = { 3792 .name = "idt77252", 3793 .id_table = idt77252_pci_tbl, 3794 .probe = idt77252_init_one, 3795 }; 3796 3797 static int __init idt77252_init(void) 3798 { 3799 struct sk_buff *skb; 3800 3801 printk("%s: at %p\n", __func__, idt77252_init); 3802 3803 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3804 sizeof(struct idt77252_skb_prv)) { 3805 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3806 __func__, (unsigned long) sizeof(skb->cb), 3807 (unsigned long) sizeof(struct atm_skb_data) + 3808 sizeof(struct idt77252_skb_prv)); 3809 return -EIO; 3810 } 3811 3812 return pci_register_driver(&idt77252_driver); 3813 } 3814 3815 static void __exit idt77252_exit(void) 3816 { 3817 struct idt77252_dev *card; 3818 struct atm_dev *dev; 3819 3820 pci_unregister_driver(&idt77252_driver); 3821 3822 while (idt77252_chain) { 3823 card = idt77252_chain; 3824 dev = card->atmdev; 3825 idt77252_chain = card->next; 3826 3827 if (dev->phy->stop) 3828 dev->phy->stop(dev); 3829 deinit_card(card); 3830 pci_disable_device(card->pcidev); 3831 kfree(card); 3832 } 3833 3834 DIPRINTK("idt77252: finished cleanup-module().\n"); 3835 } 3836 3837 module_init(idt77252_init); 3838 module_exit(idt77252_exit); 3839 3840 MODULE_LICENSE("GPL"); 3841 3842 module_param(vpibits, uint, 0); 3843 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3844 #ifdef CONFIG_ATM_IDT77252_DEBUG 3845 module_param(debug, ulong, 0644); 3846 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3847 #endif 3848 3849 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3850 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3851