1 /******************************************************************* 2 * 3 * Copyright (c) 2000 ATecoM GmbH 4 * 5 * The author may be reached at ecd@atecom.com. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 *******************************************************************/ 28 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/poison.h> 32 #include <linux/skbuff.h> 33 #include <linux/kernel.h> 34 #include <linux/vmalloc.h> 35 #include <linux/netdevice.h> 36 #include <linux/atmdev.h> 37 #include <linux/atm.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/bitops.h> 41 #include <linux/wait.h> 42 #include <linux/jiffies.h> 43 #include <linux/mutex.h> 44 45 #include <asm/io.h> 46 #include <asm/uaccess.h> 47 #include <asm/atomic.h> 48 #include <asm/byteorder.h> 49 50 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 51 #include "suni.h" 52 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 53 54 55 #include "idt77252.h" 56 #include "idt77252_tables.h" 57 58 static unsigned int vpibits = 1; 59 60 61 #define ATM_IDT77252_SEND_IDLE 1 62 63 64 /* 65 * Debug HACKs. 66 */ 67 #define DEBUG_MODULE 1 68 #undef HAVE_EEPROM /* does not work, yet. */ 69 70 #ifdef CONFIG_ATM_IDT77252_DEBUG 71 static unsigned long debug = DBG_GENERAL; 72 #endif 73 74 75 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 76 77 78 /* 79 * SCQ Handling. 80 */ 81 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 82 static void free_scq(struct idt77252_dev *, struct scq_info *); 83 static int queue_skb(struct idt77252_dev *, struct vc_map *, 84 struct sk_buff *, int oam); 85 static void drain_scq(struct idt77252_dev *, struct vc_map *); 86 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 87 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 88 89 /* 90 * FBQ Handling. 91 */ 92 static int push_rx_skb(struct idt77252_dev *, 93 struct sk_buff *, int queue); 94 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 95 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 96 static void recycle_rx_pool_skb(struct idt77252_dev *, 97 struct rx_pool *); 98 static void add_rx_skb(struct idt77252_dev *, int queue, 99 unsigned int size, unsigned int count); 100 101 /* 102 * RSQ Handling. 103 */ 104 static int init_rsq(struct idt77252_dev *); 105 static void deinit_rsq(struct idt77252_dev *); 106 static void idt77252_rx(struct idt77252_dev *); 107 108 /* 109 * TSQ handling. 110 */ 111 static int init_tsq(struct idt77252_dev *); 112 static void deinit_tsq(struct idt77252_dev *); 113 static void idt77252_tx(struct idt77252_dev *); 114 115 116 /* 117 * ATM Interface. 118 */ 119 static void idt77252_dev_close(struct atm_dev *dev); 120 static int idt77252_open(struct atm_vcc *vcc); 121 static void idt77252_close(struct atm_vcc *vcc); 122 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 123 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 124 int flags); 125 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 126 unsigned long addr); 127 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 128 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 129 int flags); 130 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 131 char *page); 132 static void idt77252_softint(struct work_struct *work); 133 134 135 static struct atmdev_ops idt77252_ops = 136 { 137 .dev_close = idt77252_dev_close, 138 .open = idt77252_open, 139 .close = idt77252_close, 140 .send = idt77252_send, 141 .send_oam = idt77252_send_oam, 142 .phy_put = idt77252_phy_put, 143 .phy_get = idt77252_phy_get, 144 .change_qos = idt77252_change_qos, 145 .proc_read = idt77252_proc_read, 146 .owner = THIS_MODULE 147 }; 148 149 static struct idt77252_dev *idt77252_chain = NULL; 150 static unsigned int idt77252_sram_write_errors = 0; 151 152 /*****************************************************************************/ 153 /* */ 154 /* I/O and Utility Bus */ 155 /* */ 156 /*****************************************************************************/ 157 158 static void 159 waitfor_idle(struct idt77252_dev *card) 160 { 161 u32 stat; 162 163 stat = readl(SAR_REG_STAT); 164 while (stat & SAR_STAT_CMDBZ) 165 stat = readl(SAR_REG_STAT); 166 } 167 168 static u32 169 read_sram(struct idt77252_dev *card, unsigned long addr) 170 { 171 unsigned long flags; 172 u32 value; 173 174 spin_lock_irqsave(&card->cmd_lock, flags); 175 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 176 waitfor_idle(card); 177 value = readl(SAR_REG_DR0); 178 spin_unlock_irqrestore(&card->cmd_lock, flags); 179 return value; 180 } 181 182 static void 183 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 184 { 185 unsigned long flags; 186 187 if ((idt77252_sram_write_errors == 0) && 188 (((addr > card->tst[0] + card->tst_size - 2) && 189 (addr < card->tst[0] + card->tst_size)) || 190 ((addr > card->tst[1] + card->tst_size - 2) && 191 (addr < card->tst[1] + card->tst_size)))) { 192 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 193 card->name, addr, value); 194 } 195 196 spin_lock_irqsave(&card->cmd_lock, flags); 197 writel(value, SAR_REG_DR0); 198 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 199 waitfor_idle(card); 200 spin_unlock_irqrestore(&card->cmd_lock, flags); 201 } 202 203 static u8 204 read_utility(void *dev, unsigned long ubus_addr) 205 { 206 struct idt77252_dev *card = dev; 207 unsigned long flags; 208 u8 value; 209 210 if (!card) { 211 printk("Error: No such device.\n"); 212 return -1; 213 } 214 215 spin_lock_irqsave(&card->cmd_lock, flags); 216 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 217 waitfor_idle(card); 218 value = readl(SAR_REG_DR0); 219 spin_unlock_irqrestore(&card->cmd_lock, flags); 220 return value; 221 } 222 223 static void 224 write_utility(void *dev, unsigned long ubus_addr, u8 value) 225 { 226 struct idt77252_dev *card = dev; 227 unsigned long flags; 228 229 if (!card) { 230 printk("Error: No such device.\n"); 231 return; 232 } 233 234 spin_lock_irqsave(&card->cmd_lock, flags); 235 writel((u32) value, SAR_REG_DR0); 236 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 237 waitfor_idle(card); 238 spin_unlock_irqrestore(&card->cmd_lock, flags); 239 } 240 241 #ifdef HAVE_EEPROM 242 static u32 rdsrtab[] = 243 { 244 SAR_GP_EECS | SAR_GP_EESCLK, 245 0, 246 SAR_GP_EESCLK, /* 0 */ 247 0, 248 SAR_GP_EESCLK, /* 0 */ 249 0, 250 SAR_GP_EESCLK, /* 0 */ 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 SAR_GP_EEDO, 256 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 257 0, 258 SAR_GP_EESCLK, /* 0 */ 259 SAR_GP_EEDO, 260 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 261 }; 262 263 static u32 wrentab[] = 264 { 265 SAR_GP_EECS | SAR_GP_EESCLK, 266 0, 267 SAR_GP_EESCLK, /* 0 */ 268 0, 269 SAR_GP_EESCLK, /* 0 */ 270 0, 271 SAR_GP_EESCLK, /* 0 */ 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 SAR_GP_EEDO, 275 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 276 SAR_GP_EEDO, 277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 278 0, 279 SAR_GP_EESCLK, /* 0 */ 280 0, 281 SAR_GP_EESCLK /* 0 */ 282 }; 283 284 static u32 rdtab[] = 285 { 286 SAR_GP_EECS | SAR_GP_EESCLK, 287 0, 288 SAR_GP_EESCLK, /* 0 */ 289 0, 290 SAR_GP_EESCLK, /* 0 */ 291 0, 292 SAR_GP_EESCLK, /* 0 */ 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 SAR_GP_EEDO, 300 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 301 SAR_GP_EEDO, 302 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 303 }; 304 305 static u32 wrtab[] = 306 { 307 SAR_GP_EECS | SAR_GP_EESCLK, 308 0, 309 SAR_GP_EESCLK, /* 0 */ 310 0, 311 SAR_GP_EESCLK, /* 0 */ 312 0, 313 SAR_GP_EESCLK, /* 0 */ 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 SAR_GP_EEDO, 321 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 322 0, 323 SAR_GP_EESCLK /* 0 */ 324 }; 325 326 static u32 clktab[] = 327 { 328 0, 329 SAR_GP_EESCLK, 330 0, 331 SAR_GP_EESCLK, 332 0, 333 SAR_GP_EESCLK, 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0 345 }; 346 347 static u32 348 idt77252_read_gp(struct idt77252_dev *card) 349 { 350 u32 gp; 351 352 gp = readl(SAR_REG_GP); 353 #if 0 354 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 355 #endif 356 return gp; 357 } 358 359 static void 360 idt77252_write_gp(struct idt77252_dev *card, u32 value) 361 { 362 unsigned long flags; 363 364 #if 0 365 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 366 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 367 value & SAR_GP_EEDO ? "1" : "0"); 368 #endif 369 370 spin_lock_irqsave(&card->cmd_lock, flags); 371 waitfor_idle(card); 372 writel(value, SAR_REG_GP); 373 spin_unlock_irqrestore(&card->cmd_lock, flags); 374 } 375 376 static u8 377 idt77252_eeprom_read_status(struct idt77252_dev *card) 378 { 379 u8 byte; 380 u32 gp; 381 int i, j; 382 383 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 384 385 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 386 idt77252_write_gp(card, gp | rdsrtab[i]); 387 udelay(5); 388 } 389 idt77252_write_gp(card, gp | SAR_GP_EECS); 390 udelay(5); 391 392 byte = 0; 393 for (i = 0, j = 0; i < 8; i++) { 394 byte <<= 1; 395 396 idt77252_write_gp(card, gp | clktab[j++]); 397 udelay(5); 398 399 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 400 401 idt77252_write_gp(card, gp | clktab[j++]); 402 udelay(5); 403 } 404 idt77252_write_gp(card, gp | SAR_GP_EECS); 405 udelay(5); 406 407 return byte; 408 } 409 410 static u8 411 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 412 { 413 u8 byte; 414 u32 gp; 415 int i, j; 416 417 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 418 419 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 420 idt77252_write_gp(card, gp | rdtab[i]); 421 udelay(5); 422 } 423 idt77252_write_gp(card, gp | SAR_GP_EECS); 424 udelay(5); 425 426 for (i = 0, j = 0; i < 8; i++) { 427 idt77252_write_gp(card, gp | clktab[j++] | 428 (offset & 1 ? SAR_GP_EEDO : 0)); 429 udelay(5); 430 431 idt77252_write_gp(card, gp | clktab[j++] | 432 (offset & 1 ? SAR_GP_EEDO : 0)); 433 udelay(5); 434 435 offset >>= 1; 436 } 437 idt77252_write_gp(card, gp | SAR_GP_EECS); 438 udelay(5); 439 440 byte = 0; 441 for (i = 0, j = 0; i < 8; i++) { 442 byte <<= 1; 443 444 idt77252_write_gp(card, gp | clktab[j++]); 445 udelay(5); 446 447 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 448 449 idt77252_write_gp(card, gp | clktab[j++]); 450 udelay(5); 451 } 452 idt77252_write_gp(card, gp | SAR_GP_EECS); 453 udelay(5); 454 455 return byte; 456 } 457 458 static void 459 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 460 { 461 u32 gp; 462 int i, j; 463 464 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 465 466 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 467 idt77252_write_gp(card, gp | wrentab[i]); 468 udelay(5); 469 } 470 idt77252_write_gp(card, gp | SAR_GP_EECS); 471 udelay(5); 472 473 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 474 idt77252_write_gp(card, gp | wrtab[i]); 475 udelay(5); 476 } 477 idt77252_write_gp(card, gp | SAR_GP_EECS); 478 udelay(5); 479 480 for (i = 0, j = 0; i < 8; i++) { 481 idt77252_write_gp(card, gp | clktab[j++] | 482 (offset & 1 ? SAR_GP_EEDO : 0)); 483 udelay(5); 484 485 idt77252_write_gp(card, gp | clktab[j++] | 486 (offset & 1 ? SAR_GP_EEDO : 0)); 487 udelay(5); 488 489 offset >>= 1; 490 } 491 idt77252_write_gp(card, gp | SAR_GP_EECS); 492 udelay(5); 493 494 for (i = 0, j = 0; i < 8; i++) { 495 idt77252_write_gp(card, gp | clktab[j++] | 496 (data & 1 ? SAR_GP_EEDO : 0)); 497 udelay(5); 498 499 idt77252_write_gp(card, gp | clktab[j++] | 500 (data & 1 ? SAR_GP_EEDO : 0)); 501 udelay(5); 502 503 data >>= 1; 504 } 505 idt77252_write_gp(card, gp | SAR_GP_EECS); 506 udelay(5); 507 } 508 509 static void 510 idt77252_eeprom_init(struct idt77252_dev *card) 511 { 512 u32 gp; 513 514 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 515 516 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 517 udelay(5); 518 idt77252_write_gp(card, gp | SAR_GP_EECS); 519 udelay(5); 520 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 521 udelay(5); 522 idt77252_write_gp(card, gp | SAR_GP_EECS); 523 udelay(5); 524 } 525 #endif /* HAVE_EEPROM */ 526 527 528 #ifdef CONFIG_ATM_IDT77252_DEBUG 529 static void 530 dump_tct(struct idt77252_dev *card, int index) 531 { 532 unsigned long tct; 533 int i; 534 535 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 536 537 printk("%s: TCT %x:", card->name, index); 538 for (i = 0; i < 8; i++) { 539 printk(" %08x", read_sram(card, tct + i)); 540 } 541 printk("\n"); 542 } 543 544 static void 545 idt77252_tx_dump(struct idt77252_dev *card) 546 { 547 struct atm_vcc *vcc; 548 struct vc_map *vc; 549 int i; 550 551 printk("%s\n", __func__); 552 for (i = 0; i < card->tct_size; i++) { 553 vc = card->vcs[i]; 554 if (!vc) 555 continue; 556 557 vcc = NULL; 558 if (vc->rx_vcc) 559 vcc = vc->rx_vcc; 560 else if (vc->tx_vcc) 561 vcc = vc->tx_vcc; 562 563 if (!vcc) 564 continue; 565 566 printk("%s: Connection %d:\n", card->name, vc->index); 567 dump_tct(card, vc->index); 568 } 569 } 570 #endif 571 572 573 /*****************************************************************************/ 574 /* */ 575 /* SCQ Handling */ 576 /* */ 577 /*****************************************************************************/ 578 579 static int 580 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 581 { 582 struct sb_pool *pool = &card->sbpool[queue]; 583 int index; 584 585 index = pool->index; 586 while (pool->skb[index]) { 587 index = (index + 1) & FBQ_MASK; 588 if (index == pool->index) 589 return -ENOBUFS; 590 } 591 592 pool->skb[index] = skb; 593 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 594 595 pool->index = (index + 1) & FBQ_MASK; 596 return 0; 597 } 598 599 static void 600 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 601 { 602 unsigned int queue, index; 603 u32 handle; 604 605 handle = IDT77252_PRV_POOL(skb); 606 607 queue = POOL_QUEUE(handle); 608 if (queue > 3) 609 return; 610 611 index = POOL_INDEX(handle); 612 if (index > FBQ_SIZE - 1) 613 return; 614 615 card->sbpool[queue].skb[index] = NULL; 616 } 617 618 static struct sk_buff * 619 sb_pool_skb(struct idt77252_dev *card, u32 handle) 620 { 621 unsigned int queue, index; 622 623 queue = POOL_QUEUE(handle); 624 if (queue > 3) 625 return NULL; 626 627 index = POOL_INDEX(handle); 628 if (index > FBQ_SIZE - 1) 629 return NULL; 630 631 return card->sbpool[queue].skb[index]; 632 } 633 634 static struct scq_info * 635 alloc_scq(struct idt77252_dev *card, int class) 636 { 637 struct scq_info *scq; 638 639 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 640 if (!scq) 641 return NULL; 642 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 643 &scq->paddr); 644 if (scq->base == NULL) { 645 kfree(scq); 646 return NULL; 647 } 648 memset(scq->base, 0, SCQ_SIZE); 649 650 scq->next = scq->base; 651 scq->last = scq->base + (SCQ_ENTRIES - 1); 652 atomic_set(&scq->used, 0); 653 654 spin_lock_init(&scq->lock); 655 spin_lock_init(&scq->skblock); 656 657 skb_queue_head_init(&scq->transmit); 658 skb_queue_head_init(&scq->pending); 659 660 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 661 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 662 663 return scq; 664 } 665 666 static void 667 free_scq(struct idt77252_dev *card, struct scq_info *scq) 668 { 669 struct sk_buff *skb; 670 struct atm_vcc *vcc; 671 672 pci_free_consistent(card->pcidev, SCQ_SIZE, 673 scq->base, scq->paddr); 674 675 while ((skb = skb_dequeue(&scq->transmit))) { 676 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 677 skb->len, PCI_DMA_TODEVICE); 678 679 vcc = ATM_SKB(skb)->vcc; 680 if (vcc->pop) 681 vcc->pop(vcc, skb); 682 else 683 dev_kfree_skb(skb); 684 } 685 686 while ((skb = skb_dequeue(&scq->pending))) { 687 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 688 skb->len, PCI_DMA_TODEVICE); 689 690 vcc = ATM_SKB(skb)->vcc; 691 if (vcc->pop) 692 vcc->pop(vcc, skb); 693 else 694 dev_kfree_skb(skb); 695 } 696 697 kfree(scq); 698 } 699 700 701 static int 702 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 703 { 704 struct scq_info *scq = vc->scq; 705 unsigned long flags; 706 struct scqe *tbd; 707 int entries; 708 709 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 710 711 atomic_inc(&scq->used); 712 entries = atomic_read(&scq->used); 713 if (entries > (SCQ_ENTRIES - 1)) { 714 atomic_dec(&scq->used); 715 goto out; 716 } 717 718 skb_queue_tail(&scq->transmit, skb); 719 720 spin_lock_irqsave(&vc->lock, flags); 721 if (vc->estimator) { 722 struct atm_vcc *vcc = vc->tx_vcc; 723 struct sock *sk = sk_atm(vcc); 724 725 vc->estimator->cells += (skb->len + 47) / 48; 726 if (atomic_read(&sk->sk_wmem_alloc) > 727 (sk->sk_sndbuf >> 1)) { 728 u32 cps = vc->estimator->maxcps; 729 730 vc->estimator->cps = cps; 731 vc->estimator->avcps = cps << 5; 732 if (vc->lacr < vc->init_er) { 733 vc->lacr = vc->init_er; 734 writel(TCMDQ_LACR | (vc->lacr << 16) | 735 vc->index, SAR_REG_TCMDQ); 736 } 737 } 738 } 739 spin_unlock_irqrestore(&vc->lock, flags); 740 741 tbd = &IDT77252_PRV_TBD(skb); 742 743 spin_lock_irqsave(&scq->lock, flags); 744 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 745 SAR_TBD_TSIF | SAR_TBD_GTSI); 746 scq->next->word_2 = cpu_to_le32(tbd->word_2); 747 scq->next->word_3 = cpu_to_le32(tbd->word_3); 748 scq->next->word_4 = cpu_to_le32(tbd->word_4); 749 750 if (scq->next == scq->last) 751 scq->next = scq->base; 752 else 753 scq->next++; 754 755 write_sram(card, scq->scd, 756 scq->paddr + 757 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 758 spin_unlock_irqrestore(&scq->lock, flags); 759 760 scq->trans_start = jiffies; 761 762 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 763 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 764 SAR_REG_TCMDQ); 765 } 766 767 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 768 769 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 770 card->name, atomic_read(&scq->used), 771 read_sram(card, scq->scd + 1), scq->next); 772 773 return 0; 774 775 out: 776 if (time_after(jiffies, scq->trans_start + HZ)) { 777 printk("%s: Error pushing TBD for %d.%d\n", 778 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 779 #ifdef CONFIG_ATM_IDT77252_DEBUG 780 idt77252_tx_dump(card); 781 #endif 782 scq->trans_start = jiffies; 783 } 784 785 return -ENOBUFS; 786 } 787 788 789 static void 790 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 791 { 792 struct scq_info *scq = vc->scq; 793 struct sk_buff *skb; 794 struct atm_vcc *vcc; 795 796 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 797 card->name, atomic_read(&scq->used), scq->next); 798 799 skb = skb_dequeue(&scq->transmit); 800 if (skb) { 801 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 802 803 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 804 skb->len, PCI_DMA_TODEVICE); 805 806 vcc = ATM_SKB(skb)->vcc; 807 808 if (vcc->pop) 809 vcc->pop(vcc, skb); 810 else 811 dev_kfree_skb(skb); 812 813 atomic_inc(&vcc->stats->tx); 814 } 815 816 atomic_dec(&scq->used); 817 818 spin_lock(&scq->skblock); 819 while ((skb = skb_dequeue(&scq->pending))) { 820 if (push_on_scq(card, vc, skb)) { 821 skb_queue_head(&vc->scq->pending, skb); 822 break; 823 } 824 } 825 spin_unlock(&scq->skblock); 826 } 827 828 static int 829 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 830 struct sk_buff *skb, int oam) 831 { 832 struct atm_vcc *vcc; 833 struct scqe *tbd; 834 unsigned long flags; 835 int error; 836 int aal; 837 838 if (skb->len == 0) { 839 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 840 return -EINVAL; 841 } 842 843 TXPRINTK("%s: Sending %d bytes of data.\n", 844 card->name, skb->len); 845 846 tbd = &IDT77252_PRV_TBD(skb); 847 vcc = ATM_SKB(skb)->vcc; 848 849 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 850 skb->len, PCI_DMA_TODEVICE); 851 852 error = -EINVAL; 853 854 if (oam) { 855 if (skb->len != 52) 856 goto errout; 857 858 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 859 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 860 tbd->word_3 = 0x00000000; 861 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 862 (skb->data[2] << 8) | (skb->data[3] << 0); 863 864 if (test_bit(VCF_RSV, &vc->flags)) 865 vc = card->vcs[0]; 866 867 goto done; 868 } 869 870 if (test_bit(VCF_RSV, &vc->flags)) { 871 printk("%s: Trying to transmit on reserved VC\n", card->name); 872 goto errout; 873 } 874 875 aal = vcc->qos.aal; 876 877 switch (aal) { 878 case ATM_AAL0: 879 case ATM_AAL34: 880 if (skb->len > 52) 881 goto errout; 882 883 if (aal == ATM_AAL0) 884 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 885 ATM_CELL_PAYLOAD; 886 else 887 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 888 ATM_CELL_PAYLOAD; 889 890 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 891 tbd->word_3 = 0x00000000; 892 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 893 (skb->data[2] << 8) | (skb->data[3] << 0); 894 break; 895 896 case ATM_AAL5: 897 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 898 tbd->word_2 = IDT77252_PRV_PADDR(skb); 899 tbd->word_3 = skb->len; 900 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 901 (vcc->vci << SAR_TBD_VCI_SHIFT); 902 break; 903 904 case ATM_AAL1: 905 case ATM_AAL2: 906 default: 907 printk("%s: Traffic type not supported.\n", card->name); 908 error = -EPROTONOSUPPORT; 909 goto errout; 910 } 911 912 done: 913 spin_lock_irqsave(&vc->scq->skblock, flags); 914 skb_queue_tail(&vc->scq->pending, skb); 915 916 while ((skb = skb_dequeue(&vc->scq->pending))) { 917 if (push_on_scq(card, vc, skb)) { 918 skb_queue_head(&vc->scq->pending, skb); 919 break; 920 } 921 } 922 spin_unlock_irqrestore(&vc->scq->skblock, flags); 923 924 return 0; 925 926 errout: 927 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 928 skb->len, PCI_DMA_TODEVICE); 929 return error; 930 } 931 932 static unsigned long 933 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 934 { 935 int i; 936 937 for (i = 0; i < card->scd_size; i++) { 938 if (!card->scd2vc[i]) { 939 card->scd2vc[i] = vc; 940 vc->scd_index = i; 941 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 942 } 943 } 944 return 0; 945 } 946 947 static void 948 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 949 { 950 write_sram(card, scq->scd, scq->paddr); 951 write_sram(card, scq->scd + 1, 0x00000000); 952 write_sram(card, scq->scd + 2, 0xffffffff); 953 write_sram(card, scq->scd + 3, 0x00000000); 954 } 955 956 static void 957 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 958 { 959 return; 960 } 961 962 /*****************************************************************************/ 963 /* */ 964 /* RSQ Handling */ 965 /* */ 966 /*****************************************************************************/ 967 968 static int 969 init_rsq(struct idt77252_dev *card) 970 { 971 struct rsq_entry *rsqe; 972 973 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 974 &card->rsq.paddr); 975 if (card->rsq.base == NULL) { 976 printk("%s: can't allocate RSQ.\n", card->name); 977 return -1; 978 } 979 memset(card->rsq.base, 0, RSQSIZE); 980 981 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 982 card->rsq.next = card->rsq.last; 983 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 984 rsqe->word_4 = 0; 985 986 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 987 SAR_REG_RSQH); 988 writel(card->rsq.paddr, SAR_REG_RSQB); 989 990 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 991 (unsigned long) card->rsq.base, 992 readl(SAR_REG_RSQB)); 993 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 994 card->name, 995 readl(SAR_REG_RSQH), 996 readl(SAR_REG_RSQB), 997 readl(SAR_REG_RSQT)); 998 999 return 0; 1000 } 1001 1002 static void 1003 deinit_rsq(struct idt77252_dev *card) 1004 { 1005 pci_free_consistent(card->pcidev, RSQSIZE, 1006 card->rsq.base, card->rsq.paddr); 1007 } 1008 1009 static void 1010 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1011 { 1012 struct atm_vcc *vcc; 1013 struct sk_buff *skb; 1014 struct rx_pool *rpp; 1015 struct vc_map *vc; 1016 u32 header, vpi, vci; 1017 u32 stat; 1018 int i; 1019 1020 stat = le32_to_cpu(rsqe->word_4); 1021 1022 if (stat & SAR_RSQE_IDLE) { 1023 RXPRINTK("%s: message about inactive connection.\n", 1024 card->name); 1025 return; 1026 } 1027 1028 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1029 if (skb == NULL) { 1030 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1031 card->name, __func__, 1032 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1033 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1034 return; 1035 } 1036 1037 header = le32_to_cpu(rsqe->word_1); 1038 vpi = (header >> 16) & 0x00ff; 1039 vci = (header >> 0) & 0xffff; 1040 1041 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1042 card->name, vpi, vci, skb, skb->data); 1043 1044 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1045 printk("%s: SDU received for out-of-range vc %u.%u\n", 1046 card->name, vpi, vci); 1047 recycle_rx_skb(card, skb); 1048 return; 1049 } 1050 1051 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1052 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1053 printk("%s: SDU received on non RX vc %u.%u\n", 1054 card->name, vpi, vci); 1055 recycle_rx_skb(card, skb); 1056 return; 1057 } 1058 1059 vcc = vc->rx_vcc; 1060 1061 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1062 skb_end_pointer(skb) - skb->data, 1063 PCI_DMA_FROMDEVICE); 1064 1065 if ((vcc->qos.aal == ATM_AAL0) || 1066 (vcc->qos.aal == ATM_AAL34)) { 1067 struct sk_buff *sb; 1068 unsigned char *cell; 1069 u32 aal0; 1070 1071 cell = skb->data; 1072 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1073 if ((sb = dev_alloc_skb(64)) == NULL) { 1074 printk("%s: Can't allocate buffers for aal0.\n", 1075 card->name); 1076 atomic_add(i, &vcc->stats->rx_drop); 1077 break; 1078 } 1079 if (!atm_charge(vcc, sb->truesize)) { 1080 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1081 card->name); 1082 atomic_add(i - 1, &vcc->stats->rx_drop); 1083 dev_kfree_skb(sb); 1084 break; 1085 } 1086 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1087 (vci << ATM_HDR_VCI_SHIFT); 1088 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1089 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1090 1091 *((u32 *) sb->data) = aal0; 1092 skb_put(sb, sizeof(u32)); 1093 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1094 cell, ATM_CELL_PAYLOAD); 1095 1096 ATM_SKB(sb)->vcc = vcc; 1097 __net_timestamp(sb); 1098 vcc->push(vcc, sb); 1099 atomic_inc(&vcc->stats->rx); 1100 1101 cell += ATM_CELL_PAYLOAD; 1102 } 1103 1104 recycle_rx_skb(card, skb); 1105 return; 1106 } 1107 if (vcc->qos.aal != ATM_AAL5) { 1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1109 card->name, vcc->qos.aal); 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1114 1115 rpp = &vc->rcv.rx_pool; 1116 1117 rpp->len += skb->len; 1118 if (!rpp->count++) 1119 rpp->first = skb; 1120 *rpp->last = skb; 1121 rpp->last = &skb->next; 1122 1123 if (stat & SAR_RSQE_EPDU) { 1124 unsigned char *l1l2; 1125 unsigned int len; 1126 1127 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1128 1129 len = (l1l2[0] << 8) | l1l2[1]; 1130 len = len ? len : 0x10000; 1131 1132 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1133 1134 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1135 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1136 "(CDC: %08x)\n", 1137 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1138 recycle_rx_pool_skb(card, rpp); 1139 atomic_inc(&vcc->stats->rx_err); 1140 return; 1141 } 1142 if (stat & SAR_RSQE_CRC) { 1143 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1144 recycle_rx_pool_skb(card, rpp); 1145 atomic_inc(&vcc->stats->rx_err); 1146 return; 1147 } 1148 if (rpp->count > 1) { 1149 struct sk_buff *sb; 1150 1151 skb = dev_alloc_skb(rpp->len); 1152 if (!skb) { 1153 RXPRINTK("%s: Can't alloc RX skb.\n", 1154 card->name); 1155 recycle_rx_pool_skb(card, rpp); 1156 atomic_inc(&vcc->stats->rx_err); 1157 return; 1158 } 1159 if (!atm_charge(vcc, skb->truesize)) { 1160 recycle_rx_pool_skb(card, rpp); 1161 dev_kfree_skb(skb); 1162 return; 1163 } 1164 sb = rpp->first; 1165 for (i = 0; i < rpp->count; i++) { 1166 memcpy(skb_put(skb, sb->len), 1167 sb->data, sb->len); 1168 sb = sb->next; 1169 } 1170 1171 recycle_rx_pool_skb(card, rpp); 1172 1173 skb_trim(skb, len); 1174 ATM_SKB(skb)->vcc = vcc; 1175 __net_timestamp(skb); 1176 1177 vcc->push(vcc, skb); 1178 atomic_inc(&vcc->stats->rx); 1179 1180 return; 1181 } 1182 1183 skb->next = NULL; 1184 flush_rx_pool(card, rpp); 1185 1186 if (!atm_charge(vcc, skb->truesize)) { 1187 recycle_rx_skb(card, skb); 1188 return; 1189 } 1190 1191 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1192 skb_end_pointer(skb) - skb->data, 1193 PCI_DMA_FROMDEVICE); 1194 sb_pool_remove(card, skb); 1195 1196 skb_trim(skb, len); 1197 ATM_SKB(skb)->vcc = vcc; 1198 __net_timestamp(skb); 1199 1200 vcc->push(vcc, skb); 1201 atomic_inc(&vcc->stats->rx); 1202 1203 if (skb->truesize > SAR_FB_SIZE_3) 1204 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1205 else if (skb->truesize > SAR_FB_SIZE_2) 1206 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1207 else if (skb->truesize > SAR_FB_SIZE_1) 1208 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1209 else 1210 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1211 return; 1212 } 1213 } 1214 1215 static void 1216 idt77252_rx(struct idt77252_dev *card) 1217 { 1218 struct rsq_entry *rsqe; 1219 1220 if (card->rsq.next == card->rsq.last) 1221 rsqe = card->rsq.base; 1222 else 1223 rsqe = card->rsq.next + 1; 1224 1225 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1226 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1227 return; 1228 } 1229 1230 do { 1231 dequeue_rx(card, rsqe); 1232 rsqe->word_4 = 0; 1233 card->rsq.next = rsqe; 1234 if (card->rsq.next == card->rsq.last) 1235 rsqe = card->rsq.base; 1236 else 1237 rsqe = card->rsq.next + 1; 1238 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1239 1240 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1241 SAR_REG_RSQH); 1242 } 1243 1244 static void 1245 idt77252_rx_raw(struct idt77252_dev *card) 1246 { 1247 struct sk_buff *queue; 1248 u32 head, tail; 1249 struct atm_vcc *vcc; 1250 struct vc_map *vc; 1251 struct sk_buff *sb; 1252 1253 if (card->raw_cell_head == NULL) { 1254 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1255 card->raw_cell_head = sb_pool_skb(card, handle); 1256 } 1257 1258 queue = card->raw_cell_head; 1259 if (!queue) 1260 return; 1261 1262 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1263 tail = readl(SAR_REG_RAWCT); 1264 1265 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1266 skb_end_pointer(queue) - queue->head - 16, 1267 PCI_DMA_FROMDEVICE); 1268 1269 while (head != tail) { 1270 unsigned int vpi, vci, pti; 1271 u32 header; 1272 1273 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1274 1275 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1276 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1277 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1278 1279 #ifdef CONFIG_ATM_IDT77252_DEBUG 1280 if (debug & DBG_RAW_CELL) { 1281 int i; 1282 1283 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1284 card->name, (header >> 28) & 0x000f, 1285 (header >> 20) & 0x00ff, 1286 (header >> 4) & 0xffff, 1287 (header >> 1) & 0x0007, 1288 (header >> 0) & 0x0001); 1289 for (i = 16; i < 64; i++) 1290 printk(" %02x", queue->data[i]); 1291 printk("\n"); 1292 } 1293 #endif 1294 1295 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1296 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1297 card->name, vpi, vci); 1298 goto drop; 1299 } 1300 1301 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1302 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1303 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1304 card->name, vpi, vci); 1305 goto drop; 1306 } 1307 1308 vcc = vc->rx_vcc; 1309 1310 if (vcc->qos.aal != ATM_AAL0) { 1311 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1312 card->name, vpi, vci); 1313 atomic_inc(&vcc->stats->rx_drop); 1314 goto drop; 1315 } 1316 1317 if ((sb = dev_alloc_skb(64)) == NULL) { 1318 printk("%s: Can't allocate buffers for AAL0.\n", 1319 card->name); 1320 atomic_inc(&vcc->stats->rx_err); 1321 goto drop; 1322 } 1323 1324 if (!atm_charge(vcc, sb->truesize)) { 1325 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1326 card->name); 1327 dev_kfree_skb(sb); 1328 goto drop; 1329 } 1330 1331 *((u32 *) sb->data) = header; 1332 skb_put(sb, sizeof(u32)); 1333 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1334 ATM_CELL_PAYLOAD); 1335 1336 ATM_SKB(sb)->vcc = vcc; 1337 __net_timestamp(sb); 1338 vcc->push(vcc, sb); 1339 atomic_inc(&vcc->stats->rx); 1340 1341 drop: 1342 skb_pull(queue, 64); 1343 1344 head = IDT77252_PRV_PADDR(queue) 1345 + (queue->data - queue->head - 16); 1346 1347 if (queue->len < 128) { 1348 struct sk_buff *next; 1349 u32 handle; 1350 1351 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1352 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1353 1354 next = sb_pool_skb(card, handle); 1355 recycle_rx_skb(card, queue); 1356 1357 if (next) { 1358 card->raw_cell_head = next; 1359 queue = card->raw_cell_head; 1360 pci_dma_sync_single_for_cpu(card->pcidev, 1361 IDT77252_PRV_PADDR(queue), 1362 (skb_end_pointer(queue) - 1363 queue->data), 1364 PCI_DMA_FROMDEVICE); 1365 } else { 1366 card->raw_cell_head = NULL; 1367 printk("%s: raw cell queue overrun\n", 1368 card->name); 1369 break; 1370 } 1371 } 1372 } 1373 } 1374 1375 1376 /*****************************************************************************/ 1377 /* */ 1378 /* TSQ Handling */ 1379 /* */ 1380 /*****************************************************************************/ 1381 1382 static int 1383 init_tsq(struct idt77252_dev *card) 1384 { 1385 struct tsq_entry *tsqe; 1386 1387 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1388 &card->tsq.paddr); 1389 if (card->tsq.base == NULL) { 1390 printk("%s: can't allocate TSQ.\n", card->name); 1391 return -1; 1392 } 1393 memset(card->tsq.base, 0, TSQSIZE); 1394 1395 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1396 card->tsq.next = card->tsq.last; 1397 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1398 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1399 1400 writel(card->tsq.paddr, SAR_REG_TSQB); 1401 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1402 SAR_REG_TSQH); 1403 1404 return 0; 1405 } 1406 1407 static void 1408 deinit_tsq(struct idt77252_dev *card) 1409 { 1410 pci_free_consistent(card->pcidev, TSQSIZE, 1411 card->tsq.base, card->tsq.paddr); 1412 } 1413 1414 static void 1415 idt77252_tx(struct idt77252_dev *card) 1416 { 1417 struct tsq_entry *tsqe; 1418 unsigned int vpi, vci; 1419 struct vc_map *vc; 1420 u32 conn, stat; 1421 1422 if (card->tsq.next == card->tsq.last) 1423 tsqe = card->tsq.base; 1424 else 1425 tsqe = card->tsq.next + 1; 1426 1427 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1428 card->tsq.base, card->tsq.next, card->tsq.last); 1429 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1430 readl(SAR_REG_TSQB), 1431 readl(SAR_REG_TSQT), 1432 readl(SAR_REG_TSQH)); 1433 1434 stat = le32_to_cpu(tsqe->word_2); 1435 1436 if (stat & SAR_TSQE_INVALID) 1437 return; 1438 1439 do { 1440 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1441 le32_to_cpu(tsqe->word_1), 1442 le32_to_cpu(tsqe->word_2)); 1443 1444 switch (stat & SAR_TSQE_TYPE) { 1445 case SAR_TSQE_TYPE_TIMER: 1446 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1447 break; 1448 1449 case SAR_TSQE_TYPE_IDLE: 1450 1451 conn = le32_to_cpu(tsqe->word_1); 1452 1453 if (SAR_TSQE_TAG(stat) == 0x10) { 1454 #ifdef NOTDEF 1455 printk("%s: Connection %d halted.\n", 1456 card->name, 1457 le32_to_cpu(tsqe->word_1) & 0x1fff); 1458 #endif 1459 break; 1460 } 1461 1462 vc = card->vcs[conn & 0x1fff]; 1463 if (!vc) { 1464 printk("%s: could not find VC from conn %d\n", 1465 card->name, conn & 0x1fff); 1466 break; 1467 } 1468 1469 printk("%s: Connection %d IDLE.\n", 1470 card->name, vc->index); 1471 1472 set_bit(VCF_IDLE, &vc->flags); 1473 break; 1474 1475 case SAR_TSQE_TYPE_TSR: 1476 1477 conn = le32_to_cpu(tsqe->word_1); 1478 1479 vc = card->vcs[conn & 0x1fff]; 1480 if (!vc) { 1481 printk("%s: no VC at index %d\n", 1482 card->name, 1483 le32_to_cpu(tsqe->word_1) & 0x1fff); 1484 break; 1485 } 1486 1487 drain_scq(card, vc); 1488 break; 1489 1490 case SAR_TSQE_TYPE_TBD_COMP: 1491 1492 conn = le32_to_cpu(tsqe->word_1); 1493 1494 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1495 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1496 1497 if (vpi >= (1 << card->vpibits) || 1498 vci >= (1 << card->vcibits)) { 1499 printk("%s: TBD complete: " 1500 "out of range VPI.VCI %u.%u\n", 1501 card->name, vpi, vci); 1502 break; 1503 } 1504 1505 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1506 if (!vc) { 1507 printk("%s: TBD complete: " 1508 "no VC at VPI.VCI %u.%u\n", 1509 card->name, vpi, vci); 1510 break; 1511 } 1512 1513 drain_scq(card, vc); 1514 break; 1515 } 1516 1517 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1518 1519 card->tsq.next = tsqe; 1520 if (card->tsq.next == card->tsq.last) 1521 tsqe = card->tsq.base; 1522 else 1523 tsqe = card->tsq.next + 1; 1524 1525 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1526 card->tsq.base, card->tsq.next, card->tsq.last); 1527 1528 stat = le32_to_cpu(tsqe->word_2); 1529 1530 } while (!(stat & SAR_TSQE_INVALID)); 1531 1532 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1533 SAR_REG_TSQH); 1534 1535 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1536 card->index, readl(SAR_REG_TSQH), 1537 readl(SAR_REG_TSQT), card->tsq.next); 1538 } 1539 1540 1541 static void 1542 tst_timer(unsigned long data) 1543 { 1544 struct idt77252_dev *card = (struct idt77252_dev *)data; 1545 unsigned long base, idle, jump; 1546 unsigned long flags; 1547 u32 pc; 1548 int e; 1549 1550 spin_lock_irqsave(&card->tst_lock, flags); 1551 1552 base = card->tst[card->tst_index]; 1553 idle = card->tst[card->tst_index ^ 1]; 1554 1555 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1556 jump = base + card->tst_size - 2; 1557 1558 pc = readl(SAR_REG_NOW) >> 2; 1559 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1560 mod_timer(&card->tst_timer, jiffies + 1); 1561 goto out; 1562 } 1563 1564 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1565 1566 card->tst_index ^= 1; 1567 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1568 1569 base = card->tst[card->tst_index]; 1570 idle = card->tst[card->tst_index ^ 1]; 1571 1572 for (e = 0; e < card->tst_size - 2; e++) { 1573 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1574 write_sram(card, idle + e, 1575 card->soft_tst[e].tste & TSTE_MASK); 1576 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1577 } 1578 } 1579 } 1580 1581 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1582 1583 for (e = 0; e < card->tst_size - 2; e++) { 1584 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1585 write_sram(card, idle + e, 1586 card->soft_tst[e].tste & TSTE_MASK); 1587 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1588 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1589 } 1590 } 1591 1592 jump = base + card->tst_size - 2; 1593 1594 write_sram(card, jump, TSTE_OPC_NULL); 1595 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1596 1597 mod_timer(&card->tst_timer, jiffies + 1); 1598 } 1599 1600 out: 1601 spin_unlock_irqrestore(&card->tst_lock, flags); 1602 } 1603 1604 static int 1605 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1606 int n, unsigned int opc) 1607 { 1608 unsigned long cl, avail; 1609 unsigned long idle; 1610 int e, r; 1611 u32 data; 1612 1613 avail = card->tst_size - 2; 1614 for (e = 0; e < avail; e++) { 1615 if (card->soft_tst[e].vc == NULL) 1616 break; 1617 } 1618 if (e >= avail) { 1619 printk("%s: No free TST entries found\n", card->name); 1620 return -1; 1621 } 1622 1623 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1624 card->name, vc ? vc->index : -1, e); 1625 1626 r = n; 1627 cl = avail; 1628 data = opc & TSTE_OPC_MASK; 1629 if (vc && (opc != TSTE_OPC_NULL)) 1630 data = opc | vc->index; 1631 1632 idle = card->tst[card->tst_index ^ 1]; 1633 1634 /* 1635 * Fill Soft TST. 1636 */ 1637 while (r > 0) { 1638 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1639 if (vc) 1640 card->soft_tst[e].vc = vc; 1641 else 1642 card->soft_tst[e].vc = (void *)-1; 1643 1644 card->soft_tst[e].tste = data; 1645 if (timer_pending(&card->tst_timer)) 1646 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1647 else { 1648 write_sram(card, idle + e, data); 1649 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1650 } 1651 1652 cl -= card->tst_size; 1653 r--; 1654 } 1655 1656 if (++e == avail) 1657 e = 0; 1658 cl += n; 1659 } 1660 1661 return 0; 1662 } 1663 1664 static int 1665 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1666 { 1667 unsigned long flags; 1668 int res; 1669 1670 spin_lock_irqsave(&card->tst_lock, flags); 1671 1672 res = __fill_tst(card, vc, n, opc); 1673 1674 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1675 if (!timer_pending(&card->tst_timer)) 1676 mod_timer(&card->tst_timer, jiffies + 1); 1677 1678 spin_unlock_irqrestore(&card->tst_lock, flags); 1679 return res; 1680 } 1681 1682 static int 1683 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1684 { 1685 unsigned long idle; 1686 int e; 1687 1688 idle = card->tst[card->tst_index ^ 1]; 1689 1690 for (e = 0; e < card->tst_size - 2; e++) { 1691 if (card->soft_tst[e].vc == vc) { 1692 card->soft_tst[e].vc = NULL; 1693 1694 card->soft_tst[e].tste = TSTE_OPC_VAR; 1695 if (timer_pending(&card->tst_timer)) 1696 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1697 else { 1698 write_sram(card, idle + e, TSTE_OPC_VAR); 1699 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1700 } 1701 } 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int 1708 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1709 { 1710 unsigned long flags; 1711 int res; 1712 1713 spin_lock_irqsave(&card->tst_lock, flags); 1714 1715 res = __clear_tst(card, vc); 1716 1717 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1718 if (!timer_pending(&card->tst_timer)) 1719 mod_timer(&card->tst_timer, jiffies + 1); 1720 1721 spin_unlock_irqrestore(&card->tst_lock, flags); 1722 return res; 1723 } 1724 1725 static int 1726 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1727 int n, unsigned int opc) 1728 { 1729 unsigned long flags; 1730 int res; 1731 1732 spin_lock_irqsave(&card->tst_lock, flags); 1733 1734 __clear_tst(card, vc); 1735 res = __fill_tst(card, vc, n, opc); 1736 1737 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1738 if (!timer_pending(&card->tst_timer)) 1739 mod_timer(&card->tst_timer, jiffies + 1); 1740 1741 spin_unlock_irqrestore(&card->tst_lock, flags); 1742 return res; 1743 } 1744 1745 1746 static int 1747 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1748 { 1749 unsigned long tct; 1750 1751 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1752 1753 switch (vc->class) { 1754 case SCHED_CBR: 1755 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1756 card->name, tct, vc->scq->scd); 1757 1758 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1759 write_sram(card, tct + 1, 0); 1760 write_sram(card, tct + 2, 0); 1761 write_sram(card, tct + 3, 0); 1762 write_sram(card, tct + 4, 0); 1763 write_sram(card, tct + 5, 0); 1764 write_sram(card, tct + 6, 0); 1765 write_sram(card, tct + 7, 0); 1766 break; 1767 1768 case SCHED_UBR: 1769 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1770 card->name, tct, vc->scq->scd); 1771 1772 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1773 write_sram(card, tct + 1, 0); 1774 write_sram(card, tct + 2, TCT_TSIF); 1775 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1776 write_sram(card, tct + 4, 0); 1777 write_sram(card, tct + 5, vc->init_er); 1778 write_sram(card, tct + 6, 0); 1779 write_sram(card, tct + 7, TCT_FLAG_UBR); 1780 break; 1781 1782 case SCHED_VBR: 1783 case SCHED_ABR: 1784 default: 1785 return -ENOSYS; 1786 } 1787 1788 return 0; 1789 } 1790 1791 /*****************************************************************************/ 1792 /* */ 1793 /* FBQ Handling */ 1794 /* */ 1795 /*****************************************************************************/ 1796 1797 static __inline__ int 1798 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1799 { 1800 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1801 } 1802 1803 static __inline__ int 1804 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1805 { 1806 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1807 } 1808 1809 static int 1810 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1811 { 1812 unsigned long flags; 1813 u32 handle; 1814 u32 addr; 1815 1816 skb->data = skb->head; 1817 skb_reset_tail_pointer(skb); 1818 skb->len = 0; 1819 1820 skb_reserve(skb, 16); 1821 1822 switch (queue) { 1823 case 0: 1824 skb_put(skb, SAR_FB_SIZE_0); 1825 break; 1826 case 1: 1827 skb_put(skb, SAR_FB_SIZE_1); 1828 break; 1829 case 2: 1830 skb_put(skb, SAR_FB_SIZE_2); 1831 break; 1832 case 3: 1833 skb_put(skb, SAR_FB_SIZE_3); 1834 break; 1835 default: 1836 return -1; 1837 } 1838 1839 if (idt77252_fbq_full(card, queue)) 1840 return -1; 1841 1842 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1843 1844 handle = IDT77252_PRV_POOL(skb); 1845 addr = IDT77252_PRV_PADDR(skb); 1846 1847 spin_lock_irqsave(&card->cmd_lock, flags); 1848 writel(handle, card->fbq[queue]); 1849 writel(addr, card->fbq[queue]); 1850 spin_unlock_irqrestore(&card->cmd_lock, flags); 1851 1852 return 0; 1853 } 1854 1855 static void 1856 add_rx_skb(struct idt77252_dev *card, int queue, 1857 unsigned int size, unsigned int count) 1858 { 1859 struct sk_buff *skb; 1860 dma_addr_t paddr; 1861 u32 handle; 1862 1863 while (count--) { 1864 skb = dev_alloc_skb(size); 1865 if (!skb) 1866 return; 1867 1868 if (sb_pool_add(card, skb, queue)) { 1869 printk("%s: SB POOL full\n", __func__); 1870 goto outfree; 1871 } 1872 1873 paddr = pci_map_single(card->pcidev, skb->data, 1874 skb_end_pointer(skb) - skb->data, 1875 PCI_DMA_FROMDEVICE); 1876 IDT77252_PRV_PADDR(skb) = paddr; 1877 1878 if (push_rx_skb(card, skb, queue)) { 1879 printk("%s: FB QUEUE full\n", __func__); 1880 goto outunmap; 1881 } 1882 } 1883 1884 return; 1885 1886 outunmap: 1887 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1888 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1889 1890 handle = IDT77252_PRV_POOL(skb); 1891 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1892 1893 outfree: 1894 dev_kfree_skb(skb); 1895 } 1896 1897 1898 static void 1899 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1900 { 1901 u32 handle = IDT77252_PRV_POOL(skb); 1902 int err; 1903 1904 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1905 skb_end_pointer(skb) - skb->data, 1906 PCI_DMA_FROMDEVICE); 1907 1908 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1909 if (err) { 1910 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1911 skb_end_pointer(skb) - skb->data, 1912 PCI_DMA_FROMDEVICE); 1913 sb_pool_remove(card, skb); 1914 dev_kfree_skb(skb); 1915 } 1916 } 1917 1918 static void 1919 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1920 { 1921 rpp->len = 0; 1922 rpp->count = 0; 1923 rpp->first = NULL; 1924 rpp->last = &rpp->first; 1925 } 1926 1927 static void 1928 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1929 { 1930 struct sk_buff *skb, *next; 1931 int i; 1932 1933 skb = rpp->first; 1934 for (i = 0; i < rpp->count; i++) { 1935 next = skb->next; 1936 skb->next = NULL; 1937 recycle_rx_skb(card, skb); 1938 skb = next; 1939 } 1940 flush_rx_pool(card, rpp); 1941 } 1942 1943 /*****************************************************************************/ 1944 /* */ 1945 /* ATM Interface */ 1946 /* */ 1947 /*****************************************************************************/ 1948 1949 static void 1950 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1951 { 1952 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1953 } 1954 1955 static unsigned char 1956 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1957 { 1958 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1959 } 1960 1961 static inline int 1962 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1963 { 1964 struct atm_dev *dev = vcc->dev; 1965 struct idt77252_dev *card = dev->dev_data; 1966 struct vc_map *vc = vcc->dev_data; 1967 int err; 1968 1969 if (vc == NULL) { 1970 printk("%s: NULL connection in send().\n", card->name); 1971 atomic_inc(&vcc->stats->tx_err); 1972 dev_kfree_skb(skb); 1973 return -EINVAL; 1974 } 1975 if (!test_bit(VCF_TX, &vc->flags)) { 1976 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1977 atomic_inc(&vcc->stats->tx_err); 1978 dev_kfree_skb(skb); 1979 return -EINVAL; 1980 } 1981 1982 switch (vcc->qos.aal) { 1983 case ATM_AAL0: 1984 case ATM_AAL1: 1985 case ATM_AAL5: 1986 break; 1987 default: 1988 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1989 atomic_inc(&vcc->stats->tx_err); 1990 dev_kfree_skb(skb); 1991 return -EINVAL; 1992 } 1993 1994 if (skb_shinfo(skb)->nr_frags != 0) { 1995 printk("%s: No scatter-gather yet.\n", card->name); 1996 atomic_inc(&vcc->stats->tx_err); 1997 dev_kfree_skb(skb); 1998 return -EINVAL; 1999 } 2000 ATM_SKB(skb)->vcc = vcc; 2001 2002 err = queue_skb(card, vc, skb, oam); 2003 if (err) { 2004 atomic_inc(&vcc->stats->tx_err); 2005 dev_kfree_skb(skb); 2006 return err; 2007 } 2008 2009 return 0; 2010 } 2011 2012 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2013 { 2014 return idt77252_send_skb(vcc, skb, 0); 2015 } 2016 2017 static int 2018 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2019 { 2020 struct atm_dev *dev = vcc->dev; 2021 struct idt77252_dev *card = dev->dev_data; 2022 struct sk_buff *skb; 2023 2024 skb = dev_alloc_skb(64); 2025 if (!skb) { 2026 printk("%s: Out of memory in send_oam().\n", card->name); 2027 atomic_inc(&vcc->stats->tx_err); 2028 return -ENOMEM; 2029 } 2030 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2031 2032 memcpy(skb_put(skb, 52), cell, 52); 2033 2034 return idt77252_send_skb(vcc, skb, 1); 2035 } 2036 2037 static __inline__ unsigned int 2038 idt77252_fls(unsigned int x) 2039 { 2040 int r = 1; 2041 2042 if (x == 0) 2043 return 0; 2044 if (x & 0xffff0000) { 2045 x >>= 16; 2046 r += 16; 2047 } 2048 if (x & 0xff00) { 2049 x >>= 8; 2050 r += 8; 2051 } 2052 if (x & 0xf0) { 2053 x >>= 4; 2054 r += 4; 2055 } 2056 if (x & 0xc) { 2057 x >>= 2; 2058 r += 2; 2059 } 2060 if (x & 0x2) 2061 r += 1; 2062 return r; 2063 } 2064 2065 static u16 2066 idt77252_int_to_atmfp(unsigned int rate) 2067 { 2068 u16 m, e; 2069 2070 if (rate == 0) 2071 return 0; 2072 e = idt77252_fls(rate) - 1; 2073 if (e < 9) 2074 m = (rate - (1 << e)) << (9 - e); 2075 else if (e == 9) 2076 m = (rate - (1 << e)); 2077 else /* e > 9 */ 2078 m = (rate - (1 << e)) >> (e - 9); 2079 return 0x4000 | (e << 9) | m; 2080 } 2081 2082 static u8 2083 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2084 { 2085 u16 afp; 2086 2087 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2088 if (pcr < 0) 2089 return rate_to_log[(afp >> 5) & 0x1ff]; 2090 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2091 } 2092 2093 static void 2094 idt77252_est_timer(unsigned long data) 2095 { 2096 struct vc_map *vc = (struct vc_map *)data; 2097 struct idt77252_dev *card = vc->card; 2098 struct rate_estimator *est; 2099 unsigned long flags; 2100 u32 rate, cps; 2101 u64 ncells; 2102 u8 lacr; 2103 2104 spin_lock_irqsave(&vc->lock, flags); 2105 est = vc->estimator; 2106 if (!est) 2107 goto out; 2108 2109 ncells = est->cells; 2110 2111 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2112 est->last_cells = ncells; 2113 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2114 est->cps = (est->avcps + 0x1f) >> 5; 2115 2116 cps = est->cps; 2117 if (cps < (est->maxcps >> 4)) 2118 cps = est->maxcps >> 4; 2119 2120 lacr = idt77252_rate_logindex(card, cps); 2121 if (lacr > vc->max_er) 2122 lacr = vc->max_er; 2123 2124 if (lacr != vc->lacr) { 2125 vc->lacr = lacr; 2126 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2127 } 2128 2129 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2130 add_timer(&est->timer); 2131 2132 out: 2133 spin_unlock_irqrestore(&vc->lock, flags); 2134 } 2135 2136 static struct rate_estimator * 2137 idt77252_init_est(struct vc_map *vc, int pcr) 2138 { 2139 struct rate_estimator *est; 2140 2141 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2142 if (!est) 2143 return NULL; 2144 est->maxcps = pcr < 0 ? -pcr : pcr; 2145 est->cps = est->maxcps; 2146 est->avcps = est->cps << 5; 2147 2148 est->interval = 2; /* XXX: make this configurable */ 2149 est->ewma_log = 2; /* XXX: make this configurable */ 2150 init_timer(&est->timer); 2151 est->timer.data = (unsigned long)vc; 2152 est->timer.function = idt77252_est_timer; 2153 2154 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2155 add_timer(&est->timer); 2156 2157 return est; 2158 } 2159 2160 static int 2161 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2162 struct atm_vcc *vcc, struct atm_qos *qos) 2163 { 2164 int tst_free, tst_used, tst_entries; 2165 unsigned long tmpl, modl; 2166 int tcr, tcra; 2167 2168 if ((qos->txtp.max_pcr == 0) && 2169 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2170 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2171 card->name); 2172 return -EINVAL; 2173 } 2174 2175 tst_used = 0; 2176 tst_free = card->tst_free; 2177 if (test_bit(VCF_TX, &vc->flags)) 2178 tst_used = vc->ntste; 2179 tst_free += tst_used; 2180 2181 tcr = atm_pcr_goal(&qos->txtp); 2182 tcra = tcr >= 0 ? tcr : -tcr; 2183 2184 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2185 2186 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2187 modl = tmpl % (unsigned long)card->utopia_pcr; 2188 2189 tst_entries = (int) (tmpl / card->utopia_pcr); 2190 if (tcr > 0) { 2191 if (modl > 0) 2192 tst_entries++; 2193 } else if (tcr == 0) { 2194 tst_entries = tst_free - SAR_TST_RESERVED; 2195 if (tst_entries <= 0) { 2196 printk("%s: no CBR bandwidth free.\n", card->name); 2197 return -ENOSR; 2198 } 2199 } 2200 2201 if (tst_entries == 0) { 2202 printk("%s: selected CBR bandwidth < granularity.\n", 2203 card->name); 2204 return -EINVAL; 2205 } 2206 2207 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2208 printk("%s: not enough CBR bandwidth free.\n", card->name); 2209 return -ENOSR; 2210 } 2211 2212 vc->ntste = tst_entries; 2213 2214 card->tst_free = tst_free - tst_entries; 2215 if (test_bit(VCF_TX, &vc->flags)) { 2216 if (tst_used == tst_entries) 2217 return 0; 2218 2219 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2220 card->name, tst_used, tst_entries); 2221 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2222 return 0; 2223 } 2224 2225 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2226 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2227 return 0; 2228 } 2229 2230 static int 2231 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2232 struct atm_vcc *vcc, struct atm_qos *qos) 2233 { 2234 unsigned long flags; 2235 int tcr; 2236 2237 spin_lock_irqsave(&vc->lock, flags); 2238 if (vc->estimator) { 2239 del_timer(&vc->estimator->timer); 2240 kfree(vc->estimator); 2241 vc->estimator = NULL; 2242 } 2243 spin_unlock_irqrestore(&vc->lock, flags); 2244 2245 tcr = atm_pcr_goal(&qos->txtp); 2246 if (tcr == 0) 2247 tcr = card->link_pcr; 2248 2249 vc->estimator = idt77252_init_est(vc, tcr); 2250 2251 vc->class = SCHED_UBR; 2252 vc->init_er = idt77252_rate_logindex(card, tcr); 2253 vc->lacr = vc->init_er; 2254 if (tcr < 0) 2255 vc->max_er = vc->init_er; 2256 else 2257 vc->max_er = 0xff; 2258 2259 return 0; 2260 } 2261 2262 static int 2263 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2264 struct atm_vcc *vcc, struct atm_qos *qos) 2265 { 2266 int error; 2267 2268 if (test_bit(VCF_TX, &vc->flags)) 2269 return -EBUSY; 2270 2271 switch (qos->txtp.traffic_class) { 2272 case ATM_CBR: 2273 vc->class = SCHED_CBR; 2274 break; 2275 2276 case ATM_UBR: 2277 vc->class = SCHED_UBR; 2278 break; 2279 2280 case ATM_VBR: 2281 case ATM_ABR: 2282 default: 2283 return -EPROTONOSUPPORT; 2284 } 2285 2286 vc->scq = alloc_scq(card, vc->class); 2287 if (!vc->scq) { 2288 printk("%s: can't get SCQ.\n", card->name); 2289 return -ENOMEM; 2290 } 2291 2292 vc->scq->scd = get_free_scd(card, vc); 2293 if (vc->scq->scd == 0) { 2294 printk("%s: no SCD available.\n", card->name); 2295 free_scq(card, vc->scq); 2296 return -ENOMEM; 2297 } 2298 2299 fill_scd(card, vc->scq, vc->class); 2300 2301 if (set_tct(card, vc)) { 2302 printk("%s: class %d not supported.\n", 2303 card->name, qos->txtp.traffic_class); 2304 2305 card->scd2vc[vc->scd_index] = NULL; 2306 free_scq(card, vc->scq); 2307 return -EPROTONOSUPPORT; 2308 } 2309 2310 switch (vc->class) { 2311 case SCHED_CBR: 2312 error = idt77252_init_cbr(card, vc, vcc, qos); 2313 if (error) { 2314 card->scd2vc[vc->scd_index] = NULL; 2315 free_scq(card, vc->scq); 2316 return error; 2317 } 2318 2319 clear_bit(VCF_IDLE, &vc->flags); 2320 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2321 break; 2322 2323 case SCHED_UBR: 2324 error = idt77252_init_ubr(card, vc, vcc, qos); 2325 if (error) { 2326 card->scd2vc[vc->scd_index] = NULL; 2327 free_scq(card, vc->scq); 2328 return error; 2329 } 2330 2331 set_bit(VCF_IDLE, &vc->flags); 2332 break; 2333 } 2334 2335 vc->tx_vcc = vcc; 2336 set_bit(VCF_TX, &vc->flags); 2337 return 0; 2338 } 2339 2340 static int 2341 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2342 struct atm_vcc *vcc, struct atm_qos *qos) 2343 { 2344 unsigned long flags; 2345 unsigned long addr; 2346 u32 rcte = 0; 2347 2348 if (test_bit(VCF_RX, &vc->flags)) 2349 return -EBUSY; 2350 2351 vc->rx_vcc = vcc; 2352 set_bit(VCF_RX, &vc->flags); 2353 2354 if ((vcc->vci == 3) || (vcc->vci == 4)) 2355 return 0; 2356 2357 flush_rx_pool(card, &vc->rcv.rx_pool); 2358 2359 rcte |= SAR_RCTE_CONNECTOPEN; 2360 rcte |= SAR_RCTE_RAWCELLINTEN; 2361 2362 switch (qos->aal) { 2363 case ATM_AAL0: 2364 rcte |= SAR_RCTE_RCQ; 2365 break; 2366 case ATM_AAL1: 2367 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2368 break; 2369 case ATM_AAL34: 2370 rcte |= SAR_RCTE_AAL34; 2371 break; 2372 case ATM_AAL5: 2373 rcte |= SAR_RCTE_AAL5; 2374 break; 2375 default: 2376 rcte |= SAR_RCTE_RCQ; 2377 break; 2378 } 2379 2380 if (qos->aal != ATM_AAL5) 2381 rcte |= SAR_RCTE_FBP_1; 2382 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2383 rcte |= SAR_RCTE_FBP_3; 2384 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2385 rcte |= SAR_RCTE_FBP_2; 2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2387 rcte |= SAR_RCTE_FBP_1; 2388 else 2389 rcte |= SAR_RCTE_FBP_01; 2390 2391 addr = card->rct_base + (vc->index << 2); 2392 2393 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2394 write_sram(card, addr, rcte); 2395 2396 spin_lock_irqsave(&card->cmd_lock, flags); 2397 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2398 waitfor_idle(card); 2399 spin_unlock_irqrestore(&card->cmd_lock, flags); 2400 2401 return 0; 2402 } 2403 2404 static int 2405 idt77252_open(struct atm_vcc *vcc) 2406 { 2407 struct atm_dev *dev = vcc->dev; 2408 struct idt77252_dev *card = dev->dev_data; 2409 struct vc_map *vc; 2410 unsigned int index; 2411 unsigned int inuse; 2412 int error; 2413 int vci = vcc->vci; 2414 short vpi = vcc->vpi; 2415 2416 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2417 return 0; 2418 2419 if (vpi >= (1 << card->vpibits)) { 2420 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2421 return -EINVAL; 2422 } 2423 2424 if (vci >= (1 << card->vcibits)) { 2425 printk("%s: unsupported VCI: %d\n", card->name, vci); 2426 return -EINVAL; 2427 } 2428 2429 set_bit(ATM_VF_ADDR, &vcc->flags); 2430 2431 mutex_lock(&card->mutex); 2432 2433 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2434 2435 switch (vcc->qos.aal) { 2436 case ATM_AAL0: 2437 case ATM_AAL1: 2438 case ATM_AAL5: 2439 break; 2440 default: 2441 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2442 mutex_unlock(&card->mutex); 2443 return -EPROTONOSUPPORT; 2444 } 2445 2446 index = VPCI2VC(card, vpi, vci); 2447 if (!card->vcs[index]) { 2448 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2449 if (!card->vcs[index]) { 2450 printk("%s: can't alloc vc in open()\n", card->name); 2451 mutex_unlock(&card->mutex); 2452 return -ENOMEM; 2453 } 2454 card->vcs[index]->card = card; 2455 card->vcs[index]->index = index; 2456 2457 spin_lock_init(&card->vcs[index]->lock); 2458 } 2459 vc = card->vcs[index]; 2460 2461 vcc->dev_data = vc; 2462 2463 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2464 card->name, vc->index, vcc->vpi, vcc->vci, 2465 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2466 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2467 vcc->qos.rxtp.max_sdu); 2468 2469 inuse = 0; 2470 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2471 test_bit(VCF_TX, &vc->flags)) 2472 inuse = 1; 2473 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2474 test_bit(VCF_RX, &vc->flags)) 2475 inuse += 2; 2476 2477 if (inuse) { 2478 printk("%s: %s vci already in use.\n", card->name, 2479 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2480 mutex_unlock(&card->mutex); 2481 return -EADDRINUSE; 2482 } 2483 2484 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2485 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2486 if (error) { 2487 mutex_unlock(&card->mutex); 2488 return error; 2489 } 2490 } 2491 2492 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2493 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2494 if (error) { 2495 mutex_unlock(&card->mutex); 2496 return error; 2497 } 2498 } 2499 2500 set_bit(ATM_VF_READY, &vcc->flags); 2501 2502 mutex_unlock(&card->mutex); 2503 return 0; 2504 } 2505 2506 static void 2507 idt77252_close(struct atm_vcc *vcc) 2508 { 2509 struct atm_dev *dev = vcc->dev; 2510 struct idt77252_dev *card = dev->dev_data; 2511 struct vc_map *vc = vcc->dev_data; 2512 unsigned long flags; 2513 unsigned long addr; 2514 unsigned long timeout; 2515 2516 mutex_lock(&card->mutex); 2517 2518 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2519 card->name, vc->index, vcc->vpi, vcc->vci); 2520 2521 clear_bit(ATM_VF_READY, &vcc->flags); 2522 2523 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2524 2525 spin_lock_irqsave(&vc->lock, flags); 2526 clear_bit(VCF_RX, &vc->flags); 2527 vc->rx_vcc = NULL; 2528 spin_unlock_irqrestore(&vc->lock, flags); 2529 2530 if ((vcc->vci == 3) || (vcc->vci == 4)) 2531 goto done; 2532 2533 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2534 2535 spin_lock_irqsave(&card->cmd_lock, flags); 2536 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2537 waitfor_idle(card); 2538 spin_unlock_irqrestore(&card->cmd_lock, flags); 2539 2540 if (vc->rcv.rx_pool.count) { 2541 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2542 card->name); 2543 2544 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2545 } 2546 } 2547 2548 done: 2549 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2550 2551 spin_lock_irqsave(&vc->lock, flags); 2552 clear_bit(VCF_TX, &vc->flags); 2553 clear_bit(VCF_IDLE, &vc->flags); 2554 clear_bit(VCF_RSV, &vc->flags); 2555 vc->tx_vcc = NULL; 2556 2557 if (vc->estimator) { 2558 del_timer(&vc->estimator->timer); 2559 kfree(vc->estimator); 2560 vc->estimator = NULL; 2561 } 2562 spin_unlock_irqrestore(&vc->lock, flags); 2563 2564 timeout = 5 * 1000; 2565 while (atomic_read(&vc->scq->used) > 0) { 2566 timeout = msleep_interruptible(timeout); 2567 if (!timeout) 2568 break; 2569 } 2570 if (!timeout) 2571 printk("%s: SCQ drain timeout: %u used\n", 2572 card->name, atomic_read(&vc->scq->used)); 2573 2574 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2575 clear_scd(card, vc->scq, vc->class); 2576 2577 if (vc->class == SCHED_CBR) { 2578 clear_tst(card, vc); 2579 card->tst_free += vc->ntste; 2580 vc->ntste = 0; 2581 } 2582 2583 card->scd2vc[vc->scd_index] = NULL; 2584 free_scq(card, vc->scq); 2585 } 2586 2587 mutex_unlock(&card->mutex); 2588 } 2589 2590 static int 2591 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2592 { 2593 struct atm_dev *dev = vcc->dev; 2594 struct idt77252_dev *card = dev->dev_data; 2595 struct vc_map *vc = vcc->dev_data; 2596 int error = 0; 2597 2598 mutex_lock(&card->mutex); 2599 2600 if (qos->txtp.traffic_class != ATM_NONE) { 2601 if (!test_bit(VCF_TX, &vc->flags)) { 2602 error = idt77252_init_tx(card, vc, vcc, qos); 2603 if (error) 2604 goto out; 2605 } else { 2606 switch (qos->txtp.traffic_class) { 2607 case ATM_CBR: 2608 error = idt77252_init_cbr(card, vc, vcc, qos); 2609 if (error) 2610 goto out; 2611 break; 2612 2613 case ATM_UBR: 2614 error = idt77252_init_ubr(card, vc, vcc, qos); 2615 if (error) 2616 goto out; 2617 2618 if (!test_bit(VCF_IDLE, &vc->flags)) { 2619 writel(TCMDQ_LACR | (vc->lacr << 16) | 2620 vc->index, SAR_REG_TCMDQ); 2621 } 2622 break; 2623 2624 case ATM_VBR: 2625 case ATM_ABR: 2626 error = -EOPNOTSUPP; 2627 goto out; 2628 } 2629 } 2630 } 2631 2632 if ((qos->rxtp.traffic_class != ATM_NONE) && 2633 !test_bit(VCF_RX, &vc->flags)) { 2634 error = idt77252_init_rx(card, vc, vcc, qos); 2635 if (error) 2636 goto out; 2637 } 2638 2639 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2640 2641 set_bit(ATM_VF_HASQOS, &vcc->flags); 2642 2643 out: 2644 mutex_unlock(&card->mutex); 2645 return error; 2646 } 2647 2648 static int 2649 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2650 { 2651 struct idt77252_dev *card = dev->dev_data; 2652 int i, left; 2653 2654 left = (int) *pos; 2655 if (!left--) 2656 return sprintf(page, "IDT77252 Interrupts:\n"); 2657 if (!left--) 2658 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2659 if (!left--) 2660 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2661 if (!left--) 2662 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2663 if (!left--) 2664 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2665 if (!left--) 2666 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2667 if (!left--) 2668 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2669 if (!left--) 2670 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2671 if (!left--) 2672 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2673 if (!left--) 2674 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2675 if (!left--) 2676 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2677 if (!left--) 2678 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2679 if (!left--) 2680 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2681 if (!left--) 2682 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2683 if (!left--) 2684 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2685 2686 for (i = 0; i < card->tct_size; i++) { 2687 unsigned long tct; 2688 struct atm_vcc *vcc; 2689 struct vc_map *vc; 2690 char *p; 2691 2692 vc = card->vcs[i]; 2693 if (!vc) 2694 continue; 2695 2696 vcc = NULL; 2697 if (vc->tx_vcc) 2698 vcc = vc->tx_vcc; 2699 if (!vcc) 2700 continue; 2701 if (left--) 2702 continue; 2703 2704 p = page; 2705 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2706 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2707 2708 for (i = 0; i < 8; i++) 2709 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2710 p += sprintf(p, "\n"); 2711 return p - page; 2712 } 2713 return 0; 2714 } 2715 2716 /*****************************************************************************/ 2717 /* */ 2718 /* Interrupt handler */ 2719 /* */ 2720 /*****************************************************************************/ 2721 2722 static void 2723 idt77252_collect_stat(struct idt77252_dev *card) 2724 { 2725 u32 cdc, vpec, icc; 2726 2727 cdc = readl(SAR_REG_CDC); 2728 vpec = readl(SAR_REG_VPEC); 2729 icc = readl(SAR_REG_ICC); 2730 2731 #ifdef NOTDEF 2732 printk("%s:", card->name); 2733 2734 if (cdc & 0x7f0000) { 2735 char *s = ""; 2736 2737 printk(" ["); 2738 if (cdc & (1 << 22)) { 2739 printk("%sRM ID", s); 2740 s = " | "; 2741 } 2742 if (cdc & (1 << 21)) { 2743 printk("%sCON TAB", s); 2744 s = " | "; 2745 } 2746 if (cdc & (1 << 20)) { 2747 printk("%sNO FB", s); 2748 s = " | "; 2749 } 2750 if (cdc & (1 << 19)) { 2751 printk("%sOAM CRC", s); 2752 s = " | "; 2753 } 2754 if (cdc & (1 << 18)) { 2755 printk("%sRM CRC", s); 2756 s = " | "; 2757 } 2758 if (cdc & (1 << 17)) { 2759 printk("%sRM FIFO", s); 2760 s = " | "; 2761 } 2762 if (cdc & (1 << 16)) { 2763 printk("%sRX FIFO", s); 2764 s = " | "; 2765 } 2766 printk("]"); 2767 } 2768 2769 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2770 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2771 #endif 2772 } 2773 2774 static irqreturn_t 2775 idt77252_interrupt(int irq, void *dev_id) 2776 { 2777 struct idt77252_dev *card = dev_id; 2778 u32 stat; 2779 2780 stat = readl(SAR_REG_STAT) & 0xffff; 2781 if (!stat) /* no interrupt for us */ 2782 return IRQ_NONE; 2783 2784 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2785 printk("%s: Re-entering irq_handler()\n", card->name); 2786 goto out; 2787 } 2788 2789 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2790 2791 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2792 INTPRINTK("%s: TSIF\n", card->name); 2793 card->irqstat[15]++; 2794 idt77252_tx(card); 2795 } 2796 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2797 INTPRINTK("%s: TXICP\n", card->name); 2798 card->irqstat[14]++; 2799 #ifdef CONFIG_ATM_IDT77252_DEBUG 2800 idt77252_tx_dump(card); 2801 #endif 2802 } 2803 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2804 INTPRINTK("%s: TSQF\n", card->name); 2805 card->irqstat[12]++; 2806 idt77252_tx(card); 2807 } 2808 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2809 INTPRINTK("%s: TMROF\n", card->name); 2810 card->irqstat[11]++; 2811 idt77252_collect_stat(card); 2812 } 2813 2814 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2815 INTPRINTK("%s: EPDU\n", card->name); 2816 card->irqstat[5]++; 2817 idt77252_rx(card); 2818 } 2819 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2820 INTPRINTK("%s: RSQAF\n", card->name); 2821 card->irqstat[1]++; 2822 idt77252_rx(card); 2823 } 2824 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2825 INTPRINTK("%s: RSQF\n", card->name); 2826 card->irqstat[6]++; 2827 idt77252_rx(card); 2828 } 2829 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2830 INTPRINTK("%s: RAWCF\n", card->name); 2831 card->irqstat[4]++; 2832 idt77252_rx_raw(card); 2833 } 2834 2835 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2836 INTPRINTK("%s: PHYI", card->name); 2837 card->irqstat[10]++; 2838 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2839 card->atmdev->phy->interrupt(card->atmdev); 2840 } 2841 2842 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2843 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2844 2845 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2846 2847 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2848 2849 if (stat & SAR_STAT_FBQ0A) 2850 card->irqstat[2]++; 2851 if (stat & SAR_STAT_FBQ1A) 2852 card->irqstat[3]++; 2853 if (stat & SAR_STAT_FBQ2A) 2854 card->irqstat[7]++; 2855 if (stat & SAR_STAT_FBQ3A) 2856 card->irqstat[8]++; 2857 2858 schedule_work(&card->tqueue); 2859 } 2860 2861 out: 2862 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2863 return IRQ_HANDLED; 2864 } 2865 2866 static void 2867 idt77252_softint(struct work_struct *work) 2868 { 2869 struct idt77252_dev *card = 2870 container_of(work, struct idt77252_dev, tqueue); 2871 u32 stat; 2872 int done; 2873 2874 for (done = 1; ; done = 1) { 2875 stat = readl(SAR_REG_STAT) >> 16; 2876 2877 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2878 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2879 done = 0; 2880 } 2881 2882 stat >>= 4; 2883 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2884 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2885 done = 0; 2886 } 2887 2888 stat >>= 4; 2889 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2890 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2891 done = 0; 2892 } 2893 2894 stat >>= 4; 2895 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2896 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2897 done = 0; 2898 } 2899 2900 if (done) 2901 break; 2902 } 2903 2904 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2905 } 2906 2907 2908 static int 2909 open_card_oam(struct idt77252_dev *card) 2910 { 2911 unsigned long flags; 2912 unsigned long addr; 2913 struct vc_map *vc; 2914 int vpi, vci; 2915 int index; 2916 u32 rcte; 2917 2918 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2919 for (vci = 3; vci < 5; vci++) { 2920 index = VPCI2VC(card, vpi, vci); 2921 2922 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2923 if (!vc) { 2924 printk("%s: can't alloc vc\n", card->name); 2925 return -ENOMEM; 2926 } 2927 vc->index = index; 2928 card->vcs[index] = vc; 2929 2930 flush_rx_pool(card, &vc->rcv.rx_pool); 2931 2932 rcte = SAR_RCTE_CONNECTOPEN | 2933 SAR_RCTE_RAWCELLINTEN | 2934 SAR_RCTE_RCQ | 2935 SAR_RCTE_FBP_1; 2936 2937 addr = card->rct_base + (vc->index << 2); 2938 write_sram(card, addr, rcte); 2939 2940 spin_lock_irqsave(&card->cmd_lock, flags); 2941 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2942 SAR_REG_CMD); 2943 waitfor_idle(card); 2944 spin_unlock_irqrestore(&card->cmd_lock, flags); 2945 } 2946 } 2947 2948 return 0; 2949 } 2950 2951 static void 2952 close_card_oam(struct idt77252_dev *card) 2953 { 2954 unsigned long flags; 2955 unsigned long addr; 2956 struct vc_map *vc; 2957 int vpi, vci; 2958 int index; 2959 2960 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2961 for (vci = 3; vci < 5; vci++) { 2962 index = VPCI2VC(card, vpi, vci); 2963 vc = card->vcs[index]; 2964 2965 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2966 2967 spin_lock_irqsave(&card->cmd_lock, flags); 2968 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2969 SAR_REG_CMD); 2970 waitfor_idle(card); 2971 spin_unlock_irqrestore(&card->cmd_lock, flags); 2972 2973 if (vc->rcv.rx_pool.count) { 2974 DPRINTK("%s: closing a VC " 2975 "with pending rx buffers.\n", 2976 card->name); 2977 2978 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2979 } 2980 } 2981 } 2982 } 2983 2984 static int 2985 open_card_ubr0(struct idt77252_dev *card) 2986 { 2987 struct vc_map *vc; 2988 2989 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2990 if (!vc) { 2991 printk("%s: can't alloc vc\n", card->name); 2992 return -ENOMEM; 2993 } 2994 card->vcs[0] = vc; 2995 vc->class = SCHED_UBR0; 2996 2997 vc->scq = alloc_scq(card, vc->class); 2998 if (!vc->scq) { 2999 printk("%s: can't get SCQ.\n", card->name); 3000 return -ENOMEM; 3001 } 3002 3003 card->scd2vc[0] = vc; 3004 vc->scd_index = 0; 3005 vc->scq->scd = card->scd_base; 3006 3007 fill_scd(card, vc->scq, vc->class); 3008 3009 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3010 write_sram(card, card->tct_base + 1, 0); 3011 write_sram(card, card->tct_base + 2, 0); 3012 write_sram(card, card->tct_base + 3, 0); 3013 write_sram(card, card->tct_base + 4, 0); 3014 write_sram(card, card->tct_base + 5, 0); 3015 write_sram(card, card->tct_base + 6, 0); 3016 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3017 3018 clear_bit(VCF_IDLE, &vc->flags); 3019 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3020 return 0; 3021 } 3022 3023 static int 3024 idt77252_dev_open(struct idt77252_dev *card) 3025 { 3026 u32 conf; 3027 3028 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3029 printk("%s: SAR not yet initialized.\n", card->name); 3030 return -1; 3031 } 3032 3033 conf = SAR_CFG_RXPTH| /* enable receive path */ 3034 SAR_RX_DELAY | /* interrupt on complete PDU */ 3035 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3036 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3037 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3038 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3039 SAR_CFG_TXEN | /* transmit operation enable */ 3040 SAR_CFG_TXINT | /* interrupt on transmit status */ 3041 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3042 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3043 SAR_CFG_PHYIE /* enable PHY interrupts */ 3044 ; 3045 3046 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 3047 /* Test RAW cell receive. */ 3048 conf |= SAR_CFG_VPECA; 3049 #endif 3050 3051 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3052 3053 if (open_card_oam(card)) { 3054 printk("%s: Error initializing OAM.\n", card->name); 3055 return -1; 3056 } 3057 3058 if (open_card_ubr0(card)) { 3059 printk("%s: Error initializing UBR0.\n", card->name); 3060 return -1; 3061 } 3062 3063 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3064 return 0; 3065 } 3066 3067 static void idt77252_dev_close(struct atm_dev *dev) 3068 { 3069 struct idt77252_dev *card = dev->dev_data; 3070 u32 conf; 3071 3072 close_card_oam(card); 3073 3074 conf = SAR_CFG_RXPTH | /* enable receive path */ 3075 SAR_RX_DELAY | /* interrupt on complete PDU */ 3076 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3077 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3078 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3079 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3080 SAR_CFG_TXEN | /* transmit operation enable */ 3081 SAR_CFG_TXINT | /* interrupt on transmit status */ 3082 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3083 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3084 ; 3085 3086 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3087 3088 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3089 } 3090 3091 3092 /*****************************************************************************/ 3093 /* */ 3094 /* Initialisation and Deinitialization of IDT77252 */ 3095 /* */ 3096 /*****************************************************************************/ 3097 3098 3099 static void 3100 deinit_card(struct idt77252_dev *card) 3101 { 3102 struct sk_buff *skb; 3103 int i, j; 3104 3105 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3106 printk("%s: SAR not yet initialized.\n", card->name); 3107 return; 3108 } 3109 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3110 3111 writel(0, SAR_REG_CFG); 3112 3113 if (card->atmdev) 3114 atm_dev_deregister(card->atmdev); 3115 3116 for (i = 0; i < 4; i++) { 3117 for (j = 0; j < FBQ_SIZE; j++) { 3118 skb = card->sbpool[i].skb[j]; 3119 if (skb) { 3120 pci_unmap_single(card->pcidev, 3121 IDT77252_PRV_PADDR(skb), 3122 (skb_end_pointer(skb) - 3123 skb->data), 3124 PCI_DMA_FROMDEVICE); 3125 card->sbpool[i].skb[j] = NULL; 3126 dev_kfree_skb(skb); 3127 } 3128 } 3129 } 3130 3131 vfree(card->soft_tst); 3132 3133 vfree(card->scd2vc); 3134 3135 vfree(card->vcs); 3136 3137 if (card->raw_cell_hnd) { 3138 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3139 card->raw_cell_hnd, card->raw_cell_paddr); 3140 } 3141 3142 if (card->rsq.base) { 3143 DIPRINTK("%s: Release RSQ ...\n", card->name); 3144 deinit_rsq(card); 3145 } 3146 3147 if (card->tsq.base) { 3148 DIPRINTK("%s: Release TSQ ...\n", card->name); 3149 deinit_tsq(card); 3150 } 3151 3152 DIPRINTK("idt77252: Release IRQ.\n"); 3153 free_irq(card->pcidev->irq, card); 3154 3155 for (i = 0; i < 4; i++) { 3156 if (card->fbq[i]) 3157 iounmap(card->fbq[i]); 3158 } 3159 3160 if (card->membase) 3161 iounmap(card->membase); 3162 3163 clear_bit(IDT77252_BIT_INIT, &card->flags); 3164 DIPRINTK("%s: Card deinitialized.\n", card->name); 3165 } 3166 3167 3168 static int __devinit 3169 init_sram(struct idt77252_dev *card) 3170 { 3171 int i; 3172 3173 for (i = 0; i < card->sramsize; i += 4) 3174 write_sram(card, (i >> 2), 0); 3175 3176 /* set SRAM layout for THIS card */ 3177 if (card->sramsize == (512 * 1024)) { 3178 card->tct_base = SAR_SRAM_TCT_128_BASE; 3179 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3180 / SAR_SRAM_TCT_SIZE; 3181 card->rct_base = SAR_SRAM_RCT_128_BASE; 3182 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3183 / SAR_SRAM_RCT_SIZE; 3184 card->rt_base = SAR_SRAM_RT_128_BASE; 3185 card->scd_base = SAR_SRAM_SCD_128_BASE; 3186 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3187 / SAR_SRAM_SCD_SIZE; 3188 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3189 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3190 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3191 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3192 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3193 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3194 card->fifo_size = SAR_RXFD_SIZE_32K; 3195 } else { 3196 card->tct_base = SAR_SRAM_TCT_32_BASE; 3197 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3198 / SAR_SRAM_TCT_SIZE; 3199 card->rct_base = SAR_SRAM_RCT_32_BASE; 3200 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3201 / SAR_SRAM_RCT_SIZE; 3202 card->rt_base = SAR_SRAM_RT_32_BASE; 3203 card->scd_base = SAR_SRAM_SCD_32_BASE; 3204 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3205 / SAR_SRAM_SCD_SIZE; 3206 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3207 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3208 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3209 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3210 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3211 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3212 card->fifo_size = SAR_RXFD_SIZE_4K; 3213 } 3214 3215 /* Initialize TCT */ 3216 for (i = 0; i < card->tct_size; i++) { 3217 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3218 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3219 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3220 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3221 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3222 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3223 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3224 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3225 } 3226 3227 /* Initialize RCT */ 3228 for (i = 0; i < card->rct_size; i++) { 3229 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3230 (u32) SAR_RCTE_RAWCELLINTEN); 3231 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3232 (u32) 0); 3233 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3234 (u32) 0); 3235 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3236 (u32) 0xffffffff); 3237 } 3238 3239 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3240 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3241 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3242 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3243 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3244 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3245 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3246 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3247 3248 /* Initialize rate table */ 3249 for (i = 0; i < 256; i++) { 3250 write_sram(card, card->rt_base + i, log_to_rate[i]); 3251 } 3252 3253 for (i = 0; i < 128; i++) { 3254 unsigned int tmp; 3255 3256 tmp = rate_to_log[(i << 2) + 0] << 0; 3257 tmp |= rate_to_log[(i << 2) + 1] << 8; 3258 tmp |= rate_to_log[(i << 2) + 2] << 16; 3259 tmp |= rate_to_log[(i << 2) + 3] << 24; 3260 write_sram(card, card->rt_base + 256 + i, tmp); 3261 } 3262 3263 #if 0 /* Fill RDF and AIR tables. */ 3264 for (i = 0; i < 128; i++) { 3265 unsigned int tmp; 3266 3267 tmp = RDF[0][(i << 1) + 0] << 16; 3268 tmp |= RDF[0][(i << 1) + 1] << 0; 3269 write_sram(card, card->rt_base + 512 + i, tmp); 3270 } 3271 3272 for (i = 0; i < 128; i++) { 3273 unsigned int tmp; 3274 3275 tmp = AIR[0][(i << 1) + 0] << 16; 3276 tmp |= AIR[0][(i << 1) + 1] << 0; 3277 write_sram(card, card->rt_base + 640 + i, tmp); 3278 } 3279 #endif 3280 3281 IPRINTK("%s: initialize rate table ...\n", card->name); 3282 writel(card->rt_base << 2, SAR_REG_RTBL); 3283 3284 /* Initialize TSTs */ 3285 IPRINTK("%s: initialize TST ...\n", card->name); 3286 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3287 3288 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3289 write_sram(card, i, TSTE_OPC_VAR); 3290 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3291 idt77252_sram_write_errors = 1; 3292 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3293 idt77252_sram_write_errors = 0; 3294 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3295 write_sram(card, i, TSTE_OPC_VAR); 3296 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3297 idt77252_sram_write_errors = 1; 3298 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3299 idt77252_sram_write_errors = 0; 3300 3301 card->tst_index = 0; 3302 writel(card->tst[0] << 2, SAR_REG_TSTB); 3303 3304 /* Initialize ABRSTD and Receive FIFO */ 3305 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3306 writel(card->abrst_size | (card->abrst_base << 2), 3307 SAR_REG_ABRSTD); 3308 3309 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3310 writel(card->fifo_size | (card->fifo_base << 2), 3311 SAR_REG_RXFD); 3312 3313 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3314 return 0; 3315 } 3316 3317 static int __devinit 3318 init_card(struct atm_dev *dev) 3319 { 3320 struct idt77252_dev *card = dev->dev_data; 3321 struct pci_dev *pcidev = card->pcidev; 3322 unsigned long tmpl, modl; 3323 unsigned int linkrate, rsvdcr; 3324 unsigned int tst_entries; 3325 struct net_device *tmp; 3326 char tname[10]; 3327 3328 u32 size; 3329 u_char pci_byte; 3330 u32 conf; 3331 int i, k; 3332 3333 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3334 printk("Error: SAR already initialized.\n"); 3335 return -1; 3336 } 3337 3338 /*****************************************************************/ 3339 /* P C I C O N F I G U R A T I O N */ 3340 /*****************************************************************/ 3341 3342 /* Set PCI Retry-Timeout and TRDY timeout */ 3343 IPRINTK("%s: Checking PCI retries.\n", card->name); 3344 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3345 printk("%s: can't read PCI retry timeout.\n", card->name); 3346 deinit_card(card); 3347 return -1; 3348 } 3349 if (pci_byte != 0) { 3350 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3351 card->name, pci_byte); 3352 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3353 printk("%s: can't set PCI retry timeout.\n", 3354 card->name); 3355 deinit_card(card); 3356 return -1; 3357 } 3358 } 3359 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3360 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3361 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3362 deinit_card(card); 3363 return -1; 3364 } 3365 if (pci_byte != 0) { 3366 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3367 card->name, pci_byte); 3368 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3369 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3370 deinit_card(card); 3371 return -1; 3372 } 3373 } 3374 /* Reset Timer register */ 3375 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3376 printk("%s: resetting timer overflow.\n", card->name); 3377 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3378 } 3379 IPRINTK("%s: Request IRQ ... ", card->name); 3380 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3381 card->name, card) != 0) { 3382 printk("%s: can't allocate IRQ.\n", card->name); 3383 deinit_card(card); 3384 return -1; 3385 } 3386 IPRINTK("got %d.\n", pcidev->irq); 3387 3388 /*****************************************************************/ 3389 /* C H E C K A N D I N I T S R A M */ 3390 /*****************************************************************/ 3391 3392 IPRINTK("%s: Initializing SRAM\n", card->name); 3393 3394 /* preset size of connecton table, so that init_sram() knows about it */ 3395 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3396 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3397 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3398 #ifndef ATM_IDT77252_SEND_IDLE 3399 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3400 #endif 3401 0; 3402 3403 if (card->sramsize == (512 * 1024)) 3404 conf |= SAR_CFG_CNTBL_1k; 3405 else 3406 conf |= SAR_CFG_CNTBL_512; 3407 3408 switch (vpibits) { 3409 case 0: 3410 conf |= SAR_CFG_VPVCS_0; 3411 break; 3412 default: 3413 case 1: 3414 conf |= SAR_CFG_VPVCS_1; 3415 break; 3416 case 2: 3417 conf |= SAR_CFG_VPVCS_2; 3418 break; 3419 case 8: 3420 conf |= SAR_CFG_VPVCS_8; 3421 break; 3422 } 3423 3424 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3425 3426 if (init_sram(card) < 0) 3427 return -1; 3428 3429 /********************************************************************/ 3430 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3431 /********************************************************************/ 3432 /* Initialize TSQ */ 3433 if (0 != init_tsq(card)) { 3434 deinit_card(card); 3435 return -1; 3436 } 3437 /* Initialize RSQ */ 3438 if (0 != init_rsq(card)) { 3439 deinit_card(card); 3440 return -1; 3441 } 3442 3443 card->vpibits = vpibits; 3444 if (card->sramsize == (512 * 1024)) { 3445 card->vcibits = 10 - card->vpibits; 3446 } else { 3447 card->vcibits = 9 - card->vpibits; 3448 } 3449 3450 card->vcimask = 0; 3451 for (k = 0, i = 1; k < card->vcibits; k++) { 3452 card->vcimask |= i; 3453 i <<= 1; 3454 } 3455 3456 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3457 writel(0, SAR_REG_VPM); 3458 3459 /* Little Endian Order */ 3460 writel(0, SAR_REG_GP); 3461 3462 /* Initialize RAW Cell Handle Register */ 3463 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3464 &card->raw_cell_paddr); 3465 if (!card->raw_cell_hnd) { 3466 printk("%s: memory allocation failure.\n", card->name); 3467 deinit_card(card); 3468 return -1; 3469 } 3470 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3471 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3472 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3473 card->raw_cell_hnd); 3474 3475 size = sizeof(struct vc_map *) * card->tct_size; 3476 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3477 if (NULL == (card->vcs = vmalloc(size))) { 3478 printk("%s: memory allocation failure.\n", card->name); 3479 deinit_card(card); 3480 return -1; 3481 } 3482 memset(card->vcs, 0, size); 3483 3484 size = sizeof(struct vc_map *) * card->scd_size; 3485 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3486 card->name, size); 3487 if (NULL == (card->scd2vc = vmalloc(size))) { 3488 printk("%s: memory allocation failure.\n", card->name); 3489 deinit_card(card); 3490 return -1; 3491 } 3492 memset(card->scd2vc, 0, size); 3493 3494 size = sizeof(struct tst_info) * (card->tst_size - 2); 3495 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3496 card->name, size); 3497 if (NULL == (card->soft_tst = vmalloc(size))) { 3498 printk("%s: memory allocation failure.\n", card->name); 3499 deinit_card(card); 3500 return -1; 3501 } 3502 for (i = 0; i < card->tst_size - 2; i++) { 3503 card->soft_tst[i].tste = TSTE_OPC_VAR; 3504 card->soft_tst[i].vc = NULL; 3505 } 3506 3507 if (dev->phy == NULL) { 3508 printk("%s: No LT device defined.\n", card->name); 3509 deinit_card(card); 3510 return -1; 3511 } 3512 if (dev->phy->ioctl == NULL) { 3513 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3514 deinit_card(card); 3515 return -1; 3516 } 3517 3518 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3519 /* 3520 * this is a jhs hack to get around special functionality in the 3521 * phy driver for the atecom hardware; the functionality doesn't 3522 * exist in the linux atm suni driver 3523 * 3524 * it isn't the right way to do things, but as the guy from NIST 3525 * said, talking about their measurement of the fine structure 3526 * constant, "it's good enough for government work." 3527 */ 3528 linkrate = 149760000; 3529 #endif 3530 3531 card->link_pcr = (linkrate / 8 / 53); 3532 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3533 card->name, linkrate, card->link_pcr); 3534 3535 #ifdef ATM_IDT77252_SEND_IDLE 3536 card->utopia_pcr = card->link_pcr; 3537 #else 3538 card->utopia_pcr = (160000000 / 8 / 54); 3539 #endif 3540 3541 rsvdcr = 0; 3542 if (card->utopia_pcr > card->link_pcr) 3543 rsvdcr = card->utopia_pcr - card->link_pcr; 3544 3545 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3546 modl = tmpl % (unsigned long)card->utopia_pcr; 3547 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3548 if (modl) 3549 tst_entries++; 3550 card->tst_free -= tst_entries; 3551 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3552 3553 #ifdef HAVE_EEPROM 3554 idt77252_eeprom_init(card); 3555 printk("%s: EEPROM: %02x:", card->name, 3556 idt77252_eeprom_read_status(card)); 3557 3558 for (i = 0; i < 0x80; i++) { 3559 printk(" %02x", 3560 idt77252_eeprom_read_byte(card, i) 3561 ); 3562 } 3563 printk("\n"); 3564 #endif /* HAVE_EEPROM */ 3565 3566 /* 3567 * XXX: <hack> 3568 */ 3569 sprintf(tname, "eth%d", card->index); 3570 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3571 if (tmp) { 3572 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3573 3574 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3575 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3576 card->atmdev->esi[2], card->atmdev->esi[3], 3577 card->atmdev->esi[4], card->atmdev->esi[5]); 3578 } 3579 /* 3580 * XXX: </hack> 3581 */ 3582 3583 /* Set Maximum Deficit Count for now. */ 3584 writel(0xffff, SAR_REG_MDFCT); 3585 3586 set_bit(IDT77252_BIT_INIT, &card->flags); 3587 3588 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3589 return 0; 3590 } 3591 3592 3593 /*****************************************************************************/ 3594 /* */ 3595 /* Probing of IDT77252 ABR SAR */ 3596 /* */ 3597 /*****************************************************************************/ 3598 3599 3600 static int __devinit 3601 idt77252_preset(struct idt77252_dev *card) 3602 { 3603 u16 pci_command; 3604 3605 /*****************************************************************/ 3606 /* P C I C O N F I G U R A T I O N */ 3607 /*****************************************************************/ 3608 3609 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3610 card->name); 3611 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3612 printk("%s: can't read PCI_COMMAND.\n", card->name); 3613 deinit_card(card); 3614 return -1; 3615 } 3616 if (!(pci_command & PCI_COMMAND_IO)) { 3617 printk("%s: PCI_COMMAND: %04x (???)\n", 3618 card->name, pci_command); 3619 deinit_card(card); 3620 return (-1); 3621 } 3622 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3623 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3624 printk("%s: can't write PCI_COMMAND.\n", card->name); 3625 deinit_card(card); 3626 return -1; 3627 } 3628 /*****************************************************************/ 3629 /* G E N E R I C R E S E T */ 3630 /*****************************************************************/ 3631 3632 /* Software reset */ 3633 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3634 mdelay(1); 3635 writel(0, SAR_REG_CFG); 3636 3637 IPRINTK("%s: Software resetted.\n", card->name); 3638 return 0; 3639 } 3640 3641 3642 static unsigned long __devinit 3643 probe_sram(struct idt77252_dev *card) 3644 { 3645 u32 data, addr; 3646 3647 writel(0, SAR_REG_DR0); 3648 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3649 3650 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3651 writel(ATM_POISON, SAR_REG_DR0); 3652 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3653 3654 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3655 data = readl(SAR_REG_DR0); 3656 3657 if (data != 0) 3658 break; 3659 } 3660 3661 return addr * sizeof(u32); 3662 } 3663 3664 static int __devinit 3665 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3666 { 3667 static struct idt77252_dev **last = &idt77252_chain; 3668 static int index = 0; 3669 3670 unsigned long membase, srambase; 3671 struct idt77252_dev *card; 3672 struct atm_dev *dev; 3673 int i, err; 3674 3675 3676 if ((err = pci_enable_device(pcidev))) { 3677 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3678 return err; 3679 } 3680 3681 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3682 if (!card) { 3683 printk("idt77252-%d: can't allocate private data\n", index); 3684 err = -ENOMEM; 3685 goto err_out_disable_pdev; 3686 } 3687 card->revision = pcidev->revision; 3688 card->index = index; 3689 card->pcidev = pcidev; 3690 sprintf(card->name, "idt77252-%d", card->index); 3691 3692 INIT_WORK(&card->tqueue, idt77252_softint); 3693 3694 membase = pci_resource_start(pcidev, 1); 3695 srambase = pci_resource_start(pcidev, 2); 3696 3697 mutex_init(&card->mutex); 3698 spin_lock_init(&card->cmd_lock); 3699 spin_lock_init(&card->tst_lock); 3700 3701 init_timer(&card->tst_timer); 3702 card->tst_timer.data = (unsigned long)card; 3703 card->tst_timer.function = tst_timer; 3704 3705 /* Do the I/O remapping... */ 3706 card->membase = ioremap(membase, 1024); 3707 if (!card->membase) { 3708 printk("%s: can't ioremap() membase\n", card->name); 3709 err = -EIO; 3710 goto err_out_free_card; 3711 } 3712 3713 if (idt77252_preset(card)) { 3714 printk("%s: preset failed\n", card->name); 3715 err = -EIO; 3716 goto err_out_iounmap; 3717 } 3718 3719 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3720 if (!dev) { 3721 printk("%s: can't register atm device\n", card->name); 3722 err = -EIO; 3723 goto err_out_iounmap; 3724 } 3725 dev->dev_data = card; 3726 card->atmdev = dev; 3727 3728 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3729 suni_init(dev); 3730 if (!dev->phy) { 3731 printk("%s: can't init SUNI\n", card->name); 3732 err = -EIO; 3733 goto err_out_deinit_card; 3734 } 3735 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3736 3737 card->sramsize = probe_sram(card); 3738 3739 for (i = 0; i < 4; i++) { 3740 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3741 if (!card->fbq[i]) { 3742 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3743 err = -EIO; 3744 goto err_out_deinit_card; 3745 } 3746 } 3747 3748 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3749 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3750 'A' + card->revision - 1 : '?', membase, srambase, 3751 card->sramsize / 1024); 3752 3753 if (init_card(dev)) { 3754 printk("%s: init_card failed\n", card->name); 3755 err = -EIO; 3756 goto err_out_deinit_card; 3757 } 3758 3759 dev->ci_range.vpi_bits = card->vpibits; 3760 dev->ci_range.vci_bits = card->vcibits; 3761 dev->link_rate = card->link_pcr; 3762 3763 if (dev->phy->start) 3764 dev->phy->start(dev); 3765 3766 if (idt77252_dev_open(card)) { 3767 printk("%s: dev_open failed\n", card->name); 3768 err = -EIO; 3769 goto err_out_stop; 3770 } 3771 3772 *last = card; 3773 last = &card->next; 3774 index++; 3775 3776 return 0; 3777 3778 err_out_stop: 3779 if (dev->phy->stop) 3780 dev->phy->stop(dev); 3781 3782 err_out_deinit_card: 3783 deinit_card(card); 3784 3785 err_out_iounmap: 3786 iounmap(card->membase); 3787 3788 err_out_free_card: 3789 kfree(card); 3790 3791 err_out_disable_pdev: 3792 pci_disable_device(pcidev); 3793 return err; 3794 } 3795 3796 static struct pci_device_id idt77252_pci_tbl[] = 3797 { 3798 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3800 { 0, } 3801 }; 3802 3803 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3804 3805 static struct pci_driver idt77252_driver = { 3806 .name = "idt77252", 3807 .id_table = idt77252_pci_tbl, 3808 .probe = idt77252_init_one, 3809 }; 3810 3811 static int __init idt77252_init(void) 3812 { 3813 struct sk_buff *skb; 3814 3815 printk("%s: at %p\n", __func__, idt77252_init); 3816 3817 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3818 sizeof(struct idt77252_skb_prv)) { 3819 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3820 __func__, (unsigned long) sizeof(skb->cb), 3821 (unsigned long) sizeof(struct atm_skb_data) + 3822 sizeof(struct idt77252_skb_prv)); 3823 return -EIO; 3824 } 3825 3826 return pci_register_driver(&idt77252_driver); 3827 } 3828 3829 static void __exit idt77252_exit(void) 3830 { 3831 struct idt77252_dev *card; 3832 struct atm_dev *dev; 3833 3834 pci_unregister_driver(&idt77252_driver); 3835 3836 while (idt77252_chain) { 3837 card = idt77252_chain; 3838 dev = card->atmdev; 3839 idt77252_chain = card->next; 3840 3841 if (dev->phy->stop) 3842 dev->phy->stop(dev); 3843 deinit_card(card); 3844 pci_disable_device(card->pcidev); 3845 kfree(card); 3846 } 3847 3848 DIPRINTK("idt77252: finished cleanup-module().\n"); 3849 } 3850 3851 module_init(idt77252_init); 3852 module_exit(idt77252_exit); 3853 3854 MODULE_LICENSE("GPL"); 3855 3856 module_param(vpibits, uint, 0); 3857 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3858 #ifdef CONFIG_ATM_IDT77252_DEBUG 3859 module_param(debug, ulong, 0644); 3860 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3861 #endif 3862 3863 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3864 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3865