1 /* 2 * AppliedMicro X-Gene SoC SATA Host Controller Driver 3 * 4 * Copyright (c) 2014, Applied Micro Circuits Corporation 5 * Author: Loc Ho <lho@apm.com> 6 * Tuan Phan <tphan@apm.com> 7 * Suman Tripathi <stripathi@apm.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 * NOTE: PM support is not currently available. 23 * 24 */ 25 #include <linux/module.h> 26 #include <linux/platform_device.h> 27 #include <linux/ahci_platform.h> 28 #include <linux/of_address.h> 29 #include <linux/of_irq.h> 30 #include <linux/phy/phy.h> 31 #include "ahci.h" 32 33 /* Max # of disk per a controller */ 34 #define MAX_AHCI_CHN_PERCTR 2 35 36 /* MUX CSR */ 37 #define SATA_ENET_CONFIG_REG 0x00000000 38 #define CFG_SATA_ENET_SELECT_MASK 0x00000001 39 40 /* SATA core host controller CSR */ 41 #define SLVRDERRATTRIBUTES 0x00000000 42 #define SLVWRERRATTRIBUTES 0x00000004 43 #define MSTRDERRATTRIBUTES 0x00000008 44 #define MSTWRERRATTRIBUTES 0x0000000c 45 #define BUSCTLREG 0x00000014 46 #define IOFMSTRWAUX 0x00000018 47 #define INTSTATUSMASK 0x0000002c 48 #define ERRINTSTATUS 0x00000030 49 #define ERRINTSTATUSMASK 0x00000034 50 51 /* SATA host AHCI CSR */ 52 #define PORTCFG 0x000000a4 53 #define PORTADDR_SET(dst, src) \ 54 (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f)) 55 #define PORTPHY1CFG 0x000000a8 56 #define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \ 57 (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000)) 58 #define PORTPHY2CFG 0x000000ac 59 #define PORTPHY3CFG 0x000000b0 60 #define PORTPHY4CFG 0x000000b4 61 #define PORTPHY5CFG 0x000000b8 62 #define SCTL0 0x0000012C 63 #define PORTPHY5CFG_RTCHG_SET(dst, src) \ 64 (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000)) 65 #define PORTAXICFG_EN_CONTEXT_SET(dst, src) \ 66 (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000)) 67 #define PORTAXICFG 0x000000bc 68 #define PORTAXICFG_OUTTRANS_SET(dst, src) \ 69 (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000)) 70 #define PORTRANSCFG 0x000000c8 71 #define PORTRANSCFG_RXWM_SET(dst, src) \ 72 (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f)) 73 74 /* SATA host controller AXI CSR */ 75 #define INT_SLV_TMOMASK 0x00000010 76 77 /* SATA diagnostic CSR */ 78 #define CFG_MEM_RAM_SHUTDOWN 0x00000070 79 #define BLOCK_MEM_RDY 0x00000074 80 81 struct xgene_ahci_context { 82 struct ahci_host_priv *hpriv; 83 struct device *dev; 84 u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/ 85 void __iomem *csr_core; /* Core CSR address of IP */ 86 void __iomem *csr_diag; /* Diag CSR address of IP */ 87 void __iomem *csr_axi; /* AXI CSR address of IP */ 88 void __iomem *csr_mux; /* MUX CSR address of IP */ 89 }; 90 91 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx) 92 { 93 dev_dbg(ctx->dev, "Release memory from shutdown\n"); 94 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); 95 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ 96 msleep(1); /* reset may take up to 1ms */ 97 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { 98 dev_err(ctx->dev, "failed to release memory from shutdown\n"); 99 return -ENODEV; 100 } 101 return 0; 102 } 103 104 /** 105 * xgene_ahci_restart_engine - Restart the dma engine. 106 * @ap : ATA port of interest 107 * 108 * Restarts the dma engine inside the controller. 109 */ 110 static int xgene_ahci_restart_engine(struct ata_port *ap) 111 { 112 struct ahci_host_priv *hpriv = ap->host->private_data; 113 114 ahci_stop_engine(ap); 115 ahci_start_fis_rx(ap); 116 hpriv->start_engine(ap); 117 118 return 0; 119 } 120 121 /** 122 * xgene_ahci_qc_issue - Issue commands to the device 123 * @qc: Command to issue 124 * 125 * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot 126 * clear the BSY bit after receiving the PIO setup FIS. This results in the dma 127 * state machine goes into the CMFatalErrorUpdate state and locks up. By 128 * restarting the dma engine, it removes the controller out of lock up state. 129 */ 130 static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc) 131 { 132 struct ata_port *ap = qc->ap; 133 struct ahci_host_priv *hpriv = ap->host->private_data; 134 struct xgene_ahci_context *ctx = hpriv->plat_data; 135 int rc = 0; 136 137 if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA)) 138 xgene_ahci_restart_engine(ap); 139 140 rc = ahci_qc_issue(qc); 141 142 /* Save the last command issued */ 143 ctx->last_cmd[ap->port_no] = qc->tf.command; 144 145 return rc; 146 } 147 148 /** 149 * xgene_ahci_read_id - Read ID data from the specified device 150 * @dev: device 151 * @tf: proposed taskfile 152 * @id: data buffer 153 * 154 * This custom read ID function is required due to the fact that the HW 155 * does not support DEVSLP. 156 */ 157 static unsigned int xgene_ahci_read_id(struct ata_device *dev, 158 struct ata_taskfile *tf, u16 *id) 159 { 160 u32 err_mask; 161 162 err_mask = ata_do_dev_read_id(dev, tf, id); 163 if (err_mask) 164 return err_mask; 165 166 /* 167 * Mask reserved area. Word78 spec of Link Power Management 168 * bit15-8: reserved 169 * bit7: NCQ autosence 170 * bit6: Software settings preservation supported 171 * bit5: reserved 172 * bit4: In-order sata delivery supported 173 * bit3: DIPM requests supported 174 * bit2: DMA Setup FIS Auto-Activate optimization supported 175 * bit1: DMA Setup FIX non-Zero buffer offsets supported 176 * bit0: Reserved 177 * 178 * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP 179 */ 180 id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8); 181 182 return 0; 183 } 184 185 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel) 186 { 187 void __iomem *mmio = ctx->hpriv->mmio; 188 u32 val; 189 190 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n", 191 mmio, channel); 192 val = readl(mmio + PORTCFG); 193 val = PORTADDR_SET(val, channel == 0 ? 2 : 3); 194 writel(val, mmio + PORTCFG); 195 readl(mmio + PORTCFG); /* Force a barrier */ 196 /* Disable fix rate */ 197 writel(0x0001fffe, mmio + PORTPHY1CFG); 198 readl(mmio + PORTPHY1CFG); /* Force a barrier */ 199 writel(0x28183219, mmio + PORTPHY2CFG); 200 readl(mmio + PORTPHY2CFG); /* Force a barrier */ 201 writel(0x13081008, mmio + PORTPHY3CFG); 202 readl(mmio + PORTPHY3CFG); /* Force a barrier */ 203 writel(0x00480815, mmio + PORTPHY4CFG); 204 readl(mmio + PORTPHY4CFG); /* Force a barrier */ 205 /* Set window negotiation */ 206 val = readl(mmio + PORTPHY5CFG); 207 val = PORTPHY5CFG_RTCHG_SET(val, 0x300); 208 writel(val, mmio + PORTPHY5CFG); 209 readl(mmio + PORTPHY5CFG); /* Force a barrier */ 210 val = readl(mmio + PORTAXICFG); 211 val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */ 212 val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */ 213 writel(val, mmio + PORTAXICFG); 214 readl(mmio + PORTAXICFG); /* Force a barrier */ 215 /* Set the watermark threshold of the receive FIFO */ 216 val = readl(mmio + PORTRANSCFG); 217 val = PORTRANSCFG_RXWM_SET(val, 0x30); 218 writel(val, mmio + PORTRANSCFG); 219 } 220 221 /** 222 * xgene_ahci_do_hardreset - Issue the actual COMRESET 223 * @link: link to reset 224 * @deadline: deadline jiffies for the operation 225 * @online: Return value to indicate if device online 226 * 227 * Due to the limitation of the hardware PHY, a difference set of setting is 228 * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps), 229 * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will 230 * report disparity error and etc. In addition, during COMRESET, there can 231 * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and 232 * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following 233 * algorithm is followed to proper configure the hardware PHY during COMRESET: 234 * 235 * Alg Part 1: 236 * 1. Start the PHY at Gen3 speed (default setting) 237 * 2. Issue the COMRESET 238 * 3. If no link, go to Alg Part 3 239 * 4. If link up, determine if the negotiated speed matches the PHY 240 * configured speed 241 * 5. If they matched, go to Alg Part 2 242 * 6. If they do not matched and first time, configure the PHY for the linked 243 * up disk speed and repeat step 2 244 * 7. Go to Alg Part 2 245 * 246 * Alg Part 2: 247 * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error 248 * reported in the register PORT_SCR_ERR, then reset the PHY receiver line 249 * 2. Go to Alg Part 3 250 * 251 * Alg Part 3: 252 * 1. Clear any pending from register PORT_SCR_ERR. 253 * 254 * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition 255 * and until the underlying PHY supports an method to reset the receiver 256 * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors, 257 * an warning message will be printed. 258 */ 259 static int xgene_ahci_do_hardreset(struct ata_link *link, 260 unsigned long deadline, bool *online) 261 { 262 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); 263 struct ata_port *ap = link->ap; 264 struct ahci_host_priv *hpriv = ap->host->private_data; 265 struct xgene_ahci_context *ctx = hpriv->plat_data; 266 struct ahci_port_priv *pp = ap->private_data; 267 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 268 void __iomem *port_mmio = ahci_port_base(ap); 269 struct ata_taskfile tf; 270 int rc; 271 u32 val; 272 273 /* clear D2H reception area to properly wait for D2H FIS */ 274 ata_tf_init(link->device, &tf); 275 tf.command = ATA_BUSY; 276 ata_tf_to_fis(&tf, 0, 0, d2h_fis); 277 rc = sata_link_hardreset(link, timing, deadline, online, 278 ahci_check_ready); 279 280 val = readl(port_mmio + PORT_SCR_ERR); 281 if (val & (SERR_DISPARITY | SERR_10B_8B_ERR)) 282 dev_warn(ctx->dev, "link has error\n"); 283 284 /* clear all errors if any pending */ 285 val = readl(port_mmio + PORT_SCR_ERR); 286 writel(val, port_mmio + PORT_SCR_ERR); 287 288 return rc; 289 } 290 291 static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class, 292 unsigned long deadline) 293 { 294 struct ata_port *ap = link->ap; 295 struct ahci_host_priv *hpriv = ap->host->private_data; 296 void __iomem *port_mmio = ahci_port_base(ap); 297 bool online; 298 int rc; 299 u32 portcmd_saved; 300 u32 portclb_saved; 301 u32 portclbhi_saved; 302 u32 portrxfis_saved; 303 u32 portrxfishi_saved; 304 305 /* As hardreset resets these CSR, save it to restore later */ 306 portcmd_saved = readl(port_mmio + PORT_CMD); 307 portclb_saved = readl(port_mmio + PORT_LST_ADDR); 308 portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI); 309 portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR); 310 portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI); 311 312 ahci_stop_engine(ap); 313 314 rc = xgene_ahci_do_hardreset(link, deadline, &online); 315 316 /* As controller hardreset clears them, restore them */ 317 writel(portcmd_saved, port_mmio + PORT_CMD); 318 writel(portclb_saved, port_mmio + PORT_LST_ADDR); 319 writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI); 320 writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR); 321 writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI); 322 323 hpriv->start_engine(ap); 324 325 if (online) 326 *class = ahci_dev_classify(ap); 327 328 return rc; 329 } 330 331 static void xgene_ahci_host_stop(struct ata_host *host) 332 { 333 struct ahci_host_priv *hpriv = host->private_data; 334 335 ahci_platform_disable_resources(hpriv); 336 } 337 338 static struct ata_port_operations xgene_ahci_ops = { 339 .inherits = &ahci_ops, 340 .host_stop = xgene_ahci_host_stop, 341 .hardreset = xgene_ahci_hardreset, 342 .read_id = xgene_ahci_read_id, 343 .qc_issue = xgene_ahci_qc_issue, 344 }; 345 346 static const struct ata_port_info xgene_ahci_port_info = { 347 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, 348 .pio_mask = ATA_PIO4, 349 .udma_mask = ATA_UDMA6, 350 .port_ops = &xgene_ahci_ops, 351 }; 352 353 static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv) 354 { 355 struct xgene_ahci_context *ctx = hpriv->plat_data; 356 int i; 357 int rc; 358 u32 val; 359 360 /* Remove IP RAM out of shutdown */ 361 rc = xgene_ahci_init_memram(ctx); 362 if (rc) 363 return rc; 364 365 for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++) 366 xgene_ahci_set_phy_cfg(ctx, i); 367 368 /* AXI disable Mask */ 369 writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT); 370 readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */ 371 writel(0, ctx->csr_core + INTSTATUSMASK); 372 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */ 373 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n", 374 INTSTATUSMASK, val); 375 376 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK); 377 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */ 378 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK); 379 readl(ctx->csr_axi + INT_SLV_TMOMASK); 380 381 /* Enable AXI Interrupt */ 382 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES); 383 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES); 384 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES); 385 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES); 386 387 /* Enable coherency */ 388 val = readl(ctx->csr_core + BUSCTLREG); 389 val &= ~0x00000002; /* Enable write coherency */ 390 val &= ~0x00000001; /* Enable read coherency */ 391 writel(val, ctx->csr_core + BUSCTLREG); 392 393 val = readl(ctx->csr_core + IOFMSTRWAUX); 394 val |= (1 << 3); /* Enable read coherency */ 395 val |= (1 << 9); /* Enable write coherency */ 396 writel(val, ctx->csr_core + IOFMSTRWAUX); 397 val = readl(ctx->csr_core + IOFMSTRWAUX); 398 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n", 399 IOFMSTRWAUX, val); 400 401 return rc; 402 } 403 404 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx) 405 { 406 u32 val; 407 408 /* Check for optional MUX resource */ 409 if (IS_ERR(ctx->csr_mux)) 410 return 0; 411 412 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); 413 val &= ~CFG_SATA_ENET_SELECT_MASK; 414 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG); 415 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG); 416 return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0; 417 } 418 419 static int xgene_ahci_probe(struct platform_device *pdev) 420 { 421 struct device *dev = &pdev->dev; 422 struct ahci_host_priv *hpriv; 423 struct xgene_ahci_context *ctx; 424 struct resource *res; 425 int rc; 426 427 hpriv = ahci_platform_get_resources(pdev); 428 if (IS_ERR(hpriv)) 429 return PTR_ERR(hpriv); 430 431 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 432 if (!ctx) 433 return -ENOMEM; 434 435 hpriv->plat_data = ctx; 436 ctx->hpriv = hpriv; 437 ctx->dev = dev; 438 439 /* Retrieve the IP core resource */ 440 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 441 ctx->csr_core = devm_ioremap_resource(dev, res); 442 if (IS_ERR(ctx->csr_core)) 443 return PTR_ERR(ctx->csr_core); 444 445 /* Retrieve the IP diagnostic resource */ 446 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 447 ctx->csr_diag = devm_ioremap_resource(dev, res); 448 if (IS_ERR(ctx->csr_diag)) 449 return PTR_ERR(ctx->csr_diag); 450 451 /* Retrieve the IP AXI resource */ 452 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 453 ctx->csr_axi = devm_ioremap_resource(dev, res); 454 if (IS_ERR(ctx->csr_axi)) 455 return PTR_ERR(ctx->csr_axi); 456 457 /* Retrieve the optional IP mux resource */ 458 res = platform_get_resource(pdev, IORESOURCE_MEM, 4); 459 ctx->csr_mux = devm_ioremap_resource(dev, res); 460 461 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core, 462 hpriv->mmio); 463 464 /* Select ATA */ 465 if ((rc = xgene_ahci_mux_select(ctx))) { 466 dev_err(dev, "SATA mux selection failed error %d\n", rc); 467 return -ENODEV; 468 } 469 470 /* Due to errata, HW requires full toggle transition */ 471 rc = ahci_platform_enable_clks(hpriv); 472 if (rc) 473 goto disable_resources; 474 ahci_platform_disable_clks(hpriv); 475 476 rc = ahci_platform_enable_resources(hpriv); 477 if (rc) 478 goto disable_resources; 479 480 /* Configure the host controller */ 481 xgene_ahci_hw_init(hpriv); 482 483 hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ; 484 485 rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info); 486 if (rc) 487 goto disable_resources; 488 489 dev_dbg(dev, "X-Gene SATA host controller initialized\n"); 490 return 0; 491 492 disable_resources: 493 ahci_platform_disable_resources(hpriv); 494 return rc; 495 } 496 497 static const struct of_device_id xgene_ahci_of_match[] = { 498 {.compatible = "apm,xgene-ahci"}, 499 {}, 500 }; 501 MODULE_DEVICE_TABLE(of, xgene_ahci_of_match); 502 503 static struct platform_driver xgene_ahci_driver = { 504 .probe = xgene_ahci_probe, 505 .remove = ata_platform_remove_one, 506 .driver = { 507 .name = "xgene-ahci", 508 .owner = THIS_MODULE, 509 .of_match_table = xgene_ahci_of_match, 510 }, 511 }; 512 513 module_platform_driver(xgene_ahci_driver); 514 515 MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver"); 516 MODULE_AUTHOR("Loc Ho <lho@apm.com>"); 517 MODULE_LICENSE("GPL"); 518 MODULE_VERSION("0.4"); 519