1 // SPDX-License-Identifier: GPL-2.0
2 
3 /*
4  * Copyright 2016-2022 HabanaLabs, Ltd.
5  * All Rights Reserved.
6  */
7 
8 #include "goyaP.h"
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
11 #include "../include/goya/asic_reg/goya_masks.h"
12 #include "../include/goya/goya_reg_map.h"
13 
14 #include <linux/pci.h>
15 #include <linux/hwmon.h>
16 #include <linux/iommu.h>
17 #include <linux/seq_file.h>
18 
19 /*
20  * GOYA security scheme:
21  *
22  * 1. Host is protected by:
23  *        - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24  *        - MMU
25  *
26  * 2. DRAM is protected by:
27  *        - Range registers (protect the first 512MB)
28  *        - MMU (isolation between users)
29  *
30  * 3. Configuration is protected by:
31  *        - Range registers
32  *        - Protection bits
33  *
34  * When MMU is disabled:
35  *
36  * QMAN DMA: PQ, CQ, CP, DMA are secured.
37  * PQ, CB and the data are on the host.
38  *
39  * QMAN TPC/MME:
40  * PQ, CQ and CP are not secured.
41  * PQ, CB and the data are on the SRAM/DRAM.
42  *
43  * Since QMAN DMA is secured, the driver is parsing the DMA CB:
44  *     - checks DMA pointer
45  *     - WREG, MSG_PROT are not allowed.
46  *     - MSG_LONG/SHORT are allowed.
47  *
48  * A read/write transaction by the QMAN to a protected area will succeed if
49  * and only if the QMAN's CP is secured and MSG_PROT is used
50  *
51  *
52  * When MMU is enabled:
53  *
54  * QMAN DMA: PQ, CQ and CP are secured.
55  * MMU is set to bypass on the Secure props register of the QMAN.
56  * The reasons we don't enable MMU for PQ, CQ and CP are:
57  *     - PQ entry is in kernel address space and the driver doesn't map it.
58  *     - CP writes to MSIX register and to kernel address space (completion
59  *       queue).
60  *
61  * DMA is not secured but because CP is secured, the driver still needs to parse
62  * the CB, but doesn't need to check the DMA addresses.
63  *
64  * For QMAN DMA 0, DMA is also secured because only the driver uses this DMA and
65  * the driver doesn't map memory in MMU.
66  *
67  * QMAN TPC/MME: PQ, CQ and CP aren't secured (no change from MMU disabled mode)
68  *
69  * DMA RR does NOT protect host because DMA is not secured
70  *
71  */
72 
73 #define GOYA_BOOT_FIT_FILE	"habanalabs/goya/goya-boot-fit.itb"
74 #define GOYA_LINUX_FW_FILE	"habanalabs/goya/goya-fit.itb"
75 
76 #define GOYA_MMU_REGS_NUM		63
77 
78 #define GOYA_DMA_POOL_BLK_SIZE		0x100		/* 256 bytes */
79 
80 #define GOYA_RESET_TIMEOUT_MSEC		500		/* 500ms */
81 #define GOYA_PLDM_RESET_TIMEOUT_MSEC	20000		/* 20s */
82 #define GOYA_RESET_WAIT_MSEC		1		/* 1ms */
83 #define GOYA_CPU_RESET_WAIT_MSEC	100		/* 100ms */
84 #define GOYA_PLDM_RESET_WAIT_MSEC	1000		/* 1s */
85 #define GOYA_TEST_QUEUE_WAIT_USEC	100000		/* 100ms */
86 #define GOYA_PLDM_MMU_TIMEOUT_USEC	(MMU_CONFIG_TIMEOUT_USEC * 100)
87 #define GOYA_PLDM_QMAN0_TIMEOUT_USEC	(HL_DEVICE_TIMEOUT_USEC * 30)
88 #define GOYA_BOOT_FIT_REQ_TIMEOUT_USEC	1000000		/* 1s */
89 #define GOYA_MSG_TO_CPU_TIMEOUT_USEC	4000000		/* 4s */
90 #define GOYA_WAIT_FOR_BL_TIMEOUT_USEC	15000000	/* 15s */
91 
92 #define GOYA_QMAN0_FENCE_VAL		0xD169B243
93 
94 #define GOYA_MAX_STRING_LEN		20
95 
96 #define GOYA_CB_POOL_CB_CNT		512
97 #define GOYA_CB_POOL_CB_SIZE		0x20000		/* 128KB */
98 
99 #define IS_QM_IDLE(engine, qm_glbl_sts0) \
100 	(((qm_glbl_sts0) & engine##_QM_IDLE_MASK) == engine##_QM_IDLE_MASK)
101 #define IS_DMA_QM_IDLE(qm_glbl_sts0)	IS_QM_IDLE(DMA, qm_glbl_sts0)
102 #define IS_TPC_QM_IDLE(qm_glbl_sts0)	IS_QM_IDLE(TPC, qm_glbl_sts0)
103 #define IS_MME_QM_IDLE(qm_glbl_sts0)	IS_QM_IDLE(MME, qm_glbl_sts0)
104 
105 #define IS_CMDQ_IDLE(engine, cmdq_glbl_sts0) \
106 	(((cmdq_glbl_sts0) & engine##_CMDQ_IDLE_MASK) == \
107 			engine##_CMDQ_IDLE_MASK)
108 #define IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) \
109 	IS_CMDQ_IDLE(TPC, cmdq_glbl_sts0)
110 #define IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) \
111 	IS_CMDQ_IDLE(MME, cmdq_glbl_sts0)
112 
113 #define IS_DMA_IDLE(dma_core_sts0) \
114 	!((dma_core_sts0) & DMA_CH_0_STS0_DMA_BUSY_MASK)
115 
116 #define IS_TPC_IDLE(tpc_cfg_sts) \
117 	(((tpc_cfg_sts) & TPC_CFG_IDLE_MASK) == TPC_CFG_IDLE_MASK)
118 
119 #define IS_MME_IDLE(mme_arch_sts) \
120 	(((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK)
121 
122 static const char goya_irq_name[GOYA_MSIX_ENTRIES][GOYA_MAX_STRING_LEN] = {
123 		"goya cq 0", "goya cq 1", "goya cq 2", "goya cq 3",
124 		"goya cq 4", "goya cpu eq"
125 };
126 
127 static u16 goya_packet_sizes[MAX_PACKET_ID] = {
128 	[PACKET_WREG_32]	= sizeof(struct packet_wreg32),
129 	[PACKET_WREG_BULK]	= sizeof(struct packet_wreg_bulk),
130 	[PACKET_MSG_LONG]	= sizeof(struct packet_msg_long),
131 	[PACKET_MSG_SHORT]	= sizeof(struct packet_msg_short),
132 	[PACKET_CP_DMA]		= sizeof(struct packet_cp_dma),
133 	[PACKET_MSG_PROT]	= sizeof(struct packet_msg_prot),
134 	[PACKET_FENCE]		= sizeof(struct packet_fence),
135 	[PACKET_LIN_DMA]	= sizeof(struct packet_lin_dma),
136 	[PACKET_NOP]		= sizeof(struct packet_nop),
137 	[PACKET_STOP]		= sizeof(struct packet_stop)
138 };
139 
140 static inline bool validate_packet_id(enum packet_id id)
141 {
142 	switch (id) {
143 	case PACKET_WREG_32:
144 	case PACKET_WREG_BULK:
145 	case PACKET_MSG_LONG:
146 	case PACKET_MSG_SHORT:
147 	case PACKET_CP_DMA:
148 	case PACKET_MSG_PROT:
149 	case PACKET_FENCE:
150 	case PACKET_LIN_DMA:
151 	case PACKET_NOP:
152 	case PACKET_STOP:
153 		return true;
154 	default:
155 		return false;
156 	}
157 }
158 
159 static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
160 	mmDMA_QM_0_GLBL_NON_SECURE_PROPS,
161 	mmDMA_QM_1_GLBL_NON_SECURE_PROPS,
162 	mmDMA_QM_2_GLBL_NON_SECURE_PROPS,
163 	mmDMA_QM_3_GLBL_NON_SECURE_PROPS,
164 	mmDMA_QM_4_GLBL_NON_SECURE_PROPS,
165 	mmTPC0_QM_GLBL_SECURE_PROPS,
166 	mmTPC0_QM_GLBL_NON_SECURE_PROPS,
167 	mmTPC0_CMDQ_GLBL_SECURE_PROPS,
168 	mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS,
169 	mmTPC0_CFG_ARUSER,
170 	mmTPC0_CFG_AWUSER,
171 	mmTPC1_QM_GLBL_SECURE_PROPS,
172 	mmTPC1_QM_GLBL_NON_SECURE_PROPS,
173 	mmTPC1_CMDQ_GLBL_SECURE_PROPS,
174 	mmTPC1_CMDQ_GLBL_NON_SECURE_PROPS,
175 	mmTPC1_CFG_ARUSER,
176 	mmTPC1_CFG_AWUSER,
177 	mmTPC2_QM_GLBL_SECURE_PROPS,
178 	mmTPC2_QM_GLBL_NON_SECURE_PROPS,
179 	mmTPC2_CMDQ_GLBL_SECURE_PROPS,
180 	mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS,
181 	mmTPC2_CFG_ARUSER,
182 	mmTPC2_CFG_AWUSER,
183 	mmTPC3_QM_GLBL_SECURE_PROPS,
184 	mmTPC3_QM_GLBL_NON_SECURE_PROPS,
185 	mmTPC3_CMDQ_GLBL_SECURE_PROPS,
186 	mmTPC3_CMDQ_GLBL_NON_SECURE_PROPS,
187 	mmTPC3_CFG_ARUSER,
188 	mmTPC3_CFG_AWUSER,
189 	mmTPC4_QM_GLBL_SECURE_PROPS,
190 	mmTPC4_QM_GLBL_NON_SECURE_PROPS,
191 	mmTPC4_CMDQ_GLBL_SECURE_PROPS,
192 	mmTPC4_CMDQ_GLBL_NON_SECURE_PROPS,
193 	mmTPC4_CFG_ARUSER,
194 	mmTPC4_CFG_AWUSER,
195 	mmTPC5_QM_GLBL_SECURE_PROPS,
196 	mmTPC5_QM_GLBL_NON_SECURE_PROPS,
197 	mmTPC5_CMDQ_GLBL_SECURE_PROPS,
198 	mmTPC5_CMDQ_GLBL_NON_SECURE_PROPS,
199 	mmTPC5_CFG_ARUSER,
200 	mmTPC5_CFG_AWUSER,
201 	mmTPC6_QM_GLBL_SECURE_PROPS,
202 	mmTPC6_QM_GLBL_NON_SECURE_PROPS,
203 	mmTPC6_CMDQ_GLBL_SECURE_PROPS,
204 	mmTPC6_CMDQ_GLBL_NON_SECURE_PROPS,
205 	mmTPC6_CFG_ARUSER,
206 	mmTPC6_CFG_AWUSER,
207 	mmTPC7_QM_GLBL_SECURE_PROPS,
208 	mmTPC7_QM_GLBL_NON_SECURE_PROPS,
209 	mmTPC7_CMDQ_GLBL_SECURE_PROPS,
210 	mmTPC7_CMDQ_GLBL_NON_SECURE_PROPS,
211 	mmTPC7_CFG_ARUSER,
212 	mmTPC7_CFG_AWUSER,
213 	mmMME_QM_GLBL_SECURE_PROPS,
214 	mmMME_QM_GLBL_NON_SECURE_PROPS,
215 	mmMME_CMDQ_GLBL_SECURE_PROPS,
216 	mmMME_CMDQ_GLBL_NON_SECURE_PROPS,
217 	mmMME_SBA_CONTROL_DATA,
218 	mmMME_SBB_CONTROL_DATA,
219 	mmMME_SBC_CONTROL_DATA,
220 	mmMME_WBC_CONTROL_DATA,
221 	mmPCIE_WRAP_PSOC_ARUSER,
222 	mmPCIE_WRAP_PSOC_AWUSER
223 };
224 
225 static u32 goya_all_events[] = {
226 	GOYA_ASYNC_EVENT_ID_PCIE_IF,
227 	GOYA_ASYNC_EVENT_ID_TPC0_ECC,
228 	GOYA_ASYNC_EVENT_ID_TPC1_ECC,
229 	GOYA_ASYNC_EVENT_ID_TPC2_ECC,
230 	GOYA_ASYNC_EVENT_ID_TPC3_ECC,
231 	GOYA_ASYNC_EVENT_ID_TPC4_ECC,
232 	GOYA_ASYNC_EVENT_ID_TPC5_ECC,
233 	GOYA_ASYNC_EVENT_ID_TPC6_ECC,
234 	GOYA_ASYNC_EVENT_ID_TPC7_ECC,
235 	GOYA_ASYNC_EVENT_ID_MME_ECC,
236 	GOYA_ASYNC_EVENT_ID_MME_ECC_EXT,
237 	GOYA_ASYNC_EVENT_ID_MMU_ECC,
238 	GOYA_ASYNC_EVENT_ID_DMA_MACRO,
239 	GOYA_ASYNC_EVENT_ID_DMA_ECC,
240 	GOYA_ASYNC_EVENT_ID_CPU_IF_ECC,
241 	GOYA_ASYNC_EVENT_ID_PSOC_MEM,
242 	GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT,
243 	GOYA_ASYNC_EVENT_ID_SRAM0,
244 	GOYA_ASYNC_EVENT_ID_SRAM1,
245 	GOYA_ASYNC_EVENT_ID_SRAM2,
246 	GOYA_ASYNC_EVENT_ID_SRAM3,
247 	GOYA_ASYNC_EVENT_ID_SRAM4,
248 	GOYA_ASYNC_EVENT_ID_SRAM5,
249 	GOYA_ASYNC_EVENT_ID_SRAM6,
250 	GOYA_ASYNC_EVENT_ID_SRAM7,
251 	GOYA_ASYNC_EVENT_ID_SRAM8,
252 	GOYA_ASYNC_EVENT_ID_SRAM9,
253 	GOYA_ASYNC_EVENT_ID_SRAM10,
254 	GOYA_ASYNC_EVENT_ID_SRAM11,
255 	GOYA_ASYNC_EVENT_ID_SRAM12,
256 	GOYA_ASYNC_EVENT_ID_SRAM13,
257 	GOYA_ASYNC_EVENT_ID_SRAM14,
258 	GOYA_ASYNC_EVENT_ID_SRAM15,
259 	GOYA_ASYNC_EVENT_ID_SRAM16,
260 	GOYA_ASYNC_EVENT_ID_SRAM17,
261 	GOYA_ASYNC_EVENT_ID_SRAM18,
262 	GOYA_ASYNC_EVENT_ID_SRAM19,
263 	GOYA_ASYNC_EVENT_ID_SRAM20,
264 	GOYA_ASYNC_EVENT_ID_SRAM21,
265 	GOYA_ASYNC_EVENT_ID_SRAM22,
266 	GOYA_ASYNC_EVENT_ID_SRAM23,
267 	GOYA_ASYNC_EVENT_ID_SRAM24,
268 	GOYA_ASYNC_EVENT_ID_SRAM25,
269 	GOYA_ASYNC_EVENT_ID_SRAM26,
270 	GOYA_ASYNC_EVENT_ID_SRAM27,
271 	GOYA_ASYNC_EVENT_ID_SRAM28,
272 	GOYA_ASYNC_EVENT_ID_SRAM29,
273 	GOYA_ASYNC_EVENT_ID_GIC500,
274 	GOYA_ASYNC_EVENT_ID_PLL0,
275 	GOYA_ASYNC_EVENT_ID_PLL1,
276 	GOYA_ASYNC_EVENT_ID_PLL3,
277 	GOYA_ASYNC_EVENT_ID_PLL4,
278 	GOYA_ASYNC_EVENT_ID_PLL5,
279 	GOYA_ASYNC_EVENT_ID_PLL6,
280 	GOYA_ASYNC_EVENT_ID_AXI_ECC,
281 	GOYA_ASYNC_EVENT_ID_L2_RAM_ECC,
282 	GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET,
283 	GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT,
284 	GOYA_ASYNC_EVENT_ID_PCIE_DEC,
285 	GOYA_ASYNC_EVENT_ID_TPC0_DEC,
286 	GOYA_ASYNC_EVENT_ID_TPC1_DEC,
287 	GOYA_ASYNC_EVENT_ID_TPC2_DEC,
288 	GOYA_ASYNC_EVENT_ID_TPC3_DEC,
289 	GOYA_ASYNC_EVENT_ID_TPC4_DEC,
290 	GOYA_ASYNC_EVENT_ID_TPC5_DEC,
291 	GOYA_ASYNC_EVENT_ID_TPC6_DEC,
292 	GOYA_ASYNC_EVENT_ID_TPC7_DEC,
293 	GOYA_ASYNC_EVENT_ID_MME_WACS,
294 	GOYA_ASYNC_EVENT_ID_MME_WACSD,
295 	GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER,
296 	GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC,
297 	GOYA_ASYNC_EVENT_ID_PSOC,
298 	GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR,
299 	GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR,
300 	GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR,
301 	GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR,
302 	GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR,
303 	GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR,
304 	GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR,
305 	GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR,
306 	GOYA_ASYNC_EVENT_ID_TPC0_CMDQ,
307 	GOYA_ASYNC_EVENT_ID_TPC1_CMDQ,
308 	GOYA_ASYNC_EVENT_ID_TPC2_CMDQ,
309 	GOYA_ASYNC_EVENT_ID_TPC3_CMDQ,
310 	GOYA_ASYNC_EVENT_ID_TPC4_CMDQ,
311 	GOYA_ASYNC_EVENT_ID_TPC5_CMDQ,
312 	GOYA_ASYNC_EVENT_ID_TPC6_CMDQ,
313 	GOYA_ASYNC_EVENT_ID_TPC7_CMDQ,
314 	GOYA_ASYNC_EVENT_ID_TPC0_QM,
315 	GOYA_ASYNC_EVENT_ID_TPC1_QM,
316 	GOYA_ASYNC_EVENT_ID_TPC2_QM,
317 	GOYA_ASYNC_EVENT_ID_TPC3_QM,
318 	GOYA_ASYNC_EVENT_ID_TPC4_QM,
319 	GOYA_ASYNC_EVENT_ID_TPC5_QM,
320 	GOYA_ASYNC_EVENT_ID_TPC6_QM,
321 	GOYA_ASYNC_EVENT_ID_TPC7_QM,
322 	GOYA_ASYNC_EVENT_ID_MME_QM,
323 	GOYA_ASYNC_EVENT_ID_MME_CMDQ,
324 	GOYA_ASYNC_EVENT_ID_DMA0_QM,
325 	GOYA_ASYNC_EVENT_ID_DMA1_QM,
326 	GOYA_ASYNC_EVENT_ID_DMA2_QM,
327 	GOYA_ASYNC_EVENT_ID_DMA3_QM,
328 	GOYA_ASYNC_EVENT_ID_DMA4_QM,
329 	GOYA_ASYNC_EVENT_ID_DMA0_CH,
330 	GOYA_ASYNC_EVENT_ID_DMA1_CH,
331 	GOYA_ASYNC_EVENT_ID_DMA2_CH,
332 	GOYA_ASYNC_EVENT_ID_DMA3_CH,
333 	GOYA_ASYNC_EVENT_ID_DMA4_CH,
334 	GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU,
335 	GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU,
336 	GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU,
337 	GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU,
338 	GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU,
339 	GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU,
340 	GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU,
341 	GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU,
342 	GOYA_ASYNC_EVENT_ID_DMA_BM_CH0,
343 	GOYA_ASYNC_EVENT_ID_DMA_BM_CH1,
344 	GOYA_ASYNC_EVENT_ID_DMA_BM_CH2,
345 	GOYA_ASYNC_EVENT_ID_DMA_BM_CH3,
346 	GOYA_ASYNC_EVENT_ID_DMA_BM_CH4,
347 	GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S,
348 	GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E,
349 	GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S,
350 	GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E
351 };
352 
353 static s64 goya_state_dump_specs_props[SP_MAX] = {0};
354 
355 static int goya_mmu_clear_pgt_range(struct hl_device *hdev);
356 static int goya_mmu_set_dram_default_page(struct hl_device *hdev);
357 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev);
358 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid);
359 
360 int goya_set_fixed_properties(struct hl_device *hdev)
361 {
362 	struct asic_fixed_properties *prop = &hdev->asic_prop;
363 	int i;
364 
365 	prop->max_queues = GOYA_QUEUE_ID_SIZE;
366 	prop->hw_queues_props = kcalloc(prop->max_queues,
367 			sizeof(struct hw_queue_properties),
368 			GFP_KERNEL);
369 
370 	if (!prop->hw_queues_props)
371 		return -ENOMEM;
372 
373 	for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
374 		prop->hw_queues_props[i].type = QUEUE_TYPE_EXT;
375 		prop->hw_queues_props[i].driver_only = 0;
376 		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
377 	}
378 
379 	for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES ; i++) {
380 		prop->hw_queues_props[i].type = QUEUE_TYPE_CPU;
381 		prop->hw_queues_props[i].driver_only = 1;
382 		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_KERNEL;
383 	}
384 
385 	for (; i < NUMBER_OF_EXT_HW_QUEUES + NUMBER_OF_CPU_HW_QUEUES +
386 			NUMBER_OF_INT_HW_QUEUES; i++) {
387 		prop->hw_queues_props[i].type = QUEUE_TYPE_INT;
388 		prop->hw_queues_props[i].driver_only = 0;
389 		prop->hw_queues_props[i].cb_alloc_flags = CB_ALLOC_USER;
390 	}
391 
392 	prop->cfg_base_address = CFG_BASE;
393 	prop->device_dma_offset_for_host_access = HOST_PHYS_BASE;
394 	prop->host_base_address = HOST_PHYS_BASE;
395 	prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE;
396 	prop->completion_queues_count = NUMBER_OF_CMPLT_QUEUES;
397 	prop->completion_mode = HL_COMPLETION_MODE_JOB;
398 	prop->dram_base_address = DRAM_PHYS_BASE;
399 	prop->dram_size = DRAM_PHYS_DEFAULT_SIZE;
400 	prop->dram_end_address = prop->dram_base_address + prop->dram_size;
401 	prop->dram_user_base_address = DRAM_BASE_ADDR_USER;
402 
403 	prop->sram_base_address = SRAM_BASE_ADDR;
404 	prop->sram_size = SRAM_SIZE;
405 	prop->sram_end_address = prop->sram_base_address + prop->sram_size;
406 	prop->sram_user_base_address = prop->sram_base_address +
407 						SRAM_USER_BASE_OFFSET;
408 
409 	prop->mmu_pgt_addr = MMU_PAGE_TABLES_ADDR;
410 	prop->mmu_dram_default_page_addr = MMU_DRAM_DEFAULT_PAGE_ADDR;
411 	if (hdev->pldm)
412 		prop->mmu_pgt_size = 0x800000; /* 8MB */
413 	else
414 		prop->mmu_pgt_size = MMU_PAGE_TABLES_SIZE;
415 	prop->mmu_pte_size = HL_PTE_SIZE;
416 	prop->mmu_hop_table_size = HOP_TABLE_SIZE_512_PTE;
417 	prop->mmu_hop0_tables_total_size = HOP0_512_PTE_TABLES_TOTAL_SIZE;
418 	prop->dram_page_size = PAGE_SIZE_2MB;
419 	prop->device_mem_alloc_default_page_size = prop->dram_page_size;
420 	prop->dram_supports_virtual_memory = true;
421 
422 	prop->dmmu.hop_shifts[MMU_HOP0] = MMU_V1_0_HOP0_SHIFT;
423 	prop->dmmu.hop_shifts[MMU_HOP1] = MMU_V1_0_HOP1_SHIFT;
424 	prop->dmmu.hop_shifts[MMU_HOP2] = MMU_V1_0_HOP2_SHIFT;
425 	prop->dmmu.hop_shifts[MMU_HOP3] = MMU_V1_0_HOP3_SHIFT;
426 	prop->dmmu.hop_shifts[MMU_HOP4] = MMU_V1_0_HOP4_SHIFT;
427 	prop->dmmu.hop_masks[MMU_HOP0] = MMU_V1_0_HOP0_MASK;
428 	prop->dmmu.hop_masks[MMU_HOP1] = MMU_V1_0_HOP1_MASK;
429 	prop->dmmu.hop_masks[MMU_HOP2] = MMU_V1_0_HOP2_MASK;
430 	prop->dmmu.hop_masks[MMU_HOP3] = MMU_V1_0_HOP3_MASK;
431 	prop->dmmu.hop_masks[MMU_HOP4] = MMU_V1_0_HOP4_MASK;
432 	prop->dmmu.start_addr = VA_DDR_SPACE_START;
433 	prop->dmmu.end_addr = VA_DDR_SPACE_END;
434 	prop->dmmu.page_size = PAGE_SIZE_2MB;
435 	prop->dmmu.num_hops = MMU_ARCH_5_HOPS;
436 	prop->dmmu.last_mask = LAST_MASK;
437 	/* TODO: will be duplicated until implementing per-MMU props */
438 	prop->dmmu.hop_table_size = prop->mmu_hop_table_size;
439 	prop->dmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size;
440 
441 	/* shifts and masks are the same in PMMU and DMMU */
442 	memcpy(&prop->pmmu, &prop->dmmu, sizeof(prop->dmmu));
443 	prop->pmmu.start_addr = VA_HOST_SPACE_START;
444 	prop->pmmu.end_addr = VA_HOST_SPACE_END;
445 	prop->pmmu.page_size = PAGE_SIZE_4KB;
446 	prop->pmmu.num_hops = MMU_ARCH_5_HOPS;
447 	prop->pmmu.last_mask = LAST_MASK;
448 	/* TODO: will be duplicated until implementing per-MMU props */
449 	prop->pmmu.hop_table_size = prop->mmu_hop_table_size;
450 	prop->pmmu.hop0_tables_total_size = prop->mmu_hop0_tables_total_size;
451 
452 	/* PMMU and HPMMU are the same except of page size */
453 	memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu));
454 	prop->pmmu_huge.page_size = PAGE_SIZE_2MB;
455 
456 	prop->dram_size_for_default_page_mapping = VA_DDR_SPACE_END;
457 	prop->cfg_size = CFG_SIZE;
458 	prop->max_asid = MAX_ASID;
459 	prop->num_of_events = GOYA_ASYNC_EVENT_ID_SIZE;
460 	prop->high_pll = PLL_HIGH_DEFAULT;
461 	prop->cb_pool_cb_cnt = GOYA_CB_POOL_CB_CNT;
462 	prop->cb_pool_cb_size = GOYA_CB_POOL_CB_SIZE;
463 	prop->max_power_default = MAX_POWER_DEFAULT;
464 	prop->dc_power_default = DC_POWER_DEFAULT;
465 	prop->tpc_enabled_mask = TPC_ENABLED_MASK;
466 	prop->pcie_dbi_base_address = mmPCIE_DBI_BASE;
467 	prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI;
468 
469 	strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
470 		CARD_NAME_MAX_LEN);
471 
472 	prop->max_pending_cs = GOYA_MAX_PENDING_CS;
473 
474 	prop->first_available_user_interrupt = USHRT_MAX;
475 
476 	for (i = 0 ; i < HL_MAX_DCORES ; i++)
477 		prop->first_available_cq[i] = USHRT_MAX;
478 
479 	prop->fw_cpu_boot_dev_sts0_valid = false;
480 	prop->fw_cpu_boot_dev_sts1_valid = false;
481 	prop->hard_reset_done_by_fw = false;
482 	prop->gic_interrupts_enable = true;
483 
484 	prop->server_type = HL_SERVER_TYPE_UNKNOWN;
485 
486 	prop->clk_pll_index = HL_GOYA_MME_PLL;
487 
488 	prop->use_get_power_for_reset_history = true;
489 
490 	prop->configurable_stop_on_err = true;
491 
492 	prop->set_max_power_on_device_init = true;
493 
494 	prop->dma_mask = 48;
495 
496 	return 0;
497 }
498 
499 /*
500  * goya_pci_bars_map - Map PCI BARS of Goya device
501  *
502  * @hdev: pointer to hl_device structure
503  *
504  * Request PCI regions and map them to kernel virtual addresses.
505  * Returns 0 on success
506  *
507  */
508 static int goya_pci_bars_map(struct hl_device *hdev)
509 {
510 	static const char * const name[] = {"SRAM_CFG", "MSIX", "DDR"};
511 	bool is_wc[3] = {false, false, true};
512 	int rc;
513 
514 	rc = hl_pci_bars_map(hdev, name, is_wc);
515 	if (rc)
516 		return rc;
517 
518 	hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] +
519 			(CFG_BASE - SRAM_BASE_ADDR);
520 
521 	return 0;
522 }
523 
524 static u64 goya_set_ddr_bar_base(struct hl_device *hdev, u64 addr)
525 {
526 	struct goya_device *goya = hdev->asic_specific;
527 	struct hl_inbound_pci_region pci_region;
528 	u64 old_addr = addr;
529 	int rc;
530 
531 	if ((goya) && (goya->ddr_bar_cur_addr == addr))
532 		return old_addr;
533 
534 	/* Inbound Region 1 - Bar 4 - Point to DDR */
535 	pci_region.mode = PCI_BAR_MATCH_MODE;
536 	pci_region.bar = DDR_BAR_ID;
537 	pci_region.addr = addr;
538 	rc = hl_pci_set_inbound_region(hdev, 1, &pci_region);
539 	if (rc)
540 		return U64_MAX;
541 
542 	if (goya) {
543 		old_addr = goya->ddr_bar_cur_addr;
544 		goya->ddr_bar_cur_addr = addr;
545 	}
546 
547 	return old_addr;
548 }
549 
550 /*
551  * goya_init_iatu - Initialize the iATU unit inside the PCI controller
552  *
553  * @hdev: pointer to hl_device structure
554  *
555  * This is needed in case the firmware doesn't initialize the iATU
556  *
557  */
558 static int goya_init_iatu(struct hl_device *hdev)
559 {
560 	struct hl_inbound_pci_region inbound_region;
561 	struct hl_outbound_pci_region outbound_region;
562 	int rc;
563 
564 	if (hdev->asic_prop.iatu_done_by_fw)
565 		return 0;
566 
567 	/* Inbound Region 0 - Bar 0 - Point to SRAM and CFG */
568 	inbound_region.mode = PCI_BAR_MATCH_MODE;
569 	inbound_region.bar = SRAM_CFG_BAR_ID;
570 	inbound_region.addr = SRAM_BASE_ADDR;
571 	rc = hl_pci_set_inbound_region(hdev, 0, &inbound_region);
572 	if (rc)
573 		goto done;
574 
575 	/* Inbound Region 1 - Bar 4 - Point to DDR */
576 	inbound_region.mode = PCI_BAR_MATCH_MODE;
577 	inbound_region.bar = DDR_BAR_ID;
578 	inbound_region.addr = DRAM_PHYS_BASE;
579 	rc = hl_pci_set_inbound_region(hdev, 1, &inbound_region);
580 	if (rc)
581 		goto done;
582 
583 	/* Outbound Region 0 - Point to Host  */
584 	outbound_region.addr = HOST_PHYS_BASE;
585 	outbound_region.size = HOST_PHYS_SIZE;
586 	rc = hl_pci_set_outbound_region(hdev, &outbound_region);
587 
588 done:
589 	return rc;
590 }
591 
592 static enum hl_device_hw_state goya_get_hw_state(struct hl_device *hdev)
593 {
594 	return RREG32(mmHW_STATE);
595 }
596 
597 /*
598  * goya_early_init - GOYA early initialization code
599  *
600  * @hdev: pointer to hl_device structure
601  *
602  * Verify PCI bars
603  * Set DMA masks
604  * PCI controller initialization
605  * Map PCI bars
606  *
607  */
608 static int goya_early_init(struct hl_device *hdev)
609 {
610 	struct asic_fixed_properties *prop = &hdev->asic_prop;
611 	struct pci_dev *pdev = hdev->pdev;
612 	resource_size_t pci_bar_size;
613 	u32 fw_boot_status, val;
614 	int rc;
615 
616 	rc = goya_set_fixed_properties(hdev);
617 	if (rc) {
618 		dev_err(hdev->dev, "Failed to get fixed properties\n");
619 		return rc;
620 	}
621 
622 	/* Check BAR sizes */
623 	pci_bar_size = pci_resource_len(pdev, SRAM_CFG_BAR_ID);
624 
625 	if (pci_bar_size != CFG_BAR_SIZE) {
626 		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
627 			SRAM_CFG_BAR_ID, &pci_bar_size, CFG_BAR_SIZE);
628 		rc = -ENODEV;
629 		goto free_queue_props;
630 	}
631 
632 	pci_bar_size = pci_resource_len(pdev, MSIX_BAR_ID);
633 
634 	if (pci_bar_size != MSIX_BAR_SIZE) {
635 		dev_err(hdev->dev, "Not " HL_NAME "? BAR %d size %pa, expecting %llu\n",
636 			MSIX_BAR_ID, &pci_bar_size, MSIX_BAR_SIZE);
637 		rc = -ENODEV;
638 		goto free_queue_props;
639 	}
640 
641 	prop->dram_pci_bar_size = pci_resource_len(pdev, DDR_BAR_ID);
642 	hdev->dram_pci_bar_start = pci_resource_start(pdev, DDR_BAR_ID);
643 
644 	/* If FW security is enabled at this point it means no access to ELBI */
645 	if (hdev->asic_prop.fw_security_enabled) {
646 		hdev->asic_prop.iatu_done_by_fw = true;
647 		goto pci_init;
648 	}
649 
650 	rc = hl_pci_elbi_read(hdev, CFG_BASE + mmCPU_BOOT_DEV_STS0,
651 				&fw_boot_status);
652 	if (rc)
653 		goto free_queue_props;
654 
655 	/* Check whether FW is configuring iATU */
656 	if ((fw_boot_status & CPU_BOOT_DEV_STS0_ENABLED) &&
657 			(fw_boot_status & CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN))
658 		hdev->asic_prop.iatu_done_by_fw = true;
659 
660 pci_init:
661 	rc = hl_pci_init(hdev);
662 	if (rc)
663 		goto free_queue_props;
664 
665 	/* Before continuing in the initialization, we need to read the preboot
666 	 * version to determine whether we run with a security-enabled firmware
667 	 */
668 	rc = hl_fw_read_preboot_status(hdev);
669 	if (rc) {
670 		if (hdev->reset_on_preboot_fail)
671 			hdev->asic_funcs->hw_fini(hdev, true, false);
672 		goto pci_fini;
673 	}
674 
675 	if (goya_get_hw_state(hdev) == HL_DEVICE_HW_STATE_DIRTY) {
676 		dev_dbg(hdev->dev, "H/W state is dirty, must reset before initializing\n");
677 		hdev->asic_funcs->hw_fini(hdev, true, false);
678 	}
679 
680 	if (!hdev->pldm) {
681 		val = RREG32(mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS);
682 		if (val & PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_SRIOV_EN_MASK)
683 			dev_warn(hdev->dev,
684 				"PCI strap is not configured correctly, PCI bus errors may occur\n");
685 	}
686 
687 	return 0;
688 
689 pci_fini:
690 	hl_pci_fini(hdev);
691 free_queue_props:
692 	kfree(hdev->asic_prop.hw_queues_props);
693 	return rc;
694 }
695 
696 /*
697  * goya_early_fini - GOYA early finalization code
698  *
699  * @hdev: pointer to hl_device structure
700  *
701  * Unmap PCI bars
702  *
703  */
704 static int goya_early_fini(struct hl_device *hdev)
705 {
706 	kfree(hdev->asic_prop.hw_queues_props);
707 	hl_pci_fini(hdev);
708 
709 	return 0;
710 }
711 
712 static void goya_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid)
713 {
714 	/* mask to zero the MMBP and ASID bits */
715 	WREG32_AND(reg, ~0x7FF);
716 	WREG32_OR(reg, asid);
717 }
718 
719 static void goya_qman0_set_security(struct hl_device *hdev, bool secure)
720 {
721 	struct goya_device *goya = hdev->asic_specific;
722 
723 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
724 		return;
725 
726 	if (secure)
727 		WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_FULLY_TRUSTED);
728 	else
729 		WREG32(mmDMA_QM_0_GLBL_PROT, QMAN_DMA_PARTLY_TRUSTED);
730 
731 	RREG32(mmDMA_QM_0_GLBL_PROT);
732 }
733 
734 /*
735  * goya_fetch_psoc_frequency - Fetch PSOC frequency values
736  *
737  * @hdev: pointer to hl_device structure
738  *
739  */
740 static void goya_fetch_psoc_frequency(struct hl_device *hdev)
741 {
742 	struct asic_fixed_properties *prop = &hdev->asic_prop;
743 	u32 nr = 0, nf = 0, od = 0, div_fctr = 0, pll_clk, div_sel;
744 	u16 pll_freq_arr[HL_PLL_NUM_OUTPUTS], freq;
745 	int rc;
746 
747 	if (hdev->asic_prop.fw_security_enabled) {
748 		struct goya_device *goya = hdev->asic_specific;
749 
750 		if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
751 			return;
752 
753 		rc = hl_fw_cpucp_pll_info_get(hdev, HL_GOYA_PCI_PLL,
754 				pll_freq_arr);
755 
756 		if (rc)
757 			return;
758 
759 		freq = pll_freq_arr[1];
760 	} else {
761 		div_fctr = RREG32(mmPSOC_PCI_PLL_DIV_FACTOR_1);
762 		div_sel = RREG32(mmPSOC_PCI_PLL_DIV_SEL_1);
763 		nr = RREG32(mmPSOC_PCI_PLL_NR);
764 		nf = RREG32(mmPSOC_PCI_PLL_NF);
765 		od = RREG32(mmPSOC_PCI_PLL_OD);
766 
767 		if (div_sel == DIV_SEL_REF_CLK ||
768 				div_sel == DIV_SEL_DIVIDED_REF) {
769 			if (div_sel == DIV_SEL_REF_CLK)
770 				freq = PLL_REF_CLK;
771 			else
772 				freq = PLL_REF_CLK / (div_fctr + 1);
773 		} else if (div_sel == DIV_SEL_PLL_CLK ||
774 				div_sel == DIV_SEL_DIVIDED_PLL) {
775 			pll_clk = PLL_REF_CLK * (nf + 1) /
776 					((nr + 1) * (od + 1));
777 			if (div_sel == DIV_SEL_PLL_CLK)
778 				freq = pll_clk;
779 			else
780 				freq = pll_clk / (div_fctr + 1);
781 		} else {
782 			dev_warn(hdev->dev,
783 				"Received invalid div select value: %d",
784 				div_sel);
785 			freq = 0;
786 		}
787 	}
788 
789 	prop->psoc_timestamp_frequency = freq;
790 	prop->psoc_pci_pll_nr = nr;
791 	prop->psoc_pci_pll_nf = nf;
792 	prop->psoc_pci_pll_od = od;
793 	prop->psoc_pci_pll_div_factor = div_fctr;
794 }
795 
796 /*
797  * goya_set_frequency - set the frequency of the device
798  *
799  * @hdev: pointer to habanalabs device structure
800  * @freq: the new frequency value
801  *
802  * Change the frequency if needed. This function has no protection against
803  * concurrency, therefore it is assumed that the calling function has protected
804  * itself against the case of calling this function from multiple threads with
805  * different values
806  *
807  * Returns 0 if no change was done, otherwise returns 1
808  */
809 int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq)
810 {
811 	struct goya_device *goya = hdev->asic_specific;
812 
813 	if ((goya->pm_mng_profile == PM_MANUAL) ||
814 			(goya->curr_pll_profile == freq))
815 		return 0;
816 
817 	dev_dbg(hdev->dev, "Changing device frequency to %s\n",
818 		freq == PLL_HIGH ? "high" : "low");
819 
820 	goya_set_pll_profile(hdev, freq);
821 
822 	goya->curr_pll_profile = freq;
823 
824 	return 1;
825 }
826 
827 static void goya_set_freq_to_low_job(struct work_struct *work)
828 {
829 	struct goya_work_freq *goya_work = container_of(work,
830 						struct goya_work_freq,
831 						work_freq.work);
832 	struct hl_device *hdev = goya_work->hdev;
833 
834 	mutex_lock(&hdev->fpriv_list_lock);
835 
836 	if (!hdev->is_compute_ctx_active)
837 		goya_set_frequency(hdev, PLL_LOW);
838 
839 	mutex_unlock(&hdev->fpriv_list_lock);
840 
841 	schedule_delayed_work(&goya_work->work_freq,
842 			usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
843 }
844 
845 int goya_late_init(struct hl_device *hdev)
846 {
847 	struct asic_fixed_properties *prop = &hdev->asic_prop;
848 	struct goya_device *goya = hdev->asic_specific;
849 	int rc;
850 
851 	goya_fetch_psoc_frequency(hdev);
852 
853 	rc = goya_mmu_clear_pgt_range(hdev);
854 	if (rc) {
855 		dev_err(hdev->dev,
856 			"Failed to clear MMU page tables range %d\n", rc);
857 		return rc;
858 	}
859 
860 	rc = goya_mmu_set_dram_default_page(hdev);
861 	if (rc) {
862 		dev_err(hdev->dev, "Failed to set DRAM default page %d\n", rc);
863 		return rc;
864 	}
865 
866 	rc = goya_mmu_add_mappings_for_device_cpu(hdev);
867 	if (rc)
868 		return rc;
869 
870 	rc = goya_init_cpu_queues(hdev);
871 	if (rc)
872 		return rc;
873 
874 	rc = goya_test_cpu_queue(hdev);
875 	if (rc)
876 		return rc;
877 
878 	rc = goya_cpucp_info_get(hdev);
879 	if (rc) {
880 		dev_err(hdev->dev, "Failed to get cpucp info %d\n", rc);
881 		return rc;
882 	}
883 
884 	/* Now that we have the DRAM size in ASIC prop, we need to check
885 	 * its size and configure the DMA_IF DDR wrap protection (which is in
886 	 * the MMU block) accordingly. The value is the log2 of the DRAM size
887 	 */
888 	WREG32(mmMMU_LOG2_DDR_SIZE, ilog2(prop->dram_size));
889 
890 	rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_ENABLE_PCI_ACCESS, 0x0);
891 	if (rc) {
892 		dev_err(hdev->dev,
893 			"Failed to enable PCI access from CPU %d\n", rc);
894 		return rc;
895 	}
896 
897 	/* force setting to low frequency */
898 	goya->curr_pll_profile = PLL_LOW;
899 
900 	goya->pm_mng_profile = PM_AUTO;
901 
902 	goya_set_pll_profile(hdev, PLL_LOW);
903 
904 	schedule_delayed_work(&goya->goya_work->work_freq,
905 		usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
906 
907 	return 0;
908 }
909 
910 /*
911  * goya_late_fini - GOYA late tear-down code
912  *
913  * @hdev: pointer to hl_device structure
914  *
915  * Free sensors allocated structures
916  */
917 void goya_late_fini(struct hl_device *hdev)
918 {
919 	struct goya_device *goya = hdev->asic_specific;
920 
921 	cancel_delayed_work_sync(&goya->goya_work->work_freq);
922 
923 	hl_hwmon_release_resources(hdev);
924 }
925 
926 static void goya_set_pci_memory_regions(struct hl_device *hdev)
927 {
928 	struct asic_fixed_properties *prop = &hdev->asic_prop;
929 	struct pci_mem_region *region;
930 
931 	/* CFG */
932 	region = &hdev->pci_mem_region[PCI_REGION_CFG];
933 	region->region_base = CFG_BASE;
934 	region->region_size = CFG_SIZE;
935 	region->offset_in_bar = CFG_BASE - SRAM_BASE_ADDR;
936 	region->bar_size = CFG_BAR_SIZE;
937 	region->bar_id = SRAM_CFG_BAR_ID;
938 	region->used = 1;
939 
940 	/* SRAM */
941 	region = &hdev->pci_mem_region[PCI_REGION_SRAM];
942 	region->region_base = SRAM_BASE_ADDR;
943 	region->region_size = SRAM_SIZE;
944 	region->offset_in_bar = 0;
945 	region->bar_size = CFG_BAR_SIZE;
946 	region->bar_id = SRAM_CFG_BAR_ID;
947 	region->used = 1;
948 
949 	/* DRAM */
950 	region = &hdev->pci_mem_region[PCI_REGION_DRAM];
951 	region->region_base = DRAM_PHYS_BASE;
952 	region->region_size = hdev->asic_prop.dram_size;
953 	region->offset_in_bar = 0;
954 	region->bar_size = prop->dram_pci_bar_size;
955 	region->bar_id = DDR_BAR_ID;
956 	region->used = 1;
957 }
958 
959 /*
960  * goya_sw_init - Goya software initialization code
961  *
962  * @hdev: pointer to hl_device structure
963  *
964  */
965 static int goya_sw_init(struct hl_device *hdev)
966 {
967 	struct goya_device *goya;
968 	int rc;
969 
970 	/* Allocate device structure */
971 	goya = kzalloc(sizeof(*goya), GFP_KERNEL);
972 	if (!goya)
973 		return -ENOMEM;
974 
975 	/* according to goya_init_iatu */
976 	goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
977 
978 	goya->mme_clk = GOYA_PLL_FREQ_LOW;
979 	goya->tpc_clk = GOYA_PLL_FREQ_LOW;
980 	goya->ic_clk = GOYA_PLL_FREQ_LOW;
981 
982 	hdev->asic_specific = goya;
983 
984 	/* Create DMA pool for small allocations */
985 	hdev->dma_pool = dma_pool_create(dev_name(hdev->dev),
986 			&hdev->pdev->dev, GOYA_DMA_POOL_BLK_SIZE, 8, 0);
987 	if (!hdev->dma_pool) {
988 		dev_err(hdev->dev, "failed to create DMA pool\n");
989 		rc = -ENOMEM;
990 		goto free_goya_device;
991 	}
992 
993 	hdev->cpu_accessible_dma_mem = hl_asic_dma_alloc_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE,
994 							&hdev->cpu_accessible_dma_address,
995 							GFP_KERNEL | __GFP_ZERO);
996 
997 	if (!hdev->cpu_accessible_dma_mem) {
998 		rc = -ENOMEM;
999 		goto free_dma_pool;
1000 	}
1001 
1002 	dev_dbg(hdev->dev, "cpu accessible memory at bus address %pad\n",
1003 		&hdev->cpu_accessible_dma_address);
1004 
1005 	hdev->cpu_accessible_dma_pool = gen_pool_create(ilog2(32), -1);
1006 	if (!hdev->cpu_accessible_dma_pool) {
1007 		dev_err(hdev->dev,
1008 			"Failed to create CPU accessible DMA pool\n");
1009 		rc = -ENOMEM;
1010 		goto free_cpu_dma_mem;
1011 	}
1012 
1013 	rc = gen_pool_add(hdev->cpu_accessible_dma_pool,
1014 				(uintptr_t) hdev->cpu_accessible_dma_mem,
1015 				HL_CPU_ACCESSIBLE_MEM_SIZE, -1);
1016 	if (rc) {
1017 		dev_err(hdev->dev,
1018 			"Failed to add memory to CPU accessible DMA pool\n");
1019 		rc = -EFAULT;
1020 		goto free_cpu_accessible_dma_pool;
1021 	}
1022 
1023 	spin_lock_init(&goya->hw_queues_lock);
1024 	hdev->supports_coresight = true;
1025 	hdev->asic_prop.supports_compute_reset = true;
1026 	hdev->asic_prop.allow_inference_soft_reset = true;
1027 	hdev->supports_wait_for_multi_cs = false;
1028 	hdev->supports_ctx_switch = true;
1029 
1030 	hdev->asic_funcs->set_pci_memory_regions(hdev);
1031 
1032 	goya->goya_work = kmalloc(sizeof(struct goya_work_freq), GFP_KERNEL);
1033 	if (!goya->goya_work) {
1034 		rc = -ENOMEM;
1035 		goto free_cpu_accessible_dma_pool;
1036 	}
1037 
1038 	goya->goya_work->hdev = hdev;
1039 	INIT_DELAYED_WORK(&goya->goya_work->work_freq, goya_set_freq_to_low_job);
1040 
1041 	return 0;
1042 
1043 free_cpu_accessible_dma_pool:
1044 	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1045 free_cpu_dma_mem:
1046 	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1047 					hdev->cpu_accessible_dma_address);
1048 free_dma_pool:
1049 	dma_pool_destroy(hdev->dma_pool);
1050 free_goya_device:
1051 	kfree(goya);
1052 
1053 	return rc;
1054 }
1055 
1056 /*
1057  * goya_sw_fini - Goya software tear-down code
1058  *
1059  * @hdev: pointer to hl_device structure
1060  *
1061  */
1062 static int goya_sw_fini(struct hl_device *hdev)
1063 {
1064 	struct goya_device *goya = hdev->asic_specific;
1065 
1066 	gen_pool_destroy(hdev->cpu_accessible_dma_pool);
1067 
1068 	hl_asic_dma_free_coherent(hdev, HL_CPU_ACCESSIBLE_MEM_SIZE, hdev->cpu_accessible_dma_mem,
1069 					hdev->cpu_accessible_dma_address);
1070 
1071 	dma_pool_destroy(hdev->dma_pool);
1072 
1073 	kfree(goya->goya_work);
1074 	kfree(goya);
1075 
1076 	return 0;
1077 }
1078 
1079 static void goya_init_dma_qman(struct hl_device *hdev, int dma_id,
1080 		dma_addr_t bus_address)
1081 {
1082 	struct goya_device *goya = hdev->asic_specific;
1083 	u32 mtr_base_lo, mtr_base_hi;
1084 	u32 so_base_lo, so_base_hi;
1085 	u32 gic_base_lo, gic_base_hi;
1086 	u32 reg_off = dma_id * (mmDMA_QM_1_PQ_PI - mmDMA_QM_0_PQ_PI);
1087 	u32 dma_err_cfg = QMAN_DMA_ERR_MSG_EN;
1088 
1089 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1090 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1091 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1092 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1093 
1094 	gic_base_lo =
1095 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1096 	gic_base_hi =
1097 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1098 
1099 	WREG32(mmDMA_QM_0_PQ_BASE_LO + reg_off, lower_32_bits(bus_address));
1100 	WREG32(mmDMA_QM_0_PQ_BASE_HI + reg_off, upper_32_bits(bus_address));
1101 
1102 	WREG32(mmDMA_QM_0_PQ_SIZE + reg_off, ilog2(HL_QUEUE_LENGTH));
1103 	WREG32(mmDMA_QM_0_PQ_PI + reg_off, 0);
1104 	WREG32(mmDMA_QM_0_PQ_CI + reg_off, 0);
1105 
1106 	WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1107 	WREG32(mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1108 	WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1109 	WREG32(mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1110 	WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1111 	WREG32(mmDMA_QM_0_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1112 	WREG32(mmDMA_QM_0_GLBL_ERR_WDATA + reg_off,
1113 			GOYA_ASYNC_EVENT_ID_DMA0_QM + dma_id);
1114 
1115 	/* PQ has buffer of 2 cache lines, while CQ has 8 lines */
1116 	WREG32(mmDMA_QM_0_PQ_CFG1 + reg_off, 0x00020002);
1117 	WREG32(mmDMA_QM_0_CQ_CFG1 + reg_off, 0x00080008);
1118 
1119 	if (goya->hw_cap_initialized & HW_CAP_MMU)
1120 		WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_PARTLY_TRUSTED);
1121 	else
1122 		WREG32(mmDMA_QM_0_GLBL_PROT + reg_off, QMAN_DMA_FULLY_TRUSTED);
1123 
1124 	if (hdev->stop_on_err)
1125 		dma_err_cfg |= 1 << DMA_QM_0_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT;
1126 
1127 	WREG32(mmDMA_QM_0_GLBL_ERR_CFG + reg_off, dma_err_cfg);
1128 	WREG32(mmDMA_QM_0_GLBL_CFG0 + reg_off, QMAN_DMA_ENABLE);
1129 }
1130 
1131 static void goya_init_dma_ch(struct hl_device *hdev, int dma_id)
1132 {
1133 	u32 gic_base_lo, gic_base_hi;
1134 	u64 sob_addr;
1135 	u32 reg_off = dma_id * (mmDMA_CH_1_CFG1 - mmDMA_CH_0_CFG1);
1136 
1137 	gic_base_lo =
1138 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1139 	gic_base_hi =
1140 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1141 
1142 	WREG32(mmDMA_CH_0_ERRMSG_ADDR_LO + reg_off, gic_base_lo);
1143 	WREG32(mmDMA_CH_0_ERRMSG_ADDR_HI + reg_off, gic_base_hi);
1144 	WREG32(mmDMA_CH_0_ERRMSG_WDATA + reg_off,
1145 			GOYA_ASYNC_EVENT_ID_DMA0_CH + dma_id);
1146 
1147 	if (dma_id)
1148 		sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
1149 				(dma_id - 1) * 4;
1150 	else
1151 		sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
1152 
1153 	WREG32(mmDMA_CH_0_WR_COMP_ADDR_HI + reg_off, upper_32_bits(sob_addr));
1154 	WREG32(mmDMA_CH_0_WR_COMP_WDATA + reg_off, 0x80000001);
1155 }
1156 
1157 /*
1158  * goya_init_dma_qmans - Initialize QMAN DMA registers
1159  *
1160  * @hdev: pointer to hl_device structure
1161  *
1162  * Initialize the H/W registers of the QMAN DMA channels
1163  *
1164  */
1165 void goya_init_dma_qmans(struct hl_device *hdev)
1166 {
1167 	struct goya_device *goya = hdev->asic_specific;
1168 	struct hl_hw_queue *q;
1169 	int i;
1170 
1171 	if (goya->hw_cap_initialized & HW_CAP_DMA)
1172 		return;
1173 
1174 	q = &hdev->kernel_queues[0];
1175 
1176 	for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++, q++) {
1177 		q->cq_id = q->msi_vec = i;
1178 		goya_init_dma_qman(hdev, i, q->bus_address);
1179 		goya_init_dma_ch(hdev, i);
1180 	}
1181 
1182 	goya->hw_cap_initialized |= HW_CAP_DMA;
1183 }
1184 
1185 /*
1186  * goya_disable_external_queues - Disable external queues
1187  *
1188  * @hdev: pointer to hl_device structure
1189  *
1190  */
1191 static void goya_disable_external_queues(struct hl_device *hdev)
1192 {
1193 	struct goya_device *goya = hdev->asic_specific;
1194 
1195 	if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1196 		return;
1197 
1198 	WREG32(mmDMA_QM_0_GLBL_CFG0, 0);
1199 	WREG32(mmDMA_QM_1_GLBL_CFG0, 0);
1200 	WREG32(mmDMA_QM_2_GLBL_CFG0, 0);
1201 	WREG32(mmDMA_QM_3_GLBL_CFG0, 0);
1202 	WREG32(mmDMA_QM_4_GLBL_CFG0, 0);
1203 }
1204 
1205 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg,
1206 				u32 cp_sts_reg, u32 glbl_sts0_reg)
1207 {
1208 	int rc;
1209 	u32 status;
1210 
1211 	/* use the values of TPC0 as they are all the same*/
1212 
1213 	WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT);
1214 
1215 	status = RREG32(cp_sts_reg);
1216 	if (status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK) {
1217 		rc = hl_poll_timeout(
1218 			hdev,
1219 			cp_sts_reg,
1220 			status,
1221 			!(status & TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK),
1222 			1000,
1223 			QMAN_FENCE_TIMEOUT_USEC);
1224 
1225 		/* if QMAN is stuck in fence no need to check for stop */
1226 		if (rc)
1227 			return 0;
1228 	}
1229 
1230 	rc = hl_poll_timeout(
1231 		hdev,
1232 		glbl_sts0_reg,
1233 		status,
1234 		(status & TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK),
1235 		1000,
1236 		QMAN_STOP_TIMEOUT_USEC);
1237 
1238 	if (rc) {
1239 		dev_err(hdev->dev,
1240 			"Timeout while waiting for QMAN to stop\n");
1241 		return -EINVAL;
1242 	}
1243 
1244 	return 0;
1245 }
1246 
1247 /*
1248  * goya_stop_external_queues - Stop external queues
1249  *
1250  * @hdev: pointer to hl_device structure
1251  *
1252  * Returns 0 on success
1253  *
1254  */
1255 static int goya_stop_external_queues(struct hl_device *hdev)
1256 {
1257 	int rc, retval = 0;
1258 
1259 	struct goya_device *goya = hdev->asic_specific;
1260 
1261 	if (!(goya->hw_cap_initialized & HW_CAP_DMA))
1262 		return retval;
1263 
1264 	rc = goya_stop_queue(hdev,
1265 			mmDMA_QM_0_GLBL_CFG1,
1266 			mmDMA_QM_0_CP_STS,
1267 			mmDMA_QM_0_GLBL_STS0);
1268 
1269 	if (rc) {
1270 		dev_err(hdev->dev, "failed to stop DMA QMAN 0\n");
1271 		retval = -EIO;
1272 	}
1273 
1274 	rc = goya_stop_queue(hdev,
1275 			mmDMA_QM_1_GLBL_CFG1,
1276 			mmDMA_QM_1_CP_STS,
1277 			mmDMA_QM_1_GLBL_STS0);
1278 
1279 	if (rc) {
1280 		dev_err(hdev->dev, "failed to stop DMA QMAN 1\n");
1281 		retval = -EIO;
1282 	}
1283 
1284 	rc = goya_stop_queue(hdev,
1285 			mmDMA_QM_2_GLBL_CFG1,
1286 			mmDMA_QM_2_CP_STS,
1287 			mmDMA_QM_2_GLBL_STS0);
1288 
1289 	if (rc) {
1290 		dev_err(hdev->dev, "failed to stop DMA QMAN 2\n");
1291 		retval = -EIO;
1292 	}
1293 
1294 	rc = goya_stop_queue(hdev,
1295 			mmDMA_QM_3_GLBL_CFG1,
1296 			mmDMA_QM_3_CP_STS,
1297 			mmDMA_QM_3_GLBL_STS0);
1298 
1299 	if (rc) {
1300 		dev_err(hdev->dev, "failed to stop DMA QMAN 3\n");
1301 		retval = -EIO;
1302 	}
1303 
1304 	rc = goya_stop_queue(hdev,
1305 			mmDMA_QM_4_GLBL_CFG1,
1306 			mmDMA_QM_4_CP_STS,
1307 			mmDMA_QM_4_GLBL_STS0);
1308 
1309 	if (rc) {
1310 		dev_err(hdev->dev, "failed to stop DMA QMAN 4\n");
1311 		retval = -EIO;
1312 	}
1313 
1314 	return retval;
1315 }
1316 
1317 /*
1318  * goya_init_cpu_queues - Initialize PQ/CQ/EQ of CPU
1319  *
1320  * @hdev: pointer to hl_device structure
1321  *
1322  * Returns 0 on success
1323  *
1324  */
1325 int goya_init_cpu_queues(struct hl_device *hdev)
1326 {
1327 	struct goya_device *goya = hdev->asic_specific;
1328 	struct asic_fixed_properties *prop = &hdev->asic_prop;
1329 	struct hl_eq *eq;
1330 	u32 status;
1331 	struct hl_hw_queue *cpu_pq = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
1332 	int err;
1333 
1334 	if (!hdev->cpu_queues_enable)
1335 		return 0;
1336 
1337 	if (goya->hw_cap_initialized & HW_CAP_CPU_Q)
1338 		return 0;
1339 
1340 	eq = &hdev->event_queue;
1341 
1342 	WREG32(mmCPU_PQ_BASE_ADDR_LOW, lower_32_bits(cpu_pq->bus_address));
1343 	WREG32(mmCPU_PQ_BASE_ADDR_HIGH, upper_32_bits(cpu_pq->bus_address));
1344 
1345 	WREG32(mmCPU_EQ_BASE_ADDR_LOW, lower_32_bits(eq->bus_address));
1346 	WREG32(mmCPU_EQ_BASE_ADDR_HIGH, upper_32_bits(eq->bus_address));
1347 
1348 	WREG32(mmCPU_CQ_BASE_ADDR_LOW,
1349 			lower_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1350 	WREG32(mmCPU_CQ_BASE_ADDR_HIGH,
1351 			upper_32_bits(VA_CPU_ACCESSIBLE_MEM_ADDR));
1352 
1353 	WREG32(mmCPU_PQ_LENGTH, HL_QUEUE_SIZE_IN_BYTES);
1354 	WREG32(mmCPU_EQ_LENGTH, HL_EQ_SIZE_IN_BYTES);
1355 	WREG32(mmCPU_CQ_LENGTH, HL_CPU_ACCESSIBLE_MEM_SIZE);
1356 
1357 	/* Used for EQ CI */
1358 	WREG32(mmCPU_EQ_CI, 0);
1359 
1360 	WREG32(mmCPU_IF_PF_PQ_PI, 0);
1361 
1362 	WREG32(mmCPU_PQ_INIT_STATUS, PQ_INIT_STATUS_READY_FOR_CP);
1363 
1364 	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
1365 			GOYA_ASYNC_EVENT_ID_PI_UPDATE);
1366 
1367 	err = hl_poll_timeout(
1368 		hdev,
1369 		mmCPU_PQ_INIT_STATUS,
1370 		status,
1371 		(status == PQ_INIT_STATUS_READY_FOR_HOST),
1372 		1000,
1373 		GOYA_CPU_TIMEOUT_USEC);
1374 
1375 	if (err) {
1376 		dev_err(hdev->dev,
1377 			"Failed to setup communication with device CPU\n");
1378 		return -EIO;
1379 	}
1380 
1381 	/* update FW application security bits */
1382 	if (prop->fw_cpu_boot_dev_sts0_valid)
1383 		prop->fw_app_cpu_boot_dev_sts0 = RREG32(mmCPU_BOOT_DEV_STS0);
1384 
1385 	if (prop->fw_cpu_boot_dev_sts1_valid)
1386 		prop->fw_app_cpu_boot_dev_sts1 = RREG32(mmCPU_BOOT_DEV_STS1);
1387 
1388 	goya->hw_cap_initialized |= HW_CAP_CPU_Q;
1389 	return 0;
1390 }
1391 
1392 static void goya_set_pll_refclk(struct hl_device *hdev)
1393 {
1394 	WREG32(mmCPU_PLL_DIV_SEL_0, 0x0);
1395 	WREG32(mmCPU_PLL_DIV_SEL_1, 0x0);
1396 	WREG32(mmCPU_PLL_DIV_SEL_2, 0x0);
1397 	WREG32(mmCPU_PLL_DIV_SEL_3, 0x0);
1398 
1399 	WREG32(mmIC_PLL_DIV_SEL_0, 0x0);
1400 	WREG32(mmIC_PLL_DIV_SEL_1, 0x0);
1401 	WREG32(mmIC_PLL_DIV_SEL_2, 0x0);
1402 	WREG32(mmIC_PLL_DIV_SEL_3, 0x0);
1403 
1404 	WREG32(mmMC_PLL_DIV_SEL_0, 0x0);
1405 	WREG32(mmMC_PLL_DIV_SEL_1, 0x0);
1406 	WREG32(mmMC_PLL_DIV_SEL_2, 0x0);
1407 	WREG32(mmMC_PLL_DIV_SEL_3, 0x0);
1408 
1409 	WREG32(mmPSOC_MME_PLL_DIV_SEL_0, 0x0);
1410 	WREG32(mmPSOC_MME_PLL_DIV_SEL_1, 0x0);
1411 	WREG32(mmPSOC_MME_PLL_DIV_SEL_2, 0x0);
1412 	WREG32(mmPSOC_MME_PLL_DIV_SEL_3, 0x0);
1413 
1414 	WREG32(mmPSOC_PCI_PLL_DIV_SEL_0, 0x0);
1415 	WREG32(mmPSOC_PCI_PLL_DIV_SEL_1, 0x0);
1416 	WREG32(mmPSOC_PCI_PLL_DIV_SEL_2, 0x0);
1417 	WREG32(mmPSOC_PCI_PLL_DIV_SEL_3, 0x0);
1418 
1419 	WREG32(mmPSOC_EMMC_PLL_DIV_SEL_0, 0x0);
1420 	WREG32(mmPSOC_EMMC_PLL_DIV_SEL_1, 0x0);
1421 	WREG32(mmPSOC_EMMC_PLL_DIV_SEL_2, 0x0);
1422 	WREG32(mmPSOC_EMMC_PLL_DIV_SEL_3, 0x0);
1423 
1424 	WREG32(mmTPC_PLL_DIV_SEL_0, 0x0);
1425 	WREG32(mmTPC_PLL_DIV_SEL_1, 0x0);
1426 	WREG32(mmTPC_PLL_DIV_SEL_2, 0x0);
1427 	WREG32(mmTPC_PLL_DIV_SEL_3, 0x0);
1428 }
1429 
1430 static void goya_disable_clk_rlx(struct hl_device *hdev)
1431 {
1432 	WREG32(mmPSOC_MME_PLL_CLK_RLX_0, 0x100010);
1433 	WREG32(mmIC_PLL_CLK_RLX_0, 0x100010);
1434 }
1435 
1436 static void _goya_tpc_mbist_workaround(struct hl_device *hdev, u8 tpc_id)
1437 {
1438 	u64 tpc_eml_address;
1439 	u32 val, tpc_offset, tpc_eml_offset, tpc_slm_offset;
1440 	int err, slm_index;
1441 
1442 	tpc_offset = tpc_id * 0x40000;
1443 	tpc_eml_offset = tpc_id * 0x200000;
1444 	tpc_eml_address = (mmTPC0_EML_CFG_BASE + tpc_eml_offset - CFG_BASE);
1445 	tpc_slm_offset = tpc_eml_address + 0x100000;
1446 
1447 	/*
1448 	 * Workaround for Bug H2 #2443 :
1449 	 * "TPC SB is not initialized on chip reset"
1450 	 */
1451 
1452 	val = RREG32(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset);
1453 	if (val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK)
1454 		dev_warn(hdev->dev, "TPC%d MBIST ACTIVE is not cleared\n",
1455 			tpc_id);
1456 
1457 	WREG32(mmTPC0_CFG_FUNC_MBIST_PAT + tpc_offset, val & 0xFFFFF000);
1458 
1459 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_0 + tpc_offset, 0x37FF);
1460 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_1 + tpc_offset, 0x303F);
1461 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_2 + tpc_offset, 0x71FF);
1462 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_3 + tpc_offset, 0x71FF);
1463 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_4 + tpc_offset, 0x70FF);
1464 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_5 + tpc_offset, 0x70FF);
1465 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_6 + tpc_offset, 0x70FF);
1466 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_7 + tpc_offset, 0x70FF);
1467 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_8 + tpc_offset, 0x70FF);
1468 	WREG32(mmTPC0_CFG_FUNC_MBIST_MEM_9 + tpc_offset, 0x70FF);
1469 
1470 	WREG32_OR(mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1471 		1 << TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT);
1472 
1473 	err = hl_poll_timeout(
1474 		hdev,
1475 		mmTPC0_CFG_FUNC_MBIST_CNTRL + tpc_offset,
1476 		val,
1477 		(val & TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK),
1478 		1000,
1479 		HL_DEVICE_TIMEOUT_USEC);
1480 
1481 	if (err)
1482 		dev_err(hdev->dev,
1483 			"Timeout while waiting for TPC%d MBIST DONE\n", tpc_id);
1484 
1485 	WREG32_OR(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1486 		1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT);
1487 
1488 	msleep(GOYA_RESET_WAIT_MSEC);
1489 
1490 	WREG32_AND(mmTPC0_EML_CFG_DBG_CNT + tpc_eml_offset,
1491 		~(1 << TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT));
1492 
1493 	msleep(GOYA_RESET_WAIT_MSEC);
1494 
1495 	for (slm_index = 0 ; slm_index < 256 ; slm_index++)
1496 		WREG32(tpc_slm_offset + (slm_index << 2), 0);
1497 
1498 	val = RREG32(tpc_slm_offset);
1499 }
1500 
1501 static void goya_tpc_mbist_workaround(struct hl_device *hdev)
1502 {
1503 	struct goya_device *goya = hdev->asic_specific;
1504 	int i;
1505 
1506 	if (hdev->pldm)
1507 		return;
1508 
1509 	if (goya->hw_cap_initialized & HW_CAP_TPC_MBIST)
1510 		return;
1511 
1512 	/* Workaround for H2 #2443 */
1513 
1514 	for (i = 0 ; i < TPC_MAX_NUM ; i++)
1515 		_goya_tpc_mbist_workaround(hdev, i);
1516 
1517 	goya->hw_cap_initialized |= HW_CAP_TPC_MBIST;
1518 }
1519 
1520 /*
1521  * goya_init_golden_registers - Initialize golden registers
1522  *
1523  * @hdev: pointer to hl_device structure
1524  *
1525  * Initialize the H/W registers of the device
1526  *
1527  */
1528 static void goya_init_golden_registers(struct hl_device *hdev)
1529 {
1530 	struct goya_device *goya = hdev->asic_specific;
1531 	u32 polynom[10], tpc_intr_mask, offset;
1532 	int i;
1533 
1534 	if (goya->hw_cap_initialized & HW_CAP_GOLDEN)
1535 		return;
1536 
1537 	polynom[0] = 0x00020080;
1538 	polynom[1] = 0x00401000;
1539 	polynom[2] = 0x00200800;
1540 	polynom[3] = 0x00002000;
1541 	polynom[4] = 0x00080200;
1542 	polynom[5] = 0x00040100;
1543 	polynom[6] = 0x00100400;
1544 	polynom[7] = 0x00004000;
1545 	polynom[8] = 0x00010000;
1546 	polynom[9] = 0x00008000;
1547 
1548 	/* Mask all arithmetic interrupts from TPC */
1549 	tpc_intr_mask = 0x7FFF;
1550 
1551 	for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x20000) {
1552 		WREG32(mmSRAM_Y0_X0_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1553 		WREG32(mmSRAM_Y0_X1_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1554 		WREG32(mmSRAM_Y0_X2_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1555 		WREG32(mmSRAM_Y0_X3_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1556 		WREG32(mmSRAM_Y0_X4_RTR_HBW_RD_RQ_L_ARB + offset, 0x302);
1557 
1558 		WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_L_ARB + offset, 0x204);
1559 		WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_L_ARB + offset, 0x204);
1560 		WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_L_ARB + offset, 0x204);
1561 		WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_L_ARB + offset, 0x204);
1562 		WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_L_ARB + offset, 0x204);
1563 
1564 
1565 		WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_E_ARB + offset, 0x206);
1566 		WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_E_ARB + offset, 0x206);
1567 		WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_E_ARB + offset, 0x206);
1568 		WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_E_ARB + offset, 0x207);
1569 		WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_E_ARB + offset, 0x207);
1570 
1571 		WREG32(mmSRAM_Y0_X0_RTR_HBW_DATA_W_ARB + offset, 0x207);
1572 		WREG32(mmSRAM_Y0_X1_RTR_HBW_DATA_W_ARB + offset, 0x207);
1573 		WREG32(mmSRAM_Y0_X2_RTR_HBW_DATA_W_ARB + offset, 0x206);
1574 		WREG32(mmSRAM_Y0_X3_RTR_HBW_DATA_W_ARB + offset, 0x206);
1575 		WREG32(mmSRAM_Y0_X4_RTR_HBW_DATA_W_ARB + offset, 0x206);
1576 
1577 		WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_E_ARB + offset, 0x101);
1578 		WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_E_ARB + offset, 0x102);
1579 		WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_E_ARB + offset, 0x103);
1580 		WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_E_ARB + offset, 0x104);
1581 		WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_E_ARB + offset, 0x105);
1582 
1583 		WREG32(mmSRAM_Y0_X0_RTR_HBW_WR_RS_W_ARB + offset, 0x105);
1584 		WREG32(mmSRAM_Y0_X1_RTR_HBW_WR_RS_W_ARB + offset, 0x104);
1585 		WREG32(mmSRAM_Y0_X2_RTR_HBW_WR_RS_W_ARB + offset, 0x103);
1586 		WREG32(mmSRAM_Y0_X3_RTR_HBW_WR_RS_W_ARB + offset, 0x102);
1587 		WREG32(mmSRAM_Y0_X4_RTR_HBW_WR_RS_W_ARB + offset, 0x101);
1588 	}
1589 
1590 	WREG32(mmMME_STORE_MAX_CREDIT, 0x21);
1591 	WREG32(mmMME_AGU, 0x0f0f0f10);
1592 	WREG32(mmMME_SEI_MASK, ~0x0);
1593 
1594 	WREG32(mmMME6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1595 	WREG32(mmMME5_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1596 	WREG32(mmMME4_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1597 	WREG32(mmMME3_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1598 	WREG32(mmMME2_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1599 	WREG32(mmMME1_RTR_HBW_RD_RQ_N_ARB, 0x07010701);
1600 	WREG32(mmMME6_RTR_HBW_RD_RQ_S_ARB, 0x04010401);
1601 	WREG32(mmMME5_RTR_HBW_RD_RQ_S_ARB, 0x04050401);
1602 	WREG32(mmMME4_RTR_HBW_RD_RQ_S_ARB, 0x03070301);
1603 	WREG32(mmMME3_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1604 	WREG32(mmMME2_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1605 	WREG32(mmMME1_RTR_HBW_RD_RQ_S_ARB, 0x01050105);
1606 	WREG32(mmMME6_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1607 	WREG32(mmMME5_RTR_HBW_RD_RQ_W_ARB, 0x01010501);
1608 	WREG32(mmMME4_RTR_HBW_RD_RQ_W_ARB, 0x01040301);
1609 	WREG32(mmMME3_RTR_HBW_RD_RQ_W_ARB, 0x01030401);
1610 	WREG32(mmMME2_RTR_HBW_RD_RQ_W_ARB, 0x01040101);
1611 	WREG32(mmMME1_RTR_HBW_RD_RQ_W_ARB, 0x01050101);
1612 	WREG32(mmMME6_RTR_HBW_WR_RQ_N_ARB, 0x02020202);
1613 	WREG32(mmMME5_RTR_HBW_WR_RQ_N_ARB, 0x01070101);
1614 	WREG32(mmMME4_RTR_HBW_WR_RQ_N_ARB, 0x02020201);
1615 	WREG32(mmMME3_RTR_HBW_WR_RQ_N_ARB, 0x07020701);
1616 	WREG32(mmMME2_RTR_HBW_WR_RQ_N_ARB, 0x01020101);
1617 	WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1618 	WREG32(mmMME6_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1619 	WREG32(mmMME5_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1620 	WREG32(mmMME4_RTR_HBW_WR_RQ_S_ARB, 0x07020701);
1621 	WREG32(mmMME3_RTR_HBW_WR_RQ_S_ARB, 0x02020201);
1622 	WREG32(mmMME2_RTR_HBW_WR_RQ_S_ARB, 0x01070101);
1623 	WREG32(mmMME1_RTR_HBW_WR_RQ_S_ARB, 0x01020102);
1624 	WREG32(mmMME6_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1625 	WREG32(mmMME5_RTR_HBW_WR_RQ_W_ARB, 0x01020701);
1626 	WREG32(mmMME4_RTR_HBW_WR_RQ_W_ARB, 0x07020707);
1627 	WREG32(mmMME3_RTR_HBW_WR_RQ_W_ARB, 0x01020201);
1628 	WREG32(mmMME2_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1629 	WREG32(mmMME1_RTR_HBW_WR_RQ_W_ARB, 0x01070201);
1630 	WREG32(mmMME6_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1631 	WREG32(mmMME5_RTR_HBW_RD_RS_N_ARB, 0x01070102);
1632 	WREG32(mmMME4_RTR_HBW_RD_RS_N_ARB, 0x01060102);
1633 	WREG32(mmMME3_RTR_HBW_RD_RS_N_ARB, 0x01040102);
1634 	WREG32(mmMME2_RTR_HBW_RD_RS_N_ARB, 0x01020102);
1635 	WREG32(mmMME1_RTR_HBW_RD_RS_N_ARB, 0x01020107);
1636 	WREG32(mmMME6_RTR_HBW_RD_RS_S_ARB, 0x01020106);
1637 	WREG32(mmMME5_RTR_HBW_RD_RS_S_ARB, 0x01020102);
1638 	WREG32(mmMME4_RTR_HBW_RD_RS_S_ARB, 0x01040102);
1639 	WREG32(mmMME3_RTR_HBW_RD_RS_S_ARB, 0x01060102);
1640 	WREG32(mmMME2_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1641 	WREG32(mmMME1_RTR_HBW_RD_RS_S_ARB, 0x01070102);
1642 	WREG32(mmMME6_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1643 	WREG32(mmMME5_RTR_HBW_RD_RS_E_ARB, 0x01020702);
1644 	WREG32(mmMME4_RTR_HBW_RD_RS_E_ARB, 0x01040602);
1645 	WREG32(mmMME3_RTR_HBW_RD_RS_E_ARB, 0x01060402);
1646 	WREG32(mmMME2_RTR_HBW_RD_RS_E_ARB, 0x01070202);
1647 	WREG32(mmMME1_RTR_HBW_RD_RS_E_ARB, 0x01070102);
1648 	WREG32(mmMME6_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1649 	WREG32(mmMME5_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1650 	WREG32(mmMME4_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1651 	WREG32(mmMME3_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1652 	WREG32(mmMME2_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1653 	WREG32(mmMME1_RTR_HBW_RD_RS_W_ARB, 0x01060401);
1654 	WREG32(mmMME6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1655 	WREG32(mmMME5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1656 	WREG32(mmMME4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1657 	WREG32(mmMME3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1658 	WREG32(mmMME2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1659 	WREG32(mmMME1_RTR_HBW_WR_RS_N_ARB, 0x01010107);
1660 	WREG32(mmMME6_RTR_HBW_WR_RS_S_ARB, 0x01010107);
1661 	WREG32(mmMME5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1662 	WREG32(mmMME4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1663 	WREG32(mmMME3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1664 	WREG32(mmMME2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1665 	WREG32(mmMME1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1666 	WREG32(mmMME6_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1667 	WREG32(mmMME5_RTR_HBW_WR_RS_E_ARB, 0x01010501);
1668 	WREG32(mmMME4_RTR_HBW_WR_RS_E_ARB, 0x01040301);
1669 	WREG32(mmMME3_RTR_HBW_WR_RS_E_ARB, 0x01030401);
1670 	WREG32(mmMME2_RTR_HBW_WR_RS_E_ARB, 0x01040101);
1671 	WREG32(mmMME1_RTR_HBW_WR_RS_E_ARB, 0x01050101);
1672 	WREG32(mmMME6_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1673 	WREG32(mmMME5_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1674 	WREG32(mmMME4_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1675 	WREG32(mmMME3_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1676 	WREG32(mmMME2_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1677 	WREG32(mmMME1_RTR_HBW_WR_RS_W_ARB, 0x01010101);
1678 
1679 	WREG32(mmTPC1_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1680 	WREG32(mmTPC1_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1681 	WREG32(mmTPC1_RTR_HBW_RD_RQ_E_ARB, 0x01060101);
1682 	WREG32(mmTPC1_RTR_HBW_WR_RQ_N_ARB, 0x02020102);
1683 	WREG32(mmTPC1_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1684 	WREG32(mmTPC1_RTR_HBW_WR_RQ_E_ARB, 0x02070202);
1685 	WREG32(mmTPC1_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1686 	WREG32(mmTPC1_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1687 	WREG32(mmTPC1_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1688 	WREG32(mmTPC1_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1689 	WREG32(mmTPC1_RTR_HBW_WR_RS_S_ARB, 0x01050101);
1690 	WREG32(mmTPC1_RTR_HBW_WR_RS_W_ARB, 0x01050101);
1691 
1692 	WREG32(mmTPC2_RTR_HBW_RD_RQ_N_ARB, 0x01020101);
1693 	WREG32(mmTPC2_RTR_HBW_RD_RQ_S_ARB, 0x01050101);
1694 	WREG32(mmTPC2_RTR_HBW_RD_RQ_E_ARB, 0x01010201);
1695 	WREG32(mmTPC2_RTR_HBW_WR_RQ_N_ARB, 0x02040102);
1696 	WREG32(mmTPC2_RTR_HBW_WR_RQ_S_ARB, 0x01050101);
1697 	WREG32(mmTPC2_RTR_HBW_WR_RQ_E_ARB, 0x02060202);
1698 	WREG32(mmTPC2_RTR_HBW_RD_RS_N_ARB, 0x01020201);
1699 	WREG32(mmTPC2_RTR_HBW_RD_RS_S_ARB, 0x01070201);
1700 	WREG32(mmTPC2_RTR_HBW_RD_RS_W_ARB, 0x01070202);
1701 	WREG32(mmTPC2_RTR_HBW_WR_RS_N_ARB, 0x01010101);
1702 	WREG32(mmTPC2_RTR_HBW_WR_RS_S_ARB, 0x01040101);
1703 	WREG32(mmTPC2_RTR_HBW_WR_RS_W_ARB, 0x01040101);
1704 
1705 	WREG32(mmTPC3_RTR_HBW_RD_RQ_N_ARB, 0x01030101);
1706 	WREG32(mmTPC3_RTR_HBW_RD_RQ_S_ARB, 0x01040101);
1707 	WREG32(mmTPC3_RTR_HBW_RD_RQ_E_ARB, 0x01040301);
1708 	WREG32(mmTPC3_RTR_HBW_WR_RQ_N_ARB, 0x02060102);
1709 	WREG32(mmTPC3_RTR_HBW_WR_RQ_S_ARB, 0x01040101);
1710 	WREG32(mmTPC3_RTR_HBW_WR_RQ_E_ARB, 0x01040301);
1711 	WREG32(mmTPC3_RTR_HBW_RD_RS_N_ARB, 0x01040201);
1712 	WREG32(mmTPC3_RTR_HBW_RD_RS_S_ARB, 0x01060201);
1713 	WREG32(mmTPC3_RTR_HBW_RD_RS_W_ARB, 0x01060402);
1714 	WREG32(mmTPC3_RTR_HBW_WR_RS_N_ARB, 0x01020101);
1715 	WREG32(mmTPC3_RTR_HBW_WR_RS_S_ARB, 0x01030101);
1716 	WREG32(mmTPC3_RTR_HBW_WR_RS_W_ARB, 0x01030401);
1717 
1718 	WREG32(mmTPC4_RTR_HBW_RD_RQ_N_ARB, 0x01040101);
1719 	WREG32(mmTPC4_RTR_HBW_RD_RQ_S_ARB, 0x01030101);
1720 	WREG32(mmTPC4_RTR_HBW_RD_RQ_E_ARB, 0x01030401);
1721 	WREG32(mmTPC4_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1722 	WREG32(mmTPC4_RTR_HBW_WR_RQ_S_ARB, 0x01030101);
1723 	WREG32(mmTPC4_RTR_HBW_WR_RQ_E_ARB, 0x02060702);
1724 	WREG32(mmTPC4_RTR_HBW_RD_RS_N_ARB, 0x01060201);
1725 	WREG32(mmTPC4_RTR_HBW_RD_RS_S_ARB, 0x01040201);
1726 	WREG32(mmTPC4_RTR_HBW_RD_RS_W_ARB, 0x01040602);
1727 	WREG32(mmTPC4_RTR_HBW_WR_RS_N_ARB, 0x01030101);
1728 	WREG32(mmTPC4_RTR_HBW_WR_RS_S_ARB, 0x01020101);
1729 	WREG32(mmTPC4_RTR_HBW_WR_RS_W_ARB, 0x01040301);
1730 
1731 	WREG32(mmTPC5_RTR_HBW_RD_RQ_N_ARB, 0x01050101);
1732 	WREG32(mmTPC5_RTR_HBW_RD_RQ_S_ARB, 0x01020101);
1733 	WREG32(mmTPC5_RTR_HBW_RD_RQ_E_ARB, 0x01200501);
1734 	WREG32(mmTPC5_RTR_HBW_WR_RQ_N_ARB, 0x02070102);
1735 	WREG32(mmTPC5_RTR_HBW_WR_RQ_S_ARB, 0x01020101);
1736 	WREG32(mmTPC5_RTR_HBW_WR_RQ_E_ARB, 0x02020602);
1737 	WREG32(mmTPC5_RTR_HBW_RD_RS_N_ARB, 0x01070201);
1738 	WREG32(mmTPC5_RTR_HBW_RD_RS_S_ARB, 0x01020201);
1739 	WREG32(mmTPC5_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1740 	WREG32(mmTPC5_RTR_HBW_WR_RS_N_ARB, 0x01040101);
1741 	WREG32(mmTPC5_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1742 	WREG32(mmTPC5_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1743 
1744 	WREG32(mmTPC6_RTR_HBW_RD_RQ_N_ARB, 0x01010101);
1745 	WREG32(mmTPC6_RTR_HBW_RD_RQ_S_ARB, 0x01010101);
1746 	WREG32(mmTPC6_RTR_HBW_RD_RQ_E_ARB, 0x01010601);
1747 	WREG32(mmTPC6_RTR_HBW_WR_RQ_N_ARB, 0x01010101);
1748 	WREG32(mmTPC6_RTR_HBW_WR_RQ_S_ARB, 0x01010101);
1749 	WREG32(mmTPC6_RTR_HBW_WR_RQ_E_ARB, 0x02020702);
1750 	WREG32(mmTPC6_RTR_HBW_RD_RS_N_ARB, 0x01010101);
1751 	WREG32(mmTPC6_RTR_HBW_RD_RS_S_ARB, 0x01010101);
1752 	WREG32(mmTPC6_RTR_HBW_RD_RS_W_ARB, 0x01020702);
1753 	WREG32(mmTPC6_RTR_HBW_WR_RS_N_ARB, 0x01050101);
1754 	WREG32(mmTPC6_RTR_HBW_WR_RS_S_ARB, 0x01010101);
1755 	WREG32(mmTPC6_RTR_HBW_WR_RS_W_ARB, 0x01010501);
1756 
1757 	for (i = 0, offset = 0 ; i < 10 ; i++, offset += 4) {
1758 		WREG32(mmMME1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1759 		WREG32(mmMME2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1760 		WREG32(mmMME3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1761 		WREG32(mmMME4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1762 		WREG32(mmMME5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1763 		WREG32(mmMME6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1764 
1765 		WREG32(mmTPC0_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1766 		WREG32(mmTPC1_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1767 		WREG32(mmTPC2_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1768 		WREG32(mmTPC3_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1769 		WREG32(mmTPC4_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1770 		WREG32(mmTPC5_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1771 		WREG32(mmTPC6_RTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1772 		WREG32(mmTPC7_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1773 
1774 		WREG32(mmPCI_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1775 		WREG32(mmDMA_NRTR_SPLIT_COEF_0 + offset, polynom[i] >> 7);
1776 	}
1777 
1778 	for (i = 0, offset = 0 ; i < 6 ; i++, offset += 0x40000) {
1779 		WREG32(mmMME1_RTR_SCRAMB_EN + offset,
1780 				1 << MME1_RTR_SCRAMB_EN_VAL_SHIFT);
1781 		WREG32(mmMME1_RTR_NON_LIN_SCRAMB + offset,
1782 				1 << MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT);
1783 	}
1784 
1785 	for (i = 0, offset = 0 ; i < 8 ; i++, offset += 0x40000) {
1786 		/*
1787 		 * Workaround for Bug H2 #2441 :
1788 		 * "ST.NOP set trace event illegal opcode"
1789 		 */
1790 		WREG32(mmTPC0_CFG_TPC_INTR_MASK + offset, tpc_intr_mask);
1791 
1792 		WREG32(mmTPC0_NRTR_SCRAMB_EN + offset,
1793 				1 << TPC0_NRTR_SCRAMB_EN_VAL_SHIFT);
1794 		WREG32(mmTPC0_NRTR_NON_LIN_SCRAMB + offset,
1795 				1 << TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1796 
1797 		WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset,
1798 				ICACHE_FETCH_LINE_NUM, 2);
1799 	}
1800 
1801 	WREG32(mmDMA_NRTR_SCRAMB_EN, 1 << DMA_NRTR_SCRAMB_EN_VAL_SHIFT);
1802 	WREG32(mmDMA_NRTR_NON_LIN_SCRAMB,
1803 			1 << DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1804 
1805 	WREG32(mmPCI_NRTR_SCRAMB_EN, 1 << PCI_NRTR_SCRAMB_EN_VAL_SHIFT);
1806 	WREG32(mmPCI_NRTR_NON_LIN_SCRAMB,
1807 			1 << PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT);
1808 
1809 	/*
1810 	 * Workaround for H2 #HW-23 bug
1811 	 * Set DMA max outstanding read requests to 240 on DMA CH 1.
1812 	 * This limitation is still large enough to not affect Gen4 bandwidth.
1813 	 * We need to only limit that DMA channel because the user can only read
1814 	 * from Host using DMA CH 1
1815 	 */
1816 	WREG32(mmDMA_CH_1_CFG0, 0x0fff00F0);
1817 
1818 	WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
1819 
1820 	goya->hw_cap_initialized |= HW_CAP_GOLDEN;
1821 }
1822 
1823 static void goya_init_mme_qman(struct hl_device *hdev)
1824 {
1825 	u32 mtr_base_lo, mtr_base_hi;
1826 	u32 so_base_lo, so_base_hi;
1827 	u32 gic_base_lo, gic_base_hi;
1828 	u64 qman_base_addr;
1829 
1830 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1831 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1832 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1833 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1834 
1835 	gic_base_lo =
1836 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1837 	gic_base_hi =
1838 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1839 
1840 	qman_base_addr = hdev->asic_prop.sram_base_address +
1841 				MME_QMAN_BASE_OFFSET;
1842 
1843 	WREG32(mmMME_QM_PQ_BASE_LO, lower_32_bits(qman_base_addr));
1844 	WREG32(mmMME_QM_PQ_BASE_HI, upper_32_bits(qman_base_addr));
1845 	WREG32(mmMME_QM_PQ_SIZE, ilog2(MME_QMAN_LENGTH));
1846 	WREG32(mmMME_QM_PQ_PI, 0);
1847 	WREG32(mmMME_QM_PQ_CI, 0);
1848 	WREG32(mmMME_QM_CP_LDMA_SRC_BASE_LO_OFFSET, 0x10C0);
1849 	WREG32(mmMME_QM_CP_LDMA_SRC_BASE_HI_OFFSET, 0x10C4);
1850 	WREG32(mmMME_QM_CP_LDMA_TSIZE_OFFSET, 0x10C8);
1851 	WREG32(mmMME_QM_CP_LDMA_COMMIT_OFFSET, 0x10CC);
1852 
1853 	WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1854 	WREG32(mmMME_QM_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1855 	WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_LO, so_base_lo);
1856 	WREG32(mmMME_QM_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1857 
1858 	/* QMAN CQ has 8 cache lines */
1859 	WREG32(mmMME_QM_CQ_CFG1, 0x00080008);
1860 
1861 	WREG32(mmMME_QM_GLBL_ERR_ADDR_LO, gic_base_lo);
1862 	WREG32(mmMME_QM_GLBL_ERR_ADDR_HI, gic_base_hi);
1863 
1864 	WREG32(mmMME_QM_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_QM);
1865 
1866 	WREG32(mmMME_QM_GLBL_ERR_CFG, QMAN_MME_ERR_MSG_EN);
1867 
1868 	WREG32(mmMME_QM_GLBL_PROT, QMAN_MME_ERR_PROT);
1869 
1870 	WREG32(mmMME_QM_GLBL_CFG0, QMAN_MME_ENABLE);
1871 }
1872 
1873 static void goya_init_mme_cmdq(struct hl_device *hdev)
1874 {
1875 	u32 mtr_base_lo, mtr_base_hi;
1876 	u32 so_base_lo, so_base_hi;
1877 	u32 gic_base_lo, gic_base_hi;
1878 
1879 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1880 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1881 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1882 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1883 
1884 	gic_base_lo =
1885 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1886 	gic_base_hi =
1887 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1888 
1889 	WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO, mtr_base_lo);
1890 	WREG32(mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI, mtr_base_hi);
1891 	WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO,	so_base_lo);
1892 	WREG32(mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI, so_base_hi);
1893 
1894 	/* CMDQ CQ has 20 cache lines */
1895 	WREG32(mmMME_CMDQ_CQ_CFG1, 0x00140014);
1896 
1897 	WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_LO, gic_base_lo);
1898 	WREG32(mmMME_CMDQ_GLBL_ERR_ADDR_HI, gic_base_hi);
1899 
1900 	WREG32(mmMME_CMDQ_GLBL_ERR_WDATA, GOYA_ASYNC_EVENT_ID_MME_CMDQ);
1901 
1902 	WREG32(mmMME_CMDQ_GLBL_ERR_CFG, CMDQ_MME_ERR_MSG_EN);
1903 
1904 	WREG32(mmMME_CMDQ_GLBL_PROT, CMDQ_MME_ERR_PROT);
1905 
1906 	WREG32(mmMME_CMDQ_GLBL_CFG0, CMDQ_MME_ENABLE);
1907 }
1908 
1909 void goya_init_mme_qmans(struct hl_device *hdev)
1910 {
1911 	struct goya_device *goya = hdev->asic_specific;
1912 	u32 so_base_lo, so_base_hi;
1913 
1914 	if (goya->hw_cap_initialized & HW_CAP_MME)
1915 		return;
1916 
1917 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1918 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1919 
1920 	WREG32(mmMME_SM_BASE_ADDRESS_LOW, so_base_lo);
1921 	WREG32(mmMME_SM_BASE_ADDRESS_HIGH, so_base_hi);
1922 
1923 	goya_init_mme_qman(hdev);
1924 	goya_init_mme_cmdq(hdev);
1925 
1926 	goya->hw_cap_initialized |= HW_CAP_MME;
1927 }
1928 
1929 static void goya_init_tpc_qman(struct hl_device *hdev, u32 base_off, int tpc_id)
1930 {
1931 	u32 mtr_base_lo, mtr_base_hi;
1932 	u32 so_base_lo, so_base_hi;
1933 	u32 gic_base_lo, gic_base_hi;
1934 	u64 qman_base_addr;
1935 	u32 reg_off = tpc_id * (mmTPC1_QM_PQ_PI - mmTPC0_QM_PQ_PI);
1936 
1937 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1938 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1939 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1940 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1941 
1942 	gic_base_lo =
1943 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1944 	gic_base_hi =
1945 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1946 
1947 	qman_base_addr = hdev->asic_prop.sram_base_address + base_off;
1948 
1949 	WREG32(mmTPC0_QM_PQ_BASE_LO + reg_off, lower_32_bits(qman_base_addr));
1950 	WREG32(mmTPC0_QM_PQ_BASE_HI + reg_off, upper_32_bits(qman_base_addr));
1951 	WREG32(mmTPC0_QM_PQ_SIZE + reg_off, ilog2(TPC_QMAN_LENGTH));
1952 	WREG32(mmTPC0_QM_PQ_PI + reg_off, 0);
1953 	WREG32(mmTPC0_QM_PQ_CI + reg_off, 0);
1954 	WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET + reg_off, 0x10C0);
1955 	WREG32(mmTPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET + reg_off, 0x10C4);
1956 	WREG32(mmTPC0_QM_CP_LDMA_TSIZE_OFFSET + reg_off, 0x10C8);
1957 	WREG32(mmTPC0_QM_CP_LDMA_COMMIT_OFFSET + reg_off, 0x10CC);
1958 
1959 	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1960 	WREG32(mmTPC0_QM_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1961 	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1962 	WREG32(mmTPC0_QM_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
1963 
1964 	WREG32(mmTPC0_QM_CQ_CFG1 + reg_off, 0x00080008);
1965 
1966 	WREG32(mmTPC0_QM_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
1967 	WREG32(mmTPC0_QM_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
1968 
1969 	WREG32(mmTPC0_QM_GLBL_ERR_WDATA + reg_off,
1970 			GOYA_ASYNC_EVENT_ID_TPC0_QM + tpc_id);
1971 
1972 	WREG32(mmTPC0_QM_GLBL_ERR_CFG + reg_off, QMAN_TPC_ERR_MSG_EN);
1973 
1974 	WREG32(mmTPC0_QM_GLBL_PROT + reg_off, QMAN_TPC_ERR_PROT);
1975 
1976 	WREG32(mmTPC0_QM_GLBL_CFG0 + reg_off, QMAN_TPC_ENABLE);
1977 }
1978 
1979 static void goya_init_tpc_cmdq(struct hl_device *hdev, int tpc_id)
1980 {
1981 	u32 mtr_base_lo, mtr_base_hi;
1982 	u32 so_base_lo, so_base_hi;
1983 	u32 gic_base_lo, gic_base_hi;
1984 	u32 reg_off = tpc_id * (mmTPC1_CMDQ_CQ_CFG1 - mmTPC0_CMDQ_CQ_CFG1);
1985 
1986 	mtr_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1987 	mtr_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_MON_PAY_ADDRL_0);
1988 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1989 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
1990 
1991 	gic_base_lo =
1992 		lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1993 	gic_base_hi =
1994 		upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR);
1995 
1996 	WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO + reg_off, mtr_base_lo);
1997 	WREG32(mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI + reg_off, mtr_base_hi);
1998 	WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO + reg_off, so_base_lo);
1999 	WREG32(mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI + reg_off, so_base_hi);
2000 
2001 	WREG32(mmTPC0_CMDQ_CQ_CFG1 + reg_off, 0x00140014);
2002 
2003 	WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_LO + reg_off, gic_base_lo);
2004 	WREG32(mmTPC0_CMDQ_GLBL_ERR_ADDR_HI + reg_off, gic_base_hi);
2005 
2006 	WREG32(mmTPC0_CMDQ_GLBL_ERR_WDATA + reg_off,
2007 			GOYA_ASYNC_EVENT_ID_TPC0_CMDQ + tpc_id);
2008 
2009 	WREG32(mmTPC0_CMDQ_GLBL_ERR_CFG + reg_off, CMDQ_TPC_ERR_MSG_EN);
2010 
2011 	WREG32(mmTPC0_CMDQ_GLBL_PROT + reg_off, CMDQ_TPC_ERR_PROT);
2012 
2013 	WREG32(mmTPC0_CMDQ_GLBL_CFG0 + reg_off, CMDQ_TPC_ENABLE);
2014 }
2015 
2016 void goya_init_tpc_qmans(struct hl_device *hdev)
2017 {
2018 	struct goya_device *goya = hdev->asic_specific;
2019 	u32 so_base_lo, so_base_hi;
2020 	u32 cfg_off = mmTPC1_CFG_SM_BASE_ADDRESS_LOW -
2021 			mmTPC0_CFG_SM_BASE_ADDRESS_LOW;
2022 	int i;
2023 
2024 	if (goya->hw_cap_initialized & HW_CAP_TPC)
2025 		return;
2026 
2027 	so_base_lo = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2028 	so_base_hi = upper_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
2029 
2030 	for (i = 0 ; i < TPC_MAX_NUM ; i++) {
2031 		WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_LOW + i * cfg_off,
2032 				so_base_lo);
2033 		WREG32(mmTPC0_CFG_SM_BASE_ADDRESS_HIGH + i * cfg_off,
2034 				so_base_hi);
2035 	}
2036 
2037 	goya_init_tpc_qman(hdev, TPC0_QMAN_BASE_OFFSET, 0);
2038 	goya_init_tpc_qman(hdev, TPC1_QMAN_BASE_OFFSET, 1);
2039 	goya_init_tpc_qman(hdev, TPC2_QMAN_BASE_OFFSET, 2);
2040 	goya_init_tpc_qman(hdev, TPC3_QMAN_BASE_OFFSET, 3);
2041 	goya_init_tpc_qman(hdev, TPC4_QMAN_BASE_OFFSET, 4);
2042 	goya_init_tpc_qman(hdev, TPC5_QMAN_BASE_OFFSET, 5);
2043 	goya_init_tpc_qman(hdev, TPC6_QMAN_BASE_OFFSET, 6);
2044 	goya_init_tpc_qman(hdev, TPC7_QMAN_BASE_OFFSET, 7);
2045 
2046 	for (i = 0 ; i < TPC_MAX_NUM ; i++)
2047 		goya_init_tpc_cmdq(hdev, i);
2048 
2049 	goya->hw_cap_initialized |= HW_CAP_TPC;
2050 }
2051 
2052 /*
2053  * goya_disable_internal_queues - Disable internal queues
2054  *
2055  * @hdev: pointer to hl_device structure
2056  *
2057  */
2058 static void goya_disable_internal_queues(struct hl_device *hdev)
2059 {
2060 	struct goya_device *goya = hdev->asic_specific;
2061 
2062 	if (!(goya->hw_cap_initialized & HW_CAP_MME))
2063 		goto disable_tpc;
2064 
2065 	WREG32(mmMME_QM_GLBL_CFG0, 0);
2066 	WREG32(mmMME_CMDQ_GLBL_CFG0, 0);
2067 
2068 disable_tpc:
2069 	if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2070 		return;
2071 
2072 	WREG32(mmTPC0_QM_GLBL_CFG0, 0);
2073 	WREG32(mmTPC0_CMDQ_GLBL_CFG0, 0);
2074 
2075 	WREG32(mmTPC1_QM_GLBL_CFG0, 0);
2076 	WREG32(mmTPC1_CMDQ_GLBL_CFG0, 0);
2077 
2078 	WREG32(mmTPC2_QM_GLBL_CFG0, 0);
2079 	WREG32(mmTPC2_CMDQ_GLBL_CFG0, 0);
2080 
2081 	WREG32(mmTPC3_QM_GLBL_CFG0, 0);
2082 	WREG32(mmTPC3_CMDQ_GLBL_CFG0, 0);
2083 
2084 	WREG32(mmTPC4_QM_GLBL_CFG0, 0);
2085 	WREG32(mmTPC4_CMDQ_GLBL_CFG0, 0);
2086 
2087 	WREG32(mmTPC5_QM_GLBL_CFG0, 0);
2088 	WREG32(mmTPC5_CMDQ_GLBL_CFG0, 0);
2089 
2090 	WREG32(mmTPC6_QM_GLBL_CFG0, 0);
2091 	WREG32(mmTPC6_CMDQ_GLBL_CFG0, 0);
2092 
2093 	WREG32(mmTPC7_QM_GLBL_CFG0, 0);
2094 	WREG32(mmTPC7_CMDQ_GLBL_CFG0, 0);
2095 }
2096 
2097 /*
2098  * goya_stop_internal_queues - Stop internal queues
2099  *
2100  * @hdev: pointer to hl_device structure
2101  *
2102  * Returns 0 on success
2103  *
2104  */
2105 static int goya_stop_internal_queues(struct hl_device *hdev)
2106 {
2107 	struct goya_device *goya = hdev->asic_specific;
2108 	int rc, retval = 0;
2109 
2110 	if (!(goya->hw_cap_initialized & HW_CAP_MME))
2111 		goto stop_tpc;
2112 
2113 	/*
2114 	 * Each queue (QMAN) is a separate H/W logic. That means that each
2115 	 * QMAN can be stopped independently and failure to stop one does NOT
2116 	 * mandate we should not try to stop other QMANs
2117 	 */
2118 
2119 	rc = goya_stop_queue(hdev,
2120 			mmMME_QM_GLBL_CFG1,
2121 			mmMME_QM_CP_STS,
2122 			mmMME_QM_GLBL_STS0);
2123 
2124 	if (rc) {
2125 		dev_err(hdev->dev, "failed to stop MME QMAN\n");
2126 		retval = -EIO;
2127 	}
2128 
2129 	rc = goya_stop_queue(hdev,
2130 			mmMME_CMDQ_GLBL_CFG1,
2131 			mmMME_CMDQ_CP_STS,
2132 			mmMME_CMDQ_GLBL_STS0);
2133 
2134 	if (rc) {
2135 		dev_err(hdev->dev, "failed to stop MME CMDQ\n");
2136 		retval = -EIO;
2137 	}
2138 
2139 stop_tpc:
2140 	if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2141 		return retval;
2142 
2143 	rc = goya_stop_queue(hdev,
2144 			mmTPC0_QM_GLBL_CFG1,
2145 			mmTPC0_QM_CP_STS,
2146 			mmTPC0_QM_GLBL_STS0);
2147 
2148 	if (rc) {
2149 		dev_err(hdev->dev, "failed to stop TPC 0 QMAN\n");
2150 		retval = -EIO;
2151 	}
2152 
2153 	rc = goya_stop_queue(hdev,
2154 			mmTPC0_CMDQ_GLBL_CFG1,
2155 			mmTPC0_CMDQ_CP_STS,
2156 			mmTPC0_CMDQ_GLBL_STS0);
2157 
2158 	if (rc) {
2159 		dev_err(hdev->dev, "failed to stop TPC 0 CMDQ\n");
2160 		retval = -EIO;
2161 	}
2162 
2163 	rc = goya_stop_queue(hdev,
2164 			mmTPC1_QM_GLBL_CFG1,
2165 			mmTPC1_QM_CP_STS,
2166 			mmTPC1_QM_GLBL_STS0);
2167 
2168 	if (rc) {
2169 		dev_err(hdev->dev, "failed to stop TPC 1 QMAN\n");
2170 		retval = -EIO;
2171 	}
2172 
2173 	rc = goya_stop_queue(hdev,
2174 			mmTPC1_CMDQ_GLBL_CFG1,
2175 			mmTPC1_CMDQ_CP_STS,
2176 			mmTPC1_CMDQ_GLBL_STS0);
2177 
2178 	if (rc) {
2179 		dev_err(hdev->dev, "failed to stop TPC 1 CMDQ\n");
2180 		retval = -EIO;
2181 	}
2182 
2183 	rc = goya_stop_queue(hdev,
2184 			mmTPC2_QM_GLBL_CFG1,
2185 			mmTPC2_QM_CP_STS,
2186 			mmTPC2_QM_GLBL_STS0);
2187 
2188 	if (rc) {
2189 		dev_err(hdev->dev, "failed to stop TPC 2 QMAN\n");
2190 		retval = -EIO;
2191 	}
2192 
2193 	rc = goya_stop_queue(hdev,
2194 			mmTPC2_CMDQ_GLBL_CFG1,
2195 			mmTPC2_CMDQ_CP_STS,
2196 			mmTPC2_CMDQ_GLBL_STS0);
2197 
2198 	if (rc) {
2199 		dev_err(hdev->dev, "failed to stop TPC 2 CMDQ\n");
2200 		retval = -EIO;
2201 	}
2202 
2203 	rc = goya_stop_queue(hdev,
2204 			mmTPC3_QM_GLBL_CFG1,
2205 			mmTPC3_QM_CP_STS,
2206 			mmTPC3_QM_GLBL_STS0);
2207 
2208 	if (rc) {
2209 		dev_err(hdev->dev, "failed to stop TPC 3 QMAN\n");
2210 		retval = -EIO;
2211 	}
2212 
2213 	rc = goya_stop_queue(hdev,
2214 			mmTPC3_CMDQ_GLBL_CFG1,
2215 			mmTPC3_CMDQ_CP_STS,
2216 			mmTPC3_CMDQ_GLBL_STS0);
2217 
2218 	if (rc) {
2219 		dev_err(hdev->dev, "failed to stop TPC 3 CMDQ\n");
2220 		retval = -EIO;
2221 	}
2222 
2223 	rc = goya_stop_queue(hdev,
2224 			mmTPC4_QM_GLBL_CFG1,
2225 			mmTPC4_QM_CP_STS,
2226 			mmTPC4_QM_GLBL_STS0);
2227 
2228 	if (rc) {
2229 		dev_err(hdev->dev, "failed to stop TPC 4 QMAN\n");
2230 		retval = -EIO;
2231 	}
2232 
2233 	rc = goya_stop_queue(hdev,
2234 			mmTPC4_CMDQ_GLBL_CFG1,
2235 			mmTPC4_CMDQ_CP_STS,
2236 			mmTPC4_CMDQ_GLBL_STS0);
2237 
2238 	if (rc) {
2239 		dev_err(hdev->dev, "failed to stop TPC 4 CMDQ\n");
2240 		retval = -EIO;
2241 	}
2242 
2243 	rc = goya_stop_queue(hdev,
2244 			mmTPC5_QM_GLBL_CFG1,
2245 			mmTPC5_QM_CP_STS,
2246 			mmTPC5_QM_GLBL_STS0);
2247 
2248 	if (rc) {
2249 		dev_err(hdev->dev, "failed to stop TPC 5 QMAN\n");
2250 		retval = -EIO;
2251 	}
2252 
2253 	rc = goya_stop_queue(hdev,
2254 			mmTPC5_CMDQ_GLBL_CFG1,
2255 			mmTPC5_CMDQ_CP_STS,
2256 			mmTPC5_CMDQ_GLBL_STS0);
2257 
2258 	if (rc) {
2259 		dev_err(hdev->dev, "failed to stop TPC 5 CMDQ\n");
2260 		retval = -EIO;
2261 	}
2262 
2263 	rc = goya_stop_queue(hdev,
2264 			mmTPC6_QM_GLBL_CFG1,
2265 			mmTPC6_QM_CP_STS,
2266 			mmTPC6_QM_GLBL_STS0);
2267 
2268 	if (rc) {
2269 		dev_err(hdev->dev, "failed to stop TPC 6 QMAN\n");
2270 		retval = -EIO;
2271 	}
2272 
2273 	rc = goya_stop_queue(hdev,
2274 			mmTPC6_CMDQ_GLBL_CFG1,
2275 			mmTPC6_CMDQ_CP_STS,
2276 			mmTPC6_CMDQ_GLBL_STS0);
2277 
2278 	if (rc) {
2279 		dev_err(hdev->dev, "failed to stop TPC 6 CMDQ\n");
2280 		retval = -EIO;
2281 	}
2282 
2283 	rc = goya_stop_queue(hdev,
2284 			mmTPC7_QM_GLBL_CFG1,
2285 			mmTPC7_QM_CP_STS,
2286 			mmTPC7_QM_GLBL_STS0);
2287 
2288 	if (rc) {
2289 		dev_err(hdev->dev, "failed to stop TPC 7 QMAN\n");
2290 		retval = -EIO;
2291 	}
2292 
2293 	rc = goya_stop_queue(hdev,
2294 			mmTPC7_CMDQ_GLBL_CFG1,
2295 			mmTPC7_CMDQ_CP_STS,
2296 			mmTPC7_CMDQ_GLBL_STS0);
2297 
2298 	if (rc) {
2299 		dev_err(hdev->dev, "failed to stop TPC 7 CMDQ\n");
2300 		retval = -EIO;
2301 	}
2302 
2303 	return retval;
2304 }
2305 
2306 static void goya_dma_stall(struct hl_device *hdev)
2307 {
2308 	struct goya_device *goya = hdev->asic_specific;
2309 
2310 	if (!(goya->hw_cap_initialized & HW_CAP_DMA))
2311 		return;
2312 
2313 	WREG32(mmDMA_QM_0_GLBL_CFG1, 1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT);
2314 	WREG32(mmDMA_QM_1_GLBL_CFG1, 1 << DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT);
2315 	WREG32(mmDMA_QM_2_GLBL_CFG1, 1 << DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT);
2316 	WREG32(mmDMA_QM_3_GLBL_CFG1, 1 << DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT);
2317 	WREG32(mmDMA_QM_4_GLBL_CFG1, 1 << DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT);
2318 }
2319 
2320 static void goya_tpc_stall(struct hl_device *hdev)
2321 {
2322 	struct goya_device *goya = hdev->asic_specific;
2323 
2324 	if (!(goya->hw_cap_initialized & HW_CAP_TPC))
2325 		return;
2326 
2327 	WREG32(mmTPC0_CFG_TPC_STALL, 1 << TPC0_CFG_TPC_STALL_V_SHIFT);
2328 	WREG32(mmTPC1_CFG_TPC_STALL, 1 << TPC1_CFG_TPC_STALL_V_SHIFT);
2329 	WREG32(mmTPC2_CFG_TPC_STALL, 1 << TPC2_CFG_TPC_STALL_V_SHIFT);
2330 	WREG32(mmTPC3_CFG_TPC_STALL, 1 << TPC3_CFG_TPC_STALL_V_SHIFT);
2331 	WREG32(mmTPC4_CFG_TPC_STALL, 1 << TPC4_CFG_TPC_STALL_V_SHIFT);
2332 	WREG32(mmTPC5_CFG_TPC_STALL, 1 << TPC5_CFG_TPC_STALL_V_SHIFT);
2333 	WREG32(mmTPC6_CFG_TPC_STALL, 1 << TPC6_CFG_TPC_STALL_V_SHIFT);
2334 	WREG32(mmTPC7_CFG_TPC_STALL, 1 << TPC7_CFG_TPC_STALL_V_SHIFT);
2335 }
2336 
2337 static void goya_mme_stall(struct hl_device *hdev)
2338 {
2339 	struct goya_device *goya = hdev->asic_specific;
2340 
2341 	if (!(goya->hw_cap_initialized & HW_CAP_MME))
2342 		return;
2343 
2344 	WREG32(mmMME_STALL, 0xFFFFFFFF);
2345 }
2346 
2347 static int goya_enable_msix(struct hl_device *hdev)
2348 {
2349 	struct goya_device *goya = hdev->asic_specific;
2350 	int cq_cnt = hdev->asic_prop.completion_queues_count;
2351 	int rc, i, irq_cnt_init, irq;
2352 
2353 	if (goya->hw_cap_initialized & HW_CAP_MSIX)
2354 		return 0;
2355 
2356 	rc = pci_alloc_irq_vectors(hdev->pdev, GOYA_MSIX_ENTRIES,
2357 				GOYA_MSIX_ENTRIES, PCI_IRQ_MSIX);
2358 	if (rc < 0) {
2359 		dev_err(hdev->dev,
2360 			"MSI-X: Failed to enable support -- %d/%d\n",
2361 			GOYA_MSIX_ENTRIES, rc);
2362 		return rc;
2363 	}
2364 
2365 	for (i = 0, irq_cnt_init = 0 ; i < cq_cnt ; i++, irq_cnt_init++) {
2366 		irq = pci_irq_vector(hdev->pdev, i);
2367 		rc = request_irq(irq, hl_irq_handler_cq, 0, goya_irq_name[i],
2368 				&hdev->completion_queue[i]);
2369 		if (rc) {
2370 			dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2371 			goto free_irqs;
2372 		}
2373 	}
2374 
2375 	irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2376 
2377 	rc = request_irq(irq, hl_irq_handler_eq, 0,
2378 			goya_irq_name[GOYA_EVENT_QUEUE_MSIX_IDX],
2379 			&hdev->event_queue);
2380 	if (rc) {
2381 		dev_err(hdev->dev, "Failed to request IRQ %d", irq);
2382 		goto free_irqs;
2383 	}
2384 
2385 	goya->hw_cap_initialized |= HW_CAP_MSIX;
2386 	return 0;
2387 
2388 free_irqs:
2389 	for (i = 0 ; i < irq_cnt_init ; i++)
2390 		free_irq(pci_irq_vector(hdev->pdev, i),
2391 			&hdev->completion_queue[i]);
2392 
2393 	pci_free_irq_vectors(hdev->pdev);
2394 	return rc;
2395 }
2396 
2397 static void goya_sync_irqs(struct hl_device *hdev)
2398 {
2399 	struct goya_device *goya = hdev->asic_specific;
2400 	int i;
2401 
2402 	if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2403 		return;
2404 
2405 	/* Wait for all pending IRQs to be finished */
2406 	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
2407 		synchronize_irq(pci_irq_vector(hdev->pdev, i));
2408 
2409 	synchronize_irq(pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX));
2410 }
2411 
2412 static void goya_disable_msix(struct hl_device *hdev)
2413 {
2414 	struct goya_device *goya = hdev->asic_specific;
2415 	int i, irq;
2416 
2417 	if (!(goya->hw_cap_initialized & HW_CAP_MSIX))
2418 		return;
2419 
2420 	goya_sync_irqs(hdev);
2421 
2422 	irq = pci_irq_vector(hdev->pdev, GOYA_EVENT_QUEUE_MSIX_IDX);
2423 	free_irq(irq, &hdev->event_queue);
2424 
2425 	for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
2426 		irq = pci_irq_vector(hdev->pdev, i);
2427 		free_irq(irq, &hdev->completion_queue[i]);
2428 	}
2429 
2430 	pci_free_irq_vectors(hdev->pdev);
2431 
2432 	goya->hw_cap_initialized &= ~HW_CAP_MSIX;
2433 }
2434 
2435 static void goya_enable_timestamp(struct hl_device *hdev)
2436 {
2437 	/* Disable the timestamp counter */
2438 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2439 
2440 	/* Zero the lower/upper parts of the 64-bit counter */
2441 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0xC, 0);
2442 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE + 0x8, 0);
2443 
2444 	/* Enable the counter */
2445 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 1);
2446 }
2447 
2448 static void goya_disable_timestamp(struct hl_device *hdev)
2449 {
2450 	/* Disable the timestamp counter */
2451 	WREG32(mmPSOC_TIMESTAMP_BASE - CFG_BASE, 0);
2452 }
2453 
2454 static void goya_halt_engines(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2455 {
2456 	u32 wait_timeout_ms;
2457 
2458 	if (hdev->pldm)
2459 		wait_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2460 	else
2461 		wait_timeout_ms = GOYA_RESET_WAIT_MSEC;
2462 
2463 	goya_stop_external_queues(hdev);
2464 	goya_stop_internal_queues(hdev);
2465 
2466 	msleep(wait_timeout_ms);
2467 
2468 	goya_dma_stall(hdev);
2469 	goya_tpc_stall(hdev);
2470 	goya_mme_stall(hdev);
2471 
2472 	msleep(wait_timeout_ms);
2473 
2474 	goya_disable_external_queues(hdev);
2475 	goya_disable_internal_queues(hdev);
2476 
2477 	goya_disable_timestamp(hdev);
2478 
2479 	if (hard_reset) {
2480 		goya_disable_msix(hdev);
2481 		goya_mmu_remove_device_cpu_mappings(hdev);
2482 	} else {
2483 		goya_sync_irqs(hdev);
2484 	}
2485 }
2486 
2487 /*
2488  * goya_load_firmware_to_device() - Load LINUX FW code to device.
2489  * @hdev: Pointer to hl_device structure.
2490  *
2491  * Copy LINUX fw code from firmware file to HBM BAR.
2492  *
2493  * Return: 0 on success, non-zero for failure.
2494  */
2495 static int goya_load_firmware_to_device(struct hl_device *hdev)
2496 {
2497 	void __iomem *dst;
2498 
2499 	dst = hdev->pcie_bar[DDR_BAR_ID] + LINUX_FW_OFFSET;
2500 
2501 	return hl_fw_load_fw_to_device(hdev, GOYA_LINUX_FW_FILE, dst, 0, 0);
2502 }
2503 
2504 /*
2505  * goya_load_boot_fit_to_device() - Load boot fit to device.
2506  * @hdev: Pointer to hl_device structure.
2507  *
2508  * Copy boot fit file to SRAM BAR.
2509  *
2510  * Return: 0 on success, non-zero for failure.
2511  */
2512 static int goya_load_boot_fit_to_device(struct hl_device *hdev)
2513 {
2514 	void __iomem *dst;
2515 
2516 	dst = hdev->pcie_bar[SRAM_CFG_BAR_ID] + BOOT_FIT_SRAM_OFFSET;
2517 
2518 	return hl_fw_load_fw_to_device(hdev, GOYA_BOOT_FIT_FILE, dst, 0, 0);
2519 }
2520 
2521 static void goya_init_dynamic_firmware_loader(struct hl_device *hdev)
2522 {
2523 	struct dynamic_fw_load_mgr *dynamic_loader;
2524 	struct cpu_dyn_regs *dyn_regs;
2525 
2526 	dynamic_loader = &hdev->fw_loader.dynamic_loader;
2527 
2528 	/*
2529 	 * here we update initial values for few specific dynamic regs (as
2530 	 * before reading the first descriptor from FW those value has to be
2531 	 * hard-coded) in later stages of the protocol those values will be
2532 	 * updated automatically by reading the FW descriptor so data there
2533 	 * will always be up-to-date
2534 	 */
2535 	dyn_regs = &dynamic_loader->comm_desc.cpu_dyn_regs;
2536 	dyn_regs->kmd_msg_to_cpu =
2537 				cpu_to_le32(mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU);
2538 	dyn_regs->cpu_cmd_status_to_host =
2539 				cpu_to_le32(mmCPU_CMD_STATUS_TO_HOST);
2540 
2541 	dynamic_loader->wait_for_bl_timeout = GOYA_WAIT_FOR_BL_TIMEOUT_USEC;
2542 }
2543 
2544 static void goya_init_static_firmware_loader(struct hl_device *hdev)
2545 {
2546 	struct static_fw_load_mgr *static_loader;
2547 
2548 	static_loader = &hdev->fw_loader.static_loader;
2549 
2550 	static_loader->preboot_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2551 	static_loader->boot_fit_version_max_off = SRAM_SIZE - VERSION_MAX_LEN;
2552 	static_loader->kmd_msg_to_cpu_reg = mmPSOC_GLOBAL_CONF_KMD_MSG_TO_CPU;
2553 	static_loader->cpu_cmd_status_to_host_reg = mmCPU_CMD_STATUS_TO_HOST;
2554 	static_loader->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2555 	static_loader->cpu_boot_dev_status0_reg = mmCPU_BOOT_DEV_STS0;
2556 	static_loader->cpu_boot_dev_status1_reg = mmCPU_BOOT_DEV_STS1;
2557 	static_loader->boot_err0_reg = mmCPU_BOOT_ERR0;
2558 	static_loader->boot_err1_reg = mmCPU_BOOT_ERR1;
2559 	static_loader->preboot_version_offset_reg = mmPREBOOT_VER_OFFSET;
2560 	static_loader->boot_fit_version_offset_reg = mmUBOOT_VER_OFFSET;
2561 	static_loader->sram_offset_mask = ~(lower_32_bits(SRAM_BASE_ADDR));
2562 }
2563 
2564 static void goya_init_firmware_preload_params(struct hl_device *hdev)
2565 {
2566 	struct pre_fw_load_props *pre_fw_load = &hdev->fw_loader.pre_fw_load;
2567 
2568 	pre_fw_load->cpu_boot_status_reg = mmPSOC_GLOBAL_CONF_CPU_BOOT_STATUS;
2569 	pre_fw_load->sts_boot_dev_sts0_reg = mmCPU_BOOT_DEV_STS0;
2570 	pre_fw_load->sts_boot_dev_sts1_reg = mmCPU_BOOT_DEV_STS1;
2571 	pre_fw_load->boot_err0_reg = mmCPU_BOOT_ERR0;
2572 	pre_fw_load->boot_err1_reg = mmCPU_BOOT_ERR1;
2573 	pre_fw_load->wait_for_preboot_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2574 }
2575 
2576 static void goya_init_firmware_loader(struct hl_device *hdev)
2577 {
2578 	struct asic_fixed_properties *prop = &hdev->asic_prop;
2579 	struct fw_load_mgr *fw_loader = &hdev->fw_loader;
2580 
2581 	/* fill common fields */
2582 	fw_loader->fw_comp_loaded = FW_TYPE_NONE;
2583 	fw_loader->boot_fit_img.image_name = GOYA_BOOT_FIT_FILE;
2584 	fw_loader->linux_img.image_name = GOYA_LINUX_FW_FILE;
2585 	fw_loader->cpu_timeout = GOYA_CPU_TIMEOUT_USEC;
2586 	fw_loader->boot_fit_timeout = GOYA_BOOT_FIT_REQ_TIMEOUT_USEC;
2587 	fw_loader->skip_bmc = false;
2588 	fw_loader->sram_bar_id = SRAM_CFG_BAR_ID;
2589 	fw_loader->dram_bar_id = DDR_BAR_ID;
2590 
2591 	if (prop->dynamic_fw_load)
2592 		goya_init_dynamic_firmware_loader(hdev);
2593 	else
2594 		goya_init_static_firmware_loader(hdev);
2595 }
2596 
2597 static int goya_init_cpu(struct hl_device *hdev)
2598 {
2599 	struct goya_device *goya = hdev->asic_specific;
2600 	int rc;
2601 
2602 	if (!(hdev->fw_components & FW_TYPE_PREBOOT_CPU))
2603 		return 0;
2604 
2605 	if (goya->hw_cap_initialized & HW_CAP_CPU)
2606 		return 0;
2607 
2608 	/*
2609 	 * Before pushing u-boot/linux to device, need to set the ddr bar to
2610 	 * base address of dram
2611 	 */
2612 	if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
2613 		dev_err(hdev->dev,
2614 			"failed to map DDR bar to DRAM base address\n");
2615 		return -EIO;
2616 	}
2617 
2618 	rc = hl_fw_init_cpu(hdev);
2619 
2620 	if (rc)
2621 		return rc;
2622 
2623 	goya->hw_cap_initialized |= HW_CAP_CPU;
2624 
2625 	return 0;
2626 }
2627 
2628 static int goya_mmu_update_asid_hop0_addr(struct hl_device *hdev, u32 asid,
2629 						u64 phys_addr)
2630 {
2631 	u32 status, timeout_usec;
2632 	int rc;
2633 
2634 	if (hdev->pldm)
2635 		timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
2636 	else
2637 		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
2638 
2639 	WREG32(MMU_HOP0_PA43_12, phys_addr >> MMU_HOP0_PA43_12_SHIFT);
2640 	WREG32(MMU_HOP0_PA49_44, phys_addr >> MMU_HOP0_PA49_44_SHIFT);
2641 	WREG32(MMU_ASID_BUSY, 0x80000000 | asid);
2642 
2643 	rc = hl_poll_timeout(
2644 		hdev,
2645 		MMU_ASID_BUSY,
2646 		status,
2647 		!(status & 0x80000000),
2648 		1000,
2649 		timeout_usec);
2650 
2651 	if (rc) {
2652 		dev_err(hdev->dev,
2653 			"Timeout during MMU hop0 config of asid %d\n", asid);
2654 		return rc;
2655 	}
2656 
2657 	return 0;
2658 }
2659 
2660 int goya_mmu_init(struct hl_device *hdev)
2661 {
2662 	struct asic_fixed_properties *prop = &hdev->asic_prop;
2663 	struct goya_device *goya = hdev->asic_specific;
2664 	u64 hop0_addr;
2665 	int rc, i;
2666 
2667 	if (!hdev->mmu_enable)
2668 		return 0;
2669 
2670 	if (goya->hw_cap_initialized & HW_CAP_MMU)
2671 		return 0;
2672 
2673 	hdev->dram_default_page_mapping = true;
2674 
2675 	for (i = 0 ; i < prop->max_asid ; i++) {
2676 		hop0_addr = prop->mmu_pgt_addr +
2677 				(i * prop->mmu_hop_table_size);
2678 
2679 		rc = goya_mmu_update_asid_hop0_addr(hdev, i, hop0_addr);
2680 		if (rc) {
2681 			dev_err(hdev->dev,
2682 				"failed to set hop0 addr for asid %d\n", i);
2683 			goto err;
2684 		}
2685 	}
2686 
2687 	goya->hw_cap_initialized |= HW_CAP_MMU;
2688 
2689 	/* init MMU cache manage page */
2690 	WREG32(mmSTLB_CACHE_INV_BASE_39_8,
2691 				lower_32_bits(MMU_CACHE_MNG_ADDR >> 8));
2692 	WREG32(mmSTLB_CACHE_INV_BASE_49_40, MMU_CACHE_MNG_ADDR >> 40);
2693 
2694 	/* Remove follower feature due to performance bug */
2695 	WREG32_AND(mmSTLB_STLB_FEATURE_EN,
2696 			(~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK));
2697 
2698 	hl_mmu_invalidate_cache(hdev, true, MMU_OP_USERPTR | MMU_OP_PHYS_PACK);
2699 
2700 	WREG32(mmMMU_MMU_ENABLE, 1);
2701 	WREG32(mmMMU_SPI_MASK, 0xF);
2702 
2703 	return 0;
2704 
2705 err:
2706 	return rc;
2707 }
2708 
2709 /*
2710  * goya_hw_init - Goya hardware initialization code
2711  *
2712  * @hdev: pointer to hl_device structure
2713  *
2714  * Returns 0 on success
2715  *
2716  */
2717 static int goya_hw_init(struct hl_device *hdev)
2718 {
2719 	struct asic_fixed_properties *prop = &hdev->asic_prop;
2720 	int rc;
2721 
2722 	/* Perform read from the device to make sure device is up */
2723 	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2724 
2725 	/*
2726 	 * Let's mark in the H/W that we have reached this point. We check
2727 	 * this value in the reset_before_init function to understand whether
2728 	 * we need to reset the chip before doing H/W init. This register is
2729 	 * cleared by the H/W upon H/W reset
2730 	 */
2731 	WREG32(mmHW_STATE, HL_DEVICE_HW_STATE_DIRTY);
2732 
2733 	rc = goya_init_cpu(hdev);
2734 	if (rc) {
2735 		dev_err(hdev->dev, "failed to initialize CPU\n");
2736 		return rc;
2737 	}
2738 
2739 	goya_tpc_mbist_workaround(hdev);
2740 
2741 	goya_init_golden_registers(hdev);
2742 
2743 	/*
2744 	 * After CPU initialization is finished, change DDR bar mapping inside
2745 	 * iATU to point to the start address of the MMU page tables
2746 	 */
2747 	if (goya_set_ddr_bar_base(hdev, (MMU_PAGE_TABLES_ADDR &
2748 			~(prop->dram_pci_bar_size - 0x1ull))) == U64_MAX) {
2749 		dev_err(hdev->dev,
2750 			"failed to map DDR bar to MMU page tables\n");
2751 		return -EIO;
2752 	}
2753 
2754 	rc = goya_mmu_init(hdev);
2755 	if (rc)
2756 		return rc;
2757 
2758 	goya_init_security(hdev);
2759 
2760 	goya_init_dma_qmans(hdev);
2761 
2762 	goya_init_mme_qmans(hdev);
2763 
2764 	goya_init_tpc_qmans(hdev);
2765 
2766 	goya_enable_timestamp(hdev);
2767 
2768 	/* MSI-X must be enabled before CPU queues are initialized */
2769 	rc = goya_enable_msix(hdev);
2770 	if (rc)
2771 		goto disable_queues;
2772 
2773 	/* Perform read from the device to flush all MSI-X configuration */
2774 	RREG32(mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG);
2775 
2776 	return 0;
2777 
2778 disable_queues:
2779 	goya_disable_internal_queues(hdev);
2780 	goya_disable_external_queues(hdev);
2781 
2782 	return rc;
2783 }
2784 
2785 static void goya_hw_fini(struct hl_device *hdev, bool hard_reset, bool fw_reset)
2786 {
2787 	struct goya_device *goya = hdev->asic_specific;
2788 	u32 reset_timeout_ms, cpu_timeout_ms, status;
2789 
2790 	if (hdev->pldm) {
2791 		reset_timeout_ms = GOYA_PLDM_RESET_TIMEOUT_MSEC;
2792 		cpu_timeout_ms = GOYA_PLDM_RESET_WAIT_MSEC;
2793 	} else {
2794 		reset_timeout_ms = GOYA_RESET_TIMEOUT_MSEC;
2795 		cpu_timeout_ms = GOYA_CPU_RESET_WAIT_MSEC;
2796 	}
2797 
2798 	if (hard_reset) {
2799 		/* I don't know what is the state of the CPU so make sure it is
2800 		 * stopped in any means necessary
2801 		 */
2802 		WREG32(mmPSOC_GLOBAL_CONF_UBOOT_MAGIC, KMD_MSG_GOTO_WFE);
2803 		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2804 			GOYA_ASYNC_EVENT_ID_HALT_MACHINE);
2805 
2806 		msleep(cpu_timeout_ms);
2807 
2808 		goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
2809 		goya_disable_clk_rlx(hdev);
2810 		goya_set_pll_refclk(hdev);
2811 
2812 		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, RESET_ALL);
2813 		dev_dbg(hdev->dev,
2814 			"Issued HARD reset command, going to wait %dms\n",
2815 			reset_timeout_ms);
2816 	} else {
2817 		WREG32(mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG, DMA_MME_TPC_RESET);
2818 		dev_dbg(hdev->dev,
2819 			"Issued SOFT reset command, going to wait %dms\n",
2820 			reset_timeout_ms);
2821 	}
2822 
2823 	/*
2824 	 * After hard reset, we can't poll the BTM_FSM register because the PSOC
2825 	 * itself is in reset. In either reset we need to wait until the reset
2826 	 * is deasserted
2827 	 */
2828 	msleep(reset_timeout_ms);
2829 
2830 	status = RREG32(mmPSOC_GLOBAL_CONF_BTM_FSM);
2831 	if (status & PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK)
2832 		dev_err(hdev->dev,
2833 			"Timeout while waiting for device to reset 0x%x\n",
2834 			status);
2835 
2836 	if (!hard_reset && goya) {
2837 		goya->hw_cap_initialized &= ~(HW_CAP_DMA | HW_CAP_MME |
2838 						HW_CAP_GOLDEN | HW_CAP_TPC);
2839 		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2840 				GOYA_ASYNC_EVENT_ID_SOFT_RESET);
2841 		return;
2842 	}
2843 
2844 	/* Chicken bit to re-initiate boot sequencer flow */
2845 	WREG32(mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START,
2846 		1 << PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT);
2847 	/* Move boot manager FSM to pre boot sequencer init state */
2848 	WREG32(mmPSOC_GLOBAL_CONF_SW_BTM_FSM,
2849 			0xA << PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT);
2850 
2851 	if (goya) {
2852 		goya->hw_cap_initialized &= ~(HW_CAP_CPU | HW_CAP_CPU_Q |
2853 				HW_CAP_DDR_0 | HW_CAP_DDR_1 |
2854 				HW_CAP_DMA | HW_CAP_MME |
2855 				HW_CAP_MMU | HW_CAP_TPC_MBIST |
2856 				HW_CAP_GOLDEN | HW_CAP_TPC);
2857 
2858 		memset(goya->events_stat, 0, sizeof(goya->events_stat));
2859 	}
2860 }
2861 
2862 int goya_suspend(struct hl_device *hdev)
2863 {
2864 	int rc;
2865 
2866 	rc = hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS, 0x0);
2867 	if (rc)
2868 		dev_err(hdev->dev, "Failed to disable PCI access from CPU\n");
2869 
2870 	return rc;
2871 }
2872 
2873 int goya_resume(struct hl_device *hdev)
2874 {
2875 	return goya_init_iatu(hdev);
2876 }
2877 
2878 static int goya_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
2879 			void *cpu_addr, dma_addr_t dma_addr, size_t size)
2880 {
2881 	int rc;
2882 
2883 	vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP |
2884 			VM_DONTCOPY | VM_NORESERVE);
2885 
2886 	rc = dma_mmap_coherent(hdev->dev, vma, cpu_addr,
2887 				(dma_addr - HOST_PHYS_BASE), size);
2888 	if (rc)
2889 		dev_err(hdev->dev, "dma_mmap_coherent error %d", rc);
2890 
2891 	return rc;
2892 }
2893 
2894 void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi)
2895 {
2896 	u32 db_reg_offset, db_value;
2897 
2898 	switch (hw_queue_id) {
2899 	case GOYA_QUEUE_ID_DMA_0:
2900 		db_reg_offset = mmDMA_QM_0_PQ_PI;
2901 		break;
2902 
2903 	case GOYA_QUEUE_ID_DMA_1:
2904 		db_reg_offset = mmDMA_QM_1_PQ_PI;
2905 		break;
2906 
2907 	case GOYA_QUEUE_ID_DMA_2:
2908 		db_reg_offset = mmDMA_QM_2_PQ_PI;
2909 		break;
2910 
2911 	case GOYA_QUEUE_ID_DMA_3:
2912 		db_reg_offset = mmDMA_QM_3_PQ_PI;
2913 		break;
2914 
2915 	case GOYA_QUEUE_ID_DMA_4:
2916 		db_reg_offset = mmDMA_QM_4_PQ_PI;
2917 		break;
2918 
2919 	case GOYA_QUEUE_ID_CPU_PQ:
2920 		db_reg_offset = mmCPU_IF_PF_PQ_PI;
2921 		break;
2922 
2923 	case GOYA_QUEUE_ID_MME:
2924 		db_reg_offset = mmMME_QM_PQ_PI;
2925 		break;
2926 
2927 	case GOYA_QUEUE_ID_TPC0:
2928 		db_reg_offset = mmTPC0_QM_PQ_PI;
2929 		break;
2930 
2931 	case GOYA_QUEUE_ID_TPC1:
2932 		db_reg_offset = mmTPC1_QM_PQ_PI;
2933 		break;
2934 
2935 	case GOYA_QUEUE_ID_TPC2:
2936 		db_reg_offset = mmTPC2_QM_PQ_PI;
2937 		break;
2938 
2939 	case GOYA_QUEUE_ID_TPC3:
2940 		db_reg_offset = mmTPC3_QM_PQ_PI;
2941 		break;
2942 
2943 	case GOYA_QUEUE_ID_TPC4:
2944 		db_reg_offset = mmTPC4_QM_PQ_PI;
2945 		break;
2946 
2947 	case GOYA_QUEUE_ID_TPC5:
2948 		db_reg_offset = mmTPC5_QM_PQ_PI;
2949 		break;
2950 
2951 	case GOYA_QUEUE_ID_TPC6:
2952 		db_reg_offset = mmTPC6_QM_PQ_PI;
2953 		break;
2954 
2955 	case GOYA_QUEUE_ID_TPC7:
2956 		db_reg_offset = mmTPC7_QM_PQ_PI;
2957 		break;
2958 
2959 	default:
2960 		/* Should never get here */
2961 		dev_err(hdev->dev, "H/W queue %d is invalid. Can't set pi\n",
2962 			hw_queue_id);
2963 		return;
2964 	}
2965 
2966 	db_value = pi;
2967 
2968 	/* ring the doorbell */
2969 	WREG32(db_reg_offset, db_value);
2970 
2971 	if (hw_queue_id == GOYA_QUEUE_ID_CPU_PQ) {
2972 		/* make sure device CPU will read latest data from host */
2973 		mb();
2974 		WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
2975 				GOYA_ASYNC_EVENT_ID_PI_UPDATE);
2976 	}
2977 }
2978 
2979 void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd)
2980 {
2981 	/* The QMANs are on the SRAM so need to copy to IO space */
2982 	memcpy_toio((void __iomem *) pqe, bd, sizeof(struct hl_bd));
2983 }
2984 
2985 static void *goya_dma_alloc_coherent(struct hl_device *hdev, size_t size,
2986 					dma_addr_t *dma_handle, gfp_t flags)
2987 {
2988 	void *kernel_addr = dma_alloc_coherent(&hdev->pdev->dev, size,
2989 						dma_handle, flags);
2990 
2991 	/* Shift to the device's base physical address of host memory */
2992 	if (kernel_addr)
2993 		*dma_handle += HOST_PHYS_BASE;
2994 
2995 	return kernel_addr;
2996 }
2997 
2998 static void goya_dma_free_coherent(struct hl_device *hdev, size_t size,
2999 					void *cpu_addr, dma_addr_t dma_handle)
3000 {
3001 	/* Cancel the device's base physical address of host memory */
3002 	dma_addr_t fixed_dma_handle = dma_handle - HOST_PHYS_BASE;
3003 
3004 	dma_free_coherent(&hdev->pdev->dev, size, cpu_addr, fixed_dma_handle);
3005 }
3006 
3007 int goya_scrub_device_mem(struct hl_device *hdev)
3008 {
3009 	return 0;
3010 }
3011 
3012 void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
3013 				dma_addr_t *dma_handle,	u16 *queue_len)
3014 {
3015 	void *base;
3016 	u32 offset;
3017 
3018 	*dma_handle = hdev->asic_prop.sram_base_address;
3019 
3020 	base = (__force void *) hdev->pcie_bar[SRAM_CFG_BAR_ID];
3021 
3022 	switch (queue_id) {
3023 	case GOYA_QUEUE_ID_MME:
3024 		offset = MME_QMAN_BASE_OFFSET;
3025 		*queue_len = MME_QMAN_LENGTH;
3026 		break;
3027 	case GOYA_QUEUE_ID_TPC0:
3028 		offset = TPC0_QMAN_BASE_OFFSET;
3029 		*queue_len = TPC_QMAN_LENGTH;
3030 		break;
3031 	case GOYA_QUEUE_ID_TPC1:
3032 		offset = TPC1_QMAN_BASE_OFFSET;
3033 		*queue_len = TPC_QMAN_LENGTH;
3034 		break;
3035 	case GOYA_QUEUE_ID_TPC2:
3036 		offset = TPC2_QMAN_BASE_OFFSET;
3037 		*queue_len = TPC_QMAN_LENGTH;
3038 		break;
3039 	case GOYA_QUEUE_ID_TPC3:
3040 		offset = TPC3_QMAN_BASE_OFFSET;
3041 		*queue_len = TPC_QMAN_LENGTH;
3042 		break;
3043 	case GOYA_QUEUE_ID_TPC4:
3044 		offset = TPC4_QMAN_BASE_OFFSET;
3045 		*queue_len = TPC_QMAN_LENGTH;
3046 		break;
3047 	case GOYA_QUEUE_ID_TPC5:
3048 		offset = TPC5_QMAN_BASE_OFFSET;
3049 		*queue_len = TPC_QMAN_LENGTH;
3050 		break;
3051 	case GOYA_QUEUE_ID_TPC6:
3052 		offset = TPC6_QMAN_BASE_OFFSET;
3053 		*queue_len = TPC_QMAN_LENGTH;
3054 		break;
3055 	case GOYA_QUEUE_ID_TPC7:
3056 		offset = TPC7_QMAN_BASE_OFFSET;
3057 		*queue_len = TPC_QMAN_LENGTH;
3058 		break;
3059 	default:
3060 		dev_err(hdev->dev, "Got invalid queue id %d\n", queue_id);
3061 		return NULL;
3062 	}
3063 
3064 	base += offset;
3065 	*dma_handle += offset;
3066 
3067 	return base;
3068 }
3069 
3070 static int goya_send_job_on_qman0(struct hl_device *hdev, struct hl_cs_job *job)
3071 {
3072 	struct packet_msg_prot *fence_pkt;
3073 	u32 *fence_ptr;
3074 	dma_addr_t fence_dma_addr;
3075 	struct hl_cb *cb;
3076 	u32 tmp, timeout;
3077 	int rc;
3078 
3079 	if (hdev->pldm)
3080 		timeout = GOYA_PLDM_QMAN0_TIMEOUT_USEC;
3081 	else
3082 		timeout = HL_DEVICE_TIMEOUT_USEC;
3083 
3084 	if (!hdev->asic_funcs->is_device_idle(hdev, NULL, 0, NULL)) {
3085 		dev_err_ratelimited(hdev->dev,
3086 			"Can't send driver job on QMAN0 because the device is not idle\n");
3087 		return -EBUSY;
3088 	}
3089 
3090 	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3091 	if (!fence_ptr) {
3092 		dev_err(hdev->dev,
3093 			"Failed to allocate fence memory for QMAN0\n");
3094 		return -ENOMEM;
3095 	}
3096 
3097 	goya_qman0_set_security(hdev, true);
3098 
3099 	cb = job->patched_cb;
3100 
3101 	fence_pkt = cb->kernel_address +
3102 			job->job_cb_size - sizeof(struct packet_msg_prot);
3103 
3104 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3105 			(1 << GOYA_PKT_CTL_EB_SHIFT) |
3106 			(1 << GOYA_PKT_CTL_MB_SHIFT);
3107 	fence_pkt->ctl = cpu_to_le32(tmp);
3108 	fence_pkt->value = cpu_to_le32(GOYA_QMAN0_FENCE_VAL);
3109 	fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3110 
3111 	rc = hl_hw_queue_send_cb_no_cmpl(hdev, GOYA_QUEUE_ID_DMA_0,
3112 					job->job_cb_size, cb->bus_address);
3113 	if (rc) {
3114 		dev_err(hdev->dev, "Failed to send CB on QMAN0, %d\n", rc);
3115 		goto free_fence_ptr;
3116 	}
3117 
3118 	rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp,
3119 				(tmp == GOYA_QMAN0_FENCE_VAL), 1000,
3120 				timeout, true);
3121 
3122 	hl_hw_queue_inc_ci_kernel(hdev, GOYA_QUEUE_ID_DMA_0);
3123 
3124 	if (rc == -ETIMEDOUT) {
3125 		dev_err(hdev->dev, "QMAN0 Job timeout (0x%x)\n", tmp);
3126 		goto free_fence_ptr;
3127 	}
3128 
3129 free_fence_ptr:
3130 	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3131 
3132 	goya_qman0_set_security(hdev, false);
3133 
3134 	return rc;
3135 }
3136 
3137 int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
3138 				u32 timeout, u64 *result)
3139 {
3140 	struct goya_device *goya = hdev->asic_specific;
3141 
3142 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q)) {
3143 		if (result)
3144 			*result = 0;
3145 		return 0;
3146 	}
3147 
3148 	if (!timeout)
3149 		timeout = GOYA_MSG_TO_CPU_TIMEOUT_USEC;
3150 
3151 	return hl_fw_send_cpu_message(hdev, GOYA_QUEUE_ID_CPU_PQ, msg, len,
3152 					timeout, result);
3153 }
3154 
3155 int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id)
3156 {
3157 	struct packet_msg_prot *fence_pkt;
3158 	dma_addr_t pkt_dma_addr;
3159 	u32 fence_val, tmp;
3160 	dma_addr_t fence_dma_addr;
3161 	u32 *fence_ptr;
3162 	int rc;
3163 
3164 	fence_val = GOYA_QMAN0_FENCE_VAL;
3165 
3166 	fence_ptr = hl_asic_dma_pool_zalloc(hdev, 4, GFP_KERNEL, &fence_dma_addr);
3167 	if (!fence_ptr) {
3168 		dev_err(hdev->dev,
3169 			"Failed to allocate memory for H/W queue %d testing\n",
3170 			hw_queue_id);
3171 		return -ENOMEM;
3172 	}
3173 
3174 	*fence_ptr = 0;
3175 
3176 	fence_pkt = hl_asic_dma_pool_zalloc(hdev, sizeof(struct packet_msg_prot), GFP_KERNEL,
3177 						&pkt_dma_addr);
3178 	if (!fence_pkt) {
3179 		dev_err(hdev->dev,
3180 			"Failed to allocate packet for H/W queue %d testing\n",
3181 			hw_queue_id);
3182 		rc = -ENOMEM;
3183 		goto free_fence_ptr;
3184 	}
3185 
3186 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
3187 			(1 << GOYA_PKT_CTL_EB_SHIFT) |
3188 			(1 << GOYA_PKT_CTL_MB_SHIFT);
3189 	fence_pkt->ctl = cpu_to_le32(tmp);
3190 	fence_pkt->value = cpu_to_le32(fence_val);
3191 	fence_pkt->addr = cpu_to_le64(fence_dma_addr);
3192 
3193 	rc = hl_hw_queue_send_cb_no_cmpl(hdev, hw_queue_id,
3194 					sizeof(struct packet_msg_prot),
3195 					pkt_dma_addr);
3196 	if (rc) {
3197 		dev_err(hdev->dev,
3198 			"Failed to send fence packet to H/W queue %d\n",
3199 			hw_queue_id);
3200 		goto free_pkt;
3201 	}
3202 
3203 	rc = hl_poll_timeout_memory(hdev, fence_ptr, tmp, (tmp == fence_val),
3204 					1000, GOYA_TEST_QUEUE_WAIT_USEC, true);
3205 
3206 	hl_hw_queue_inc_ci_kernel(hdev, hw_queue_id);
3207 
3208 	if (rc == -ETIMEDOUT) {
3209 		dev_err(hdev->dev,
3210 			"H/W queue %d test failed (scratch(0x%08llX) == 0x%08X)\n",
3211 			hw_queue_id, (unsigned long long) fence_dma_addr, tmp);
3212 		rc = -EIO;
3213 	}
3214 
3215 free_pkt:
3216 	hl_asic_dma_pool_free(hdev, (void *) fence_pkt, pkt_dma_addr);
3217 free_fence_ptr:
3218 	hl_asic_dma_pool_free(hdev, (void *) fence_ptr, fence_dma_addr);
3219 	return rc;
3220 }
3221 
3222 int goya_test_cpu_queue(struct hl_device *hdev)
3223 {
3224 	struct goya_device *goya = hdev->asic_specific;
3225 
3226 	/*
3227 	 * check capability here as send_cpu_message() won't update the result
3228 	 * value if no capability
3229 	 */
3230 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
3231 		return 0;
3232 
3233 	return hl_fw_test_cpu_queue(hdev);
3234 }
3235 
3236 int goya_test_queues(struct hl_device *hdev)
3237 {
3238 	int i, rc, ret_val = 0;
3239 
3240 	for (i = 0 ; i < NUMBER_OF_EXT_HW_QUEUES ; i++) {
3241 		rc = goya_test_queue(hdev, i);
3242 		if (rc)
3243 			ret_val = -EINVAL;
3244 	}
3245 
3246 	return ret_val;
3247 }
3248 
3249 static void *goya_dma_pool_zalloc(struct hl_device *hdev, size_t size,
3250 					gfp_t mem_flags, dma_addr_t *dma_handle)
3251 {
3252 	void *kernel_addr;
3253 
3254 	if (size > GOYA_DMA_POOL_BLK_SIZE)
3255 		return NULL;
3256 
3257 	kernel_addr =  dma_pool_zalloc(hdev->dma_pool, mem_flags, dma_handle);
3258 
3259 	/* Shift to the device's base physical address of host memory */
3260 	if (kernel_addr)
3261 		*dma_handle += HOST_PHYS_BASE;
3262 
3263 	return kernel_addr;
3264 }
3265 
3266 static void goya_dma_pool_free(struct hl_device *hdev, void *vaddr,
3267 				dma_addr_t dma_addr)
3268 {
3269 	/* Cancel the device's base physical address of host memory */
3270 	dma_addr_t fixed_dma_addr = dma_addr - HOST_PHYS_BASE;
3271 
3272 	dma_pool_free(hdev->dma_pool, vaddr, fixed_dma_addr);
3273 }
3274 
3275 void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
3276 					dma_addr_t *dma_handle)
3277 {
3278 	void *vaddr;
3279 
3280 	vaddr = hl_fw_cpu_accessible_dma_pool_alloc(hdev, size, dma_handle);
3281 	*dma_handle = (*dma_handle) - hdev->cpu_accessible_dma_address +
3282 			VA_CPU_ACCESSIBLE_MEM_ADDR;
3283 
3284 	return vaddr;
3285 }
3286 
3287 void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
3288 					void *vaddr)
3289 {
3290 	hl_fw_cpu_accessible_dma_pool_free(hdev, size, vaddr);
3291 }
3292 
3293 u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt)
3294 {
3295 	struct scatterlist *sg, *sg_next_iter;
3296 	u32 count, dma_desc_cnt;
3297 	u64 len, len_next;
3298 	dma_addr_t addr, addr_next;
3299 
3300 	dma_desc_cnt = 0;
3301 
3302 	for_each_sgtable_dma_sg(sgt, sg, count) {
3303 		len = sg_dma_len(sg);
3304 		addr = sg_dma_address(sg);
3305 
3306 		if (len == 0)
3307 			break;
3308 
3309 		while ((count + 1) < sgt->nents) {
3310 			sg_next_iter = sg_next(sg);
3311 			len_next = sg_dma_len(sg_next_iter);
3312 			addr_next = sg_dma_address(sg_next_iter);
3313 
3314 			if (len_next == 0)
3315 				break;
3316 
3317 			if ((addr + len == addr_next) &&
3318 				(len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3319 				len += len_next;
3320 				count++;
3321 				sg = sg_next_iter;
3322 			} else {
3323 				break;
3324 			}
3325 		}
3326 
3327 		dma_desc_cnt++;
3328 	}
3329 
3330 	return dma_desc_cnt * sizeof(struct packet_lin_dma);
3331 }
3332 
3333 static int goya_pin_memory_before_cs(struct hl_device *hdev,
3334 				struct hl_cs_parser *parser,
3335 				struct packet_lin_dma *user_dma_pkt,
3336 				u64 addr, enum dma_data_direction dir)
3337 {
3338 	struct hl_userptr *userptr;
3339 	int rc;
3340 
3341 	if (hl_userptr_is_pinned(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3342 			parser->job_userptr_list, &userptr))
3343 		goto already_pinned;
3344 
3345 	userptr = kzalloc(sizeof(*userptr), GFP_KERNEL);
3346 	if (!userptr)
3347 		return -ENOMEM;
3348 
3349 	rc = hl_pin_host_memory(hdev, addr, le32_to_cpu(user_dma_pkt->tsize),
3350 				userptr);
3351 	if (rc)
3352 		goto free_userptr;
3353 
3354 	list_add_tail(&userptr->job_node, parser->job_userptr_list);
3355 
3356 	rc = hdev->asic_funcs->asic_dma_map_sgtable(hdev, userptr->sgt, dir);
3357 	if (rc) {
3358 		dev_err(hdev->dev, "failed to map sgt with DMA region\n");
3359 		goto unpin_memory;
3360 	}
3361 
3362 	userptr->dma_mapped = true;
3363 	userptr->dir = dir;
3364 
3365 already_pinned:
3366 	parser->patched_cb_size +=
3367 			goya_get_dma_desc_list_size(hdev, userptr->sgt);
3368 
3369 	return 0;
3370 
3371 unpin_memory:
3372 	list_del(&userptr->job_node);
3373 	hl_unpin_host_memory(hdev, userptr);
3374 free_userptr:
3375 	kfree(userptr);
3376 	return rc;
3377 }
3378 
3379 static int goya_validate_dma_pkt_host(struct hl_device *hdev,
3380 				struct hl_cs_parser *parser,
3381 				struct packet_lin_dma *user_dma_pkt)
3382 {
3383 	u64 device_memory_addr, addr;
3384 	enum dma_data_direction dir;
3385 	enum hl_goya_dma_direction user_dir;
3386 	bool sram_addr = true;
3387 	bool skip_host_mem_pin = false;
3388 	bool user_memset;
3389 	u32 ctl;
3390 	int rc = 0;
3391 
3392 	ctl = le32_to_cpu(user_dma_pkt->ctl);
3393 
3394 	user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3395 			GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3396 
3397 	user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3398 			GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3399 
3400 	switch (user_dir) {
3401 	case HL_DMA_HOST_TO_DRAM:
3402 		dev_dbg(hdev->dev, "DMA direction is HOST --> DRAM\n");
3403 		dir = DMA_TO_DEVICE;
3404 		sram_addr = false;
3405 		addr = le64_to_cpu(user_dma_pkt->src_addr);
3406 		device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3407 		if (user_memset)
3408 			skip_host_mem_pin = true;
3409 		break;
3410 
3411 	case HL_DMA_DRAM_TO_HOST:
3412 		dev_dbg(hdev->dev, "DMA direction is DRAM --> HOST\n");
3413 		dir = DMA_FROM_DEVICE;
3414 		sram_addr = false;
3415 		addr = le64_to_cpu(user_dma_pkt->dst_addr);
3416 		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3417 		break;
3418 
3419 	case HL_DMA_HOST_TO_SRAM:
3420 		dev_dbg(hdev->dev, "DMA direction is HOST --> SRAM\n");
3421 		dir = DMA_TO_DEVICE;
3422 		addr = le64_to_cpu(user_dma_pkt->src_addr);
3423 		device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3424 		if (user_memset)
3425 			skip_host_mem_pin = true;
3426 		break;
3427 
3428 	case HL_DMA_SRAM_TO_HOST:
3429 		dev_dbg(hdev->dev, "DMA direction is SRAM --> HOST\n");
3430 		dir = DMA_FROM_DEVICE;
3431 		addr = le64_to_cpu(user_dma_pkt->dst_addr);
3432 		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3433 		break;
3434 	default:
3435 		dev_err(hdev->dev, "DMA direction %d is unsupported/undefined\n", user_dir);
3436 		return -EFAULT;
3437 	}
3438 
3439 	if (sram_addr) {
3440 		if (!hl_mem_area_inside_range(device_memory_addr,
3441 				le32_to_cpu(user_dma_pkt->tsize),
3442 				hdev->asic_prop.sram_user_base_address,
3443 				hdev->asic_prop.sram_end_address)) {
3444 
3445 			dev_err(hdev->dev,
3446 				"SRAM address 0x%llx + 0x%x is invalid\n",
3447 				device_memory_addr,
3448 				user_dma_pkt->tsize);
3449 			return -EFAULT;
3450 		}
3451 	} else {
3452 		if (!hl_mem_area_inside_range(device_memory_addr,
3453 				le32_to_cpu(user_dma_pkt->tsize),
3454 				hdev->asic_prop.dram_user_base_address,
3455 				hdev->asic_prop.dram_end_address)) {
3456 
3457 			dev_err(hdev->dev,
3458 				"DRAM address 0x%llx + 0x%x is invalid\n",
3459 				device_memory_addr,
3460 				user_dma_pkt->tsize);
3461 			return -EFAULT;
3462 		}
3463 	}
3464 
3465 	if (skip_host_mem_pin)
3466 		parser->patched_cb_size += sizeof(*user_dma_pkt);
3467 	else {
3468 		if ((dir == DMA_TO_DEVICE) &&
3469 				(parser->hw_queue_id > GOYA_QUEUE_ID_DMA_1)) {
3470 			dev_err(hdev->dev,
3471 				"Can't DMA from host on queue other then 1\n");
3472 			return -EFAULT;
3473 		}
3474 
3475 		rc = goya_pin_memory_before_cs(hdev, parser, user_dma_pkt,
3476 						addr, dir);
3477 	}
3478 
3479 	return rc;
3480 }
3481 
3482 static int goya_validate_dma_pkt_no_host(struct hl_device *hdev,
3483 				struct hl_cs_parser *parser,
3484 				struct packet_lin_dma *user_dma_pkt)
3485 {
3486 	u64 sram_memory_addr, dram_memory_addr;
3487 	enum hl_goya_dma_direction user_dir;
3488 	u32 ctl;
3489 
3490 	ctl = le32_to_cpu(user_dma_pkt->ctl);
3491 	user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3492 			GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3493 
3494 	if (user_dir == HL_DMA_DRAM_TO_SRAM) {
3495 		dev_dbg(hdev->dev, "DMA direction is DRAM --> SRAM\n");
3496 		dram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3497 		sram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3498 	} else {
3499 		dev_dbg(hdev->dev, "DMA direction is SRAM --> DRAM\n");
3500 		sram_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3501 		dram_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3502 	}
3503 
3504 	if (!hl_mem_area_inside_range(sram_memory_addr,
3505 				le32_to_cpu(user_dma_pkt->tsize),
3506 				hdev->asic_prop.sram_user_base_address,
3507 				hdev->asic_prop.sram_end_address)) {
3508 		dev_err(hdev->dev, "SRAM address 0x%llx + 0x%x is invalid\n",
3509 			sram_memory_addr, user_dma_pkt->tsize);
3510 		return -EFAULT;
3511 	}
3512 
3513 	if (!hl_mem_area_inside_range(dram_memory_addr,
3514 				le32_to_cpu(user_dma_pkt->tsize),
3515 				hdev->asic_prop.dram_user_base_address,
3516 				hdev->asic_prop.dram_end_address)) {
3517 		dev_err(hdev->dev, "DRAM address 0x%llx + 0x%x is invalid\n",
3518 			dram_memory_addr, user_dma_pkt->tsize);
3519 		return -EFAULT;
3520 	}
3521 
3522 	parser->patched_cb_size += sizeof(*user_dma_pkt);
3523 
3524 	return 0;
3525 }
3526 
3527 static int goya_validate_dma_pkt_no_mmu(struct hl_device *hdev,
3528 				struct hl_cs_parser *parser,
3529 				struct packet_lin_dma *user_dma_pkt)
3530 {
3531 	enum hl_goya_dma_direction user_dir;
3532 	u32 ctl;
3533 	int rc;
3534 
3535 	dev_dbg(hdev->dev, "DMA packet details:\n");
3536 	dev_dbg(hdev->dev, "source == 0x%llx\n",
3537 		le64_to_cpu(user_dma_pkt->src_addr));
3538 	dev_dbg(hdev->dev, "destination == 0x%llx\n",
3539 		le64_to_cpu(user_dma_pkt->dst_addr));
3540 	dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3541 
3542 	ctl = le32_to_cpu(user_dma_pkt->ctl);
3543 	user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3544 			GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3545 
3546 	/*
3547 	 * Special handling for DMA with size 0. The H/W has a bug where
3548 	 * this can cause the QMAN DMA to get stuck, so block it here.
3549 	 */
3550 	if (user_dma_pkt->tsize == 0) {
3551 		dev_err(hdev->dev,
3552 			"Got DMA with size 0, might reset the device\n");
3553 		return -EINVAL;
3554 	}
3555 
3556 	if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM))
3557 		rc = goya_validate_dma_pkt_no_host(hdev, parser, user_dma_pkt);
3558 	else
3559 		rc = goya_validate_dma_pkt_host(hdev, parser, user_dma_pkt);
3560 
3561 	return rc;
3562 }
3563 
3564 static int goya_validate_dma_pkt_mmu(struct hl_device *hdev,
3565 				struct hl_cs_parser *parser,
3566 				struct packet_lin_dma *user_dma_pkt)
3567 {
3568 	dev_dbg(hdev->dev, "DMA packet details:\n");
3569 	dev_dbg(hdev->dev, "source == 0x%llx\n",
3570 		le64_to_cpu(user_dma_pkt->src_addr));
3571 	dev_dbg(hdev->dev, "destination == 0x%llx\n",
3572 		le64_to_cpu(user_dma_pkt->dst_addr));
3573 	dev_dbg(hdev->dev, "size == %u\n", le32_to_cpu(user_dma_pkt->tsize));
3574 
3575 	/*
3576 	 * WA for HW-23.
3577 	 * We can't allow user to read from Host using QMANs other than 1.
3578 	 * PMMU and HPMMU addresses are equal, check only one of them.
3579 	 */
3580 	if (parser->hw_queue_id != GOYA_QUEUE_ID_DMA_1 &&
3581 		hl_mem_area_inside_range(le64_to_cpu(user_dma_pkt->src_addr),
3582 				le32_to_cpu(user_dma_pkt->tsize),
3583 				hdev->asic_prop.pmmu.start_addr,
3584 				hdev->asic_prop.pmmu.end_addr)) {
3585 		dev_err(hdev->dev,
3586 			"Can't DMA from host on queue other then 1\n");
3587 		return -EFAULT;
3588 	}
3589 
3590 	if (user_dma_pkt->tsize == 0) {
3591 		dev_err(hdev->dev,
3592 			"Got DMA with size 0, might reset the device\n");
3593 		return -EINVAL;
3594 	}
3595 
3596 	parser->patched_cb_size += sizeof(*user_dma_pkt);
3597 
3598 	return 0;
3599 }
3600 
3601 static int goya_validate_wreg32(struct hl_device *hdev,
3602 				struct hl_cs_parser *parser,
3603 				struct packet_wreg32 *wreg_pkt)
3604 {
3605 	struct goya_device *goya = hdev->asic_specific;
3606 	u32 sob_start_addr, sob_end_addr;
3607 	u16 reg_offset;
3608 
3609 	reg_offset = le32_to_cpu(wreg_pkt->ctl) &
3610 			GOYA_PKT_WREG32_CTL_REG_OFFSET_MASK;
3611 
3612 	dev_dbg(hdev->dev, "WREG32 packet details:\n");
3613 	dev_dbg(hdev->dev, "reg_offset == 0x%x\n", reg_offset);
3614 	dev_dbg(hdev->dev, "value      == 0x%x\n",
3615 		le32_to_cpu(wreg_pkt->value));
3616 
3617 	if (reg_offset != (mmDMA_CH_0_WR_COMP_ADDR_LO & 0x1FFF)) {
3618 		dev_err(hdev->dev, "WREG32 packet with illegal address 0x%x\n",
3619 			reg_offset);
3620 		return -EPERM;
3621 	}
3622 
3623 	/*
3624 	 * With MMU, DMA channels are not secured, so it doesn't matter where
3625 	 * the WR COMP will be written to because it will go out with
3626 	 * non-secured property
3627 	 */
3628 	if (goya->hw_cap_initialized & HW_CAP_MMU)
3629 		return 0;
3630 
3631 	sob_start_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_0);
3632 	sob_end_addr = lower_32_bits(CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1023);
3633 
3634 	if ((le32_to_cpu(wreg_pkt->value) < sob_start_addr) ||
3635 			(le32_to_cpu(wreg_pkt->value) > sob_end_addr)) {
3636 
3637 		dev_err(hdev->dev, "WREG32 packet with illegal value 0x%x\n",
3638 			wreg_pkt->value);
3639 		return -EPERM;
3640 	}
3641 
3642 	return 0;
3643 }
3644 
3645 static int goya_validate_cb(struct hl_device *hdev,
3646 			struct hl_cs_parser *parser, bool is_mmu)
3647 {
3648 	u32 cb_parsed_length = 0;
3649 	int rc = 0;
3650 
3651 	parser->patched_cb_size = 0;
3652 
3653 	/* cb_user_size is more than 0 so loop will always be executed */
3654 	while (cb_parsed_length < parser->user_cb_size) {
3655 		enum packet_id pkt_id;
3656 		u16 pkt_size;
3657 		struct goya_packet *user_pkt;
3658 
3659 		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3660 
3661 		pkt_id = (enum packet_id) (
3662 				(le64_to_cpu(user_pkt->header) &
3663 				PACKET_HEADER_PACKET_ID_MASK) >>
3664 					PACKET_HEADER_PACKET_ID_SHIFT);
3665 
3666 		if (!validate_packet_id(pkt_id)) {
3667 			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3668 			rc = -EINVAL;
3669 			break;
3670 		}
3671 
3672 		pkt_size = goya_packet_sizes[pkt_id];
3673 		cb_parsed_length += pkt_size;
3674 		if (cb_parsed_length > parser->user_cb_size) {
3675 			dev_err(hdev->dev,
3676 				"packet 0x%x is out of CB boundary\n", pkt_id);
3677 			rc = -EINVAL;
3678 			break;
3679 		}
3680 
3681 		switch (pkt_id) {
3682 		case PACKET_WREG_32:
3683 			/*
3684 			 * Although it is validated after copy in patch_cb(),
3685 			 * need to validate here as well because patch_cb() is
3686 			 * not called in MMU path while this function is called
3687 			 */
3688 			rc = goya_validate_wreg32(hdev,
3689 				parser, (struct packet_wreg32 *) user_pkt);
3690 			parser->patched_cb_size += pkt_size;
3691 			break;
3692 
3693 		case PACKET_WREG_BULK:
3694 			dev_err(hdev->dev,
3695 				"User not allowed to use WREG_BULK\n");
3696 			rc = -EPERM;
3697 			break;
3698 
3699 		case PACKET_MSG_PROT:
3700 			dev_err(hdev->dev,
3701 				"User not allowed to use MSG_PROT\n");
3702 			rc = -EPERM;
3703 			break;
3704 
3705 		case PACKET_CP_DMA:
3706 			dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3707 			rc = -EPERM;
3708 			break;
3709 
3710 		case PACKET_STOP:
3711 			dev_err(hdev->dev, "User not allowed to use STOP\n");
3712 			rc = -EPERM;
3713 			break;
3714 
3715 		case PACKET_LIN_DMA:
3716 			if (is_mmu)
3717 				rc = goya_validate_dma_pkt_mmu(hdev, parser,
3718 					(struct packet_lin_dma *) user_pkt);
3719 			else
3720 				rc = goya_validate_dma_pkt_no_mmu(hdev, parser,
3721 					(struct packet_lin_dma *) user_pkt);
3722 			break;
3723 
3724 		case PACKET_MSG_LONG:
3725 		case PACKET_MSG_SHORT:
3726 		case PACKET_FENCE:
3727 		case PACKET_NOP:
3728 			parser->patched_cb_size += pkt_size;
3729 			break;
3730 
3731 		default:
3732 			dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3733 				pkt_id);
3734 			rc = -EINVAL;
3735 			break;
3736 		}
3737 
3738 		if (rc)
3739 			break;
3740 	}
3741 
3742 	/*
3743 	 * The new CB should have space at the end for two MSG_PROT packets:
3744 	 * 1. A packet that will act as a completion packet
3745 	 * 2. A packet that will generate MSI-X interrupt
3746 	 */
3747 	parser->patched_cb_size += sizeof(struct packet_msg_prot) * 2;
3748 
3749 	return rc;
3750 }
3751 
3752 static int goya_patch_dma_packet(struct hl_device *hdev,
3753 				struct hl_cs_parser *parser,
3754 				struct packet_lin_dma *user_dma_pkt,
3755 				struct packet_lin_dma *new_dma_pkt,
3756 				u32 *new_dma_pkt_size)
3757 {
3758 	struct hl_userptr *userptr;
3759 	struct scatterlist *sg, *sg_next_iter;
3760 	u32 count, dma_desc_cnt;
3761 	u64 len, len_next;
3762 	dma_addr_t dma_addr, dma_addr_next;
3763 	enum hl_goya_dma_direction user_dir;
3764 	u64 device_memory_addr, addr;
3765 	enum dma_data_direction dir;
3766 	struct sg_table *sgt;
3767 	bool skip_host_mem_pin = false;
3768 	bool user_memset;
3769 	u32 user_rdcomp_mask, user_wrcomp_mask, ctl;
3770 
3771 	ctl = le32_to_cpu(user_dma_pkt->ctl);
3772 
3773 	user_dir = (ctl & GOYA_PKT_LIN_DMA_CTL_DMA_DIR_MASK) >>
3774 			GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
3775 
3776 	user_memset = (ctl & GOYA_PKT_LIN_DMA_CTL_MEMSET_MASK) >>
3777 			GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT;
3778 
3779 	if ((user_dir == HL_DMA_DRAM_TO_SRAM) || (user_dir == HL_DMA_SRAM_TO_DRAM) ||
3780 			(user_dma_pkt->tsize == 0)) {
3781 		memcpy(new_dma_pkt, user_dma_pkt, sizeof(*new_dma_pkt));
3782 		*new_dma_pkt_size = sizeof(*new_dma_pkt);
3783 		return 0;
3784 	}
3785 
3786 	if ((user_dir == HL_DMA_HOST_TO_DRAM) || (user_dir == HL_DMA_HOST_TO_SRAM)) {
3787 		addr = le64_to_cpu(user_dma_pkt->src_addr);
3788 		device_memory_addr = le64_to_cpu(user_dma_pkt->dst_addr);
3789 		dir = DMA_TO_DEVICE;
3790 		if (user_memset)
3791 			skip_host_mem_pin = true;
3792 	} else {
3793 		addr = le64_to_cpu(user_dma_pkt->dst_addr);
3794 		device_memory_addr = le64_to_cpu(user_dma_pkt->src_addr);
3795 		dir = DMA_FROM_DEVICE;
3796 	}
3797 
3798 	if ((!skip_host_mem_pin) &&
3799 		(hl_userptr_is_pinned(hdev, addr,
3800 			le32_to_cpu(user_dma_pkt->tsize),
3801 			parser->job_userptr_list, &userptr) == false)) {
3802 		dev_err(hdev->dev, "Userptr 0x%llx + 0x%x NOT mapped\n",
3803 				addr, user_dma_pkt->tsize);
3804 		return -EFAULT;
3805 	}
3806 
3807 	if ((user_memset) && (dir == DMA_TO_DEVICE)) {
3808 		memcpy(new_dma_pkt, user_dma_pkt, sizeof(*user_dma_pkt));
3809 		*new_dma_pkt_size = sizeof(*user_dma_pkt);
3810 		return 0;
3811 	}
3812 
3813 	user_rdcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK;
3814 
3815 	user_wrcomp_mask = ctl & GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK;
3816 
3817 	sgt = userptr->sgt;
3818 	dma_desc_cnt = 0;
3819 
3820 	for_each_sgtable_dma_sg(sgt, sg, count) {
3821 		len = sg_dma_len(sg);
3822 		dma_addr = sg_dma_address(sg);
3823 
3824 		if (len == 0)
3825 			break;
3826 
3827 		while ((count + 1) < sgt->nents) {
3828 			sg_next_iter = sg_next(sg);
3829 			len_next = sg_dma_len(sg_next_iter);
3830 			dma_addr_next = sg_dma_address(sg_next_iter);
3831 
3832 			if (len_next == 0)
3833 				break;
3834 
3835 			if ((dma_addr + len == dma_addr_next) &&
3836 				(len + len_next <= DMA_MAX_TRANSFER_SIZE)) {
3837 				len += len_next;
3838 				count++;
3839 				sg = sg_next_iter;
3840 			} else {
3841 				break;
3842 			}
3843 		}
3844 
3845 		ctl = le32_to_cpu(user_dma_pkt->ctl);
3846 		if (likely(dma_desc_cnt))
3847 			ctl &= ~GOYA_PKT_CTL_EB_MASK;
3848 		ctl &= ~(GOYA_PKT_LIN_DMA_CTL_RDCOMP_MASK |
3849 				GOYA_PKT_LIN_DMA_CTL_WRCOMP_MASK);
3850 		new_dma_pkt->ctl = cpu_to_le32(ctl);
3851 		new_dma_pkt->tsize = cpu_to_le32((u32) len);
3852 
3853 		if (dir == DMA_TO_DEVICE) {
3854 			new_dma_pkt->src_addr = cpu_to_le64(dma_addr);
3855 			new_dma_pkt->dst_addr = cpu_to_le64(device_memory_addr);
3856 		} else {
3857 			new_dma_pkt->src_addr = cpu_to_le64(device_memory_addr);
3858 			new_dma_pkt->dst_addr = cpu_to_le64(dma_addr);
3859 		}
3860 
3861 		if (!user_memset)
3862 			device_memory_addr += len;
3863 		dma_desc_cnt++;
3864 		new_dma_pkt++;
3865 	}
3866 
3867 	if (!dma_desc_cnt) {
3868 		dev_err(hdev->dev,
3869 			"Error of 0 SG entries when patching DMA packet\n");
3870 		return -EFAULT;
3871 	}
3872 
3873 	/* Fix the last dma packet - rdcomp/wrcomp must be as user set them */
3874 	new_dma_pkt--;
3875 	new_dma_pkt->ctl |= cpu_to_le32(user_rdcomp_mask | user_wrcomp_mask);
3876 
3877 	*new_dma_pkt_size = dma_desc_cnt * sizeof(struct packet_lin_dma);
3878 
3879 	return 0;
3880 }
3881 
3882 static int goya_patch_cb(struct hl_device *hdev,
3883 				struct hl_cs_parser *parser)
3884 {
3885 	u32 cb_parsed_length = 0;
3886 	u32 cb_patched_cur_length = 0;
3887 	int rc = 0;
3888 
3889 	/* cb_user_size is more than 0 so loop will always be executed */
3890 	while (cb_parsed_length < parser->user_cb_size) {
3891 		enum packet_id pkt_id;
3892 		u16 pkt_size;
3893 		u32 new_pkt_size = 0;
3894 		struct goya_packet *user_pkt, *kernel_pkt;
3895 
3896 		user_pkt = parser->user_cb->kernel_address + cb_parsed_length;
3897 		kernel_pkt = parser->patched_cb->kernel_address +
3898 					cb_patched_cur_length;
3899 
3900 		pkt_id = (enum packet_id) (
3901 				(le64_to_cpu(user_pkt->header) &
3902 				PACKET_HEADER_PACKET_ID_MASK) >>
3903 					PACKET_HEADER_PACKET_ID_SHIFT);
3904 
3905 		if (!validate_packet_id(pkt_id)) {
3906 			dev_err(hdev->dev, "Invalid packet id %u\n", pkt_id);
3907 			rc = -EINVAL;
3908 			break;
3909 		}
3910 
3911 		pkt_size = goya_packet_sizes[pkt_id];
3912 		cb_parsed_length += pkt_size;
3913 		if (cb_parsed_length > parser->user_cb_size) {
3914 			dev_err(hdev->dev,
3915 				"packet 0x%x is out of CB boundary\n", pkt_id);
3916 			rc = -EINVAL;
3917 			break;
3918 		}
3919 
3920 		switch (pkt_id) {
3921 		case PACKET_LIN_DMA:
3922 			rc = goya_patch_dma_packet(hdev, parser,
3923 					(struct packet_lin_dma *) user_pkt,
3924 					(struct packet_lin_dma *) kernel_pkt,
3925 					&new_pkt_size);
3926 			cb_patched_cur_length += new_pkt_size;
3927 			break;
3928 
3929 		case PACKET_WREG_32:
3930 			memcpy(kernel_pkt, user_pkt, pkt_size);
3931 			cb_patched_cur_length += pkt_size;
3932 			rc = goya_validate_wreg32(hdev, parser,
3933 					(struct packet_wreg32 *) kernel_pkt);
3934 			break;
3935 
3936 		case PACKET_WREG_BULK:
3937 			dev_err(hdev->dev,
3938 				"User not allowed to use WREG_BULK\n");
3939 			rc = -EPERM;
3940 			break;
3941 
3942 		case PACKET_MSG_PROT:
3943 			dev_err(hdev->dev,
3944 				"User not allowed to use MSG_PROT\n");
3945 			rc = -EPERM;
3946 			break;
3947 
3948 		case PACKET_CP_DMA:
3949 			dev_err(hdev->dev, "User not allowed to use CP_DMA\n");
3950 			rc = -EPERM;
3951 			break;
3952 
3953 		case PACKET_STOP:
3954 			dev_err(hdev->dev, "User not allowed to use STOP\n");
3955 			rc = -EPERM;
3956 			break;
3957 
3958 		case PACKET_MSG_LONG:
3959 		case PACKET_MSG_SHORT:
3960 		case PACKET_FENCE:
3961 		case PACKET_NOP:
3962 			memcpy(kernel_pkt, user_pkt, pkt_size);
3963 			cb_patched_cur_length += pkt_size;
3964 			break;
3965 
3966 		default:
3967 			dev_err(hdev->dev, "Invalid packet header 0x%x\n",
3968 				pkt_id);
3969 			rc = -EINVAL;
3970 			break;
3971 		}
3972 
3973 		if (rc)
3974 			break;
3975 	}
3976 
3977 	return rc;
3978 }
3979 
3980 static int goya_parse_cb_mmu(struct hl_device *hdev,
3981 		struct hl_cs_parser *parser)
3982 {
3983 	u64 handle;
3984 	u32 patched_cb_size;
3985 	struct hl_cb *user_cb;
3986 	int rc;
3987 
3988 	/*
3989 	 * The new CB should have space at the end for two MSG_PROT pkt:
3990 	 * 1. A packet that will act as a completion packet
3991 	 * 2. A packet that will generate MSI-X interrupt
3992 	 */
3993 	parser->patched_cb_size = parser->user_cb_size +
3994 			sizeof(struct packet_msg_prot) * 2;
3995 
3996 	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
3997 				parser->patched_cb_size, false, false,
3998 				&handle);
3999 
4000 	if (rc) {
4001 		dev_err(hdev->dev,
4002 			"Failed to allocate patched CB for DMA CS %d\n",
4003 			rc);
4004 		return rc;
4005 	}
4006 
4007 	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4008 	/* hl_cb_get should never fail here */
4009 	if (!parser->patched_cb) {
4010 		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4011 		rc = -EFAULT;
4012 		goto out;
4013 	}
4014 
4015 	/*
4016 	 * The check that parser->user_cb_size <= parser->user_cb->size was done
4017 	 * in validate_queue_index().
4018 	 */
4019 	memcpy(parser->patched_cb->kernel_address,
4020 		parser->user_cb->kernel_address,
4021 		parser->user_cb_size);
4022 
4023 	patched_cb_size = parser->patched_cb_size;
4024 
4025 	/* validate patched CB instead of user CB */
4026 	user_cb = parser->user_cb;
4027 	parser->user_cb = parser->patched_cb;
4028 	rc = goya_validate_cb(hdev, parser, true);
4029 	parser->user_cb = user_cb;
4030 
4031 	if (rc) {
4032 		hl_cb_put(parser->patched_cb);
4033 		goto out;
4034 	}
4035 
4036 	if (patched_cb_size != parser->patched_cb_size) {
4037 		dev_err(hdev->dev, "user CB size mismatch\n");
4038 		hl_cb_put(parser->patched_cb);
4039 		rc = -EINVAL;
4040 		goto out;
4041 	}
4042 
4043 out:
4044 	/*
4045 	 * Always call cb destroy here because we still have 1 reference
4046 	 * to it by calling cb_get earlier. After the job will be completed,
4047 	 * cb_put will release it, but here we want to remove it from the
4048 	 * idr
4049 	 */
4050 	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4051 
4052 	return rc;
4053 }
4054 
4055 static int goya_parse_cb_no_mmu(struct hl_device *hdev,
4056 				struct hl_cs_parser *parser)
4057 {
4058 	u64 handle;
4059 	int rc;
4060 
4061 	rc = goya_validate_cb(hdev, parser, false);
4062 
4063 	if (rc)
4064 		goto free_userptr;
4065 
4066 	rc = hl_cb_create(hdev, &hdev->kernel_mem_mgr, hdev->kernel_ctx,
4067 				parser->patched_cb_size, false, false,
4068 				&handle);
4069 	if (rc) {
4070 		dev_err(hdev->dev,
4071 			"Failed to allocate patched CB for DMA CS %d\n", rc);
4072 		goto free_userptr;
4073 	}
4074 
4075 	parser->patched_cb = hl_cb_get(&hdev->kernel_mem_mgr, handle);
4076 	/* hl_cb_get should never fail here */
4077 	if (!parser->patched_cb) {
4078 		dev_crit(hdev->dev, "DMA CB handle invalid 0x%llx\n", handle);
4079 		rc = -EFAULT;
4080 		goto out;
4081 	}
4082 
4083 	rc = goya_patch_cb(hdev, parser);
4084 
4085 	if (rc)
4086 		hl_cb_put(parser->patched_cb);
4087 
4088 out:
4089 	/*
4090 	 * Always call cb destroy here because we still have 1 reference
4091 	 * to it by calling cb_get earlier. After the job will be completed,
4092 	 * cb_put will release it, but here we want to remove it from the
4093 	 * idr
4094 	 */
4095 	hl_cb_destroy(&hdev->kernel_mem_mgr, handle);
4096 
4097 free_userptr:
4098 	if (rc)
4099 		hl_userptr_delete_list(hdev, parser->job_userptr_list);
4100 	return rc;
4101 }
4102 
4103 static int goya_parse_cb_no_ext_queue(struct hl_device *hdev,
4104 					struct hl_cs_parser *parser)
4105 {
4106 	struct asic_fixed_properties *asic_prop = &hdev->asic_prop;
4107 	struct goya_device *goya = hdev->asic_specific;
4108 
4109 	if (goya->hw_cap_initialized & HW_CAP_MMU)
4110 		return 0;
4111 
4112 	/* For internal queue jobs, just check if CB address is valid */
4113 	if (hl_mem_area_inside_range(
4114 			(u64) (uintptr_t) parser->user_cb,
4115 			parser->user_cb_size,
4116 			asic_prop->sram_user_base_address,
4117 			asic_prop->sram_end_address))
4118 		return 0;
4119 
4120 	if (hl_mem_area_inside_range(
4121 			(u64) (uintptr_t) parser->user_cb,
4122 			parser->user_cb_size,
4123 			asic_prop->dram_user_base_address,
4124 			asic_prop->dram_end_address))
4125 		return 0;
4126 
4127 	dev_err(hdev->dev,
4128 		"Internal CB address 0x%px + 0x%x is not in SRAM nor in DRAM\n",
4129 		parser->user_cb, parser->user_cb_size);
4130 
4131 	return -EFAULT;
4132 }
4133 
4134 int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser)
4135 {
4136 	struct goya_device *goya = hdev->asic_specific;
4137 
4138 	if (parser->queue_type == QUEUE_TYPE_INT)
4139 		return goya_parse_cb_no_ext_queue(hdev, parser);
4140 
4141 	if (goya->hw_cap_initialized & HW_CAP_MMU)
4142 		return goya_parse_cb_mmu(hdev, parser);
4143 	else
4144 		return goya_parse_cb_no_mmu(hdev, parser);
4145 }
4146 
4147 void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
4148 				u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
4149 				u32 msix_vec, bool eb)
4150 {
4151 	struct packet_msg_prot *cq_pkt;
4152 	u32 tmp;
4153 
4154 	cq_pkt = kernel_address + len - (sizeof(struct packet_msg_prot) * 2);
4155 
4156 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4157 			(1 << GOYA_PKT_CTL_EB_SHIFT) |
4158 			(1 << GOYA_PKT_CTL_MB_SHIFT);
4159 	cq_pkt->ctl = cpu_to_le32(tmp);
4160 	cq_pkt->value = cpu_to_le32(cq_val);
4161 	cq_pkt->addr = cpu_to_le64(cq_addr);
4162 
4163 	cq_pkt++;
4164 
4165 	tmp = (PACKET_MSG_PROT << GOYA_PKT_CTL_OPCODE_SHIFT) |
4166 			(1 << GOYA_PKT_CTL_MB_SHIFT);
4167 	cq_pkt->ctl = cpu_to_le32(tmp);
4168 	cq_pkt->value = cpu_to_le32(msix_vec & 0x7FF);
4169 	cq_pkt->addr = cpu_to_le64(CFG_BASE + mmPCIE_DBI_MSIX_DOORBELL_OFF);
4170 }
4171 
4172 void goya_update_eq_ci(struct hl_device *hdev, u32 val)
4173 {
4174 	WREG32(mmCPU_EQ_CI, val);
4175 }
4176 
4177 void goya_restore_phase_topology(struct hl_device *hdev)
4178 {
4179 
4180 }
4181 
4182 static void goya_clear_sm_regs(struct hl_device *hdev)
4183 {
4184 	int i, num_of_sob_in_longs, num_of_mon_in_longs;
4185 
4186 	num_of_sob_in_longs =
4187 		((mmSYNC_MNGR_SOB_OBJ_1023 - mmSYNC_MNGR_SOB_OBJ_0) + 4);
4188 
4189 	num_of_mon_in_longs =
4190 		((mmSYNC_MNGR_MON_STATUS_255 - mmSYNC_MNGR_MON_STATUS_0) + 4);
4191 
4192 	for (i = 0 ; i < num_of_sob_in_longs ; i += 4)
4193 		WREG32(mmSYNC_MNGR_SOB_OBJ_0 + i, 0);
4194 
4195 	for (i = 0 ; i < num_of_mon_in_longs ; i += 4)
4196 		WREG32(mmSYNC_MNGR_MON_STATUS_0 + i, 0);
4197 
4198 	/* Flush all WREG to prevent race */
4199 	i = RREG32(mmSYNC_MNGR_SOB_OBJ_0);
4200 }
4201 
4202 static int goya_debugfs_read_dma(struct hl_device *hdev, u64 addr, u32 size, void *blob_addr)
4203 {
4204 	dev_err(hdev->dev, "Reading via DMA is unimplemented yet\n");
4205 	return -EPERM;
4206 }
4207 
4208 static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
4209 {
4210 	struct goya_device *goya = hdev->asic_specific;
4211 
4212 	if (hdev->reset_info.hard_reset_pending)
4213 		return U64_MAX;
4214 
4215 	return readq(hdev->pcie_bar[DDR_BAR_ID] +
4216 			(addr - goya->ddr_bar_cur_addr));
4217 }
4218 
4219 static void goya_write_pte(struct hl_device *hdev, u64 addr, u64 val)
4220 {
4221 	struct goya_device *goya = hdev->asic_specific;
4222 
4223 	if (hdev->reset_info.hard_reset_pending)
4224 		return;
4225 
4226 	writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
4227 			(addr - goya->ddr_bar_cur_addr));
4228 }
4229 
4230 static const char *_goya_get_event_desc(u16 event_type)
4231 {
4232 	switch (event_type) {
4233 	case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4234 		return "PCIe_if";
4235 	case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4236 	case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4237 	case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4238 	case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4239 	case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4240 	case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4241 	case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4242 	case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4243 		return "TPC%d_ecc";
4244 	case GOYA_ASYNC_EVENT_ID_MME_ECC:
4245 		return "MME_ecc";
4246 	case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4247 		return "MME_ecc_ext";
4248 	case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4249 		return "MMU_ecc";
4250 	case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4251 		return "DMA_macro";
4252 	case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4253 		return "DMA_ecc";
4254 	case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4255 		return "CPU_if_ecc";
4256 	case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4257 		return "PSOC_mem";
4258 	case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4259 		return "PSOC_coresight";
4260 	case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4261 		return "SRAM%d";
4262 	case GOYA_ASYNC_EVENT_ID_GIC500:
4263 		return "GIC500";
4264 	case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4265 		return "PLL%d";
4266 	case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4267 		return "AXI_ecc";
4268 	case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4269 		return "L2_ram_ecc";
4270 	case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4271 		return "PSOC_gpio_05_sw_reset";
4272 	case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4273 		return "PSOC_gpio_10_vrhot_icrit";
4274 	case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4275 		return "PCIe_dec";
4276 	case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4277 	case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4278 	case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4279 	case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4280 	case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4281 	case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4282 	case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4283 	case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4284 		return "TPC%d_dec";
4285 	case GOYA_ASYNC_EVENT_ID_MME_WACS:
4286 		return "MME_wacs";
4287 	case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4288 		return "MME_wacsd";
4289 	case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4290 		return "CPU_axi_splitter";
4291 	case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4292 		return "PSOC_axi_dec";
4293 	case GOYA_ASYNC_EVENT_ID_PSOC:
4294 		return "PSOC";
4295 	case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4296 	case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4297 	case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4298 	case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4299 	case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4300 	case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4301 	case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4302 	case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4303 		return "TPC%d_krn_err";
4304 	case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4305 		return "TPC%d_cq";
4306 	case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4307 		return "TPC%d_qm";
4308 	case GOYA_ASYNC_EVENT_ID_MME_QM:
4309 		return "MME_qm";
4310 	case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4311 		return "MME_cq";
4312 	case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4313 		return "DMA%d_qm";
4314 	case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4315 		return "DMA%d_ch";
4316 	case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4317 	case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4318 	case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4319 	case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4320 	case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4321 	case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4322 	case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4323 	case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4324 		return "TPC%d_bmon_spmu";
4325 	case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4326 		return "DMA_bm_ch%d";
4327 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4328 		return "POWER_ENV_S";
4329 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4330 		return "POWER_ENV_E";
4331 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4332 		return "THERMAL_ENV_S";
4333 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4334 		return "THERMAL_ENV_E";
4335 	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4336 		return "QUEUE_OUT_OF_SYNC";
4337 	default:
4338 		return "N/A";
4339 	}
4340 }
4341 
4342 static void goya_get_event_desc(u16 event_type, char *desc, size_t size)
4343 {
4344 	u8 index;
4345 
4346 	switch (event_type) {
4347 	case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4348 	case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4349 	case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4350 	case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4351 	case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4352 	case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4353 	case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4354 	case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4355 		index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_ECC) / 3;
4356 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4357 		break;
4358 	case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4359 		index = event_type - GOYA_ASYNC_EVENT_ID_SRAM0;
4360 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4361 		break;
4362 	case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4363 		index = event_type - GOYA_ASYNC_EVENT_ID_PLL0;
4364 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4365 		break;
4366 	case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4367 	case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4368 	case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4369 	case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4370 	case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4371 	case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4372 	case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4373 	case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4374 		index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_DEC) / 3;
4375 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4376 		break;
4377 	case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4378 	case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4379 	case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4380 	case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4381 	case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4382 	case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4383 	case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4384 	case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4385 		index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR) / 10;
4386 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4387 		break;
4388 	case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_CMDQ:
4389 		index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_CMDQ;
4390 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4391 		break;
4392 	case GOYA_ASYNC_EVENT_ID_TPC0_QM ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4393 		index = event_type - GOYA_ASYNC_EVENT_ID_TPC0_QM;
4394 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4395 		break;
4396 	case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4397 		index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_QM;
4398 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4399 		break;
4400 	case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4401 		index = event_type - GOYA_ASYNC_EVENT_ID_DMA0_CH;
4402 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4403 		break;
4404 	case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4405 	case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4406 	case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4407 	case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4408 	case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4409 	case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4410 	case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4411 	case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4412 		index = (event_type - GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU) / 10;
4413 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4414 		break;
4415 	case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4416 		index = event_type - GOYA_ASYNC_EVENT_ID_DMA_BM_CH0;
4417 		snprintf(desc, size, _goya_get_event_desc(event_type), index);
4418 		break;
4419 	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4420 		snprintf(desc, size, _goya_get_event_desc(event_type));
4421 		break;
4422 	default:
4423 		snprintf(desc, size, _goya_get_event_desc(event_type));
4424 		break;
4425 	}
4426 }
4427 
4428 static void goya_print_razwi_info(struct hl_device *hdev)
4429 {
4430 	if (RREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD)) {
4431 		dev_err_ratelimited(hdev->dev, "Illegal write to LBW\n");
4432 		WREG32(mmDMA_MACRO_RAZWI_LBW_WT_VLD, 0);
4433 	}
4434 
4435 	if (RREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD)) {
4436 		dev_err_ratelimited(hdev->dev, "Illegal read from LBW\n");
4437 		WREG32(mmDMA_MACRO_RAZWI_LBW_RD_VLD, 0);
4438 	}
4439 
4440 	if (RREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD)) {
4441 		dev_err_ratelimited(hdev->dev, "Illegal write to HBW\n");
4442 		WREG32(mmDMA_MACRO_RAZWI_HBW_WT_VLD, 0);
4443 	}
4444 
4445 	if (RREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD)) {
4446 		dev_err_ratelimited(hdev->dev, "Illegal read from HBW\n");
4447 		WREG32(mmDMA_MACRO_RAZWI_HBW_RD_VLD, 0);
4448 	}
4449 }
4450 
4451 static void goya_print_mmu_error_info(struct hl_device *hdev)
4452 {
4453 	struct goya_device *goya = hdev->asic_specific;
4454 	u64 addr;
4455 	u32 val;
4456 
4457 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4458 		return;
4459 
4460 	val = RREG32(mmMMU_PAGE_ERROR_CAPTURE);
4461 	if (val & MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK) {
4462 		addr = val & MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK;
4463 		addr <<= 32;
4464 		addr |= RREG32(mmMMU_PAGE_ERROR_CAPTURE_VA);
4465 
4466 		dev_err_ratelimited(hdev->dev, "MMU page fault on va 0x%llx\n",
4467 					addr);
4468 
4469 		WREG32(mmMMU_PAGE_ERROR_CAPTURE, 0);
4470 	}
4471 }
4472 
4473 static void goya_print_out_of_sync_info(struct hl_device *hdev,
4474 					struct cpucp_pkt_sync_err *sync_err)
4475 {
4476 	struct hl_hw_queue *q = &hdev->kernel_queues[GOYA_QUEUE_ID_CPU_PQ];
4477 
4478 	dev_err(hdev->dev, "Out of sync with FW, FW: pi=%u, ci=%u, LKD: pi=%u, ci=%d\n",
4479 		le32_to_cpu(sync_err->pi), le32_to_cpu(sync_err->ci), q->pi, atomic_read(&q->ci));
4480 }
4481 
4482 static void goya_print_irq_info(struct hl_device *hdev, u16 event_type,
4483 				bool razwi)
4484 {
4485 	char desc[20] = "";
4486 
4487 	goya_get_event_desc(event_type, desc, sizeof(desc));
4488 	dev_err_ratelimited(hdev->dev, "Received H/W interrupt %d [\"%s\"]\n",
4489 		event_type, desc);
4490 
4491 	if (razwi) {
4492 		goya_print_razwi_info(hdev);
4493 		goya_print_mmu_error_info(hdev);
4494 	}
4495 }
4496 
4497 static int goya_unmask_irq_arr(struct hl_device *hdev, u32 *irq_arr,
4498 		size_t irq_arr_size)
4499 {
4500 	struct cpucp_unmask_irq_arr_packet *pkt;
4501 	size_t total_pkt_size;
4502 	u64 result;
4503 	int rc;
4504 	int irq_num_entries, irq_arr_index;
4505 	__le32 *goya_irq_arr;
4506 
4507 	total_pkt_size = sizeof(struct cpucp_unmask_irq_arr_packet) +
4508 			irq_arr_size;
4509 
4510 	/* data should be aligned to 8 bytes in order to CPU-CP to copy it */
4511 	total_pkt_size = (total_pkt_size + 0x7) & ~0x7;
4512 
4513 	/* total_pkt_size is casted to u16 later on */
4514 	if (total_pkt_size > USHRT_MAX) {
4515 		dev_err(hdev->dev, "too many elements in IRQ array\n");
4516 		return -EINVAL;
4517 	}
4518 
4519 	pkt = kzalloc(total_pkt_size, GFP_KERNEL);
4520 	if (!pkt)
4521 		return -ENOMEM;
4522 
4523 	irq_num_entries = irq_arr_size / sizeof(irq_arr[0]);
4524 	pkt->length = cpu_to_le32(irq_num_entries);
4525 
4526 	/* We must perform any necessary endianness conversation on the irq
4527 	 * array being passed to the goya hardware
4528 	 */
4529 	for (irq_arr_index = 0, goya_irq_arr = (__le32 *) &pkt->irqs;
4530 			irq_arr_index < irq_num_entries ; irq_arr_index++)
4531 		goya_irq_arr[irq_arr_index] =
4532 				cpu_to_le32(irq_arr[irq_arr_index]);
4533 
4534 	pkt->cpucp_pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY <<
4535 						CPUCP_PKT_CTL_OPCODE_SHIFT);
4536 
4537 	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) pkt,
4538 						total_pkt_size,	0, &result);
4539 
4540 	if (rc)
4541 		dev_err(hdev->dev, "failed to unmask IRQ array\n");
4542 
4543 	kfree(pkt);
4544 
4545 	return rc;
4546 }
4547 
4548 static int goya_compute_reset_late_init(struct hl_device *hdev)
4549 {
4550 	/*
4551 	 * Unmask all IRQs since some could have been received
4552 	 * during the soft reset
4553 	 */
4554 	return goya_unmask_irq_arr(hdev, goya_all_events,
4555 					sizeof(goya_all_events));
4556 }
4557 
4558 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)
4559 {
4560 	struct cpucp_packet pkt;
4561 	u64 result;
4562 	int rc;
4563 
4564 	memset(&pkt, 0, sizeof(pkt));
4565 
4566 	pkt.ctl = cpu_to_le32(CPUCP_PACKET_UNMASK_RAZWI_IRQ <<
4567 				CPUCP_PKT_CTL_OPCODE_SHIFT);
4568 	pkt.value = cpu_to_le64(event_type);
4569 
4570 	rc = hdev->asic_funcs->send_cpu_message(hdev, (u32 *) &pkt, sizeof(pkt),
4571 						0, &result);
4572 
4573 	if (rc)
4574 		dev_err(hdev->dev, "failed to unmask RAZWI IRQ %d", event_type);
4575 
4576 	return rc;
4577 }
4578 
4579 static void goya_print_clk_change_info(struct hl_device *hdev, u16 event_type)
4580 {
4581 	ktime_t zero_time = ktime_set(0, 0);
4582 
4583 	mutex_lock(&hdev->clk_throttling.lock);
4584 
4585 	switch (event_type) {
4586 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4587 		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_POWER;
4588 		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_POWER;
4589 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].start = ktime_get();
4590 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = zero_time;
4591 		dev_info_ratelimited(hdev->dev,
4592 			"Clock throttling due to power consumption\n");
4593 		break;
4594 
4595 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4596 		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_POWER;
4597 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_POWER].end = ktime_get();
4598 		dev_info_ratelimited(hdev->dev,
4599 			"Power envelop is safe, back to optimal clock\n");
4600 		break;
4601 
4602 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4603 		hdev->clk_throttling.current_reason |= HL_CLK_THROTTLE_THERMAL;
4604 		hdev->clk_throttling.aggregated_reason |= HL_CLK_THROTTLE_THERMAL;
4605 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].start = ktime_get();
4606 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = zero_time;
4607 		dev_info_ratelimited(hdev->dev,
4608 			"Clock throttling due to overheating\n");
4609 		break;
4610 
4611 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4612 		hdev->clk_throttling.current_reason &= ~HL_CLK_THROTTLE_THERMAL;
4613 		hdev->clk_throttling.timestamp[HL_CLK_THROTTLE_TYPE_THERMAL].end = ktime_get();
4614 		dev_info_ratelimited(hdev->dev,
4615 			"Thermal envelop is safe, back to optimal clock\n");
4616 		break;
4617 
4618 	default:
4619 		dev_err(hdev->dev, "Received invalid clock change event %d\n",
4620 			event_type);
4621 		break;
4622 	}
4623 
4624 	mutex_unlock(&hdev->clk_throttling.lock);
4625 }
4626 
4627 void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry)
4628 {
4629 	u32 ctl = le32_to_cpu(eq_entry->hdr.ctl);
4630 	u16 event_type = ((ctl & EQ_CTL_EVENT_TYPE_MASK)
4631 				>> EQ_CTL_EVENT_TYPE_SHIFT);
4632 	struct goya_device *goya = hdev->asic_specific;
4633 
4634 	if (event_type >= GOYA_ASYNC_EVENT_ID_SIZE) {
4635 		dev_err(hdev->dev, "Event type %u exceeds maximum of %u",
4636 				event_type, GOYA_ASYNC_EVENT_ID_SIZE - 1);
4637 		return;
4638 	}
4639 
4640 	goya->events_stat[event_type]++;
4641 	goya->events_stat_aggregate[event_type]++;
4642 
4643 	switch (event_type) {
4644 	case GOYA_ASYNC_EVENT_ID_PCIE_IF:
4645 	case GOYA_ASYNC_EVENT_ID_TPC0_ECC:
4646 	case GOYA_ASYNC_EVENT_ID_TPC1_ECC:
4647 	case GOYA_ASYNC_EVENT_ID_TPC2_ECC:
4648 	case GOYA_ASYNC_EVENT_ID_TPC3_ECC:
4649 	case GOYA_ASYNC_EVENT_ID_TPC4_ECC:
4650 	case GOYA_ASYNC_EVENT_ID_TPC5_ECC:
4651 	case GOYA_ASYNC_EVENT_ID_TPC6_ECC:
4652 	case GOYA_ASYNC_EVENT_ID_TPC7_ECC:
4653 	case GOYA_ASYNC_EVENT_ID_MME_ECC:
4654 	case GOYA_ASYNC_EVENT_ID_MME_ECC_EXT:
4655 	case GOYA_ASYNC_EVENT_ID_MMU_ECC:
4656 	case GOYA_ASYNC_EVENT_ID_DMA_MACRO:
4657 	case GOYA_ASYNC_EVENT_ID_DMA_ECC:
4658 	case GOYA_ASYNC_EVENT_ID_CPU_IF_ECC:
4659 	case GOYA_ASYNC_EVENT_ID_PSOC_MEM:
4660 	case GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT:
4661 	case GOYA_ASYNC_EVENT_ID_SRAM0 ... GOYA_ASYNC_EVENT_ID_SRAM29:
4662 	case GOYA_ASYNC_EVENT_ID_GIC500:
4663 	case GOYA_ASYNC_EVENT_ID_PLL0 ... GOYA_ASYNC_EVENT_ID_PLL6:
4664 	case GOYA_ASYNC_EVENT_ID_AXI_ECC:
4665 	case GOYA_ASYNC_EVENT_ID_L2_RAM_ECC:
4666 		goya_print_irq_info(hdev, event_type, false);
4667 		if (hdev->hard_reset_on_fw_events)
4668 			hl_device_reset(hdev, (HL_DRV_RESET_HARD |
4669 						HL_DRV_RESET_FW_FATAL_ERR));
4670 		break;
4671 
4672 	case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET:
4673 		goya_print_irq_info(hdev, event_type, false);
4674 		if (hdev->hard_reset_on_fw_events)
4675 			hl_device_reset(hdev, HL_DRV_RESET_HARD);
4676 		break;
4677 
4678 	case GOYA_ASYNC_EVENT_ID_PCIE_DEC:
4679 	case GOYA_ASYNC_EVENT_ID_TPC0_DEC:
4680 	case GOYA_ASYNC_EVENT_ID_TPC1_DEC:
4681 	case GOYA_ASYNC_EVENT_ID_TPC2_DEC:
4682 	case GOYA_ASYNC_EVENT_ID_TPC3_DEC:
4683 	case GOYA_ASYNC_EVENT_ID_TPC4_DEC:
4684 	case GOYA_ASYNC_EVENT_ID_TPC5_DEC:
4685 	case GOYA_ASYNC_EVENT_ID_TPC6_DEC:
4686 	case GOYA_ASYNC_EVENT_ID_TPC7_DEC:
4687 	case GOYA_ASYNC_EVENT_ID_MME_WACS:
4688 	case GOYA_ASYNC_EVENT_ID_MME_WACSD:
4689 	case GOYA_ASYNC_EVENT_ID_CPU_AXI_SPLITTER:
4690 	case GOYA_ASYNC_EVENT_ID_PSOC_AXI_DEC:
4691 	case GOYA_ASYNC_EVENT_ID_PSOC:
4692 	case GOYA_ASYNC_EVENT_ID_TPC0_KRN_ERR:
4693 	case GOYA_ASYNC_EVENT_ID_TPC1_KRN_ERR:
4694 	case GOYA_ASYNC_EVENT_ID_TPC2_KRN_ERR:
4695 	case GOYA_ASYNC_EVENT_ID_TPC3_KRN_ERR:
4696 	case GOYA_ASYNC_EVENT_ID_TPC4_KRN_ERR:
4697 	case GOYA_ASYNC_EVENT_ID_TPC5_KRN_ERR:
4698 	case GOYA_ASYNC_EVENT_ID_TPC6_KRN_ERR:
4699 	case GOYA_ASYNC_EVENT_ID_TPC7_KRN_ERR:
4700 	case GOYA_ASYNC_EVENT_ID_TPC0_CMDQ ... GOYA_ASYNC_EVENT_ID_TPC7_QM:
4701 	case GOYA_ASYNC_EVENT_ID_MME_QM:
4702 	case GOYA_ASYNC_EVENT_ID_MME_CMDQ:
4703 	case GOYA_ASYNC_EVENT_ID_DMA0_QM ... GOYA_ASYNC_EVENT_ID_DMA4_QM:
4704 	case GOYA_ASYNC_EVENT_ID_DMA0_CH ... GOYA_ASYNC_EVENT_ID_DMA4_CH:
4705 		goya_print_irq_info(hdev, event_type, true);
4706 		goya_unmask_irq(hdev, event_type);
4707 		break;
4708 
4709 	case GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT:
4710 	case GOYA_ASYNC_EVENT_ID_TPC0_BMON_SPMU:
4711 	case GOYA_ASYNC_EVENT_ID_TPC1_BMON_SPMU:
4712 	case GOYA_ASYNC_EVENT_ID_TPC2_BMON_SPMU:
4713 	case GOYA_ASYNC_EVENT_ID_TPC3_BMON_SPMU:
4714 	case GOYA_ASYNC_EVENT_ID_TPC4_BMON_SPMU:
4715 	case GOYA_ASYNC_EVENT_ID_TPC5_BMON_SPMU:
4716 	case GOYA_ASYNC_EVENT_ID_TPC6_BMON_SPMU:
4717 	case GOYA_ASYNC_EVENT_ID_TPC7_BMON_SPMU:
4718 	case GOYA_ASYNC_EVENT_ID_DMA_BM_CH0 ... GOYA_ASYNC_EVENT_ID_DMA_BM_CH4:
4719 		goya_print_irq_info(hdev, event_type, false);
4720 		goya_unmask_irq(hdev, event_type);
4721 		break;
4722 
4723 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_S:
4724 	case GOYA_ASYNC_EVENT_ID_FIX_POWER_ENV_E:
4725 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_S:
4726 	case GOYA_ASYNC_EVENT_ID_FIX_THERMAL_ENV_E:
4727 		goya_print_clk_change_info(hdev, event_type);
4728 		goya_unmask_irq(hdev, event_type);
4729 		break;
4730 
4731 	case GOYA_ASYNC_EVENT_PKT_QUEUE_OUT_SYNC:
4732 		goya_print_irq_info(hdev, event_type, false);
4733 		goya_print_out_of_sync_info(hdev, &eq_entry->pkt_sync_err);
4734 		if (hdev->hard_reset_on_fw_events)
4735 			hl_device_reset(hdev, HL_DRV_RESET_HARD);
4736 		else
4737 			hl_fw_unmask_irq(hdev, event_type);
4738 		break;
4739 
4740 	default:
4741 		dev_err(hdev->dev, "Received invalid H/W interrupt %d\n",
4742 				event_type);
4743 		break;
4744 	}
4745 }
4746 
4747 void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size)
4748 {
4749 	struct goya_device *goya = hdev->asic_specific;
4750 
4751 	if (aggregate) {
4752 		*size = (u32) sizeof(goya->events_stat_aggregate);
4753 		return goya->events_stat_aggregate;
4754 	}
4755 
4756 	*size = (u32) sizeof(goya->events_stat);
4757 	return goya->events_stat;
4758 }
4759 
4760 static int goya_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size,
4761 				u64 val, bool is_dram)
4762 {
4763 	struct packet_lin_dma *lin_dma_pkt;
4764 	struct hl_cs_job *job;
4765 	u32 cb_size, ctl;
4766 	struct hl_cb *cb;
4767 	int rc, lin_dma_pkts_cnt;
4768 
4769 	lin_dma_pkts_cnt = DIV_ROUND_UP_ULL(size, SZ_2G);
4770 	cb_size = lin_dma_pkts_cnt * sizeof(struct packet_lin_dma) +
4771 						sizeof(struct packet_msg_prot);
4772 	cb = hl_cb_kernel_create(hdev, cb_size, false);
4773 	if (!cb)
4774 		return -ENOMEM;
4775 
4776 	lin_dma_pkt = cb->kernel_address;
4777 
4778 	do {
4779 		memset(lin_dma_pkt, 0, sizeof(*lin_dma_pkt));
4780 
4781 		ctl = ((PACKET_LIN_DMA << GOYA_PKT_CTL_OPCODE_SHIFT) |
4782 				(1 << GOYA_PKT_LIN_DMA_CTL_MEMSET_SHIFT) |
4783 				(1 << GOYA_PKT_LIN_DMA_CTL_WO_SHIFT) |
4784 				(1 << GOYA_PKT_CTL_RB_SHIFT) |
4785 				(1 << GOYA_PKT_CTL_MB_SHIFT));
4786 		ctl |= (is_dram ? HL_DMA_HOST_TO_DRAM : HL_DMA_HOST_TO_SRAM) <<
4787 				GOYA_PKT_LIN_DMA_CTL_DMA_DIR_SHIFT;
4788 		lin_dma_pkt->ctl = cpu_to_le32(ctl);
4789 
4790 		lin_dma_pkt->src_addr = cpu_to_le64(val);
4791 		lin_dma_pkt->dst_addr = cpu_to_le64(addr);
4792 		if (lin_dma_pkts_cnt > 1)
4793 			lin_dma_pkt->tsize = cpu_to_le32(SZ_2G);
4794 		else
4795 			lin_dma_pkt->tsize = cpu_to_le32(size);
4796 
4797 		size -= SZ_2G;
4798 		addr += SZ_2G;
4799 		lin_dma_pkt++;
4800 	} while (--lin_dma_pkts_cnt);
4801 
4802 	job = hl_cs_allocate_job(hdev, QUEUE_TYPE_EXT, true);
4803 	if (!job) {
4804 		dev_err(hdev->dev, "Failed to allocate a new job\n");
4805 		rc = -ENOMEM;
4806 		goto release_cb;
4807 	}
4808 
4809 	job->id = 0;
4810 	job->user_cb = cb;
4811 	atomic_inc(&job->user_cb->cs_cnt);
4812 	job->user_cb_size = cb_size;
4813 	job->hw_queue_id = GOYA_QUEUE_ID_DMA_0;
4814 	job->patched_cb = job->user_cb;
4815 	job->job_cb_size = job->user_cb_size;
4816 
4817 	hl_debugfs_add_job(hdev, job);
4818 
4819 	rc = goya_send_job_on_qman0(hdev, job);
4820 
4821 	hl_debugfs_remove_job(hdev, job);
4822 	kfree(job);
4823 	atomic_dec(&cb->cs_cnt);
4824 
4825 release_cb:
4826 	hl_cb_put(cb);
4827 	hl_cb_destroy(&hdev->kernel_mem_mgr, cb->buf->handle);
4828 
4829 	return rc;
4830 }
4831 
4832 int goya_context_switch(struct hl_device *hdev, u32 asid)
4833 {
4834 	struct asic_fixed_properties *prop = &hdev->asic_prop;
4835 	u64 addr = prop->sram_base_address, sob_addr;
4836 	u32 size = hdev->pldm ? 0x10000 : prop->sram_size;
4837 	u64 val = 0x7777777777777777ull;
4838 	int rc, dma_id;
4839 	u32 channel_off = mmDMA_CH_1_WR_COMP_ADDR_LO -
4840 					mmDMA_CH_0_WR_COMP_ADDR_LO;
4841 
4842 	rc = goya_memset_device_memory(hdev, addr, size, val, false);
4843 	if (rc) {
4844 		dev_err(hdev->dev, "Failed to clear SRAM in context switch\n");
4845 		return rc;
4846 	}
4847 
4848 	/* we need to reset registers that the user is allowed to change */
4849 	sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1007;
4850 	WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO, lower_32_bits(sob_addr));
4851 
4852 	for (dma_id = 1 ; dma_id < NUMBER_OF_EXT_HW_QUEUES ; dma_id++) {
4853 		sob_addr = CFG_BASE + mmSYNC_MNGR_SOB_OBJ_1000 +
4854 							(dma_id - 1) * 4;
4855 		WREG32(mmDMA_CH_0_WR_COMP_ADDR_LO + channel_off * dma_id,
4856 						lower_32_bits(sob_addr));
4857 	}
4858 
4859 	WREG32(mmTPC_PLL_CLK_RLX_0, 0x200020);
4860 
4861 	goya_clear_sm_regs(hdev);
4862 
4863 	return 0;
4864 }
4865 
4866 static int goya_mmu_clear_pgt_range(struct hl_device *hdev)
4867 {
4868 	struct asic_fixed_properties *prop = &hdev->asic_prop;
4869 	struct goya_device *goya = hdev->asic_specific;
4870 	u64 addr = prop->mmu_pgt_addr;
4871 	u32 size = prop->mmu_pgt_size + MMU_DRAM_DEFAULT_PAGE_SIZE +
4872 			MMU_CACHE_MNG_SIZE;
4873 
4874 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4875 		return 0;
4876 
4877 	return goya_memset_device_memory(hdev, addr, size, 0, true);
4878 }
4879 
4880 static int goya_mmu_set_dram_default_page(struct hl_device *hdev)
4881 {
4882 	struct goya_device *goya = hdev->asic_specific;
4883 	u64 addr = hdev->asic_prop.mmu_dram_default_page_addr;
4884 	u32 size = MMU_DRAM_DEFAULT_PAGE_SIZE;
4885 	u64 val = 0x9999999999999999ull;
4886 
4887 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4888 		return 0;
4889 
4890 	return goya_memset_device_memory(hdev, addr, size, val, true);
4891 }
4892 
4893 static int goya_mmu_add_mappings_for_device_cpu(struct hl_device *hdev)
4894 {
4895 	struct asic_fixed_properties *prop = &hdev->asic_prop;
4896 	struct goya_device *goya = hdev->asic_specific;
4897 	s64 off, cpu_off;
4898 	int rc;
4899 
4900 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4901 		return 0;
4902 
4903 	for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB) {
4904 		rc = hl_mmu_map_page(hdev->kernel_ctx,
4905 			prop->dram_base_address + off,
4906 			prop->dram_base_address + off, PAGE_SIZE_2MB,
4907 			(off + PAGE_SIZE_2MB) == CPU_FW_IMAGE_SIZE);
4908 		if (rc) {
4909 			dev_err(hdev->dev, "Map failed for address 0x%llx\n",
4910 				prop->dram_base_address + off);
4911 			goto unmap;
4912 		}
4913 	}
4914 
4915 	if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4916 		rc = hl_mmu_map_page(hdev->kernel_ctx,
4917 			VA_CPU_ACCESSIBLE_MEM_ADDR,
4918 			hdev->cpu_accessible_dma_address,
4919 			PAGE_SIZE_2MB, true);
4920 
4921 		if (rc) {
4922 			dev_err(hdev->dev,
4923 				"Map failed for CPU accessible memory\n");
4924 			off -= PAGE_SIZE_2MB;
4925 			goto unmap;
4926 		}
4927 	} else {
4928 		for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB) {
4929 			rc = hl_mmu_map_page(hdev->kernel_ctx,
4930 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4931 				hdev->cpu_accessible_dma_address + cpu_off,
4932 				PAGE_SIZE_4KB, true);
4933 			if (rc) {
4934 				dev_err(hdev->dev,
4935 					"Map failed for CPU accessible memory\n");
4936 				cpu_off -= PAGE_SIZE_4KB;
4937 				goto unmap_cpu;
4938 			}
4939 		}
4940 	}
4941 
4942 	goya_mmu_prepare_reg(hdev, mmCPU_IF_ARUSER_OVR, HL_KERNEL_ASID_ID);
4943 	goya_mmu_prepare_reg(hdev, mmCPU_IF_AWUSER_OVR, HL_KERNEL_ASID_ID);
4944 	WREG32(mmCPU_IF_ARUSER_OVR_EN, 0x7FF);
4945 	WREG32(mmCPU_IF_AWUSER_OVR_EN, 0x7FF);
4946 
4947 	/* Make sure configuration is flushed to device */
4948 	RREG32(mmCPU_IF_AWUSER_OVR_EN);
4949 
4950 	goya->device_cpu_mmu_mappings_done = true;
4951 
4952 	return 0;
4953 
4954 unmap_cpu:
4955 	for (; cpu_off >= 0 ; cpu_off -= PAGE_SIZE_4KB)
4956 		if (hl_mmu_unmap_page(hdev->kernel_ctx,
4957 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4958 				PAGE_SIZE_4KB, true))
4959 			dev_warn_ratelimited(hdev->dev,
4960 				"failed to unmap address 0x%llx\n",
4961 				VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
4962 unmap:
4963 	for (; off >= 0 ; off -= PAGE_SIZE_2MB)
4964 		if (hl_mmu_unmap_page(hdev->kernel_ctx,
4965 				prop->dram_base_address + off, PAGE_SIZE_2MB,
4966 				true))
4967 			dev_warn_ratelimited(hdev->dev,
4968 				"failed to unmap address 0x%llx\n",
4969 				prop->dram_base_address + off);
4970 
4971 	return rc;
4972 }
4973 
4974 void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev)
4975 {
4976 	struct asic_fixed_properties *prop = &hdev->asic_prop;
4977 	struct goya_device *goya = hdev->asic_specific;
4978 	u32 off, cpu_off;
4979 
4980 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
4981 		return;
4982 
4983 	if (!goya->device_cpu_mmu_mappings_done)
4984 		return;
4985 
4986 	WREG32(mmCPU_IF_ARUSER_OVR_EN, 0);
4987 	WREG32(mmCPU_IF_AWUSER_OVR_EN, 0);
4988 
4989 	if (!(hdev->cpu_accessible_dma_address & (PAGE_SIZE_2MB - 1))) {
4990 		if (hl_mmu_unmap_page(hdev->kernel_ctx,
4991 				VA_CPU_ACCESSIBLE_MEM_ADDR,
4992 				PAGE_SIZE_2MB, true))
4993 			dev_warn(hdev->dev,
4994 				"Failed to unmap CPU accessible memory\n");
4995 	} else {
4996 		for (cpu_off = 0 ; cpu_off < SZ_2M ; cpu_off += PAGE_SIZE_4KB)
4997 			if (hl_mmu_unmap_page(hdev->kernel_ctx,
4998 					VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off,
4999 					PAGE_SIZE_4KB,
5000 					(cpu_off + PAGE_SIZE_4KB) >= SZ_2M))
5001 				dev_warn_ratelimited(hdev->dev,
5002 					"failed to unmap address 0x%llx\n",
5003 					VA_CPU_ACCESSIBLE_MEM_ADDR + cpu_off);
5004 	}
5005 
5006 	for (off = 0 ; off < CPU_FW_IMAGE_SIZE ; off += PAGE_SIZE_2MB)
5007 		if (hl_mmu_unmap_page(hdev->kernel_ctx,
5008 				prop->dram_base_address + off, PAGE_SIZE_2MB,
5009 				(off + PAGE_SIZE_2MB) >= CPU_FW_IMAGE_SIZE))
5010 			dev_warn_ratelimited(hdev->dev,
5011 					"Failed to unmap address 0x%llx\n",
5012 					prop->dram_base_address + off);
5013 
5014 	goya->device_cpu_mmu_mappings_done = false;
5015 }
5016 
5017 static void goya_mmu_prepare(struct hl_device *hdev, u32 asid)
5018 {
5019 	struct goya_device *goya = hdev->asic_specific;
5020 	int i;
5021 
5022 	if (!(goya->hw_cap_initialized & HW_CAP_MMU))
5023 		return;
5024 
5025 	if (asid & ~MME_QM_GLBL_SECURE_PROPS_ASID_MASK) {
5026 		dev_crit(hdev->dev, "asid %u is too big\n", asid);
5027 		return;
5028 	}
5029 
5030 	/* zero the MMBP and ASID bits and then set the ASID */
5031 	for (i = 0 ; i < GOYA_MMU_REGS_NUM ; i++)
5032 		goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid);
5033 }
5034 
5035 static int goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard,
5036 					u32 flags)
5037 {
5038 	struct goya_device *goya = hdev->asic_specific;
5039 	u32 status, timeout_usec;
5040 	int rc;
5041 
5042 	if (!(goya->hw_cap_initialized & HW_CAP_MMU) ||
5043 		hdev->reset_info.hard_reset_pending)
5044 		return 0;
5045 
5046 	/* no need in L1 only invalidation in Goya */
5047 	if (!is_hard)
5048 		return 0;
5049 
5050 	if (hdev->pldm)
5051 		timeout_usec = GOYA_PLDM_MMU_TIMEOUT_USEC;
5052 	else
5053 		timeout_usec = MMU_CONFIG_TIMEOUT_USEC;
5054 
5055 	/* L0 & L1 invalidation */
5056 	WREG32(mmSTLB_INV_ALL_START, 1);
5057 
5058 	rc = hl_poll_timeout(
5059 		hdev,
5060 		mmSTLB_INV_ALL_START,
5061 		status,
5062 		!status,
5063 		1000,
5064 		timeout_usec);
5065 
5066 	return rc;
5067 }
5068 
5069 static int goya_mmu_invalidate_cache_range(struct hl_device *hdev,
5070 						bool is_hard, u32 flags,
5071 						u32 asid, u64 va, u64 size)
5072 {
5073 	/* Treat as invalidate all because there is no range invalidation
5074 	 * in Goya
5075 	 */
5076 	return hl_mmu_invalidate_cache(hdev, is_hard, flags);
5077 }
5078 
5079 int goya_send_heartbeat(struct hl_device *hdev)
5080 {
5081 	struct goya_device *goya = hdev->asic_specific;
5082 
5083 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5084 		return 0;
5085 
5086 	return hl_fw_send_heartbeat(hdev);
5087 }
5088 
5089 int goya_cpucp_info_get(struct hl_device *hdev)
5090 {
5091 	struct goya_device *goya = hdev->asic_specific;
5092 	struct asic_fixed_properties *prop = &hdev->asic_prop;
5093 	u64 dram_size;
5094 	int rc;
5095 
5096 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5097 		return 0;
5098 
5099 	rc = hl_fw_cpucp_handshake(hdev, mmCPU_BOOT_DEV_STS0,
5100 					mmCPU_BOOT_DEV_STS1, mmCPU_BOOT_ERR0,
5101 					mmCPU_BOOT_ERR1);
5102 	if (rc)
5103 		return rc;
5104 
5105 	dram_size = le64_to_cpu(prop->cpucp_info.dram_size);
5106 	if (dram_size) {
5107 		if ((!is_power_of_2(dram_size)) ||
5108 				(dram_size < DRAM_PHYS_DEFAULT_SIZE)) {
5109 			dev_err(hdev->dev,
5110 				"F/W reported invalid DRAM size %llu. Trying to use default size\n",
5111 				dram_size);
5112 			dram_size = DRAM_PHYS_DEFAULT_SIZE;
5113 		}
5114 
5115 		prop->dram_size = dram_size;
5116 		prop->dram_end_address = prop->dram_base_address + dram_size;
5117 	}
5118 
5119 	if (!strlen(prop->cpucp_info.card_name))
5120 		strncpy(prop->cpucp_info.card_name, GOYA_DEFAULT_CARD_NAME,
5121 				CARD_NAME_MAX_LEN);
5122 
5123 	return 0;
5124 }
5125 
5126 static bool goya_is_device_idle(struct hl_device *hdev, u64 *mask_arr, u8 mask_len,
5127 				struct engines_data *e)
5128 {
5129 	const char *fmt = "%-5d%-9s%#-14x%#-16x%#x\n";
5130 	const char *dma_fmt = "%-5d%-9s%#-14x%#x\n";
5131 	unsigned long *mask = (unsigned long *)mask_arr;
5132 	u32 qm_glbl_sts0, cmdq_glbl_sts0, dma_core_sts0, tpc_cfg_sts,
5133 		mme_arch_sts;
5134 	bool is_idle = true, is_eng_idle;
5135 	u64 offset;
5136 	int i;
5137 
5138 	if (e)
5139 		hl_engine_data_sprintf(e, "\nDMA  is_idle  QM_GLBL_STS0  DMA_CORE_STS0\n"
5140 					"---  -------  ------------  -------------\n");
5141 
5142 	offset = mmDMA_QM_1_GLBL_STS0 - mmDMA_QM_0_GLBL_STS0;
5143 
5144 	for (i = 0 ; i < DMA_MAX_NUM ; i++) {
5145 		qm_glbl_sts0 = RREG32(mmDMA_QM_0_GLBL_STS0 + i * offset);
5146 		dma_core_sts0 = RREG32(mmDMA_CH_0_STS0 + i * offset);
5147 		is_eng_idle = IS_DMA_QM_IDLE(qm_glbl_sts0) &&
5148 				IS_DMA_IDLE(dma_core_sts0);
5149 		is_idle &= is_eng_idle;
5150 
5151 		if (mask && !is_eng_idle)
5152 			set_bit(GOYA_ENGINE_ID_DMA_0 + i, mask);
5153 		if (e)
5154 			hl_engine_data_sprintf(e, dma_fmt, i, is_eng_idle ? "Y" : "N",
5155 					qm_glbl_sts0, dma_core_sts0);
5156 	}
5157 
5158 	if (e)
5159 		hl_engine_data_sprintf(e,
5160 			"\nTPC  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  CFG_STATUS\n"
5161 			"---  -------  ------------  --------------  ----------\n");
5162 
5163 	offset = mmTPC1_QM_GLBL_STS0 - mmTPC0_QM_GLBL_STS0;
5164 
5165 	for (i = 0 ; i < TPC_MAX_NUM ; i++) {
5166 		qm_glbl_sts0 = RREG32(mmTPC0_QM_GLBL_STS0 + i * offset);
5167 		cmdq_glbl_sts0 = RREG32(mmTPC0_CMDQ_GLBL_STS0 + i * offset);
5168 		tpc_cfg_sts = RREG32(mmTPC0_CFG_STATUS + i * offset);
5169 		is_eng_idle = IS_TPC_QM_IDLE(qm_glbl_sts0) &&
5170 				IS_TPC_CMDQ_IDLE(cmdq_glbl_sts0) &&
5171 				IS_TPC_IDLE(tpc_cfg_sts);
5172 		is_idle &= is_eng_idle;
5173 
5174 		if (mask && !is_eng_idle)
5175 			set_bit(GOYA_ENGINE_ID_TPC_0 + i, mask);
5176 		if (e)
5177 			hl_engine_data_sprintf(e, fmt, i, is_eng_idle ? "Y" : "N",
5178 				qm_glbl_sts0, cmdq_glbl_sts0, tpc_cfg_sts);
5179 	}
5180 
5181 	if (e)
5182 		hl_engine_data_sprintf(e,
5183 			"\nMME  is_idle  QM_GLBL_STS0  CMDQ_GLBL_STS0  ARCH_STATUS\n"
5184 			"---  -------  ------------  --------------  -----------\n");
5185 
5186 	qm_glbl_sts0 = RREG32(mmMME_QM_GLBL_STS0);
5187 	cmdq_glbl_sts0 = RREG32(mmMME_CMDQ_GLBL_STS0);
5188 	mme_arch_sts = RREG32(mmMME_ARCH_STATUS);
5189 	is_eng_idle = IS_MME_QM_IDLE(qm_glbl_sts0) &&
5190 			IS_MME_CMDQ_IDLE(cmdq_glbl_sts0) &&
5191 			IS_MME_IDLE(mme_arch_sts);
5192 	is_idle &= is_eng_idle;
5193 
5194 	if (mask && !is_eng_idle)
5195 		set_bit(GOYA_ENGINE_ID_MME_0, mask);
5196 	if (e) {
5197 		hl_engine_data_sprintf(e, fmt, 0, is_eng_idle ? "Y" : "N", qm_glbl_sts0,
5198 				cmdq_glbl_sts0, mme_arch_sts);
5199 		hl_engine_data_sprintf(e, "\n");
5200 	}
5201 
5202 	return is_idle;
5203 }
5204 
5205 static void goya_hw_queues_lock(struct hl_device *hdev)
5206 	__acquires(&goya->hw_queues_lock)
5207 {
5208 	struct goya_device *goya = hdev->asic_specific;
5209 
5210 	spin_lock(&goya->hw_queues_lock);
5211 }
5212 
5213 static void goya_hw_queues_unlock(struct hl_device *hdev)
5214 	__releases(&goya->hw_queues_lock)
5215 {
5216 	struct goya_device *goya = hdev->asic_specific;
5217 
5218 	spin_unlock(&goya->hw_queues_lock);
5219 }
5220 
5221 static u32 goya_get_pci_id(struct hl_device *hdev)
5222 {
5223 	return hdev->pdev->device;
5224 }
5225 
5226 static int goya_get_eeprom_data(struct hl_device *hdev, void *data,
5227 				size_t max_size)
5228 {
5229 	struct goya_device *goya = hdev->asic_specific;
5230 
5231 	if (!(goya->hw_cap_initialized & HW_CAP_CPU_Q))
5232 		return 0;
5233 
5234 	return hl_fw_get_eeprom_data(hdev, data, max_size);
5235 }
5236 
5237 static void goya_cpu_init_scrambler_dram(struct hl_device *hdev)
5238 {
5239 
5240 }
5241 
5242 static int goya_ctx_init(struct hl_ctx *ctx)
5243 {
5244 	if (ctx->asid != HL_KERNEL_ASID_ID)
5245 		goya_mmu_prepare(ctx->hdev, ctx->asid);
5246 
5247 	return 0;
5248 }
5249 
5250 static int goya_pre_schedule_cs(struct hl_cs *cs)
5251 {
5252 	return 0;
5253 }
5254 
5255 u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx)
5256 {
5257 	return cq_idx;
5258 }
5259 
5260 static u32 goya_get_signal_cb_size(struct hl_device *hdev)
5261 {
5262 	return 0;
5263 }
5264 
5265 static u32 goya_get_wait_cb_size(struct hl_device *hdev)
5266 {
5267 	return 0;
5268 }
5269 
5270 static u32 goya_gen_signal_cb(struct hl_device *hdev, void *data, u16 sob_id,
5271 				u32 size, bool eb)
5272 {
5273 	return 0;
5274 }
5275 
5276 static u32 goya_gen_wait_cb(struct hl_device *hdev,
5277 		struct hl_gen_wait_properties *prop)
5278 {
5279 	return 0;
5280 }
5281 
5282 static void goya_reset_sob(struct hl_device *hdev, void *data)
5283 {
5284 
5285 }
5286 
5287 static void goya_reset_sob_group(struct hl_device *hdev, u16 sob_group)
5288 {
5289 
5290 }
5291 
5292 u64 goya_get_device_time(struct hl_device *hdev)
5293 {
5294 	u64 device_time = ((u64) RREG32(mmPSOC_TIMESTAMP_CNTCVU)) << 32;
5295 
5296 	return device_time | RREG32(mmPSOC_TIMESTAMP_CNTCVL);
5297 }
5298 
5299 static int goya_collective_wait_init_cs(struct hl_cs *cs)
5300 {
5301 	return 0;
5302 }
5303 
5304 static int goya_collective_wait_create_jobs(struct hl_device *hdev,
5305 		struct hl_ctx *ctx, struct hl_cs *cs, u32 wait_queue_id,
5306 		u32 collective_engine_id, u32 encaps_signal_offset)
5307 {
5308 	return -EINVAL;
5309 }
5310 
5311 static void goya_ctx_fini(struct hl_ctx *ctx)
5312 {
5313 
5314 }
5315 
5316 static int goya_get_hw_block_id(struct hl_device *hdev, u64 block_addr,
5317 			u32 *block_size, u32 *block_id)
5318 {
5319 	return -EPERM;
5320 }
5321 
5322 static int goya_block_mmap(struct hl_device *hdev, struct vm_area_struct *vma,
5323 				u32 block_id, u32 block_size)
5324 {
5325 	return -EPERM;
5326 }
5327 
5328 static void goya_enable_events_from_fw(struct hl_device *hdev)
5329 {
5330 	WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR,
5331 			GOYA_ASYNC_EVENT_ID_INTS_REGISTER);
5332 }
5333 
5334 static int goya_ack_mmu_page_fault_or_access_error(struct hl_device *hdev, u64 mmu_cap_mask)
5335 {
5336 	return -EINVAL;
5337 }
5338 
5339 static int goya_map_pll_idx_to_fw_idx(u32 pll_idx)
5340 {
5341 	switch (pll_idx) {
5342 	case HL_GOYA_CPU_PLL: return CPU_PLL;
5343 	case HL_GOYA_PCI_PLL: return PCI_PLL;
5344 	case HL_GOYA_MME_PLL: return MME_PLL;
5345 	case HL_GOYA_TPC_PLL: return TPC_PLL;
5346 	case HL_GOYA_IC_PLL: return IC_PLL;
5347 	case HL_GOYA_MC_PLL: return MC_PLL;
5348 	case HL_GOYA_EMMC_PLL: return EMMC_PLL;
5349 	default: return -EINVAL;
5350 	}
5351 }
5352 
5353 static int goya_gen_sync_to_engine_map(struct hl_device *hdev,
5354 				struct hl_sync_to_engine_map *map)
5355 {
5356 	/* Not implemented */
5357 	return 0;
5358 }
5359 
5360 static int goya_monitor_valid(struct hl_mon_state_dump *mon)
5361 {
5362 	/* Not implemented */
5363 	return 0;
5364 }
5365 
5366 static int goya_print_single_monitor(char **buf, size_t *size, size_t *offset,
5367 				struct hl_device *hdev,
5368 				struct hl_mon_state_dump *mon)
5369 {
5370 	/* Not implemented */
5371 	return 0;
5372 }
5373 
5374 
5375 static int goya_print_fences_single_engine(
5376 	struct hl_device *hdev, u64 base_offset, u64 status_base_offset,
5377 	enum hl_sync_engine_type engine_type, u32 engine_id, char **buf,
5378 	size_t *size, size_t *offset)
5379 {
5380 	/* Not implemented */
5381 	return 0;
5382 }
5383 
5384 
5385 static struct hl_state_dump_specs_funcs goya_state_dump_funcs = {
5386 	.monitor_valid = goya_monitor_valid,
5387 	.print_single_monitor = goya_print_single_monitor,
5388 	.gen_sync_to_engine_map = goya_gen_sync_to_engine_map,
5389 	.print_fences_single_engine = goya_print_fences_single_engine,
5390 };
5391 
5392 static void goya_state_dump_init(struct hl_device *hdev)
5393 {
5394 	/* Not implemented */
5395 	hdev->state_dump_specs.props = goya_state_dump_specs_props;
5396 	hdev->state_dump_specs.funcs = goya_state_dump_funcs;
5397 }
5398 
5399 static u32 goya_get_sob_addr(struct hl_device *hdev, u32 sob_id)
5400 {
5401 	return 0;
5402 }
5403 
5404 static u32 *goya_get_stream_master_qid_arr(void)
5405 {
5406 	return NULL;
5407 }
5408 
5409 static int goya_get_monitor_dump(struct hl_device *hdev, void *data)
5410 {
5411 	return -EOPNOTSUPP;
5412 }
5413 
5414 static void goya_check_if_razwi_happened(struct hl_device *hdev)
5415 {
5416 }
5417 
5418 static int goya_scrub_device_dram(struct hl_device *hdev, u64 val)
5419 {
5420 	return -EOPNOTSUPP;
5421 }
5422 
5423 static int goya_set_dram_properties(struct hl_device *hdev)
5424 {
5425 	return 0;
5426 }
5427 
5428 static int goya_set_binning_masks(struct hl_device *hdev)
5429 {
5430 	return 0;
5431 }
5432 
5433 static int goya_send_device_activity(struct hl_device *hdev, bool open)
5434 {
5435 	return 0;
5436 }
5437 
5438 static const struct hl_asic_funcs goya_funcs = {
5439 	.early_init = goya_early_init,
5440 	.early_fini = goya_early_fini,
5441 	.late_init = goya_late_init,
5442 	.late_fini = goya_late_fini,
5443 	.sw_init = goya_sw_init,
5444 	.sw_fini = goya_sw_fini,
5445 	.hw_init = goya_hw_init,
5446 	.hw_fini = goya_hw_fini,
5447 	.halt_engines = goya_halt_engines,
5448 	.suspend = goya_suspend,
5449 	.resume = goya_resume,
5450 	.mmap = goya_mmap,
5451 	.ring_doorbell = goya_ring_doorbell,
5452 	.pqe_write = goya_pqe_write,
5453 	.asic_dma_alloc_coherent = goya_dma_alloc_coherent,
5454 	.asic_dma_free_coherent = goya_dma_free_coherent,
5455 	.scrub_device_mem = goya_scrub_device_mem,
5456 	.scrub_device_dram = goya_scrub_device_dram,
5457 	.get_int_queue_base = goya_get_int_queue_base,
5458 	.test_queues = goya_test_queues,
5459 	.asic_dma_pool_zalloc = goya_dma_pool_zalloc,
5460 	.asic_dma_pool_free = goya_dma_pool_free,
5461 	.cpu_accessible_dma_pool_alloc = goya_cpu_accessible_dma_pool_alloc,
5462 	.cpu_accessible_dma_pool_free = goya_cpu_accessible_dma_pool_free,
5463 	.hl_dma_unmap_sgtable = hl_dma_unmap_sgtable,
5464 	.cs_parser = goya_cs_parser,
5465 	.asic_dma_map_sgtable = hl_dma_map_sgtable,
5466 	.add_end_of_cb_packets = goya_add_end_of_cb_packets,
5467 	.update_eq_ci = goya_update_eq_ci,
5468 	.context_switch = goya_context_switch,
5469 	.restore_phase_topology = goya_restore_phase_topology,
5470 	.debugfs_read_dma = goya_debugfs_read_dma,
5471 	.add_device_attr = goya_add_device_attr,
5472 	.handle_eqe = goya_handle_eqe,
5473 	.get_events_stat = goya_get_events_stat,
5474 	.read_pte = goya_read_pte,
5475 	.write_pte = goya_write_pte,
5476 	.mmu_invalidate_cache = goya_mmu_invalidate_cache,
5477 	.mmu_invalidate_cache_range = goya_mmu_invalidate_cache_range,
5478 	.mmu_prefetch_cache_range = NULL,
5479 	.send_heartbeat = goya_send_heartbeat,
5480 	.debug_coresight = goya_debug_coresight,
5481 	.is_device_idle = goya_is_device_idle,
5482 	.compute_reset_late_init = goya_compute_reset_late_init,
5483 	.hw_queues_lock = goya_hw_queues_lock,
5484 	.hw_queues_unlock = goya_hw_queues_unlock,
5485 	.get_pci_id = goya_get_pci_id,
5486 	.get_eeprom_data = goya_get_eeprom_data,
5487 	.get_monitor_dump = goya_get_monitor_dump,
5488 	.send_cpu_message = goya_send_cpu_message,
5489 	.pci_bars_map = goya_pci_bars_map,
5490 	.init_iatu = goya_init_iatu,
5491 	.rreg = hl_rreg,
5492 	.wreg = hl_wreg,
5493 	.halt_coresight = goya_halt_coresight,
5494 	.ctx_init = goya_ctx_init,
5495 	.ctx_fini = goya_ctx_fini,
5496 	.pre_schedule_cs = goya_pre_schedule_cs,
5497 	.get_queue_id_for_cq = goya_get_queue_id_for_cq,
5498 	.load_firmware_to_device = goya_load_firmware_to_device,
5499 	.load_boot_fit_to_device = goya_load_boot_fit_to_device,
5500 	.get_signal_cb_size = goya_get_signal_cb_size,
5501 	.get_wait_cb_size = goya_get_wait_cb_size,
5502 	.gen_signal_cb = goya_gen_signal_cb,
5503 	.gen_wait_cb = goya_gen_wait_cb,
5504 	.reset_sob = goya_reset_sob,
5505 	.reset_sob_group = goya_reset_sob_group,
5506 	.get_device_time = goya_get_device_time,
5507 	.pb_print_security_errors = NULL,
5508 	.collective_wait_init_cs = goya_collective_wait_init_cs,
5509 	.collective_wait_create_jobs = goya_collective_wait_create_jobs,
5510 	.get_dec_base_addr = NULL,
5511 	.scramble_addr = hl_mmu_scramble_addr,
5512 	.descramble_addr = hl_mmu_descramble_addr,
5513 	.ack_protection_bits_errors = goya_ack_protection_bits_errors,
5514 	.get_hw_block_id = goya_get_hw_block_id,
5515 	.hw_block_mmap = goya_block_mmap,
5516 	.enable_events_from_fw = goya_enable_events_from_fw,
5517 	.ack_mmu_errors = goya_ack_mmu_page_fault_or_access_error,
5518 	.map_pll_idx_to_fw_idx = goya_map_pll_idx_to_fw_idx,
5519 	.init_firmware_preload_params = goya_init_firmware_preload_params,
5520 	.init_firmware_loader = goya_init_firmware_loader,
5521 	.init_cpu_scrambler_dram = goya_cpu_init_scrambler_dram,
5522 	.state_dump_init = goya_state_dump_init,
5523 	.get_sob_addr = &goya_get_sob_addr,
5524 	.set_pci_memory_regions = goya_set_pci_memory_regions,
5525 	.get_stream_master_qid_arr = goya_get_stream_master_qid_arr,
5526 	.check_if_razwi_happened = goya_check_if_razwi_happened,
5527 	.mmu_get_real_page_size = hl_mmu_get_real_page_size,
5528 	.access_dev_mem = hl_access_dev_mem,
5529 	.set_dram_bar_base = goya_set_ddr_bar_base,
5530 	.send_device_activity = goya_send_device_activity,
5531 	.set_dram_properties = goya_set_dram_properties,
5532 	.set_binning_masks = goya_set_binning_masks,
5533 };
5534 
5535 /*
5536  * goya_set_asic_funcs - set Goya function pointers
5537  *
5538  * @*hdev: pointer to hl_device structure
5539  *
5540  */
5541 void goya_set_asic_funcs(struct hl_device *hdev)
5542 {
5543 	hdev->asic_funcs = &goya_funcs;
5544 }
5545