1 /*
2  * arch/xtensa/platform/xtavnet/include/platform/hardware.h
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 2006 Tensilica Inc.
9  */
10 
11 /*
12  * This file contains the hardware configuration of the XTAVNET boards.
13  */
14 
15 #include <asm/types.h>
16 
17 #ifndef __XTENSA_XTAVNET_HARDWARE_H
18 #define __XTENSA_XTAVNET_HARDWARE_H
19 
20 /* Default assignment of LX60 devices to external interrupts. */
21 
22 #ifdef CONFIG_XTENSA_MX
23 #define DUART16552_INTNUM	XCHAL_EXTINT3_NUM
24 #define OETH_IRQ		XCHAL_EXTINT4_NUM
25 #define C67X00_IRQ		XCHAL_EXTINT8_NUM
26 #else
27 #define DUART16552_INTNUM	XCHAL_EXTINT0_NUM
28 #define OETH_IRQ		XCHAL_EXTINT1_NUM
29 #define C67X00_IRQ		XCHAL_EXTINT5_NUM
30 #endif
31 
32 /*
33  *  Device addresses and parameters.
34  */
35 
36 /* UART */
37 #define DUART16552_PADDR	(XCHAL_KIO_PADDR + 0x0D050020)
38 
39 /* Misc. */
40 #define XTFPGA_FPGAREGS_VADDR	IOADDR(0x0D020000)
41 /* Clock frequency in Hz (read-only):  */
42 #define XTFPGA_CLKFRQ_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x04)
43 /* Setting of 8 DIP switches:  */
44 #define DIP_SWITCHES_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x0C)
45 /* Software reset (write 0xdead):  */
46 #define XTFPGA_SWRST_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x10)
47 
48 /*  OpenCores Ethernet controller:  */
49 				/* regs + RX/TX descriptors */
50 #define OETH_REGS_PADDR		(XCHAL_KIO_PADDR + 0x0D030000)
51 #define OETH_REGS_SIZE		0x1000
52 #define OETH_SRAMBUFF_PADDR	(XCHAL_KIO_PADDR + 0x0D800000)
53 
54 				/* 5*rx buffs + 5*tx buffs */
55 #define OETH_SRAMBUFF_SIZE	(5 * 0x600 + 5 * 0x600)
56 
57 #define C67X00_PADDR		(XCHAL_KIO_PADDR + 0x0D0D0000)
58 #define C67X00_SIZE		0x10
59 
60 #endif /* __XTENSA_XTAVNET_HARDWARE_H */
61