1 /* 2 * arch/xtensa/mm/cache.c 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2001-2006 Tensilica Inc. 9 * 10 * Chris Zankel <chris@zankel.net> 11 * Joe Taylor 12 * Marc Gauthier 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/signal.h> 18 #include <linux/sched.h> 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/string.h> 22 #include <linux/types.h> 23 #include <linux/ptrace.h> 24 #include <linux/memblock.h> 25 #include <linux/swap.h> 26 #include <linux/pagemap.h> 27 #include <linux/pgtable.h> 28 29 #include <asm/bootparam.h> 30 #include <asm/mmu_context.h> 31 #include <asm/tlb.h> 32 #include <asm/tlbflush.h> 33 #include <asm/page.h> 34 35 /* 36 * Note: 37 * The kernel provides one architecture bit PG_arch_1 in the page flags that 38 * can be used for cache coherency. 39 * 40 * I$-D$ coherency. 41 * 42 * The Xtensa architecture doesn't keep the instruction cache coherent with 43 * the data cache. We use the architecture bit to indicate if the caches 44 * are coherent. The kernel clears this bit whenever a page is added to the 45 * page cache. At that time, the caches might not be in sync. We, therefore, 46 * define this flag as 'clean' if set. 47 * 48 * D-cache aliasing. 49 * 50 * With cache aliasing, we have to always flush the cache when pages are 51 * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty 52 * page. 53 * 54 * 55 * 56 */ 57 58 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 59 static inline void kmap_invalidate_coherent(struct page *page, 60 unsigned long vaddr) 61 { 62 if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) { 63 unsigned long kvaddr; 64 65 if (!PageHighMem(page)) { 66 kvaddr = (unsigned long)page_to_virt(page); 67 68 __invalidate_dcache_page(kvaddr); 69 } else { 70 kvaddr = TLBTEMP_BASE_1 + 71 (page_to_phys(page) & DCACHE_ALIAS_MASK); 72 73 preempt_disable(); 74 __invalidate_dcache_page_alias(kvaddr, 75 page_to_phys(page)); 76 preempt_enable(); 77 } 78 } 79 } 80 81 static inline void *coherent_kvaddr(struct page *page, unsigned long base, 82 unsigned long vaddr, unsigned long *paddr) 83 { 84 *paddr = page_to_phys(page); 85 return (void *)(base + (vaddr & DCACHE_ALIAS_MASK)); 86 } 87 88 void clear_user_highpage(struct page *page, unsigned long vaddr) 89 { 90 unsigned long paddr; 91 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr); 92 93 preempt_disable(); 94 kmap_invalidate_coherent(page, vaddr); 95 set_bit(PG_arch_1, &page->flags); 96 clear_page_alias(kvaddr, paddr); 97 preempt_enable(); 98 } 99 EXPORT_SYMBOL(clear_user_highpage); 100 101 void copy_user_highpage(struct page *dst, struct page *src, 102 unsigned long vaddr, struct vm_area_struct *vma) 103 { 104 unsigned long dst_paddr, src_paddr; 105 void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr, 106 &dst_paddr); 107 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr, 108 &src_paddr); 109 110 preempt_disable(); 111 kmap_invalidate_coherent(dst, vaddr); 112 set_bit(PG_arch_1, &dst->flags); 113 copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr); 114 preempt_enable(); 115 } 116 EXPORT_SYMBOL(copy_user_highpage); 117 118 /* 119 * Any time the kernel writes to a user page cache page, or it is about to 120 * read from a page cache page this routine is called. 121 * 122 */ 123 124 void flush_dcache_page(struct page *page) 125 { 126 struct address_space *mapping = page_mapping_file(page); 127 128 /* 129 * If we have a mapping but the page is not mapped to user-space 130 * yet, we simply mark this page dirty and defer flushing the 131 * caches until update_mmu(). 132 */ 133 134 if (mapping && !mapping_mapped(mapping)) { 135 if (!test_bit(PG_arch_1, &page->flags)) 136 set_bit(PG_arch_1, &page->flags); 137 return; 138 139 } else { 140 141 unsigned long phys = page_to_phys(page); 142 unsigned long temp = page->index << PAGE_SHIFT; 143 unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys)); 144 unsigned long virt; 145 146 /* 147 * Flush the page in kernel space and user space. 148 * Note that we can omit that step if aliasing is not 149 * an issue, but we do have to synchronize I$ and D$ 150 * if we have a mapping. 151 */ 152 153 if (!alias && !mapping) 154 return; 155 156 preempt_disable(); 157 virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); 158 __flush_invalidate_dcache_page_alias(virt, phys); 159 160 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK); 161 162 if (alias) 163 __flush_invalidate_dcache_page_alias(virt, phys); 164 165 if (mapping) 166 __invalidate_icache_page_alias(virt, phys); 167 preempt_enable(); 168 } 169 170 /* There shouldn't be an entry in the cache for this page anymore. */ 171 } 172 EXPORT_SYMBOL(flush_dcache_page); 173 174 /* 175 * For now, flush the whole cache. FIXME?? 176 */ 177 178 void local_flush_cache_range(struct vm_area_struct *vma, 179 unsigned long start, unsigned long end) 180 { 181 __flush_invalidate_dcache_all(); 182 __invalidate_icache_all(); 183 } 184 EXPORT_SYMBOL(local_flush_cache_range); 185 186 /* 187 * Remove any entry in the cache for this page. 188 * 189 * Note that this function is only called for user pages, so use the 190 * alias versions of the cache flush functions. 191 */ 192 193 void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address, 194 unsigned long pfn) 195 { 196 /* Note that we have to use the 'alias' address to avoid multi-hit */ 197 198 unsigned long phys = page_to_phys(pfn_to_page(pfn)); 199 unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK); 200 201 preempt_disable(); 202 __flush_invalidate_dcache_page_alias(virt, phys); 203 __invalidate_icache_page_alias(virt, phys); 204 preempt_enable(); 205 } 206 EXPORT_SYMBOL(local_flush_cache_page); 207 208 #endif /* DCACHE_WAY_SIZE > PAGE_SIZE */ 209 210 void 211 update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep) 212 { 213 unsigned long pfn = pte_pfn(*ptep); 214 struct page *page; 215 216 if (!pfn_valid(pfn)) 217 return; 218 219 page = pfn_to_page(pfn); 220 221 /* Invalidate old entry in TLBs */ 222 223 flush_tlb_page(vma, addr); 224 225 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 226 227 if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) { 228 unsigned long phys = page_to_phys(page); 229 unsigned long tmp; 230 231 preempt_disable(); 232 tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK); 233 __flush_invalidate_dcache_page_alias(tmp, phys); 234 tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK); 235 __flush_invalidate_dcache_page_alias(tmp, phys); 236 __invalidate_icache_page_alias(tmp, phys); 237 preempt_enable(); 238 239 clear_bit(PG_arch_1, &page->flags); 240 } 241 #else 242 if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) 243 && (vma->vm_flags & VM_EXEC) != 0) { 244 unsigned long paddr = (unsigned long)kmap_atomic(page); 245 __flush_dcache_page(paddr); 246 __invalidate_icache_page(paddr); 247 set_bit(PG_arch_1, &page->flags); 248 kunmap_atomic((void *)paddr); 249 } 250 #endif 251 } 252 253 /* 254 * access_process_vm() has called get_user_pages(), which has done a 255 * flush_dcache_page() on the page. 256 */ 257 258 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 259 260 void copy_to_user_page(struct vm_area_struct *vma, struct page *page, 261 unsigned long vaddr, void *dst, const void *src, 262 unsigned long len) 263 { 264 unsigned long phys = page_to_phys(page); 265 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys)); 266 267 /* Flush and invalidate user page if aliased. */ 268 269 if (alias) { 270 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); 271 preempt_disable(); 272 __flush_invalidate_dcache_page_alias(t, phys); 273 preempt_enable(); 274 } 275 276 /* Copy data */ 277 278 memcpy(dst, src, len); 279 280 /* 281 * Flush and invalidate kernel page if aliased and synchronize 282 * data and instruction caches for executable pages. 283 */ 284 285 if (alias) { 286 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); 287 288 preempt_disable(); 289 __flush_invalidate_dcache_range((unsigned long) dst, len); 290 if ((vma->vm_flags & VM_EXEC) != 0) 291 __invalidate_icache_page_alias(t, phys); 292 preempt_enable(); 293 294 } else if ((vma->vm_flags & VM_EXEC) != 0) { 295 __flush_dcache_range((unsigned long)dst,len); 296 __invalidate_icache_range((unsigned long) dst, len); 297 } 298 } 299 300 extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page, 301 unsigned long vaddr, void *dst, const void *src, 302 unsigned long len) 303 { 304 unsigned long phys = page_to_phys(page); 305 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys)); 306 307 /* 308 * Flush user page if aliased. 309 * (Note: a simply flush would be sufficient) 310 */ 311 312 if (alias) { 313 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK); 314 preempt_disable(); 315 __flush_invalidate_dcache_page_alias(t, phys); 316 preempt_enable(); 317 } 318 319 memcpy(dst, src, len); 320 } 321 322 #endif 323