1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/bitmap.h> 17 #include <linux/sort.h> 18 #include <asm/e820.h> 19 #include <asm/pci_x86.h> 20 21 /* aperture is up to 256MB but BIOS may reserve less */ 22 #define MMCONFIG_APER_MIN (2 * 1024*1024) 23 #define MMCONFIG_APER_MAX (256 * 1024*1024) 24 25 /* Indicate if the mmcfg resources have been placed into the resource table. */ 26 static int __initdata pci_mmcfg_resources_inserted; 27 28 static __init int extend_mmcfg(int num) 29 { 30 struct acpi_mcfg_allocation *new; 31 int new_num = pci_mmcfg_config_num + num; 32 33 new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL); 34 if (!new) 35 return -1; 36 37 if (pci_mmcfg_config) { 38 memcpy(new, pci_mmcfg_config, 39 sizeof(pci_mmcfg_config[0]) * new_num); 40 kfree(pci_mmcfg_config); 41 } 42 pci_mmcfg_config = new; 43 44 return 0; 45 } 46 47 static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end) 48 { 49 int i = pci_mmcfg_config_num; 50 51 pci_mmcfg_config_num++; 52 pci_mmcfg_config[i].address = addr; 53 pci_mmcfg_config[i].pci_segment = segment; 54 pci_mmcfg_config[i].start_bus_number = start; 55 pci_mmcfg_config[i].end_bus_number = end; 56 } 57 58 static const char __init *pci_mmcfg_e7520(void) 59 { 60 u32 win; 61 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 62 63 win = win & 0xf000; 64 if (win == 0x0000 || win == 0xf000) 65 return NULL; 66 67 if (extend_mmcfg(1) == -1) 68 return NULL; 69 70 fill_one_mmcfg(win << 16, 0, 0, 255); 71 72 return "Intel Corporation E7520 Memory Controller Hub"; 73 } 74 75 static const char __init *pci_mmcfg_intel_945(void) 76 { 77 u32 pciexbar, mask = 0, len = 0; 78 79 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 80 81 /* Enable bit */ 82 if (!(pciexbar & 1)) 83 return NULL; 84 85 /* Size bits */ 86 switch ((pciexbar >> 1) & 3) { 87 case 0: 88 mask = 0xf0000000U; 89 len = 0x10000000U; 90 break; 91 case 1: 92 mask = 0xf8000000U; 93 len = 0x08000000U; 94 break; 95 case 2: 96 mask = 0xfc000000U; 97 len = 0x04000000U; 98 break; 99 default: 100 return NULL; 101 } 102 103 /* Errata #2, things break when not aligned on a 256Mb boundary */ 104 /* Can only happen in 64M/128M mode */ 105 106 if ((pciexbar & mask) & 0x0fffffffU) 107 return NULL; 108 109 /* Don't hit the APIC registers and their friends */ 110 if ((pciexbar & mask) >= 0xf0000000U) 111 return NULL; 112 113 if (extend_mmcfg(1) == -1) 114 return NULL; 115 116 fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1); 117 118 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 119 } 120 121 static const char __init *pci_mmcfg_amd_fam10h(void) 122 { 123 u32 low, high, address; 124 u64 base, msr; 125 int i; 126 unsigned segnbits = 0, busnbits; 127 128 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 129 return NULL; 130 131 address = MSR_FAM10H_MMIO_CONF_BASE; 132 if (rdmsr_safe(address, &low, &high)) 133 return NULL; 134 135 msr = high; 136 msr <<= 32; 137 msr |= low; 138 139 /* mmconfig is not enable */ 140 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 141 return NULL; 142 143 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 144 145 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 146 FAM10H_MMIO_CONF_BUSRANGE_MASK; 147 148 /* 149 * only handle bus 0 ? 150 * need to skip it 151 */ 152 if (!busnbits) 153 return NULL; 154 155 if (busnbits > 8) { 156 segnbits = busnbits - 8; 157 busnbits = 8; 158 } 159 160 if (extend_mmcfg(1 << segnbits) == -1) 161 return NULL; 162 163 for (i = 0; i < (1 << segnbits); i++) 164 fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1); 165 166 return "AMD Family 10h NB"; 167 } 168 169 static bool __initdata mcp55_checked; 170 static const char __init *pci_mmcfg_nvidia_mcp55(void) 171 { 172 int bus; 173 int mcp55_mmconf_found = 0; 174 175 static const u32 extcfg_regnum = 0x90; 176 static const u32 extcfg_regsize = 4; 177 static const u32 extcfg_enable_mask = 1<<31; 178 static const u32 extcfg_start_mask = 0xff<<16; 179 static const int extcfg_start_shift = 16; 180 static const u32 extcfg_size_mask = 0x3<<28; 181 static const int extcfg_size_shift = 28; 182 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; 183 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; 184 static const int extcfg_base_lshift = 25; 185 186 /* 187 * do check if amd fam10h already took over 188 */ 189 if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked) 190 return NULL; 191 192 mcp55_checked = true; 193 for (bus = 0; bus < 256; bus++) { 194 u64 base; 195 u32 l, extcfg; 196 u16 vendor, device; 197 int start, size_index, end; 198 199 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); 200 vendor = l & 0xffff; 201 device = (l >> 16) & 0xffff; 202 203 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) 204 continue; 205 206 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, 207 extcfg_regsize, &extcfg); 208 209 if (!(extcfg & extcfg_enable_mask)) 210 continue; 211 212 if (extend_mmcfg(1) == -1) 213 continue; 214 215 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; 216 base = extcfg & extcfg_base_mask[size_index]; 217 /* base could > 4G */ 218 base <<= extcfg_base_lshift; 219 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; 220 end = start + extcfg_sizebus[size_index] - 1; 221 fill_one_mmcfg(base, 0, start, end); 222 mcp55_mmconf_found++; 223 } 224 225 if (!mcp55_mmconf_found) 226 return NULL; 227 228 return "nVidia MCP55"; 229 } 230 231 struct pci_mmcfg_hostbridge_probe { 232 u32 bus; 233 u32 devfn; 234 u32 vendor; 235 u32 device; 236 const char *(*probe)(void); 237 }; 238 239 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 240 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 241 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 242 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 243 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 244 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 245 0x1200, pci_mmcfg_amd_fam10h }, 246 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 247 0x1200, pci_mmcfg_amd_fam10h }, 248 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, 249 0x0369, pci_mmcfg_nvidia_mcp55 }, 250 }; 251 252 static int __init cmp_mmcfg(const void *x1, const void *x2) 253 { 254 const typeof(pci_mmcfg_config[0]) *m1 = x1; 255 const typeof(pci_mmcfg_config[0]) *m2 = x2; 256 int start1, start2; 257 258 start1 = m1->start_bus_number; 259 start2 = m2->start_bus_number; 260 261 return start1 - start2; 262 } 263 264 static void __init pci_mmcfg_check_end_bus_number(void) 265 { 266 int i; 267 typeof(pci_mmcfg_config[0]) *cfg, *cfgx; 268 269 /* sort them at first */ 270 sort(pci_mmcfg_config, pci_mmcfg_config_num, 271 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL); 272 273 /* last one*/ 274 if (pci_mmcfg_config_num > 0) { 275 i = pci_mmcfg_config_num - 1; 276 cfg = &pci_mmcfg_config[i]; 277 if (cfg->end_bus_number < cfg->start_bus_number) 278 cfg->end_bus_number = 255; 279 } 280 281 /* don't overlap please */ 282 for (i = 0; i < pci_mmcfg_config_num - 1; i++) { 283 cfg = &pci_mmcfg_config[i]; 284 cfgx = &pci_mmcfg_config[i+1]; 285 286 if (cfg->end_bus_number < cfg->start_bus_number) 287 cfg->end_bus_number = 255; 288 289 if (cfg->end_bus_number >= cfgx->start_bus_number) 290 cfg->end_bus_number = cfgx->start_bus_number - 1; 291 } 292 } 293 294 static int __init pci_mmcfg_check_hostbridge(void) 295 { 296 u32 l; 297 u32 bus, devfn; 298 u16 vendor, device; 299 int i; 300 const char *name; 301 302 if (!raw_pci_ops) 303 return 0; 304 305 pci_mmcfg_config_num = 0; 306 pci_mmcfg_config = NULL; 307 308 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 309 bus = pci_mmcfg_probes[i].bus; 310 devfn = pci_mmcfg_probes[i].devfn; 311 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 312 vendor = l & 0xffff; 313 device = (l >> 16) & 0xffff; 314 315 name = NULL; 316 if (pci_mmcfg_probes[i].vendor == vendor && 317 pci_mmcfg_probes[i].device == device) 318 name = pci_mmcfg_probes[i].probe(); 319 320 if (name) 321 printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", 322 name); 323 } 324 325 /* some end_bus_number is crazy, fix it */ 326 pci_mmcfg_check_end_bus_number(); 327 328 return pci_mmcfg_config_num != 0; 329 } 330 331 static void __init pci_mmcfg_insert_resources(void) 332 { 333 #define PCI_MMCFG_RESOURCE_NAME_LEN 24 334 int i; 335 struct resource *res; 336 char *names; 337 unsigned num_buses; 338 339 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), 340 pci_mmcfg_config_num, GFP_KERNEL); 341 if (!res) { 342 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); 343 return; 344 } 345 346 names = (void *)&res[pci_mmcfg_config_num]; 347 for (i = 0; i < pci_mmcfg_config_num; i++, res++) { 348 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; 349 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; 350 res->name = names; 351 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, 352 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment, 353 cfg->start_bus_number, cfg->end_bus_number); 354 res->start = cfg->address + (cfg->start_bus_number << 20); 355 res->end = res->start + (num_buses << 20) - 1; 356 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 357 insert_resource(&iomem_resource, res); 358 names += PCI_MMCFG_RESOURCE_NAME_LEN; 359 } 360 361 /* Mark that the resources have been inserted. */ 362 pci_mmcfg_resources_inserted = 1; 363 } 364 365 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 366 void *data) 367 { 368 struct resource *mcfg_res = data; 369 struct acpi_resource_address64 address; 370 acpi_status status; 371 372 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 373 struct acpi_resource_fixed_memory32 *fixmem32 = 374 &res->data.fixed_memory32; 375 if (!fixmem32) 376 return AE_OK; 377 if ((mcfg_res->start >= fixmem32->address) && 378 (mcfg_res->end < (fixmem32->address + 379 fixmem32->address_length))) { 380 mcfg_res->flags = 1; 381 return AE_CTRL_TERMINATE; 382 } 383 } 384 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 385 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 386 return AE_OK; 387 388 status = acpi_resource_to_address64(res, &address); 389 if (ACPI_FAILURE(status) || 390 (address.address_length <= 0) || 391 (address.resource_type != ACPI_MEMORY_RANGE)) 392 return AE_OK; 393 394 if ((mcfg_res->start >= address.minimum) && 395 (mcfg_res->end < (address.minimum + address.address_length))) { 396 mcfg_res->flags = 1; 397 return AE_CTRL_TERMINATE; 398 } 399 return AE_OK; 400 } 401 402 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 403 void *context, void **rv) 404 { 405 struct resource *mcfg_res = context; 406 407 acpi_walk_resources(handle, METHOD_NAME__CRS, 408 check_mcfg_resource, context); 409 410 if (mcfg_res->flags) 411 return AE_CTRL_TERMINATE; 412 413 return AE_OK; 414 } 415 416 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) 417 { 418 struct resource mcfg_res; 419 420 mcfg_res.start = start; 421 mcfg_res.end = end - 1; 422 mcfg_res.flags = 0; 423 424 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 425 426 if (!mcfg_res.flags) 427 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 428 NULL); 429 430 return mcfg_res.flags; 431 } 432 433 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); 434 435 static int __init is_mmconf_reserved(check_reserved_t is_reserved, 436 u64 addr, u64 size, int i, 437 typeof(pci_mmcfg_config[0]) *cfg, int with_e820) 438 { 439 u64 old_size = size; 440 int valid = 0; 441 442 while (!is_reserved(addr, addr + size, E820_RESERVED)) { 443 size >>= 1; 444 if (size < (16UL<<20)) 445 break; 446 } 447 448 if (size >= (16UL<<20) || size == old_size) { 449 printk(KERN_NOTICE 450 "PCI: MCFG area at %Lx reserved in %s\n", 451 addr, with_e820?"E820":"ACPI motherboard resources"); 452 valid = 1; 453 454 if (old_size != size) { 455 /* update end_bus_number */ 456 cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1); 457 printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx " 458 "segment %hu buses %u - %u\n", 459 i, (unsigned long)cfg->address, cfg->pci_segment, 460 (unsigned int)cfg->start_bus_number, 461 (unsigned int)cfg->end_bus_number); 462 } 463 } 464 465 return valid; 466 } 467 468 static void __init pci_mmcfg_reject_broken(int early) 469 { 470 typeof(pci_mmcfg_config[0]) *cfg; 471 int i; 472 473 if ((pci_mmcfg_config_num == 0) || 474 (pci_mmcfg_config == NULL) || 475 (pci_mmcfg_config[0].address == 0)) 476 return; 477 478 for (i = 0; i < pci_mmcfg_config_num; i++) { 479 int valid = 0; 480 u64 addr, size; 481 482 cfg = &pci_mmcfg_config[i]; 483 addr = cfg->start_bus_number; 484 addr <<= 20; 485 addr += cfg->address; 486 size = cfg->end_bus_number + 1 - cfg->start_bus_number; 487 size <<= 20; 488 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " 489 "segment %hu buses %u - %u\n", 490 i, (unsigned long)cfg->address, cfg->pci_segment, 491 (unsigned int)cfg->start_bus_number, 492 (unsigned int)cfg->end_bus_number); 493 494 if (!early) 495 valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); 496 497 if (valid) 498 continue; 499 500 if (!early) 501 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" 502 " reserved in ACPI motherboard resources\n", 503 cfg->address); 504 505 /* Don't try to do this check unless configuration 506 type 1 is available. how about type 2 ?*/ 507 if (raw_pci_ops) 508 valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1); 509 510 if (!valid) 511 goto reject; 512 } 513 514 return; 515 516 reject: 517 printk(KERN_INFO "PCI: Not using MMCONFIG.\n"); 518 pci_mmcfg_arch_free(); 519 kfree(pci_mmcfg_config); 520 pci_mmcfg_config = NULL; 521 pci_mmcfg_config_num = 0; 522 } 523 524 static int __initdata known_bridge; 525 526 static int acpi_mcfg_64bit_base_addr __initdata = FALSE; 527 528 /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ 529 struct acpi_mcfg_allocation *pci_mmcfg_config; 530 int pci_mmcfg_config_num; 531 532 static int __init acpi_mcfg_oem_check(struct acpi_table_mcfg *mcfg) 533 { 534 if (!strcmp(mcfg->header.oem_id, "SGI")) 535 acpi_mcfg_64bit_base_addr = TRUE; 536 537 return 0; 538 } 539 540 static int __init pci_parse_mcfg(struct acpi_table_header *header) 541 { 542 struct acpi_table_mcfg *mcfg; 543 unsigned long i; 544 int config_size; 545 546 if (!header) 547 return -EINVAL; 548 549 mcfg = (struct acpi_table_mcfg *)header; 550 551 /* how many config structures do we have */ 552 pci_mmcfg_config_num = 0; 553 i = header->length - sizeof(struct acpi_table_mcfg); 554 while (i >= sizeof(struct acpi_mcfg_allocation)) { 555 ++pci_mmcfg_config_num; 556 i -= sizeof(struct acpi_mcfg_allocation); 557 }; 558 if (pci_mmcfg_config_num == 0) { 559 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); 560 return -ENODEV; 561 } 562 563 config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config); 564 pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL); 565 if (!pci_mmcfg_config) { 566 printk(KERN_WARNING PREFIX 567 "No memory for MCFG config tables\n"); 568 return -ENOMEM; 569 } 570 571 memcpy(pci_mmcfg_config, &mcfg[1], config_size); 572 573 acpi_mcfg_oem_check(mcfg); 574 575 for (i = 0; i < pci_mmcfg_config_num; ++i) { 576 if ((pci_mmcfg_config[i].address > 0xFFFFFFFF) && 577 !acpi_mcfg_64bit_base_addr) { 578 printk(KERN_ERR PREFIX 579 "MMCONFIG not in low 4GB of memory\n"); 580 kfree(pci_mmcfg_config); 581 pci_mmcfg_config_num = 0; 582 return -ENODEV; 583 } 584 } 585 586 return 0; 587 } 588 589 static void __init __pci_mmcfg_init(int early) 590 { 591 /* MMCONFIG disabled */ 592 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 593 return; 594 595 /* MMCONFIG already enabled */ 596 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 597 return; 598 599 /* for late to exit */ 600 if (known_bridge) 601 return; 602 603 if (early) { 604 if (pci_mmcfg_check_hostbridge()) 605 known_bridge = 1; 606 } 607 608 if (!known_bridge) 609 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 610 611 pci_mmcfg_reject_broken(early); 612 613 if ((pci_mmcfg_config_num == 0) || 614 (pci_mmcfg_config == NULL) || 615 (pci_mmcfg_config[0].address == 0)) 616 return; 617 618 if (pci_mmcfg_arch_init()) 619 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 620 else { 621 /* 622 * Signal not to attempt to insert mmcfg resources because 623 * the architecture mmcfg setup could not initialize. 624 */ 625 pci_mmcfg_resources_inserted = 1; 626 } 627 } 628 629 void __init pci_mmcfg_early_init(void) 630 { 631 __pci_mmcfg_init(1); 632 } 633 634 void __init pci_mmcfg_late_init(void) 635 { 636 __pci_mmcfg_init(0); 637 } 638 639 static int __init pci_mmcfg_late_insert_resources(void) 640 { 641 /* 642 * If resources are already inserted or we are not using MMCONFIG, 643 * don't insert the resources. 644 */ 645 if ((pci_mmcfg_resources_inserted == 1) || 646 (pci_probe & PCI_PROBE_MMCONF) == 0 || 647 (pci_mmcfg_config_num == 0) || 648 (pci_mmcfg_config == NULL) || 649 (pci_mmcfg_config[0].address == 0)) 650 return 1; 651 652 /* 653 * Attempt to insert the mmcfg resources but not with the busy flag 654 * marked so it won't cause request errors when __request_region is 655 * called. 656 */ 657 pci_mmcfg_insert_resources(); 658 659 return 0; 660 } 661 662 /* 663 * Perform MMCONFIG resource insertion after PCI initialization to allow for 664 * misprogrammed MCFG tables that state larger sizes but actually conflict 665 * with other system resources. 666 */ 667 late_initcall(pci_mmcfg_late_insert_resources); 668