1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/bitmap.h> 17 #include <asm/e820.h> 18 19 #include "pci.h" 20 21 /* aperture is up to 256MB but BIOS may reserve less */ 22 #define MMCONFIG_APER_MIN (2 * 1024*1024) 23 #define MMCONFIG_APER_MAX (256 * 1024*1024) 24 25 /* Indicate if the mmcfg resources have been placed into the resource table. */ 26 static int __initdata pci_mmcfg_resources_inserted; 27 28 static const char __init *pci_mmcfg_e7520(void) 29 { 30 u32 win; 31 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 32 33 win = win & 0xf000; 34 if(win == 0x0000 || win == 0xf000) 35 pci_mmcfg_config_num = 0; 36 else { 37 pci_mmcfg_config_num = 1; 38 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 39 if (!pci_mmcfg_config) 40 return NULL; 41 pci_mmcfg_config[0].address = win << 16; 42 pci_mmcfg_config[0].pci_segment = 0; 43 pci_mmcfg_config[0].start_bus_number = 0; 44 pci_mmcfg_config[0].end_bus_number = 255; 45 } 46 47 return "Intel Corporation E7520 Memory Controller Hub"; 48 } 49 50 static const char __init *pci_mmcfg_intel_945(void) 51 { 52 u32 pciexbar, mask = 0, len = 0; 53 54 pci_mmcfg_config_num = 1; 55 56 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 57 58 /* Enable bit */ 59 if (!(pciexbar & 1)) 60 pci_mmcfg_config_num = 0; 61 62 /* Size bits */ 63 switch ((pciexbar >> 1) & 3) { 64 case 0: 65 mask = 0xf0000000U; 66 len = 0x10000000U; 67 break; 68 case 1: 69 mask = 0xf8000000U; 70 len = 0x08000000U; 71 break; 72 case 2: 73 mask = 0xfc000000U; 74 len = 0x04000000U; 75 break; 76 default: 77 pci_mmcfg_config_num = 0; 78 } 79 80 /* Errata #2, things break when not aligned on a 256Mb boundary */ 81 /* Can only happen in 64M/128M mode */ 82 83 if ((pciexbar & mask) & 0x0fffffffU) 84 pci_mmcfg_config_num = 0; 85 86 /* Don't hit the APIC registers and their friends */ 87 if ((pciexbar & mask) >= 0xf0000000U) 88 pci_mmcfg_config_num = 0; 89 90 if (pci_mmcfg_config_num) { 91 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 92 if (!pci_mmcfg_config) 93 return NULL; 94 pci_mmcfg_config[0].address = pciexbar & mask; 95 pci_mmcfg_config[0].pci_segment = 0; 96 pci_mmcfg_config[0].start_bus_number = 0; 97 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1; 98 } 99 100 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 101 } 102 103 static const char __init *pci_mmcfg_amd_fam10h(void) 104 { 105 u32 low, high, address; 106 u64 base, msr; 107 int i; 108 unsigned segnbits = 0, busnbits; 109 110 address = MSR_FAM10H_MMIO_CONF_BASE; 111 if (rdmsr_safe(address, &low, &high)) 112 return NULL; 113 114 msr = high; 115 msr <<= 32; 116 msr |= low; 117 118 /* mmconfig is not enable */ 119 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 120 return NULL; 121 122 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 123 124 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 125 FAM10H_MMIO_CONF_BUSRANGE_MASK; 126 127 /* 128 * only handle bus 0 ? 129 * need to skip it 130 */ 131 if (!busnbits) 132 return NULL; 133 134 if (busnbits > 8) { 135 segnbits = busnbits - 8; 136 busnbits = 8; 137 } 138 139 pci_mmcfg_config_num = (1 << segnbits); 140 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) * 141 pci_mmcfg_config_num, GFP_KERNEL); 142 if (!pci_mmcfg_config) 143 return NULL; 144 145 for (i = 0; i < (1 << segnbits); i++) { 146 pci_mmcfg_config[i].address = base + (1<<28) * i; 147 pci_mmcfg_config[i].pci_segment = i; 148 pci_mmcfg_config[i].start_bus_number = 0; 149 pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1; 150 } 151 152 return "AMD Family 10h NB"; 153 } 154 155 struct pci_mmcfg_hostbridge_probe { 156 u32 bus; 157 u32 devfn; 158 u32 vendor; 159 u32 device; 160 const char *(*probe)(void); 161 }; 162 163 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 164 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 165 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 166 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 167 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 168 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 169 0x1200, pci_mmcfg_amd_fam10h }, 170 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 171 0x1200, pci_mmcfg_amd_fam10h }, 172 }; 173 174 static int __init pci_mmcfg_check_hostbridge(void) 175 { 176 u32 l; 177 u32 bus, devfn; 178 u16 vendor, device; 179 int i; 180 const char *name; 181 182 if (!raw_pci_ops) 183 return 0; 184 185 pci_mmcfg_config_num = 0; 186 pci_mmcfg_config = NULL; 187 name = NULL; 188 189 for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 190 bus = pci_mmcfg_probes[i].bus; 191 devfn = pci_mmcfg_probes[i].devfn; 192 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 193 vendor = l & 0xffff; 194 device = (l >> 16) & 0xffff; 195 196 if (pci_mmcfg_probes[i].vendor == vendor && 197 pci_mmcfg_probes[i].device == device) 198 name = pci_mmcfg_probes[i].probe(); 199 } 200 201 if (name) { 202 printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n", 203 name, pci_mmcfg_config_num ? "with" : "without"); 204 } 205 206 return name != NULL; 207 } 208 209 static void __init pci_mmcfg_insert_resources(unsigned long resource_flags) 210 { 211 #define PCI_MMCFG_RESOURCE_NAME_LEN 19 212 int i; 213 struct resource *res; 214 char *names; 215 unsigned num_buses; 216 217 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), 218 pci_mmcfg_config_num, GFP_KERNEL); 219 if (!res) { 220 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); 221 return; 222 } 223 224 names = (void *)&res[pci_mmcfg_config_num]; 225 for (i = 0; i < pci_mmcfg_config_num; i++, res++) { 226 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; 227 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; 228 res->name = names; 229 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u", 230 cfg->pci_segment); 231 res->start = cfg->address; 232 res->end = res->start + (num_buses << 20) - 1; 233 res->flags = IORESOURCE_MEM | resource_flags; 234 insert_resource(&iomem_resource, res); 235 names += PCI_MMCFG_RESOURCE_NAME_LEN; 236 } 237 238 /* Mark that the resources have been inserted. */ 239 pci_mmcfg_resources_inserted = 1; 240 } 241 242 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 243 void *data) 244 { 245 struct resource *mcfg_res = data; 246 struct acpi_resource_address64 address; 247 acpi_status status; 248 249 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 250 struct acpi_resource_fixed_memory32 *fixmem32 = 251 &res->data.fixed_memory32; 252 if (!fixmem32) 253 return AE_OK; 254 if ((mcfg_res->start >= fixmem32->address) && 255 (mcfg_res->end < (fixmem32->address + 256 fixmem32->address_length))) { 257 mcfg_res->flags = 1; 258 return AE_CTRL_TERMINATE; 259 } 260 } 261 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 262 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 263 return AE_OK; 264 265 status = acpi_resource_to_address64(res, &address); 266 if (ACPI_FAILURE(status) || 267 (address.address_length <= 0) || 268 (address.resource_type != ACPI_MEMORY_RANGE)) 269 return AE_OK; 270 271 if ((mcfg_res->start >= address.minimum) && 272 (mcfg_res->end < (address.minimum + address.address_length))) { 273 mcfg_res->flags = 1; 274 return AE_CTRL_TERMINATE; 275 } 276 return AE_OK; 277 } 278 279 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 280 void *context, void **rv) 281 { 282 struct resource *mcfg_res = context; 283 284 acpi_walk_resources(handle, METHOD_NAME__CRS, 285 check_mcfg_resource, context); 286 287 if (mcfg_res->flags) 288 return AE_CTRL_TERMINATE; 289 290 return AE_OK; 291 } 292 293 static int __init is_acpi_reserved(unsigned long start, unsigned long end) 294 { 295 struct resource mcfg_res; 296 297 mcfg_res.start = start; 298 mcfg_res.end = end; 299 mcfg_res.flags = 0; 300 301 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 302 303 if (!mcfg_res.flags) 304 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 305 NULL); 306 307 return mcfg_res.flags; 308 } 309 310 static void __init pci_mmcfg_reject_broken(int early) 311 { 312 typeof(pci_mmcfg_config[0]) *cfg; 313 int i; 314 315 if ((pci_mmcfg_config_num == 0) || 316 (pci_mmcfg_config == NULL) || 317 (pci_mmcfg_config[0].address == 0)) 318 return; 319 320 cfg = &pci_mmcfg_config[0]; 321 322 for (i = 0; i < pci_mmcfg_config_num; i++) { 323 int valid = 0; 324 u32 size = (cfg->end_bus_number + 1) << 20; 325 cfg = &pci_mmcfg_config[i]; 326 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " 327 "segment %hu buses %u - %u\n", 328 i, (unsigned long)cfg->address, cfg->pci_segment, 329 (unsigned int)cfg->start_bus_number, 330 (unsigned int)cfg->end_bus_number); 331 332 if (!early && 333 is_acpi_reserved(cfg->address, cfg->address + size - 1)) { 334 printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved " 335 "in ACPI motherboard resources\n", 336 cfg->address); 337 valid = 1; 338 } 339 340 if (valid) 341 continue; 342 343 if (!early) 344 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" 345 " reserved in ACPI motherboard resources\n", 346 cfg->address); 347 /* Don't try to do this check unless configuration 348 type 1 is available. how about type 2 ?*/ 349 if (raw_pci_ops && e820_all_mapped(cfg->address, 350 cfg->address + size - 1, 351 E820_RESERVED)) { 352 printk(KERN_NOTICE 353 "PCI: MCFG area at %Lx reserved in E820\n", 354 cfg->address); 355 valid = 1; 356 } 357 358 if (!valid) 359 goto reject; 360 } 361 362 return; 363 364 reject: 365 printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); 366 pci_mmcfg_arch_free(); 367 kfree(pci_mmcfg_config); 368 pci_mmcfg_config = NULL; 369 pci_mmcfg_config_num = 0; 370 } 371 372 static int __initdata known_bridge; 373 374 void __init __pci_mmcfg_init(int early) 375 { 376 /* MMCONFIG disabled */ 377 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 378 return; 379 380 /* MMCONFIG already enabled */ 381 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 382 return; 383 384 /* for late to exit */ 385 if (known_bridge) 386 return; 387 388 if (early) { 389 if (pci_mmcfg_check_hostbridge()) 390 known_bridge = 1; 391 } 392 393 if (!known_bridge) { 394 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); 395 pci_mmcfg_reject_broken(early); 396 } 397 398 if ((pci_mmcfg_config_num == 0) || 399 (pci_mmcfg_config == NULL) || 400 (pci_mmcfg_config[0].address == 0)) 401 return; 402 403 if (pci_mmcfg_arch_init()) { 404 if (known_bridge) 405 pci_mmcfg_insert_resources(IORESOURCE_BUSY); 406 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 407 } else { 408 /* 409 * Signal not to attempt to insert mmcfg resources because 410 * the architecture mmcfg setup could not initialize. 411 */ 412 pci_mmcfg_resources_inserted = 1; 413 } 414 } 415 416 void __init pci_mmcfg_early_init(void) 417 { 418 __pci_mmcfg_init(1); 419 } 420 421 void __init pci_mmcfg_late_init(void) 422 { 423 __pci_mmcfg_init(0); 424 } 425 426 static int __init pci_mmcfg_late_insert_resources(void) 427 { 428 /* 429 * If resources are already inserted or we are not using MMCONFIG, 430 * don't insert the resources. 431 */ 432 if ((pci_mmcfg_resources_inserted == 1) || 433 (pci_probe & PCI_PROBE_MMCONF) == 0 || 434 (pci_mmcfg_config_num == 0) || 435 (pci_mmcfg_config == NULL) || 436 (pci_mmcfg_config[0].address == 0)) 437 return 1; 438 439 /* 440 * Attempt to insert the mmcfg resources but not with the busy flag 441 * marked so it won't cause request errors when __request_region is 442 * called. 443 */ 444 pci_mmcfg_insert_resources(0); 445 446 return 0; 447 } 448 449 /* 450 * Perform MMCONFIG resource insertion after PCI initialization to allow for 451 * misprogrammed MCFG tables that state larger sizes but actually conflict 452 * with other system resources. 453 */ 454 late_initcall(pci_mmcfg_late_insert_resources); 455