1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/sfi_acpi.h> 17 #include <linux/bitmap.h> 18 #include <linux/dmi.h> 19 #include <asm/e820.h> 20 #include <asm/pci_x86.h> 21 #include <asm/acpi.h> 22 23 #define PREFIX "PCI: " 24 25 /* Indicate if the mmcfg resources have been placed into the resource table. */ 26 static int __initdata pci_mmcfg_resources_inserted; 27 28 LIST_HEAD(pci_mmcfg_list); 29 30 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg) 31 { 32 if (cfg->res.parent) 33 release_resource(&cfg->res); 34 list_del(&cfg->list); 35 kfree(cfg); 36 } 37 38 static __init void free_all_mmcfg(void) 39 { 40 struct pci_mmcfg_region *cfg, *tmp; 41 42 pci_mmcfg_arch_free(); 43 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) 44 pci_mmconfig_remove(cfg); 45 } 46 47 static __init void list_add_sorted(struct pci_mmcfg_region *new) 48 { 49 struct pci_mmcfg_region *cfg; 50 51 /* keep list sorted by segment and starting bus number */ 52 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 53 if (cfg->segment > new->segment || 54 (cfg->segment == new->segment && 55 cfg->start_bus >= new->start_bus)) { 56 list_add_tail(&new->list, &cfg->list); 57 return; 58 } 59 } 60 list_add_tail(&new->list, &pci_mmcfg_list); 61 } 62 63 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, 64 int end, u64 addr) 65 { 66 struct pci_mmcfg_region *new; 67 int num_buses; 68 struct resource *res; 69 70 if (addr == 0) 71 return NULL; 72 73 new = kzalloc(sizeof(*new), GFP_KERNEL); 74 if (!new) 75 return NULL; 76 77 new->address = addr; 78 new->segment = segment; 79 new->start_bus = start; 80 new->end_bus = end; 81 82 list_add_sorted(new); 83 84 num_buses = end - start + 1; 85 res = &new->res; 86 res->start = addr + PCI_MMCFG_BUS_OFFSET(start); 87 res->end = addr + PCI_MMCFG_BUS_OFFSET(num_buses) - 1; 88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, 90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); 91 res->name = new->name; 92 93 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at " 94 "%pR (base %#lx)\n", segment, start, end, &new->res, 95 (unsigned long) addr); 96 97 return new; 98 } 99 100 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) 101 { 102 struct pci_mmcfg_region *cfg; 103 104 list_for_each_entry(cfg, &pci_mmcfg_list, list) 105 if (cfg->segment == segment && 106 cfg->start_bus <= bus && bus <= cfg->end_bus) 107 return cfg; 108 109 return NULL; 110 } 111 112 static const char __init *pci_mmcfg_e7520(void) 113 { 114 u32 win; 115 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 116 117 win = win & 0xf000; 118 if (win == 0x0000 || win == 0xf000) 119 return NULL; 120 121 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL) 122 return NULL; 123 124 return "Intel Corporation E7520 Memory Controller Hub"; 125 } 126 127 static const char __init *pci_mmcfg_intel_945(void) 128 { 129 u32 pciexbar, mask = 0, len = 0; 130 131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 132 133 /* Enable bit */ 134 if (!(pciexbar & 1)) 135 return NULL; 136 137 /* Size bits */ 138 switch ((pciexbar >> 1) & 3) { 139 case 0: 140 mask = 0xf0000000U; 141 len = 0x10000000U; 142 break; 143 case 1: 144 mask = 0xf8000000U; 145 len = 0x08000000U; 146 break; 147 case 2: 148 mask = 0xfc000000U; 149 len = 0x04000000U; 150 break; 151 default: 152 return NULL; 153 } 154 155 /* Errata #2, things break when not aligned on a 256Mb boundary */ 156 /* Can only happen in 64M/128M mode */ 157 158 if ((pciexbar & mask) & 0x0fffffffU) 159 return NULL; 160 161 /* Don't hit the APIC registers and their friends */ 162 if ((pciexbar & mask) >= 0xf0000000U) 163 return NULL; 164 165 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) 166 return NULL; 167 168 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 169 } 170 171 static const char __init *pci_mmcfg_amd_fam10h(void) 172 { 173 u32 low, high, address; 174 u64 base, msr; 175 int i; 176 unsigned segnbits = 0, busnbits, end_bus; 177 178 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 179 return NULL; 180 181 address = MSR_FAM10H_MMIO_CONF_BASE; 182 if (rdmsr_safe(address, &low, &high)) 183 return NULL; 184 185 msr = high; 186 msr <<= 32; 187 msr |= low; 188 189 /* mmconfig is not enable */ 190 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 191 return NULL; 192 193 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 194 195 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 196 FAM10H_MMIO_CONF_BUSRANGE_MASK; 197 198 /* 199 * only handle bus 0 ? 200 * need to skip it 201 */ 202 if (!busnbits) 203 return NULL; 204 205 if (busnbits > 8) { 206 segnbits = busnbits - 8; 207 busnbits = 8; 208 } 209 210 end_bus = (1 << busnbits) - 1; 211 for (i = 0; i < (1 << segnbits); i++) 212 if (pci_mmconfig_add(i, 0, end_bus, 213 base + (1<<28) * i) == NULL) { 214 free_all_mmcfg(); 215 return NULL; 216 } 217 218 return "AMD Family 10h NB"; 219 } 220 221 static bool __initdata mcp55_checked; 222 static const char __init *pci_mmcfg_nvidia_mcp55(void) 223 { 224 int bus; 225 int mcp55_mmconf_found = 0; 226 227 static const u32 extcfg_regnum = 0x90; 228 static const u32 extcfg_regsize = 4; 229 static const u32 extcfg_enable_mask = 1<<31; 230 static const u32 extcfg_start_mask = 0xff<<16; 231 static const int extcfg_start_shift = 16; 232 static const u32 extcfg_size_mask = 0x3<<28; 233 static const int extcfg_size_shift = 28; 234 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; 235 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; 236 static const int extcfg_base_lshift = 25; 237 238 /* 239 * do check if amd fam10h already took over 240 */ 241 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked) 242 return NULL; 243 244 mcp55_checked = true; 245 for (bus = 0; bus < 256; bus++) { 246 u64 base; 247 u32 l, extcfg; 248 u16 vendor, device; 249 int start, size_index, end; 250 251 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); 252 vendor = l & 0xffff; 253 device = (l >> 16) & 0xffff; 254 255 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) 256 continue; 257 258 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, 259 extcfg_regsize, &extcfg); 260 261 if (!(extcfg & extcfg_enable_mask)) 262 continue; 263 264 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; 265 base = extcfg & extcfg_base_mask[size_index]; 266 /* base could > 4G */ 267 base <<= extcfg_base_lshift; 268 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; 269 end = start + extcfg_sizebus[size_index] - 1; 270 if (pci_mmconfig_add(0, start, end, base) == NULL) 271 continue; 272 mcp55_mmconf_found++; 273 } 274 275 if (!mcp55_mmconf_found) 276 return NULL; 277 278 return "nVidia MCP55"; 279 } 280 281 struct pci_mmcfg_hostbridge_probe { 282 u32 bus; 283 u32 devfn; 284 u32 vendor; 285 u32 device; 286 const char *(*probe)(void); 287 }; 288 289 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 290 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 291 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 292 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 293 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 294 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 295 0x1200, pci_mmcfg_amd_fam10h }, 296 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 297 0x1200, pci_mmcfg_amd_fam10h }, 298 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, 299 0x0369, pci_mmcfg_nvidia_mcp55 }, 300 }; 301 302 static void __init pci_mmcfg_check_end_bus_number(void) 303 { 304 struct pci_mmcfg_region *cfg, *cfgx; 305 306 /* last one*/ 307 cfg = list_entry(pci_mmcfg_list.prev, typeof(*cfg), list); 308 if (cfg) 309 if (cfg->end_bus < cfg->start_bus) 310 cfg->end_bus = 255; 311 312 if (list_is_singular(&pci_mmcfg_list)) 313 return; 314 315 /* don't overlap please */ 316 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 317 if (cfg->end_bus < cfg->start_bus) 318 cfg->end_bus = 255; 319 320 cfgx = list_entry(cfg->list.next, typeof(*cfg), list); 321 if (cfg != cfgx && cfg->end_bus >= cfgx->start_bus) 322 cfg->end_bus = cfgx->start_bus - 1; 323 } 324 } 325 326 static int __init pci_mmcfg_check_hostbridge(void) 327 { 328 u32 l; 329 u32 bus, devfn; 330 u16 vendor, device; 331 int i; 332 const char *name; 333 334 if (!raw_pci_ops) 335 return 0; 336 337 free_all_mmcfg(); 338 339 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 340 bus = pci_mmcfg_probes[i].bus; 341 devfn = pci_mmcfg_probes[i].devfn; 342 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 343 vendor = l & 0xffff; 344 device = (l >> 16) & 0xffff; 345 346 name = NULL; 347 if (pci_mmcfg_probes[i].vendor == vendor && 348 pci_mmcfg_probes[i].device == device) 349 name = pci_mmcfg_probes[i].probe(); 350 351 if (name) 352 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n", 353 name); 354 } 355 356 /* some end_bus_number is crazy, fix it */ 357 pci_mmcfg_check_end_bus_number(); 358 359 return !list_empty(&pci_mmcfg_list); 360 } 361 362 static void __init pci_mmcfg_insert_resources(void) 363 { 364 struct pci_mmcfg_region *cfg; 365 366 list_for_each_entry(cfg, &pci_mmcfg_list, list) 367 insert_resource(&iomem_resource, &cfg->res); 368 369 /* Mark that the resources have been inserted. */ 370 pci_mmcfg_resources_inserted = 1; 371 } 372 373 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 374 void *data) 375 { 376 struct resource *mcfg_res = data; 377 struct acpi_resource_address64 address; 378 acpi_status status; 379 380 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 381 struct acpi_resource_fixed_memory32 *fixmem32 = 382 &res->data.fixed_memory32; 383 if (!fixmem32) 384 return AE_OK; 385 if ((mcfg_res->start >= fixmem32->address) && 386 (mcfg_res->end < (fixmem32->address + 387 fixmem32->address_length))) { 388 mcfg_res->flags = 1; 389 return AE_CTRL_TERMINATE; 390 } 391 } 392 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 393 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 394 return AE_OK; 395 396 status = acpi_resource_to_address64(res, &address); 397 if (ACPI_FAILURE(status) || 398 (address.address_length <= 0) || 399 (address.resource_type != ACPI_MEMORY_RANGE)) 400 return AE_OK; 401 402 if ((mcfg_res->start >= address.minimum) && 403 (mcfg_res->end < (address.minimum + address.address_length))) { 404 mcfg_res->flags = 1; 405 return AE_CTRL_TERMINATE; 406 } 407 return AE_OK; 408 } 409 410 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 411 void *context, void **rv) 412 { 413 struct resource *mcfg_res = context; 414 415 acpi_walk_resources(handle, METHOD_NAME__CRS, 416 check_mcfg_resource, context); 417 418 if (mcfg_res->flags) 419 return AE_CTRL_TERMINATE; 420 421 return AE_OK; 422 } 423 424 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) 425 { 426 struct resource mcfg_res; 427 428 mcfg_res.start = start; 429 mcfg_res.end = end - 1; 430 mcfg_res.flags = 0; 431 432 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 433 434 if (!mcfg_res.flags) 435 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 436 NULL); 437 438 return mcfg_res.flags; 439 } 440 441 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); 442 443 static int __init is_mmconf_reserved(check_reserved_t is_reserved, 444 struct pci_mmcfg_region *cfg, int with_e820) 445 { 446 u64 addr = cfg->res.start; 447 u64 size = resource_size(&cfg->res); 448 u64 old_size = size; 449 int valid = 0, num_buses; 450 451 while (!is_reserved(addr, addr + size, E820_RESERVED)) { 452 size >>= 1; 453 if (size < (16UL<<20)) 454 break; 455 } 456 457 if (size >= (16UL<<20) || size == old_size) { 458 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n", 459 &cfg->res, 460 with_e820 ? "E820" : "ACPI motherboard resources"); 461 valid = 1; 462 463 if (old_size != size) { 464 /* update end_bus */ 465 cfg->end_bus = cfg->start_bus + ((size>>20) - 1); 466 num_buses = cfg->end_bus - cfg->start_bus + 1; 467 cfg->res.end = cfg->res.start + 468 PCI_MMCFG_BUS_OFFSET(num_buses) - 1; 469 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN, 470 "PCI MMCONFIG %04x [bus %02x-%02x]", 471 cfg->segment, cfg->start_bus, cfg->end_bus); 472 printk(KERN_INFO PREFIX 473 "MMCONFIG for %04x [bus%02x-%02x] " 474 "at %pR (base %#lx) (size reduced!)\n", 475 cfg->segment, cfg->start_bus, cfg->end_bus, 476 &cfg->res, (unsigned long) cfg->address); 477 } 478 } 479 480 return valid; 481 } 482 483 static void __init pci_mmcfg_reject_broken(int early) 484 { 485 struct pci_mmcfg_region *cfg; 486 487 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 488 int valid = 0; 489 490 if (!early && !acpi_disabled) 491 valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0); 492 493 if (valid) 494 continue; 495 496 if (!early) 497 printk(KERN_ERR FW_BUG PREFIX 498 "MMCONFIG at %pR not reserved in " 499 "ACPI motherboard resources\n", &cfg->res); 500 501 /* Don't try to do this check unless configuration 502 type 1 is available. how about type 2 ?*/ 503 if (raw_pci_ops) 504 valid = is_mmconf_reserved(e820_all_mapped, cfg, 1); 505 506 if (!valid) 507 goto reject; 508 } 509 510 return; 511 512 reject: 513 printk(KERN_INFO PREFIX "not using MMCONFIG\n"); 514 free_all_mmcfg(); 515 } 516 517 static int __initdata known_bridge; 518 519 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, 520 struct acpi_mcfg_allocation *cfg) 521 { 522 int year; 523 524 if (cfg->address < 0xFFFFFFFF) 525 return 0; 526 527 if (!strcmp(mcfg->header.oem_id, "SGI")) 528 return 0; 529 530 if (mcfg->header.revision >= 1) { 531 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && 532 year >= 2010) 533 return 0; 534 } 535 536 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx " 537 "is above 4GB, ignored\n", cfg->pci_segment, 538 cfg->start_bus_number, cfg->end_bus_number, cfg->address); 539 return -EINVAL; 540 } 541 542 static int __init pci_parse_mcfg(struct acpi_table_header *header) 543 { 544 struct acpi_table_mcfg *mcfg; 545 struct acpi_mcfg_allocation *cfg_table, *cfg; 546 unsigned long i; 547 int entries; 548 549 if (!header) 550 return -EINVAL; 551 552 mcfg = (struct acpi_table_mcfg *)header; 553 554 /* how many config structures do we have */ 555 free_all_mmcfg(); 556 entries = 0; 557 i = header->length - sizeof(struct acpi_table_mcfg); 558 while (i >= sizeof(struct acpi_mcfg_allocation)) { 559 entries++; 560 i -= sizeof(struct acpi_mcfg_allocation); 561 }; 562 if (entries == 0) { 563 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); 564 return -ENODEV; 565 } 566 567 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; 568 for (i = 0; i < entries; i++) { 569 cfg = &cfg_table[i]; 570 if (acpi_mcfg_check_entry(mcfg, cfg)) { 571 free_all_mmcfg(); 572 return -ENODEV; 573 } 574 575 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, 576 cfg->end_bus_number, cfg->address) == NULL) { 577 printk(KERN_WARNING PREFIX 578 "no memory for MCFG entries\n"); 579 free_all_mmcfg(); 580 return -ENOMEM; 581 } 582 } 583 584 return 0; 585 } 586 587 static void __init __pci_mmcfg_init(int early) 588 { 589 /* MMCONFIG disabled */ 590 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 591 return; 592 593 /* MMCONFIG already enabled */ 594 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 595 return; 596 597 /* for late to exit */ 598 if (known_bridge) 599 return; 600 601 if (early) { 602 if (pci_mmcfg_check_hostbridge()) 603 known_bridge = 1; 604 } 605 606 if (!known_bridge) 607 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 608 609 pci_mmcfg_reject_broken(early); 610 611 if (list_empty(&pci_mmcfg_list)) 612 return; 613 614 if (pci_mmcfg_arch_init()) 615 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 616 else { 617 /* 618 * Signal not to attempt to insert mmcfg resources because 619 * the architecture mmcfg setup could not initialize. 620 */ 621 pci_mmcfg_resources_inserted = 1; 622 } 623 } 624 625 void __init pci_mmcfg_early_init(void) 626 { 627 __pci_mmcfg_init(1); 628 } 629 630 void __init pci_mmcfg_late_init(void) 631 { 632 __pci_mmcfg_init(0); 633 } 634 635 static int __init pci_mmcfg_late_insert_resources(void) 636 { 637 /* 638 * If resources are already inserted or we are not using MMCONFIG, 639 * don't insert the resources. 640 */ 641 if ((pci_mmcfg_resources_inserted == 1) || 642 (pci_probe & PCI_PROBE_MMCONF) == 0 || 643 list_empty(&pci_mmcfg_list)) 644 return 1; 645 646 /* 647 * Attempt to insert the mmcfg resources but not with the busy flag 648 * marked so it won't cause request errors when __request_region is 649 * called. 650 */ 651 pci_mmcfg_insert_resources(); 652 653 return 0; 654 } 655 656 /* 657 * Perform MMCONFIG resource insertion after PCI initialization to allow for 658 * misprogrammed MCFG tables that state larger sizes but actually conflict 659 * with other system resources. 660 */ 661 late_initcall(pci_mmcfg_late_insert_resources); 662