1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/bitmap.h> 17 #include <asm/e820.h> 18 19 #include "pci.h" 20 21 /* aperture is up to 256MB but BIOS may reserve less */ 22 #define MMCONFIG_APER_MIN (2 * 1024*1024) 23 #define MMCONFIG_APER_MAX (256 * 1024*1024) 24 25 /* Indicate if the mmcfg resources have been placed into the resource table. */ 26 static int __initdata pci_mmcfg_resources_inserted; 27 28 static const char __init *pci_mmcfg_e7520(void) 29 { 30 u32 win; 31 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 32 33 win = win & 0xf000; 34 if(win == 0x0000 || win == 0xf000) 35 pci_mmcfg_config_num = 0; 36 else { 37 pci_mmcfg_config_num = 1; 38 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 39 if (!pci_mmcfg_config) 40 return NULL; 41 pci_mmcfg_config[0].address = win << 16; 42 pci_mmcfg_config[0].pci_segment = 0; 43 pci_mmcfg_config[0].start_bus_number = 0; 44 pci_mmcfg_config[0].end_bus_number = 255; 45 } 46 47 return "Intel Corporation E7520 Memory Controller Hub"; 48 } 49 50 static const char __init *pci_mmcfg_intel_945(void) 51 { 52 u32 pciexbar, mask = 0, len = 0; 53 54 pci_mmcfg_config_num = 1; 55 56 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 57 58 /* Enable bit */ 59 if (!(pciexbar & 1)) 60 pci_mmcfg_config_num = 0; 61 62 /* Size bits */ 63 switch ((pciexbar >> 1) & 3) { 64 case 0: 65 mask = 0xf0000000U; 66 len = 0x10000000U; 67 break; 68 case 1: 69 mask = 0xf8000000U; 70 len = 0x08000000U; 71 break; 72 case 2: 73 mask = 0xfc000000U; 74 len = 0x04000000U; 75 break; 76 default: 77 pci_mmcfg_config_num = 0; 78 } 79 80 /* Errata #2, things break when not aligned on a 256Mb boundary */ 81 /* Can only happen in 64M/128M mode */ 82 83 if ((pciexbar & mask) & 0x0fffffffU) 84 pci_mmcfg_config_num = 0; 85 86 /* Don't hit the APIC registers and their friends */ 87 if ((pciexbar & mask) >= 0xf0000000U) 88 pci_mmcfg_config_num = 0; 89 90 if (pci_mmcfg_config_num) { 91 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 92 if (!pci_mmcfg_config) 93 return NULL; 94 pci_mmcfg_config[0].address = pciexbar & mask; 95 pci_mmcfg_config[0].pci_segment = 0; 96 pci_mmcfg_config[0].start_bus_number = 0; 97 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1; 98 } 99 100 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 101 } 102 103 static const char __init *pci_mmcfg_amd_fam10h(void) 104 { 105 u32 low, high, address; 106 u64 base, msr; 107 int i; 108 unsigned segnbits = 0, busnbits; 109 110 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 111 return NULL; 112 113 address = MSR_FAM10H_MMIO_CONF_BASE; 114 if (rdmsr_safe(address, &low, &high)) 115 return NULL; 116 117 msr = high; 118 msr <<= 32; 119 msr |= low; 120 121 /* mmconfig is not enable */ 122 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 123 return NULL; 124 125 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 126 127 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 128 FAM10H_MMIO_CONF_BUSRANGE_MASK; 129 130 /* 131 * only handle bus 0 ? 132 * need to skip it 133 */ 134 if (!busnbits) 135 return NULL; 136 137 if (busnbits > 8) { 138 segnbits = busnbits - 8; 139 busnbits = 8; 140 } 141 142 pci_mmcfg_config_num = (1 << segnbits); 143 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) * 144 pci_mmcfg_config_num, GFP_KERNEL); 145 if (!pci_mmcfg_config) 146 return NULL; 147 148 for (i = 0; i < (1 << segnbits); i++) { 149 pci_mmcfg_config[i].address = base + (1<<28) * i; 150 pci_mmcfg_config[i].pci_segment = i; 151 pci_mmcfg_config[i].start_bus_number = 0; 152 pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1; 153 } 154 155 return "AMD Family 10h NB"; 156 } 157 158 struct pci_mmcfg_hostbridge_probe { 159 u32 bus; 160 u32 devfn; 161 u32 vendor; 162 u32 device; 163 const char *(*probe)(void); 164 }; 165 166 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 167 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 168 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 169 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 170 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 171 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 172 0x1200, pci_mmcfg_amd_fam10h }, 173 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 174 0x1200, pci_mmcfg_amd_fam10h }, 175 }; 176 177 static int __init pci_mmcfg_check_hostbridge(void) 178 { 179 u32 l; 180 u32 bus, devfn; 181 u16 vendor, device; 182 int i; 183 const char *name; 184 185 if (!raw_pci_ops) 186 return 0; 187 188 pci_mmcfg_config_num = 0; 189 pci_mmcfg_config = NULL; 190 name = NULL; 191 192 for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 193 bus = pci_mmcfg_probes[i].bus; 194 devfn = pci_mmcfg_probes[i].devfn; 195 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 196 vendor = l & 0xffff; 197 device = (l >> 16) & 0xffff; 198 199 if (pci_mmcfg_probes[i].vendor == vendor && 200 pci_mmcfg_probes[i].device == device) 201 name = pci_mmcfg_probes[i].probe(); 202 } 203 204 if (name) { 205 printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n", 206 name, pci_mmcfg_config_num ? "with" : "without"); 207 } 208 209 return name != NULL; 210 } 211 212 static void __init pci_mmcfg_insert_resources(unsigned long resource_flags) 213 { 214 #define PCI_MMCFG_RESOURCE_NAME_LEN 19 215 int i; 216 struct resource *res; 217 char *names; 218 unsigned num_buses; 219 220 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), 221 pci_mmcfg_config_num, GFP_KERNEL); 222 if (!res) { 223 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); 224 return; 225 } 226 227 names = (void *)&res[pci_mmcfg_config_num]; 228 for (i = 0; i < pci_mmcfg_config_num; i++, res++) { 229 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; 230 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; 231 res->name = names; 232 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u", 233 cfg->pci_segment); 234 res->start = cfg->address; 235 res->end = res->start + (num_buses << 20) - 1; 236 res->flags = IORESOURCE_MEM | resource_flags; 237 insert_resource(&iomem_resource, res); 238 names += PCI_MMCFG_RESOURCE_NAME_LEN; 239 } 240 241 /* Mark that the resources have been inserted. */ 242 pci_mmcfg_resources_inserted = 1; 243 } 244 245 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 246 void *data) 247 { 248 struct resource *mcfg_res = data; 249 struct acpi_resource_address64 address; 250 acpi_status status; 251 252 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 253 struct acpi_resource_fixed_memory32 *fixmem32 = 254 &res->data.fixed_memory32; 255 if (!fixmem32) 256 return AE_OK; 257 if ((mcfg_res->start >= fixmem32->address) && 258 (mcfg_res->end < (fixmem32->address + 259 fixmem32->address_length))) { 260 mcfg_res->flags = 1; 261 return AE_CTRL_TERMINATE; 262 } 263 } 264 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 265 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 266 return AE_OK; 267 268 status = acpi_resource_to_address64(res, &address); 269 if (ACPI_FAILURE(status) || 270 (address.address_length <= 0) || 271 (address.resource_type != ACPI_MEMORY_RANGE)) 272 return AE_OK; 273 274 if ((mcfg_res->start >= address.minimum) && 275 (mcfg_res->end < (address.minimum + address.address_length))) { 276 mcfg_res->flags = 1; 277 return AE_CTRL_TERMINATE; 278 } 279 return AE_OK; 280 } 281 282 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 283 void *context, void **rv) 284 { 285 struct resource *mcfg_res = context; 286 287 acpi_walk_resources(handle, METHOD_NAME__CRS, 288 check_mcfg_resource, context); 289 290 if (mcfg_res->flags) 291 return AE_CTRL_TERMINATE; 292 293 return AE_OK; 294 } 295 296 static int __init is_acpi_reserved(unsigned long start, unsigned long end) 297 { 298 struct resource mcfg_res; 299 300 mcfg_res.start = start; 301 mcfg_res.end = end; 302 mcfg_res.flags = 0; 303 304 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 305 306 if (!mcfg_res.flags) 307 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 308 NULL); 309 310 return mcfg_res.flags; 311 } 312 313 static void __init pci_mmcfg_reject_broken(int early) 314 { 315 typeof(pci_mmcfg_config[0]) *cfg; 316 int i; 317 318 if ((pci_mmcfg_config_num == 0) || 319 (pci_mmcfg_config == NULL) || 320 (pci_mmcfg_config[0].address == 0)) 321 return; 322 323 cfg = &pci_mmcfg_config[0]; 324 325 for (i = 0; i < pci_mmcfg_config_num; i++) { 326 int valid = 0; 327 u32 size = (cfg->end_bus_number + 1) << 20; 328 cfg = &pci_mmcfg_config[i]; 329 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " 330 "segment %hu buses %u - %u\n", 331 i, (unsigned long)cfg->address, cfg->pci_segment, 332 (unsigned int)cfg->start_bus_number, 333 (unsigned int)cfg->end_bus_number); 334 335 if (!early && 336 is_acpi_reserved(cfg->address, cfg->address + size - 1)) { 337 printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved " 338 "in ACPI motherboard resources\n", 339 cfg->address); 340 valid = 1; 341 } 342 343 if (valid) 344 continue; 345 346 if (!early) 347 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" 348 " reserved in ACPI motherboard resources\n", 349 cfg->address); 350 /* Don't try to do this check unless configuration 351 type 1 is available. how about type 2 ?*/ 352 if (raw_pci_ops && e820_all_mapped(cfg->address, 353 cfg->address + size - 1, 354 E820_RESERVED)) { 355 printk(KERN_NOTICE 356 "PCI: MCFG area at %Lx reserved in E820\n", 357 cfg->address); 358 valid = 1; 359 } 360 361 if (!valid) 362 goto reject; 363 } 364 365 return; 366 367 reject: 368 printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); 369 pci_mmcfg_arch_free(); 370 kfree(pci_mmcfg_config); 371 pci_mmcfg_config = NULL; 372 pci_mmcfg_config_num = 0; 373 } 374 375 static int __initdata known_bridge; 376 377 static void __init __pci_mmcfg_init(int early) 378 { 379 /* MMCONFIG disabled */ 380 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 381 return; 382 383 /* MMCONFIG already enabled */ 384 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 385 return; 386 387 /* for late to exit */ 388 if (known_bridge) 389 return; 390 391 if (early) { 392 if (pci_mmcfg_check_hostbridge()) 393 known_bridge = 1; 394 } 395 396 if (!known_bridge) { 397 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); 398 pci_mmcfg_reject_broken(early); 399 } 400 401 if ((pci_mmcfg_config_num == 0) || 402 (pci_mmcfg_config == NULL) || 403 (pci_mmcfg_config[0].address == 0)) 404 return; 405 406 if (pci_mmcfg_arch_init()) { 407 if (known_bridge) 408 pci_mmcfg_insert_resources(IORESOURCE_BUSY); 409 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 410 } else { 411 /* 412 * Signal not to attempt to insert mmcfg resources because 413 * the architecture mmcfg setup could not initialize. 414 */ 415 pci_mmcfg_resources_inserted = 1; 416 } 417 } 418 419 void __init pci_mmcfg_early_init(void) 420 { 421 __pci_mmcfg_init(1); 422 } 423 424 void __init pci_mmcfg_late_init(void) 425 { 426 __pci_mmcfg_init(0); 427 } 428 429 static int __init pci_mmcfg_late_insert_resources(void) 430 { 431 /* 432 * If resources are already inserted or we are not using MMCONFIG, 433 * don't insert the resources. 434 */ 435 if ((pci_mmcfg_resources_inserted == 1) || 436 (pci_probe & PCI_PROBE_MMCONF) == 0 || 437 (pci_mmcfg_config_num == 0) || 438 (pci_mmcfg_config == NULL) || 439 (pci_mmcfg_config[0].address == 0)) 440 return 1; 441 442 /* 443 * Attempt to insert the mmcfg resources but not with the busy flag 444 * marked so it won't cause request errors when __request_region is 445 * called. 446 */ 447 pci_mmcfg_insert_resources(0); 448 449 return 0; 450 } 451 452 /* 453 * Perform MMCONFIG resource insertion after PCI initialization to allow for 454 * misprogrammed MCFG tables that state larger sizes but actually conflict 455 * with other system resources. 456 */ 457 late_initcall(pci_mmcfg_late_insert_resources); 458