1 /* 2 * mmconfig-shared.c - Low-level direct PCI config space access via 3 * MMCONFIG - common code between i386 and x86-64. 4 * 5 * This code does: 6 * - known chipset handling 7 * - ACPI decoding and validation 8 * 9 * Per-architecture code takes care of the mappings and accesses 10 * themselves. 11 */ 12 13 #include <linux/pci.h> 14 #include <linux/init.h> 15 #include <linux/acpi.h> 16 #include <linux/bitmap.h> 17 #include <asm/e820.h> 18 19 #include "pci.h" 20 21 /* aperture is up to 256MB but BIOS may reserve less */ 22 #define MMCONFIG_APER_MIN (2 * 1024*1024) 23 #define MMCONFIG_APER_MAX (256 * 1024*1024) 24 25 /* Indicate if the mmcfg resources have been placed into the resource table. */ 26 static int __initdata pci_mmcfg_resources_inserted; 27 28 static const char __init *pci_mmcfg_e7520(void) 29 { 30 u32 win; 31 pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win); 32 33 win = win & 0xf000; 34 if(win == 0x0000 || win == 0xf000) 35 pci_mmcfg_config_num = 0; 36 else { 37 pci_mmcfg_config_num = 1; 38 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 39 if (!pci_mmcfg_config) 40 return NULL; 41 pci_mmcfg_config[0].address = win << 16; 42 pci_mmcfg_config[0].pci_segment = 0; 43 pci_mmcfg_config[0].start_bus_number = 0; 44 pci_mmcfg_config[0].end_bus_number = 255; 45 } 46 47 return "Intel Corporation E7520 Memory Controller Hub"; 48 } 49 50 static const char __init *pci_mmcfg_intel_945(void) 51 { 52 u32 pciexbar, mask = 0, len = 0; 53 54 pci_mmcfg_config_num = 1; 55 56 pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar); 57 58 /* Enable bit */ 59 if (!(pciexbar & 1)) 60 pci_mmcfg_config_num = 0; 61 62 /* Size bits */ 63 switch ((pciexbar >> 1) & 3) { 64 case 0: 65 mask = 0xf0000000U; 66 len = 0x10000000U; 67 break; 68 case 1: 69 mask = 0xf8000000U; 70 len = 0x08000000U; 71 break; 72 case 2: 73 mask = 0xfc000000U; 74 len = 0x04000000U; 75 break; 76 default: 77 pci_mmcfg_config_num = 0; 78 } 79 80 /* Errata #2, things break when not aligned on a 256Mb boundary */ 81 /* Can only happen in 64M/128M mode */ 82 83 if ((pciexbar & mask) & 0x0fffffffU) 84 pci_mmcfg_config_num = 0; 85 86 /* Don't hit the APIC registers and their friends */ 87 if ((pciexbar & mask) >= 0xf0000000U) 88 pci_mmcfg_config_num = 0; 89 90 if (pci_mmcfg_config_num) { 91 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL); 92 if (!pci_mmcfg_config) 93 return NULL; 94 pci_mmcfg_config[0].address = pciexbar & mask; 95 pci_mmcfg_config[0].pci_segment = 0; 96 pci_mmcfg_config[0].start_bus_number = 0; 97 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1; 98 } 99 100 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 101 } 102 103 struct pci_mmcfg_hostbridge_probe { 104 u32 vendor; 105 u32 device; 106 const char *(*probe)(void); 107 }; 108 109 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { 110 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 111 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 112 }; 113 114 static int __init pci_mmcfg_check_hostbridge(void) 115 { 116 u32 l; 117 u16 vendor, device; 118 int i; 119 const char *name; 120 121 pci_direct_conf1.read(0, 0, PCI_DEVFN(0,0), 0, 4, &l); 122 vendor = l & 0xffff; 123 device = (l >> 16) & 0xffff; 124 125 pci_mmcfg_config_num = 0; 126 pci_mmcfg_config = NULL; 127 name = NULL; 128 129 for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 130 if (pci_mmcfg_probes[i].vendor == vendor && 131 pci_mmcfg_probes[i].device == device) 132 name = pci_mmcfg_probes[i].probe(); 133 } 134 135 if (name) { 136 printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n", 137 name, pci_mmcfg_config_num ? "with" : "without"); 138 } 139 140 return name != NULL; 141 } 142 143 static void __init pci_mmcfg_insert_resources(unsigned long resource_flags) 144 { 145 #define PCI_MMCFG_RESOURCE_NAME_LEN 19 146 int i; 147 struct resource *res; 148 char *names; 149 unsigned num_buses; 150 151 res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), 152 pci_mmcfg_config_num, GFP_KERNEL); 153 if (!res) { 154 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); 155 return; 156 } 157 158 names = (void *)&res[pci_mmcfg_config_num]; 159 for (i = 0; i < pci_mmcfg_config_num; i++, res++) { 160 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i]; 161 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; 162 res->name = names; 163 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u", 164 cfg->pci_segment); 165 res->start = cfg->address; 166 res->end = res->start + (num_buses << 20) - 1; 167 res->flags = IORESOURCE_MEM | resource_flags; 168 insert_resource(&iomem_resource, res); 169 names += PCI_MMCFG_RESOURCE_NAME_LEN; 170 } 171 172 /* Mark that the resources have been inserted. */ 173 pci_mmcfg_resources_inserted = 1; 174 } 175 176 static acpi_status __init check_mcfg_resource(struct acpi_resource *res, 177 void *data) 178 { 179 struct resource *mcfg_res = data; 180 struct acpi_resource_address64 address; 181 acpi_status status; 182 183 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 184 struct acpi_resource_fixed_memory32 *fixmem32 = 185 &res->data.fixed_memory32; 186 if (!fixmem32) 187 return AE_OK; 188 if ((mcfg_res->start >= fixmem32->address) && 189 (mcfg_res->end < (fixmem32->address + 190 fixmem32->address_length))) { 191 mcfg_res->flags = 1; 192 return AE_CTRL_TERMINATE; 193 } 194 } 195 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 196 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 197 return AE_OK; 198 199 status = acpi_resource_to_address64(res, &address); 200 if (ACPI_FAILURE(status) || 201 (address.address_length <= 0) || 202 (address.resource_type != ACPI_MEMORY_RANGE)) 203 return AE_OK; 204 205 if ((mcfg_res->start >= address.minimum) && 206 (mcfg_res->end < (address.minimum + address.address_length))) { 207 mcfg_res->flags = 1; 208 return AE_CTRL_TERMINATE; 209 } 210 return AE_OK; 211 } 212 213 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, 214 void *context, void **rv) 215 { 216 struct resource *mcfg_res = context; 217 218 acpi_walk_resources(handle, METHOD_NAME__CRS, 219 check_mcfg_resource, context); 220 221 if (mcfg_res->flags) 222 return AE_CTRL_TERMINATE; 223 224 return AE_OK; 225 } 226 227 static int __init is_acpi_reserved(unsigned long start, unsigned long end) 228 { 229 struct resource mcfg_res; 230 231 mcfg_res.start = start; 232 mcfg_res.end = end; 233 mcfg_res.flags = 0; 234 235 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 236 237 if (!mcfg_res.flags) 238 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 239 NULL); 240 241 return mcfg_res.flags; 242 } 243 244 static void __init pci_mmcfg_reject_broken(int type, int early) 245 { 246 typeof(pci_mmcfg_config[0]) *cfg; 247 int i; 248 249 if ((pci_mmcfg_config_num == 0) || 250 (pci_mmcfg_config == NULL) || 251 (pci_mmcfg_config[0].address == 0)) 252 return; 253 254 cfg = &pci_mmcfg_config[0]; 255 256 /* 257 * Handle more broken MCFG tables on Asus etc. 258 * They only contain a single entry for bus 0-0. 259 */ 260 if (pci_mmcfg_config_num == 1 && 261 cfg->pci_segment == 0 && 262 (cfg->start_bus_number | cfg->end_bus_number) == 0) { 263 printk(KERN_ERR "PCI: start and end of bus number is 0. " 264 "Rejected as broken MCFG.\n"); 265 goto reject; 266 } 267 268 for (i = 0; i < pci_mmcfg_config_num; i++) { 269 int valid = 0; 270 u32 size = (cfg->end_bus_number + 1) << 20; 271 cfg = &pci_mmcfg_config[i]; 272 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " 273 "segment %hu buses %u - %u\n", 274 i, (unsigned long)cfg->address, cfg->pci_segment, 275 (unsigned int)cfg->start_bus_number, 276 (unsigned int)cfg->end_bus_number); 277 278 if (!early && 279 is_acpi_reserved(cfg->address, cfg->address + size - 1)) { 280 printk(KERN_NOTICE "PCI: MCFG area at %Lx reserved " 281 "in ACPI motherboard resources\n", 282 cfg->address); 283 valid = 1; 284 } 285 286 if (valid) 287 continue; 288 289 if (!early) 290 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" 291 " reserved in ACPI motherboard resources\n", 292 cfg->address); 293 /* Don't try to do this check unless configuration 294 type 1 is available. */ 295 if (type == 1 && e820_all_mapped(cfg->address, 296 cfg->address + size - 1, 297 E820_RESERVED)) { 298 printk(KERN_NOTICE 299 "PCI: MCFG area at %Lx reserved in E820\n", 300 cfg->address); 301 valid = 1; 302 } 303 304 if (!valid) 305 goto reject; 306 } 307 308 return; 309 310 reject: 311 printk(KERN_ERR "PCI: Not using MMCONFIG.\n"); 312 pci_mmcfg_arch_free(); 313 kfree(pci_mmcfg_config); 314 pci_mmcfg_config = NULL; 315 pci_mmcfg_config_num = 0; 316 } 317 318 static int __initdata known_bridge; 319 320 void __init __pci_mmcfg_init(int type, int early) 321 { 322 /* MMCONFIG disabled */ 323 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 324 return; 325 326 /* MMCONFIG already enabled */ 327 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) 328 return; 329 330 /* for late to exit */ 331 if (known_bridge) 332 return; 333 334 if (early && type == 1) { 335 if (pci_mmcfg_check_hostbridge()) 336 known_bridge = 1; 337 } 338 339 if (!known_bridge) { 340 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg); 341 pci_mmcfg_reject_broken(type, early); 342 } 343 344 if ((pci_mmcfg_config_num == 0) || 345 (pci_mmcfg_config == NULL) || 346 (pci_mmcfg_config[0].address == 0)) 347 return; 348 349 if (pci_mmcfg_arch_init()) { 350 if (known_bridge) 351 pci_mmcfg_insert_resources(IORESOURCE_BUSY); 352 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 353 } else { 354 /* 355 * Signal not to attempt to insert mmcfg resources because 356 * the architecture mmcfg setup could not initialize. 357 */ 358 pci_mmcfg_resources_inserted = 1; 359 } 360 } 361 362 void __init pci_mmcfg_early_init(int type) 363 { 364 __pci_mmcfg_init(type, 1); 365 } 366 367 void __init pci_mmcfg_late_init(void) 368 { 369 int type = 0; 370 371 if (pci_probe & PCI_PROBE_CONF1) 372 type = 1; 373 374 __pci_mmcfg_init(type, 0); 375 } 376 377 static int __init pci_mmcfg_late_insert_resources(void) 378 { 379 /* 380 * If resources are already inserted or we are not using MMCONFIG, 381 * don't insert the resources. 382 */ 383 if ((pci_mmcfg_resources_inserted == 1) || 384 (pci_probe & PCI_PROBE_MMCONF) == 0 || 385 (pci_mmcfg_config_num == 0) || 386 (pci_mmcfg_config == NULL) || 387 (pci_mmcfg_config[0].address == 0)) 388 return 1; 389 390 /* 391 * Attempt to insert the mmcfg resources but not with the busy flag 392 * marked so it won't cause request errors when __request_region is 393 * called. 394 */ 395 pci_mmcfg_insert_resources(0); 396 397 return 0; 398 } 399 400 /* 401 * Perform MMCONFIG resource insertion after PCI initialization to allow for 402 * misprogrammed MCFG tables that state larger sizes but actually conflict 403 * with other system resources. 404 */ 405 late_initcall(pci_mmcfg_late_insert_resources); 406