1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mmconfig-shared.c - Low-level direct PCI config space access via 4 * MMCONFIG - common code between i386 and x86-64. 5 * 6 * This code does: 7 * - known chipset handling 8 * - ACPI decoding and validation 9 * 10 * Per-architecture code takes care of the mappings and accesses 11 * themselves. 12 */ 13 14 #include <linux/acpi.h> 15 #include <linux/efi.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/bitmap.h> 19 #include <linux/dmi.h> 20 #include <linux/slab.h> 21 #include <linux/mutex.h> 22 #include <linux/rculist.h> 23 #include <asm/e820/api.h> 24 #include <asm/pci_x86.h> 25 #include <asm/acpi.h> 26 27 #define PREFIX "PCI: " 28 29 /* Indicate if the mmcfg resources have been placed into the resource table. */ 30 static bool pci_mmcfg_running_state; 31 static bool pci_mmcfg_arch_init_failed; 32 static DEFINE_MUTEX(pci_mmcfg_lock); 33 #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map) 34 35 LIST_HEAD(pci_mmcfg_list); 36 37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) 38 { 39 if (cfg->res.parent) 40 release_resource(&cfg->res); 41 list_del(&cfg->list); 42 kfree(cfg); 43 } 44 45 static void __init free_all_mmcfg(void) 46 { 47 struct pci_mmcfg_region *cfg, *tmp; 48 49 pci_mmcfg_arch_free(); 50 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) 51 pci_mmconfig_remove(cfg); 52 } 53 54 static void list_add_sorted(struct pci_mmcfg_region *new) 55 { 56 struct pci_mmcfg_region *cfg; 57 58 /* keep list sorted by segment and starting bus number */ 59 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { 60 if (cfg->segment > new->segment || 61 (cfg->segment == new->segment && 62 cfg->start_bus >= new->start_bus)) { 63 list_add_tail_rcu(&new->list, &cfg->list); 64 return; 65 } 66 } 67 list_add_tail_rcu(&new->list, &pci_mmcfg_list); 68 } 69 70 static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start, 71 int end, u64 addr) 72 { 73 struct pci_mmcfg_region *new; 74 struct resource *res; 75 76 if (addr == 0) 77 return NULL; 78 79 new = kzalloc(sizeof(*new), GFP_KERNEL); 80 if (!new) 81 return NULL; 82 83 new->address = addr; 84 new->segment = segment; 85 new->start_bus = start; 86 new->end_bus = end; 87 88 res = &new->res; 89 res->start = addr + PCI_MMCFG_BUS_OFFSET(start); 90 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; 91 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; 92 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, 93 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); 94 res->name = new->name; 95 96 return new; 97 } 98 99 struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, 100 int end, u64 addr) 101 { 102 struct pci_mmcfg_region *new; 103 104 new = pci_mmconfig_alloc(segment, start, end, addr); 105 if (new) { 106 mutex_lock(&pci_mmcfg_lock); 107 list_add_sorted(new); 108 mutex_unlock(&pci_mmcfg_lock); 109 110 pr_info(PREFIX 111 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR " 112 "(base %#lx)\n", 113 segment, start, end, &new->res, (unsigned long)addr); 114 } 115 116 return new; 117 } 118 119 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) 120 { 121 struct pci_mmcfg_region *cfg; 122 123 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) 124 if (cfg->segment == segment && 125 cfg->start_bus <= bus && bus <= cfg->end_bus) 126 return cfg; 127 128 return NULL; 129 } 130 131 static const char *__init pci_mmcfg_e7520(void) 132 { 133 u32 win; 134 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); 135 136 win = win & 0xf000; 137 if (win == 0x0000 || win == 0xf000) 138 return NULL; 139 140 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL) 141 return NULL; 142 143 return "Intel Corporation E7520 Memory Controller Hub"; 144 } 145 146 static const char *__init pci_mmcfg_intel_945(void) 147 { 148 u32 pciexbar, mask = 0, len = 0; 149 150 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); 151 152 /* Enable bit */ 153 if (!(pciexbar & 1)) 154 return NULL; 155 156 /* Size bits */ 157 switch ((pciexbar >> 1) & 3) { 158 case 0: 159 mask = 0xf0000000U; 160 len = 0x10000000U; 161 break; 162 case 1: 163 mask = 0xf8000000U; 164 len = 0x08000000U; 165 break; 166 case 2: 167 mask = 0xfc000000U; 168 len = 0x04000000U; 169 break; 170 default: 171 return NULL; 172 } 173 174 /* Errata #2, things break when not aligned on a 256Mb boundary */ 175 /* Can only happen in 64M/128M mode */ 176 177 if ((pciexbar & mask) & 0x0fffffffU) 178 return NULL; 179 180 /* Don't hit the APIC registers and their friends */ 181 if ((pciexbar & mask) >= 0xf0000000U) 182 return NULL; 183 184 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) 185 return NULL; 186 187 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; 188 } 189 190 static const char *__init pci_mmcfg_amd_fam10h(void) 191 { 192 u32 low, high, address; 193 u64 base, msr; 194 int i; 195 unsigned segnbits = 0, busnbits, end_bus; 196 197 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) 198 return NULL; 199 200 address = MSR_FAM10H_MMIO_CONF_BASE; 201 if (rdmsr_safe(address, &low, &high)) 202 return NULL; 203 204 msr = high; 205 msr <<= 32; 206 msr |= low; 207 208 /* mmconfig is not enable */ 209 if (!(msr & FAM10H_MMIO_CONF_ENABLE)) 210 return NULL; 211 212 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); 213 214 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & 215 FAM10H_MMIO_CONF_BUSRANGE_MASK; 216 217 /* 218 * only handle bus 0 ? 219 * need to skip it 220 */ 221 if (!busnbits) 222 return NULL; 223 224 if (busnbits > 8) { 225 segnbits = busnbits - 8; 226 busnbits = 8; 227 } 228 229 end_bus = (1 << busnbits) - 1; 230 for (i = 0; i < (1 << segnbits); i++) 231 if (pci_mmconfig_add(i, 0, end_bus, 232 base + (1<<28) * i) == NULL) { 233 free_all_mmcfg(); 234 return NULL; 235 } 236 237 return "AMD Family 10h NB"; 238 } 239 240 static bool __initdata mcp55_checked; 241 static const char *__init pci_mmcfg_nvidia_mcp55(void) 242 { 243 int bus; 244 int mcp55_mmconf_found = 0; 245 246 static const u32 extcfg_regnum __initconst = 0x90; 247 static const u32 extcfg_regsize __initconst = 4; 248 static const u32 extcfg_enable_mask __initconst = 1 << 31; 249 static const u32 extcfg_start_mask __initconst = 0xff << 16; 250 static const int extcfg_start_shift __initconst = 16; 251 static const u32 extcfg_size_mask __initconst = 0x3 << 28; 252 static const int extcfg_size_shift __initconst = 28; 253 static const int extcfg_sizebus[] __initconst = { 254 0x100, 0x80, 0x40, 0x20 255 }; 256 static const u32 extcfg_base_mask[] __initconst = { 257 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff 258 }; 259 static const int extcfg_base_lshift __initconst = 25; 260 261 /* 262 * do check if amd fam10h already took over 263 */ 264 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked) 265 return NULL; 266 267 mcp55_checked = true; 268 for (bus = 0; bus < 256; bus++) { 269 u64 base; 270 u32 l, extcfg; 271 u16 vendor, device; 272 int start, size_index, end; 273 274 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); 275 vendor = l & 0xffff; 276 device = (l >> 16) & 0xffff; 277 278 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) 279 continue; 280 281 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, 282 extcfg_regsize, &extcfg); 283 284 if (!(extcfg & extcfg_enable_mask)) 285 continue; 286 287 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; 288 base = extcfg & extcfg_base_mask[size_index]; 289 /* base could > 4G */ 290 base <<= extcfg_base_lshift; 291 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; 292 end = start + extcfg_sizebus[size_index] - 1; 293 if (pci_mmconfig_add(0, start, end, base) == NULL) 294 continue; 295 mcp55_mmconf_found++; 296 } 297 298 if (!mcp55_mmconf_found) 299 return NULL; 300 301 return "nVidia MCP55"; 302 } 303 304 struct pci_mmcfg_hostbridge_probe { 305 u32 bus; 306 u32 devfn; 307 u32 vendor; 308 u32 device; 309 const char *(*probe)(void); 310 }; 311 312 static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = { 313 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 314 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, 315 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, 316 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, 317 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, 318 0x1200, pci_mmcfg_amd_fam10h }, 319 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, 320 0x1200, pci_mmcfg_amd_fam10h }, 321 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, 322 0x0369, pci_mmcfg_nvidia_mcp55 }, 323 }; 324 325 static void __init pci_mmcfg_check_end_bus_number(void) 326 { 327 struct pci_mmcfg_region *cfg, *cfgx; 328 329 /* Fixup overlaps */ 330 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 331 if (cfg->end_bus < cfg->start_bus) 332 cfg->end_bus = 255; 333 334 /* Don't access the list head ! */ 335 if (cfg->list.next == &pci_mmcfg_list) 336 break; 337 338 cfgx = list_entry(cfg->list.next, typeof(*cfg), list); 339 if (cfg->end_bus >= cfgx->start_bus) 340 cfg->end_bus = cfgx->start_bus - 1; 341 } 342 } 343 344 static int __init pci_mmcfg_check_hostbridge(void) 345 { 346 u32 l; 347 u32 bus, devfn; 348 u16 vendor, device; 349 int i; 350 const char *name; 351 352 if (!raw_pci_ops) 353 return 0; 354 355 free_all_mmcfg(); 356 357 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { 358 bus = pci_mmcfg_probes[i].bus; 359 devfn = pci_mmcfg_probes[i].devfn; 360 raw_pci_ops->read(0, bus, devfn, 0, 4, &l); 361 vendor = l & 0xffff; 362 device = (l >> 16) & 0xffff; 363 364 name = NULL; 365 if (pci_mmcfg_probes[i].vendor == vendor && 366 pci_mmcfg_probes[i].device == device) 367 name = pci_mmcfg_probes[i].probe(); 368 369 if (name) 370 pr_info(PREFIX "%s with MMCONFIG support\n", name); 371 } 372 373 /* some end_bus_number is crazy, fix it */ 374 pci_mmcfg_check_end_bus_number(); 375 376 return !list_empty(&pci_mmcfg_list); 377 } 378 379 static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data) 380 { 381 struct resource *mcfg_res = data; 382 struct acpi_resource_address64 address; 383 acpi_status status; 384 385 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { 386 struct acpi_resource_fixed_memory32 *fixmem32 = 387 &res->data.fixed_memory32; 388 if (!fixmem32) 389 return AE_OK; 390 if ((mcfg_res->start >= fixmem32->address) && 391 (mcfg_res->end < (fixmem32->address + 392 fixmem32->address_length))) { 393 mcfg_res->flags = 1; 394 return AE_CTRL_TERMINATE; 395 } 396 } 397 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && 398 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) 399 return AE_OK; 400 401 status = acpi_resource_to_address64(res, &address); 402 if (ACPI_FAILURE(status) || 403 (address.address.address_length <= 0) || 404 (address.resource_type != ACPI_MEMORY_RANGE)) 405 return AE_OK; 406 407 if ((mcfg_res->start >= address.address.minimum) && 408 (mcfg_res->end < (address.address.minimum + address.address.address_length))) { 409 mcfg_res->flags = 1; 410 return AE_CTRL_TERMINATE; 411 } 412 return AE_OK; 413 } 414 415 static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl, 416 void *context, void **rv) 417 { 418 struct resource *mcfg_res = context; 419 420 acpi_walk_resources(handle, METHOD_NAME__CRS, 421 check_mcfg_resource, context); 422 423 if (mcfg_res->flags) 424 return AE_CTRL_TERMINATE; 425 426 return AE_OK; 427 } 428 429 static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used) 430 { 431 struct resource mcfg_res; 432 433 mcfg_res.start = start; 434 mcfg_res.end = end - 1; 435 mcfg_res.flags = 0; 436 437 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); 438 439 if (!mcfg_res.flags) 440 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, 441 NULL); 442 443 return mcfg_res.flags; 444 } 445 446 static bool is_efi_mmio(u64 start, u64 end, enum e820_type not_used) 447 { 448 #ifdef CONFIG_EFI 449 efi_memory_desc_t *md; 450 u64 size, mmio_start, mmio_end; 451 452 for_each_efi_memory_desc(md) { 453 if (md->type == EFI_MEMORY_MAPPED_IO) { 454 size = md->num_pages << EFI_PAGE_SHIFT; 455 mmio_start = md->phys_addr; 456 mmio_end = mmio_start + size; 457 458 /* 459 * N.B. Caller supplies (start, start + size), 460 * so to match, mmio_end is the first address 461 * *past* the EFI_MEMORY_MAPPED_IO area. 462 */ 463 if (mmio_start <= start && end <= mmio_end) 464 return true; 465 } 466 } 467 #endif 468 469 return false; 470 } 471 472 typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type); 473 474 static bool __ref is_mmconf_reserved(check_reserved_t is_reserved, 475 struct pci_mmcfg_region *cfg, 476 struct device *dev, const char *method) 477 { 478 u64 addr = cfg->res.start; 479 u64 size = resource_size(&cfg->res); 480 u64 old_size = size; 481 int num_buses; 482 483 while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) { 484 size >>= 1; 485 if (size < (16UL<<20)) 486 break; 487 } 488 489 if (size < (16UL<<20) && size != old_size) 490 return false; 491 492 if (dev) 493 dev_info(dev, "MMCONFIG at %pR reserved as %s\n", 494 &cfg->res, method); 495 else 496 pr_info(PREFIX "MMCONFIG at %pR reserved as %s\n", 497 &cfg->res, method); 498 499 if (old_size != size) { 500 /* update end_bus */ 501 cfg->end_bus = cfg->start_bus + ((size>>20) - 1); 502 num_buses = cfg->end_bus - cfg->start_bus + 1; 503 cfg->res.end = cfg->res.start + 504 PCI_MMCFG_BUS_OFFSET(num_buses) - 1; 505 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN, 506 "PCI MMCONFIG %04x [bus %02x-%02x]", 507 cfg->segment, cfg->start_bus, cfg->end_bus); 508 509 if (dev) 510 dev_info(dev, 511 "MMCONFIG " 512 "at %pR (base %#lx) (size reduced!)\n", 513 &cfg->res, (unsigned long) cfg->address); 514 else 515 pr_info(PREFIX 516 "MMCONFIG for %04x [bus%02x-%02x] " 517 "at %pR (base %#lx) (size reduced!)\n", 518 cfg->segment, cfg->start_bus, cfg->end_bus, 519 &cfg->res, (unsigned long) cfg->address); 520 } 521 522 return true; 523 } 524 525 static bool __ref 526 pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int early) 527 { 528 if (!early && !acpi_disabled) { 529 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 530 "ACPI motherboard resource")) 531 return true; 532 533 if (dev) 534 dev_info(dev, FW_INFO 535 "MMCONFIG at %pR not reserved in " 536 "ACPI motherboard resources\n", 537 &cfg->res); 538 else 539 pr_info(FW_INFO PREFIX 540 "MMCONFIG at %pR not reserved in " 541 "ACPI motherboard resources\n", 542 &cfg->res); 543 544 if (is_mmconf_reserved(is_efi_mmio, cfg, dev, 545 "EfiMemoryMappedIO")) 546 return true; 547 } 548 549 /* 550 * e820__mapped_all() is marked as __init. 551 * All entries from ACPI MCFG table have been checked at boot time. 552 * For MCFG information constructed from hotpluggable host bridge's 553 * _CBA method, just assume it's reserved. 554 */ 555 if (pci_mmcfg_running_state) 556 return true; 557 558 /* Don't try to do this check unless configuration 559 type 1 is available. how about type 2 ?*/ 560 if (raw_pci_ops) 561 return is_mmconf_reserved(e820__mapped_all, cfg, dev, 562 "E820 entry"); 563 564 return false; 565 } 566 567 static void __init pci_mmcfg_reject_broken(int early) 568 { 569 struct pci_mmcfg_region *cfg; 570 571 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 572 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) { 573 pr_info(PREFIX "not using MMCONFIG\n"); 574 free_all_mmcfg(); 575 return; 576 } 577 } 578 } 579 580 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, 581 struct acpi_mcfg_allocation *cfg) 582 { 583 if (cfg->address < 0xFFFFFFFF) 584 return 0; 585 586 if (!strncmp(mcfg->header.oem_id, "SGI", 3)) 587 return 0; 588 589 if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010)) 590 return 0; 591 592 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx " 593 "is above 4GB, ignored\n", cfg->pci_segment, 594 cfg->start_bus_number, cfg->end_bus_number, cfg->address); 595 return -EINVAL; 596 } 597 598 static int __init pci_parse_mcfg(struct acpi_table_header *header) 599 { 600 struct acpi_table_mcfg *mcfg; 601 struct acpi_mcfg_allocation *cfg_table, *cfg; 602 unsigned long i; 603 int entries; 604 605 if (!header) 606 return -EINVAL; 607 608 mcfg = (struct acpi_table_mcfg *)header; 609 610 /* how many config structures do we have */ 611 free_all_mmcfg(); 612 entries = 0; 613 i = header->length - sizeof(struct acpi_table_mcfg); 614 while (i >= sizeof(struct acpi_mcfg_allocation)) { 615 entries++; 616 i -= sizeof(struct acpi_mcfg_allocation); 617 } 618 if (entries == 0) { 619 pr_err(PREFIX "MMCONFIG has no entries\n"); 620 return -ENODEV; 621 } 622 623 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; 624 for (i = 0; i < entries; i++) { 625 cfg = &cfg_table[i]; 626 if (acpi_mcfg_check_entry(mcfg, cfg)) { 627 free_all_mmcfg(); 628 return -ENODEV; 629 } 630 631 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, 632 cfg->end_bus_number, cfg->address) == NULL) { 633 pr_warn(PREFIX "no memory for MCFG entries\n"); 634 free_all_mmcfg(); 635 return -ENOMEM; 636 } 637 } 638 639 return 0; 640 } 641 642 #ifdef CONFIG_ACPI_APEI 643 extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size, 644 void *data), void *data); 645 646 static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size, 647 void *data), void *data) 648 { 649 struct pci_mmcfg_region *cfg; 650 int rc; 651 652 if (list_empty(&pci_mmcfg_list)) 653 return 0; 654 655 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 656 rc = func(cfg->res.start, resource_size(&cfg->res), data); 657 if (rc) 658 return rc; 659 } 660 661 return 0; 662 } 663 #define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region) 664 #else 665 #define set_apei_filter() 666 #endif 667 668 static void __init __pci_mmcfg_init(int early) 669 { 670 pci_mmcfg_reject_broken(early); 671 if (list_empty(&pci_mmcfg_list)) 672 return; 673 674 if (pcibios_last_bus < 0) { 675 const struct pci_mmcfg_region *cfg; 676 677 list_for_each_entry(cfg, &pci_mmcfg_list, list) { 678 if (cfg->segment) 679 break; 680 pcibios_last_bus = cfg->end_bus; 681 } 682 } 683 684 if (pci_mmcfg_arch_init()) 685 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 686 else { 687 free_all_mmcfg(); 688 pci_mmcfg_arch_init_failed = true; 689 } 690 } 691 692 static int __initdata known_bridge; 693 694 void __init pci_mmcfg_early_init(void) 695 { 696 if (pci_probe & PCI_PROBE_MMCONF) { 697 if (pci_mmcfg_check_hostbridge()) 698 known_bridge = 1; 699 else 700 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 701 __pci_mmcfg_init(1); 702 703 set_apei_filter(); 704 } 705 } 706 707 void __init pci_mmcfg_late_init(void) 708 { 709 /* MMCONFIG disabled */ 710 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 711 return; 712 713 if (known_bridge) 714 return; 715 716 /* MMCONFIG hasn't been enabled yet, try again */ 717 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) { 718 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); 719 __pci_mmcfg_init(0); 720 } 721 } 722 723 static int __init pci_mmcfg_late_insert_resources(void) 724 { 725 struct pci_mmcfg_region *cfg; 726 727 pci_mmcfg_running_state = true; 728 729 /* If we are not using MMCONFIG, don't insert the resources. */ 730 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 731 return 1; 732 733 /* 734 * Attempt to insert the mmcfg resources but not with the busy flag 735 * marked so it won't cause request errors when __request_region is 736 * called. 737 */ 738 list_for_each_entry(cfg, &pci_mmcfg_list, list) 739 if (!cfg->res.parent) 740 insert_resource(&iomem_resource, &cfg->res); 741 742 return 0; 743 } 744 745 /* 746 * Perform MMCONFIG resource insertion after PCI initialization to allow for 747 * misprogrammed MCFG tables that state larger sizes but actually conflict 748 * with other system resources. 749 */ 750 late_initcall(pci_mmcfg_late_insert_resources); 751 752 /* Add MMCFG information for host bridges */ 753 int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, 754 phys_addr_t addr) 755 { 756 int rc; 757 struct resource *tmp = NULL; 758 struct pci_mmcfg_region *cfg; 759 760 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed) 761 return -ENODEV; 762 763 if (start > end) 764 return -EINVAL; 765 766 mutex_lock(&pci_mmcfg_lock); 767 cfg = pci_mmconfig_lookup(seg, start); 768 if (cfg) { 769 if (cfg->end_bus < end) 770 dev_info(dev, FW_INFO 771 "MMCONFIG for " 772 "domain %04x [bus %02x-%02x] " 773 "only partially covers this bridge\n", 774 cfg->segment, cfg->start_bus, cfg->end_bus); 775 mutex_unlock(&pci_mmcfg_lock); 776 return -EEXIST; 777 } 778 779 if (!addr) { 780 mutex_unlock(&pci_mmcfg_lock); 781 return -EINVAL; 782 } 783 784 rc = -EBUSY; 785 cfg = pci_mmconfig_alloc(seg, start, end, addr); 786 if (cfg == NULL) { 787 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n"); 788 rc = -ENOMEM; 789 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) { 790 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n", 791 &cfg->res); 792 } else { 793 /* Insert resource if it's not in boot stage */ 794 if (pci_mmcfg_running_state) 795 tmp = insert_resource_conflict(&iomem_resource, 796 &cfg->res); 797 798 if (tmp) { 799 dev_warn(dev, 800 "MMCONFIG %pR conflicts with " 801 "%s %pR\n", 802 &cfg->res, tmp->name, tmp); 803 } else if (pci_mmcfg_arch_map(cfg)) { 804 dev_warn(dev, "fail to map MMCONFIG %pR.\n", 805 &cfg->res); 806 } else { 807 list_add_sorted(cfg); 808 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n", 809 &cfg->res, (unsigned long)addr); 810 cfg = NULL; 811 rc = 0; 812 } 813 } 814 815 if (cfg) { 816 if (cfg->res.parent) 817 release_resource(&cfg->res); 818 kfree(cfg); 819 } 820 821 mutex_unlock(&pci_mmcfg_lock); 822 823 return rc; 824 } 825 826 /* Delete MMCFG information for host bridges */ 827 int pci_mmconfig_delete(u16 seg, u8 start, u8 end) 828 { 829 struct pci_mmcfg_region *cfg; 830 831 mutex_lock(&pci_mmcfg_lock); 832 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) 833 if (cfg->segment == seg && cfg->start_bus == start && 834 cfg->end_bus == end) { 835 list_del_rcu(&cfg->list); 836 synchronize_rcu(); 837 pci_mmcfg_arch_unmap(cfg); 838 if (cfg->res.parent) 839 release_resource(&cfg->res); 840 mutex_unlock(&pci_mmcfg_lock); 841 kfree(cfg); 842 return 0; 843 } 844 mutex_unlock(&pci_mmcfg_lock); 845 846 return -ENOENT; 847 } 848