1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AMD Memory Encryption Support 4 * 5 * Copyright (C) 2016 Advanced Micro Devices, Inc. 6 * 7 * Author: Tom Lendacky <thomas.lendacky@amd.com> 8 */ 9 10 #define DISABLE_BRANCH_PROFILING 11 12 /* 13 * Since we're dealing with identity mappings, physical and virtual 14 * addresses are the same, so override these defines which are ultimately 15 * used by the headers in misc.h. 16 */ 17 #define __pa(x) ((unsigned long)(x)) 18 #define __va(x) ((void *)((unsigned long)(x))) 19 20 /* 21 * Special hack: we have to be careful, because no indirections are 22 * allowed here, and paravirt_ops is a kind of one. As it will only run in 23 * baremetal anyway, we just keep it from happening. (This list needs to 24 * be extended when new paravirt and debugging variants are added.) 25 */ 26 #undef CONFIG_PARAVIRT 27 #undef CONFIG_PARAVIRT_XXL 28 #undef CONFIG_PARAVIRT_SPINLOCKS 29 30 /* 31 * This code runs before CPU feature bits are set. By default, the 32 * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if 33 * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5 34 * is provided to handle this situation and, instead, use a variable that 35 * has been set by the early boot code. 36 */ 37 #define USE_EARLY_PGTABLE_L5 38 39 #include <linux/kernel.h> 40 #include <linux/mm.h> 41 #include <linux/mem_encrypt.h> 42 #include <linux/cc_platform.h> 43 44 #include <asm/setup.h> 45 #include <asm/sections.h> 46 #include <asm/cmdline.h> 47 #include <asm/coco.h> 48 49 #include "mm_internal.h" 50 51 #define PGD_FLAGS _KERNPG_TABLE_NOENC 52 #define P4D_FLAGS _KERNPG_TABLE_NOENC 53 #define PUD_FLAGS _KERNPG_TABLE_NOENC 54 #define PMD_FLAGS _KERNPG_TABLE_NOENC 55 56 #define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL) 57 58 #define PMD_FLAGS_DEC PMD_FLAGS_LARGE 59 #define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_LARGE_CACHE_MASK) | \ 60 (_PAGE_PAT_LARGE | _PAGE_PWT)) 61 62 #define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC) 63 64 #define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL) 65 66 #define PTE_FLAGS_DEC PTE_FLAGS 67 #define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \ 68 (_PAGE_PAT | _PAGE_PWT)) 69 70 #define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC) 71 72 struct sme_populate_pgd_data { 73 void *pgtable_area; 74 pgd_t *pgd; 75 76 pmdval_t pmd_flags; 77 pteval_t pte_flags; 78 unsigned long paddr; 79 80 unsigned long vaddr; 81 unsigned long vaddr_end; 82 }; 83 84 /* 85 * This work area lives in the .init.scratch section, which lives outside of 86 * the kernel proper. It is sized to hold the intermediate copy buffer and 87 * more than enough pagetable pages. 88 * 89 * By using this section, the kernel can be encrypted in place and it 90 * avoids any possibility of boot parameters or initramfs images being 91 * placed such that the in-place encryption logic overwrites them. This 92 * section is 2MB aligned to allow for simple pagetable setup using only 93 * PMD entries (see vmlinux.lds.S). 94 */ 95 static char sme_workarea[2 * PMD_PAGE_SIZE] __section(".init.scratch"); 96 97 static char sme_cmdline_arg[] __initdata = "mem_encrypt"; 98 static char sme_cmdline_on[] __initdata = "on"; 99 static char sme_cmdline_off[] __initdata = "off"; 100 101 static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd) 102 { 103 unsigned long pgd_start, pgd_end, pgd_size; 104 pgd_t *pgd_p; 105 106 pgd_start = ppd->vaddr & PGDIR_MASK; 107 pgd_end = ppd->vaddr_end & PGDIR_MASK; 108 109 pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t); 110 111 pgd_p = ppd->pgd + pgd_index(ppd->vaddr); 112 113 memset(pgd_p, 0, pgd_size); 114 } 115 116 static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd) 117 { 118 pgd_t *pgd; 119 p4d_t *p4d; 120 pud_t *pud; 121 pmd_t *pmd; 122 123 pgd = ppd->pgd + pgd_index(ppd->vaddr); 124 if (pgd_none(*pgd)) { 125 p4d = ppd->pgtable_area; 126 memset(p4d, 0, sizeof(*p4d) * PTRS_PER_P4D); 127 ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D; 128 set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d))); 129 } 130 131 p4d = p4d_offset(pgd, ppd->vaddr); 132 if (p4d_none(*p4d)) { 133 pud = ppd->pgtable_area; 134 memset(pud, 0, sizeof(*pud) * PTRS_PER_PUD); 135 ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD; 136 set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud))); 137 } 138 139 pud = pud_offset(p4d, ppd->vaddr); 140 if (pud_none(*pud)) { 141 pmd = ppd->pgtable_area; 142 memset(pmd, 0, sizeof(*pmd) * PTRS_PER_PMD); 143 ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD; 144 set_pud(pud, __pud(PUD_FLAGS | __pa(pmd))); 145 } 146 147 if (pud_large(*pud)) 148 return NULL; 149 150 return pud; 151 } 152 153 static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd) 154 { 155 pud_t *pud; 156 pmd_t *pmd; 157 158 pud = sme_prepare_pgd(ppd); 159 if (!pud) 160 return; 161 162 pmd = pmd_offset(pud, ppd->vaddr); 163 if (pmd_large(*pmd)) 164 return; 165 166 set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags)); 167 } 168 169 static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd) 170 { 171 pud_t *pud; 172 pmd_t *pmd; 173 pte_t *pte; 174 175 pud = sme_prepare_pgd(ppd); 176 if (!pud) 177 return; 178 179 pmd = pmd_offset(pud, ppd->vaddr); 180 if (pmd_none(*pmd)) { 181 pte = ppd->pgtable_area; 182 memset(pte, 0, sizeof(*pte) * PTRS_PER_PTE); 183 ppd->pgtable_area += sizeof(*pte) * PTRS_PER_PTE; 184 set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte))); 185 } 186 187 if (pmd_large(*pmd)) 188 return; 189 190 pte = pte_offset_map(pmd, ppd->vaddr); 191 if (pte_none(*pte)) 192 set_pte(pte, __pte(ppd->paddr | ppd->pte_flags)); 193 } 194 195 static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd) 196 { 197 while (ppd->vaddr < ppd->vaddr_end) { 198 sme_populate_pgd_large(ppd); 199 200 ppd->vaddr += PMD_PAGE_SIZE; 201 ppd->paddr += PMD_PAGE_SIZE; 202 } 203 } 204 205 static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd) 206 { 207 while (ppd->vaddr < ppd->vaddr_end) { 208 sme_populate_pgd(ppd); 209 210 ppd->vaddr += PAGE_SIZE; 211 ppd->paddr += PAGE_SIZE; 212 } 213 } 214 215 static void __init __sme_map_range(struct sme_populate_pgd_data *ppd, 216 pmdval_t pmd_flags, pteval_t pte_flags) 217 { 218 unsigned long vaddr_end; 219 220 ppd->pmd_flags = pmd_flags; 221 ppd->pte_flags = pte_flags; 222 223 /* Save original end value since we modify the struct value */ 224 vaddr_end = ppd->vaddr_end; 225 226 /* If start is not 2MB aligned, create PTE entries */ 227 ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_PAGE_SIZE); 228 __sme_map_range_pte(ppd); 229 230 /* Create PMD entries */ 231 ppd->vaddr_end = vaddr_end & PMD_PAGE_MASK; 232 __sme_map_range_pmd(ppd); 233 234 /* If end is not 2MB aligned, create PTE entries */ 235 ppd->vaddr_end = vaddr_end; 236 __sme_map_range_pte(ppd); 237 } 238 239 static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd) 240 { 241 __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC); 242 } 243 244 static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd) 245 { 246 __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC); 247 } 248 249 static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd) 250 { 251 __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP); 252 } 253 254 static unsigned long __init sme_pgtable_calc(unsigned long len) 255 { 256 unsigned long entries = 0, tables = 0; 257 258 /* 259 * Perform a relatively simplistic calculation of the pagetable 260 * entries that are needed. Those mappings will be covered mostly 261 * by 2MB PMD entries so we can conservatively calculate the required 262 * number of P4D, PUD and PMD structures needed to perform the 263 * mappings. For mappings that are not 2MB aligned, PTE mappings 264 * would be needed for the start and end portion of the address range 265 * that fall outside of the 2MB alignment. This results in, at most, 266 * two extra pages to hold PTE entries for each range that is mapped. 267 * Incrementing the count for each covers the case where the addresses 268 * cross entries. 269 */ 270 271 /* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */ 272 if (PTRS_PER_P4D > 1) 273 entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D; 274 entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD; 275 entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD; 276 entries += 2 * sizeof(pte_t) * PTRS_PER_PTE; 277 278 /* 279 * Now calculate the added pagetable structures needed to populate 280 * the new pagetables. 281 */ 282 283 if (PTRS_PER_P4D > 1) 284 tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D; 285 tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD; 286 tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD; 287 288 return entries + tables; 289 } 290 291 void __init sme_encrypt_kernel(struct boot_params *bp) 292 { 293 unsigned long workarea_start, workarea_end, workarea_len; 294 unsigned long execute_start, execute_end, execute_len; 295 unsigned long kernel_start, kernel_end, kernel_len; 296 unsigned long initrd_start, initrd_end, initrd_len; 297 struct sme_populate_pgd_data ppd; 298 unsigned long pgtable_area_len; 299 unsigned long decrypted_base; 300 301 /* 302 * This is early code, use an open coded check for SME instead of 303 * using cc_platform_has(). This eliminates worries about removing 304 * instrumentation or checking boot_cpu_data in the cc_platform_has() 305 * function. 306 */ 307 if (!sme_get_me_mask() || sev_status & MSR_AMD64_SEV_ENABLED) 308 return; 309 310 /* 311 * Prepare for encrypting the kernel and initrd by building new 312 * pagetables with the necessary attributes needed to encrypt the 313 * kernel in place. 314 * 315 * One range of virtual addresses will map the memory occupied 316 * by the kernel and initrd as encrypted. 317 * 318 * Another range of virtual addresses will map the memory occupied 319 * by the kernel and initrd as decrypted and write-protected. 320 * 321 * The use of write-protect attribute will prevent any of the 322 * memory from being cached. 323 */ 324 325 /* Physical addresses gives us the identity mapped virtual addresses */ 326 kernel_start = __pa_symbol(_text); 327 kernel_end = ALIGN(__pa_symbol(_end), PMD_PAGE_SIZE); 328 kernel_len = kernel_end - kernel_start; 329 330 initrd_start = 0; 331 initrd_end = 0; 332 initrd_len = 0; 333 #ifdef CONFIG_BLK_DEV_INITRD 334 initrd_len = (unsigned long)bp->hdr.ramdisk_size | 335 ((unsigned long)bp->ext_ramdisk_size << 32); 336 if (initrd_len) { 337 initrd_start = (unsigned long)bp->hdr.ramdisk_image | 338 ((unsigned long)bp->ext_ramdisk_image << 32); 339 initrd_end = PAGE_ALIGN(initrd_start + initrd_len); 340 initrd_len = initrd_end - initrd_start; 341 } 342 #endif 343 344 /* 345 * We're running identity mapped, so we must obtain the address to the 346 * SME encryption workarea using rip-relative addressing. 347 */ 348 asm ("lea sme_workarea(%%rip), %0" 349 : "=r" (workarea_start) 350 : "p" (sme_workarea)); 351 352 /* 353 * Calculate required number of workarea bytes needed: 354 * executable encryption area size: 355 * stack page (PAGE_SIZE) 356 * encryption routine page (PAGE_SIZE) 357 * intermediate copy buffer (PMD_PAGE_SIZE) 358 * pagetable structures for the encryption of the kernel 359 * pagetable structures for workarea (in case not currently mapped) 360 */ 361 execute_start = workarea_start; 362 execute_end = execute_start + (PAGE_SIZE * 2) + PMD_PAGE_SIZE; 363 execute_len = execute_end - execute_start; 364 365 /* 366 * One PGD for both encrypted and decrypted mappings and a set of 367 * PUDs and PMDs for each of the encrypted and decrypted mappings. 368 */ 369 pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD; 370 pgtable_area_len += sme_pgtable_calc(execute_end - kernel_start) * 2; 371 if (initrd_len) 372 pgtable_area_len += sme_pgtable_calc(initrd_len) * 2; 373 374 /* PUDs and PMDs needed in the current pagetables for the workarea */ 375 pgtable_area_len += sme_pgtable_calc(execute_len + pgtable_area_len); 376 377 /* 378 * The total workarea includes the executable encryption area and 379 * the pagetable area. The start of the workarea is already 2MB 380 * aligned, align the end of the workarea on a 2MB boundary so that 381 * we don't try to create/allocate PTE entries from the workarea 382 * before it is mapped. 383 */ 384 workarea_len = execute_len + pgtable_area_len; 385 workarea_end = ALIGN(workarea_start + workarea_len, PMD_PAGE_SIZE); 386 387 /* 388 * Set the address to the start of where newly created pagetable 389 * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable 390 * structures are created when the workarea is added to the current 391 * pagetables and when the new encrypted and decrypted kernel 392 * mappings are populated. 393 */ 394 ppd.pgtable_area = (void *)execute_end; 395 396 /* 397 * Make sure the current pagetable structure has entries for 398 * addressing the workarea. 399 */ 400 ppd.pgd = (pgd_t *)native_read_cr3_pa(); 401 ppd.paddr = workarea_start; 402 ppd.vaddr = workarea_start; 403 ppd.vaddr_end = workarea_end; 404 sme_map_range_decrypted(&ppd); 405 406 /* Flush the TLB - no globals so cr3 is enough */ 407 native_write_cr3(__native_read_cr3()); 408 409 /* 410 * A new pagetable structure is being built to allow for the kernel 411 * and initrd to be encrypted. It starts with an empty PGD that will 412 * then be populated with new PUDs and PMDs as the encrypted and 413 * decrypted kernel mappings are created. 414 */ 415 ppd.pgd = ppd.pgtable_area; 416 memset(ppd.pgd, 0, sizeof(pgd_t) * PTRS_PER_PGD); 417 ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD; 418 419 /* 420 * A different PGD index/entry must be used to get different 421 * pagetable entries for the decrypted mapping. Choose the next 422 * PGD index and convert it to a virtual address to be used as 423 * the base of the mapping. 424 */ 425 decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1); 426 if (initrd_len) { 427 unsigned long check_base; 428 429 check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1); 430 decrypted_base = max(decrypted_base, check_base); 431 } 432 decrypted_base <<= PGDIR_SHIFT; 433 434 /* Add encrypted kernel (identity) mappings */ 435 ppd.paddr = kernel_start; 436 ppd.vaddr = kernel_start; 437 ppd.vaddr_end = kernel_end; 438 sme_map_range_encrypted(&ppd); 439 440 /* Add decrypted, write-protected kernel (non-identity) mappings */ 441 ppd.paddr = kernel_start; 442 ppd.vaddr = kernel_start + decrypted_base; 443 ppd.vaddr_end = kernel_end + decrypted_base; 444 sme_map_range_decrypted_wp(&ppd); 445 446 if (initrd_len) { 447 /* Add encrypted initrd (identity) mappings */ 448 ppd.paddr = initrd_start; 449 ppd.vaddr = initrd_start; 450 ppd.vaddr_end = initrd_end; 451 sme_map_range_encrypted(&ppd); 452 /* 453 * Add decrypted, write-protected initrd (non-identity) mappings 454 */ 455 ppd.paddr = initrd_start; 456 ppd.vaddr = initrd_start + decrypted_base; 457 ppd.vaddr_end = initrd_end + decrypted_base; 458 sme_map_range_decrypted_wp(&ppd); 459 } 460 461 /* Add decrypted workarea mappings to both kernel mappings */ 462 ppd.paddr = workarea_start; 463 ppd.vaddr = workarea_start; 464 ppd.vaddr_end = workarea_end; 465 sme_map_range_decrypted(&ppd); 466 467 ppd.paddr = workarea_start; 468 ppd.vaddr = workarea_start + decrypted_base; 469 ppd.vaddr_end = workarea_end + decrypted_base; 470 sme_map_range_decrypted(&ppd); 471 472 /* Perform the encryption */ 473 sme_encrypt_execute(kernel_start, kernel_start + decrypted_base, 474 kernel_len, workarea_start, (unsigned long)ppd.pgd); 475 476 if (initrd_len) 477 sme_encrypt_execute(initrd_start, initrd_start + decrypted_base, 478 initrd_len, workarea_start, 479 (unsigned long)ppd.pgd); 480 481 /* 482 * At this point we are running encrypted. Remove the mappings for 483 * the decrypted areas - all that is needed for this is to remove 484 * the PGD entry/entries. 485 */ 486 ppd.vaddr = kernel_start + decrypted_base; 487 ppd.vaddr_end = kernel_end + decrypted_base; 488 sme_clear_pgd(&ppd); 489 490 if (initrd_len) { 491 ppd.vaddr = initrd_start + decrypted_base; 492 ppd.vaddr_end = initrd_end + decrypted_base; 493 sme_clear_pgd(&ppd); 494 } 495 496 ppd.vaddr = workarea_start + decrypted_base; 497 ppd.vaddr_end = workarea_end + decrypted_base; 498 sme_clear_pgd(&ppd); 499 500 /* Flush the TLB - no globals so cr3 is enough */ 501 native_write_cr3(__native_read_cr3()); 502 } 503 504 void __init sme_enable(struct boot_params *bp) 505 { 506 const char *cmdline_ptr, *cmdline_arg, *cmdline_on, *cmdline_off; 507 unsigned int eax, ebx, ecx, edx; 508 unsigned long feature_mask; 509 bool active_by_default; 510 unsigned long me_mask; 511 char buffer[16]; 512 u64 msr; 513 514 /* Check for the SME/SEV support leaf */ 515 eax = 0x80000000; 516 ecx = 0; 517 native_cpuid(&eax, &ebx, &ecx, &edx); 518 if (eax < 0x8000001f) 519 return; 520 521 #define AMD_SME_BIT BIT(0) 522 #define AMD_SEV_BIT BIT(1) 523 524 /* 525 * Check for the SME/SEV feature: 526 * CPUID Fn8000_001F[EAX] 527 * - Bit 0 - Secure Memory Encryption support 528 * - Bit 1 - Secure Encrypted Virtualization support 529 * CPUID Fn8000_001F[EBX] 530 * - Bits 5:0 - Pagetable bit position used to indicate encryption 531 */ 532 eax = 0x8000001f; 533 ecx = 0; 534 native_cpuid(&eax, &ebx, &ecx, &edx); 535 /* Check whether SEV or SME is supported */ 536 if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT))) 537 return; 538 539 me_mask = 1UL << (ebx & 0x3f); 540 541 /* Check the SEV MSR whether SEV or SME is enabled */ 542 sev_status = __rdmsr(MSR_AMD64_SEV); 543 feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; 544 545 /* Check if memory encryption is enabled */ 546 if (feature_mask == AMD_SME_BIT) { 547 /* 548 * No SME if Hypervisor bit is set. This check is here to 549 * prevent a guest from trying to enable SME. For running as a 550 * KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there 551 * might be other hypervisors which emulate that MSR as non-zero 552 * or even pass it through to the guest. 553 * A malicious hypervisor can still trick a guest into this 554 * path, but there is no way to protect against that. 555 */ 556 eax = 1; 557 ecx = 0; 558 native_cpuid(&eax, &ebx, &ecx, &edx); 559 if (ecx & BIT(31)) 560 return; 561 562 /* For SME, check the SYSCFG MSR */ 563 msr = __rdmsr(MSR_AMD64_SYSCFG); 564 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 565 return; 566 } else { 567 /* SEV state cannot be controlled by a command line option */ 568 sme_me_mask = me_mask; 569 goto out; 570 } 571 572 /* 573 * Fixups have not been applied to phys_base yet and we're running 574 * identity mapped, so we must obtain the address to the SME command 575 * line argument data using rip-relative addressing. 576 */ 577 asm ("lea sme_cmdline_arg(%%rip), %0" 578 : "=r" (cmdline_arg) 579 : "p" (sme_cmdline_arg)); 580 asm ("lea sme_cmdline_on(%%rip), %0" 581 : "=r" (cmdline_on) 582 : "p" (sme_cmdline_on)); 583 asm ("lea sme_cmdline_off(%%rip), %0" 584 : "=r" (cmdline_off) 585 : "p" (sme_cmdline_off)); 586 587 if (IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT)) 588 active_by_default = true; 589 else 590 active_by_default = false; 591 592 cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr | 593 ((u64)bp->ext_cmd_line_ptr << 32)); 594 595 cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)); 596 597 if (!strncmp(buffer, cmdline_on, sizeof(buffer))) 598 sme_me_mask = me_mask; 599 else if (!strncmp(buffer, cmdline_off, sizeof(buffer))) 600 sme_me_mask = 0; 601 else 602 sme_me_mask = active_by_default ? me_mask : 0; 603 out: 604 if (sme_me_mask) { 605 physical_mask &= ~sme_me_mask; 606 cc_set_vendor(CC_VENDOR_AMD); 607 cc_set_mask(sme_me_mask); 608 } 609 } 610