1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <linux/module.h> 26 #include <asm/kvm_emulate.h> 27 28 #include "x86.h" 29 #include "tss.h" 30 31 /* 32 * Operand types 33 */ 34 #define OpNone 0ull 35 #define OpImplicit 1ull /* No generic decode */ 36 #define OpReg 2ull /* Register */ 37 #define OpMem 3ull /* Memory */ 38 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 39 #define OpDI 5ull /* ES:DI/EDI/RDI */ 40 #define OpMem64 6ull /* Memory, 64-bit */ 41 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 42 #define OpDX 8ull /* DX register */ 43 #define OpCL 9ull /* CL register (for shifts) */ 44 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 45 #define OpOne 11ull /* Implied 1 */ 46 #define OpImm 12ull /* Sign extended immediate */ 47 #define OpMem16 13ull /* Memory operand (16-bit). */ 48 #define OpMem32 14ull /* Memory operand (32-bit). */ 49 #define OpImmU 15ull /* Immediate operand, zero extended */ 50 #define OpSI 16ull /* SI/ESI/RSI */ 51 #define OpImmFAddr 17ull /* Immediate far address */ 52 #define OpMemFAddr 18ull /* Far address in memory */ 53 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 54 #define OpES 20ull /* ES */ 55 #define OpCS 21ull /* CS */ 56 #define OpSS 22ull /* SS */ 57 #define OpDS 23ull /* DS */ 58 #define OpFS 24ull /* FS */ 59 #define OpGS 25ull /* GS */ 60 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 61 62 #define OpBits 5 /* Width of operand field */ 63 #define OpMask ((1ull << OpBits) - 1) 64 65 /* 66 * Opcode effective-address decode tables. 67 * Note that we only emulate instructions that have at least one memory 68 * operand (excluding implicit stack references). We assume that stack 69 * references and instruction fetches will never occur in special memory 70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 71 * not be handled. 72 */ 73 74 /* Operand sizes: 8-bit operands or specified/overridden size. */ 75 #define ByteOp (1<<0) /* 8-bit operands. */ 76 /* Destination operand type. */ 77 #define DstShift 1 78 #define ImplicitOps (OpImplicit << DstShift) 79 #define DstReg (OpReg << DstShift) 80 #define DstMem (OpMem << DstShift) 81 #define DstAcc (OpAcc << DstShift) 82 #define DstDI (OpDI << DstShift) 83 #define DstMem64 (OpMem64 << DstShift) 84 #define DstImmUByte (OpImmUByte << DstShift) 85 #define DstDX (OpDX << DstShift) 86 #define DstMask (OpMask << DstShift) 87 /* Source operand type. */ 88 #define SrcShift 6 89 #define SrcNone (OpNone << SrcShift) 90 #define SrcReg (OpReg << SrcShift) 91 #define SrcMem (OpMem << SrcShift) 92 #define SrcMem16 (OpMem16 << SrcShift) 93 #define SrcMem32 (OpMem32 << SrcShift) 94 #define SrcImm (OpImm << SrcShift) 95 #define SrcImmByte (OpImmByte << SrcShift) 96 #define SrcOne (OpOne << SrcShift) 97 #define SrcImmUByte (OpImmUByte << SrcShift) 98 #define SrcImmU (OpImmU << SrcShift) 99 #define SrcSI (OpSI << SrcShift) 100 #define SrcImmFAddr (OpImmFAddr << SrcShift) 101 #define SrcMemFAddr (OpMemFAddr << SrcShift) 102 #define SrcAcc (OpAcc << SrcShift) 103 #define SrcImmU16 (OpImmU16 << SrcShift) 104 #define SrcDX (OpDX << SrcShift) 105 #define SrcMem8 (OpMem8 << SrcShift) 106 #define SrcMask (OpMask << SrcShift) 107 #define BitOp (1<<11) 108 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 109 #define String (1<<13) /* String instruction (rep capable) */ 110 #define Stack (1<<14) /* Stack instruction (push/pop) */ 111 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 112 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 113 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 114 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 115 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 116 #define Sse (1<<18) /* SSE Vector instruction */ 117 /* Generic ModRM decode. */ 118 #define ModRM (1<<19) 119 /* Destination is only written; never read. */ 120 #define Mov (1<<20) 121 /* Misc flags */ 122 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 123 #define VendorSpecific (1<<22) /* Vendor specific instruction */ 124 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 125 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 126 #define Undefined (1<<25) /* No Such Instruction */ 127 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 128 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 129 #define No64 (1<<28) 130 #define PageTable (1 << 29) /* instruction used to write page table */ 131 /* Source 2 operand type */ 132 #define Src2Shift (30) 133 #define Src2None (OpNone << Src2Shift) 134 #define Src2CL (OpCL << Src2Shift) 135 #define Src2ImmByte (OpImmByte << Src2Shift) 136 #define Src2One (OpOne << Src2Shift) 137 #define Src2Imm (OpImm << Src2Shift) 138 #define Src2ES (OpES << Src2Shift) 139 #define Src2CS (OpCS << Src2Shift) 140 #define Src2SS (OpSS << Src2Shift) 141 #define Src2DS (OpDS << Src2Shift) 142 #define Src2FS (OpFS << Src2Shift) 143 #define Src2GS (OpGS << Src2Shift) 144 #define Src2Mask (OpMask << Src2Shift) 145 146 #define X2(x...) x, x 147 #define X3(x...) X2(x), x 148 #define X4(x...) X2(x), X2(x) 149 #define X5(x...) X4(x), x 150 #define X6(x...) X4(x), X2(x) 151 #define X7(x...) X4(x), X3(x) 152 #define X8(x...) X4(x), X4(x) 153 #define X16(x...) X8(x), X8(x) 154 155 struct opcode { 156 u64 flags : 56; 157 u64 intercept : 8; 158 union { 159 int (*execute)(struct x86_emulate_ctxt *ctxt); 160 struct opcode *group; 161 struct group_dual *gdual; 162 struct gprefix *gprefix; 163 } u; 164 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 165 }; 166 167 struct group_dual { 168 struct opcode mod012[8]; 169 struct opcode mod3[8]; 170 }; 171 172 struct gprefix { 173 struct opcode pfx_no; 174 struct opcode pfx_66; 175 struct opcode pfx_f2; 176 struct opcode pfx_f3; 177 }; 178 179 /* EFLAGS bit definitions. */ 180 #define EFLG_ID (1<<21) 181 #define EFLG_VIP (1<<20) 182 #define EFLG_VIF (1<<19) 183 #define EFLG_AC (1<<18) 184 #define EFLG_VM (1<<17) 185 #define EFLG_RF (1<<16) 186 #define EFLG_IOPL (3<<12) 187 #define EFLG_NT (1<<14) 188 #define EFLG_OF (1<<11) 189 #define EFLG_DF (1<<10) 190 #define EFLG_IF (1<<9) 191 #define EFLG_TF (1<<8) 192 #define EFLG_SF (1<<7) 193 #define EFLG_ZF (1<<6) 194 #define EFLG_AF (1<<4) 195 #define EFLG_PF (1<<2) 196 #define EFLG_CF (1<<0) 197 198 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 199 #define EFLG_RESERVED_ONE_MASK 2 200 201 /* 202 * Instruction emulation: 203 * Most instructions are emulated directly via a fragment of inline assembly 204 * code. This allows us to save/restore EFLAGS and thus very easily pick up 205 * any modified flags. 206 */ 207 208 #if defined(CONFIG_X86_64) 209 #define _LO32 "k" /* force 32-bit operand */ 210 #define _STK "%%rsp" /* stack pointer */ 211 #elif defined(__i386__) 212 #define _LO32 "" /* force 32-bit operand */ 213 #define _STK "%%esp" /* stack pointer */ 214 #endif 215 216 /* 217 * These EFLAGS bits are restored from saved value during emulation, and 218 * any changes are written back to the saved value after emulation. 219 */ 220 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) 221 222 /* Before executing instruction: restore necessary bits in EFLAGS. */ 223 #define _PRE_EFLAGS(_sav, _msk, _tmp) \ 224 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ 225 "movl %"_sav",%"_LO32 _tmp"; " \ 226 "push %"_tmp"; " \ 227 "push %"_tmp"; " \ 228 "movl %"_msk",%"_LO32 _tmp"; " \ 229 "andl %"_LO32 _tmp",("_STK"); " \ 230 "pushf; " \ 231 "notl %"_LO32 _tmp"; " \ 232 "andl %"_LO32 _tmp",("_STK"); " \ 233 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ 234 "pop %"_tmp"; " \ 235 "orl %"_LO32 _tmp",("_STK"); " \ 236 "popf; " \ 237 "pop %"_sav"; " 238 239 /* After executing instruction: write-back necessary bits in EFLAGS. */ 240 #define _POST_EFLAGS(_sav, _msk, _tmp) \ 241 /* _sav |= EFLAGS & _msk; */ \ 242 "pushf; " \ 243 "pop %"_tmp"; " \ 244 "andl %"_msk",%"_LO32 _tmp"; " \ 245 "orl %"_LO32 _tmp",%"_sav"; " 246 247 #ifdef CONFIG_X86_64 248 #define ON64(x) x 249 #else 250 #define ON64(x) 251 #endif 252 253 #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ 254 do { \ 255 __asm__ __volatile__ ( \ 256 _PRE_EFLAGS("0", "4", "2") \ 257 _op _suffix " %"_x"3,%1; " \ 258 _POST_EFLAGS("0", "4", "2") \ 259 : "=m" ((ctxt)->eflags), \ 260 "+q" (*(_dsttype*)&(ctxt)->dst.val), \ 261 "=&r" (_tmp) \ 262 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ 263 } while (0) 264 265 266 /* Raw emulation: instruction has two explicit operands. */ 267 #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ 268 do { \ 269 unsigned long _tmp; \ 270 \ 271 switch ((ctxt)->dst.bytes) { \ 272 case 2: \ 273 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ 274 break; \ 275 case 4: \ 276 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ 277 break; \ 278 case 8: \ 279 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ 280 break; \ 281 } \ 282 } while (0) 283 284 #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ 285 do { \ 286 unsigned long _tmp; \ 287 switch ((ctxt)->dst.bytes) { \ 288 case 1: \ 289 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ 290 break; \ 291 default: \ 292 __emulate_2op_nobyte(ctxt, _op, \ 293 _wx, _wy, _lx, _ly, _qx, _qy); \ 294 break; \ 295 } \ 296 } while (0) 297 298 /* Source operand is byte-sized and may be restricted to just %cl. */ 299 #define emulate_2op_SrcB(ctxt, _op) \ 300 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") 301 302 /* Source operand is byte, word, long or quad sized. */ 303 #define emulate_2op_SrcV(ctxt, _op) \ 304 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") 305 306 /* Source operand is word, long or quad sized. */ 307 #define emulate_2op_SrcV_nobyte(ctxt, _op) \ 308 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") 309 310 /* Instruction has three operands and one operand is stored in ECX register */ 311 #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ 312 do { \ 313 unsigned long _tmp; \ 314 _type _clv = (ctxt)->src2.val; \ 315 _type _srcv = (ctxt)->src.val; \ 316 _type _dstv = (ctxt)->dst.val; \ 317 \ 318 __asm__ __volatile__ ( \ 319 _PRE_EFLAGS("0", "5", "2") \ 320 _op _suffix " %4,%1 \n" \ 321 _POST_EFLAGS("0", "5", "2") \ 322 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ 323 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ 324 ); \ 325 \ 326 (ctxt)->src2.val = (unsigned long) _clv; \ 327 (ctxt)->src2.val = (unsigned long) _srcv; \ 328 (ctxt)->dst.val = (unsigned long) _dstv; \ 329 } while (0) 330 331 #define emulate_2op_cl(ctxt, _op) \ 332 do { \ 333 switch ((ctxt)->dst.bytes) { \ 334 case 2: \ 335 __emulate_2op_cl(ctxt, _op, "w", u16); \ 336 break; \ 337 case 4: \ 338 __emulate_2op_cl(ctxt, _op, "l", u32); \ 339 break; \ 340 case 8: \ 341 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ 342 break; \ 343 } \ 344 } while (0) 345 346 #define __emulate_1op(ctxt, _op, _suffix) \ 347 do { \ 348 unsigned long _tmp; \ 349 \ 350 __asm__ __volatile__ ( \ 351 _PRE_EFLAGS("0", "3", "2") \ 352 _op _suffix " %1; " \ 353 _POST_EFLAGS("0", "3", "2") \ 354 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ 355 "=&r" (_tmp) \ 356 : "i" (EFLAGS_MASK)); \ 357 } while (0) 358 359 /* Instruction has only one explicit operand (no source operand). */ 360 #define emulate_1op(ctxt, _op) \ 361 do { \ 362 switch ((ctxt)->dst.bytes) { \ 363 case 1: __emulate_1op(ctxt, _op, "b"); break; \ 364 case 2: __emulate_1op(ctxt, _op, "w"); break; \ 365 case 4: __emulate_1op(ctxt, _op, "l"); break; \ 366 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ 367 } \ 368 } while (0) 369 370 #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ 371 do { \ 372 unsigned long _tmp; \ 373 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \ 374 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \ 375 \ 376 __asm__ __volatile__ ( \ 377 _PRE_EFLAGS("0", "5", "1") \ 378 "1: \n\t" \ 379 _op _suffix " %6; " \ 380 "2: \n\t" \ 381 _POST_EFLAGS("0", "5", "1") \ 382 ".pushsection .fixup,\"ax\" \n\t" \ 383 "3: movb $1, %4 \n\t" \ 384 "jmp 2b \n\t" \ 385 ".popsection \n\t" \ 386 _ASM_EXTABLE(1b, 3b) \ 387 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ 388 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ 389 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ 390 "a" (*rax), "d" (*rdx)); \ 391 } while (0) 392 393 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ 394 #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ 395 do { \ 396 switch((ctxt)->src.bytes) { \ 397 case 1: \ 398 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ 399 break; \ 400 case 2: \ 401 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ 402 break; \ 403 case 4: \ 404 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ 405 break; \ 406 case 8: ON64( \ 407 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ 408 break; \ 409 } \ 410 } while (0) 411 412 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 413 enum x86_intercept intercept, 414 enum x86_intercept_stage stage) 415 { 416 struct x86_instruction_info info = { 417 .intercept = intercept, 418 .rep_prefix = ctxt->rep_prefix, 419 .modrm_mod = ctxt->modrm_mod, 420 .modrm_reg = ctxt->modrm_reg, 421 .modrm_rm = ctxt->modrm_rm, 422 .src_val = ctxt->src.val64, 423 .src_bytes = ctxt->src.bytes, 424 .dst_bytes = ctxt->dst.bytes, 425 .ad_bytes = ctxt->ad_bytes, 426 .next_rip = ctxt->eip, 427 }; 428 429 return ctxt->ops->intercept(ctxt, &info, stage); 430 } 431 432 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 433 { 434 return (1UL << (ctxt->ad_bytes << 3)) - 1; 435 } 436 437 /* Access/update address held in a register, based on addressing mode. */ 438 static inline unsigned long 439 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 440 { 441 if (ctxt->ad_bytes == sizeof(unsigned long)) 442 return reg; 443 else 444 return reg & ad_mask(ctxt); 445 } 446 447 static inline unsigned long 448 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) 449 { 450 return address_mask(ctxt, reg); 451 } 452 453 static inline void 454 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) 455 { 456 if (ctxt->ad_bytes == sizeof(unsigned long)) 457 *reg += inc; 458 else 459 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); 460 } 461 462 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 463 { 464 register_address_increment(ctxt, &ctxt->_eip, rel); 465 } 466 467 static u32 desc_limit_scaled(struct desc_struct *desc) 468 { 469 u32 limit = get_desc_limit(desc); 470 471 return desc->g ? (limit << 12) | 0xfff : limit; 472 } 473 474 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) 475 { 476 ctxt->has_seg_override = true; 477 ctxt->seg_override = seg; 478 } 479 480 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 481 { 482 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 483 return 0; 484 485 return ctxt->ops->get_cached_segment_base(ctxt, seg); 486 } 487 488 static unsigned seg_override(struct x86_emulate_ctxt *ctxt) 489 { 490 if (!ctxt->has_seg_override) 491 return 0; 492 493 return ctxt->seg_override; 494 } 495 496 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 497 u32 error, bool valid) 498 { 499 ctxt->exception.vector = vec; 500 ctxt->exception.error_code = error; 501 ctxt->exception.error_code_valid = valid; 502 return X86EMUL_PROPAGATE_FAULT; 503 } 504 505 static int emulate_db(struct x86_emulate_ctxt *ctxt) 506 { 507 return emulate_exception(ctxt, DB_VECTOR, 0, false); 508 } 509 510 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 511 { 512 return emulate_exception(ctxt, GP_VECTOR, err, true); 513 } 514 515 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 516 { 517 return emulate_exception(ctxt, SS_VECTOR, err, true); 518 } 519 520 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 521 { 522 return emulate_exception(ctxt, UD_VECTOR, 0, false); 523 } 524 525 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 526 { 527 return emulate_exception(ctxt, TS_VECTOR, err, true); 528 } 529 530 static int emulate_de(struct x86_emulate_ctxt *ctxt) 531 { 532 return emulate_exception(ctxt, DE_VECTOR, 0, false); 533 } 534 535 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 536 { 537 return emulate_exception(ctxt, NM_VECTOR, 0, false); 538 } 539 540 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 541 { 542 u16 selector; 543 struct desc_struct desc; 544 545 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 546 return selector; 547 } 548 549 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 550 unsigned seg) 551 { 552 u16 dummy; 553 u32 base3; 554 struct desc_struct desc; 555 556 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 557 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 558 } 559 560 static int __linearize(struct x86_emulate_ctxt *ctxt, 561 struct segmented_address addr, 562 unsigned size, bool write, bool fetch, 563 ulong *linear) 564 { 565 struct desc_struct desc; 566 bool usable; 567 ulong la; 568 u32 lim; 569 u16 sel; 570 unsigned cpl, rpl; 571 572 la = seg_base(ctxt, addr.seg) + addr.ea; 573 switch (ctxt->mode) { 574 case X86EMUL_MODE_REAL: 575 break; 576 case X86EMUL_MODE_PROT64: 577 if (((signed long)la << 16) >> 16 != la) 578 return emulate_gp(ctxt, 0); 579 break; 580 default: 581 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 582 addr.seg); 583 if (!usable) 584 goto bad; 585 /* code segment or read-only data segment */ 586 if (((desc.type & 8) || !(desc.type & 2)) && write) 587 goto bad; 588 /* unreadable code segment */ 589 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 590 goto bad; 591 lim = desc_limit_scaled(&desc); 592 if ((desc.type & 8) || !(desc.type & 4)) { 593 /* expand-up segment */ 594 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 595 goto bad; 596 } else { 597 /* exapand-down segment */ 598 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) 599 goto bad; 600 lim = desc.d ? 0xffffffff : 0xffff; 601 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 602 goto bad; 603 } 604 cpl = ctxt->ops->cpl(ctxt); 605 rpl = sel & 3; 606 cpl = max(cpl, rpl); 607 if (!(desc.type & 8)) { 608 /* data segment */ 609 if (cpl > desc.dpl) 610 goto bad; 611 } else if ((desc.type & 8) && !(desc.type & 4)) { 612 /* nonconforming code segment */ 613 if (cpl != desc.dpl) 614 goto bad; 615 } else if ((desc.type & 8) && (desc.type & 4)) { 616 /* conforming code segment */ 617 if (cpl < desc.dpl) 618 goto bad; 619 } 620 break; 621 } 622 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) 623 la &= (u32)-1; 624 *linear = la; 625 return X86EMUL_CONTINUE; 626 bad: 627 if (addr.seg == VCPU_SREG_SS) 628 return emulate_ss(ctxt, addr.seg); 629 else 630 return emulate_gp(ctxt, addr.seg); 631 } 632 633 static int linearize(struct x86_emulate_ctxt *ctxt, 634 struct segmented_address addr, 635 unsigned size, bool write, 636 ulong *linear) 637 { 638 return __linearize(ctxt, addr, size, write, false, linear); 639 } 640 641 642 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 643 struct segmented_address addr, 644 void *data, 645 unsigned size) 646 { 647 int rc; 648 ulong linear; 649 650 rc = linearize(ctxt, addr, size, false, &linear); 651 if (rc != X86EMUL_CONTINUE) 652 return rc; 653 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 654 } 655 656 /* 657 * Fetch the next byte of the instruction being emulated which is pointed to 658 * by ctxt->_eip, then increment ctxt->_eip. 659 * 660 * Also prefetch the remaining bytes of the instruction without crossing page 661 * boundary if they are not in fetch_cache yet. 662 */ 663 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) 664 { 665 struct fetch_cache *fc = &ctxt->fetch; 666 int rc; 667 int size, cur_size; 668 669 if (ctxt->_eip == fc->end) { 670 unsigned long linear; 671 struct segmented_address addr = { .seg = VCPU_SREG_CS, 672 .ea = ctxt->_eip }; 673 cur_size = fc->end - fc->start; 674 size = min(15UL - cur_size, 675 PAGE_SIZE - offset_in_page(ctxt->_eip)); 676 rc = __linearize(ctxt, addr, size, false, true, &linear); 677 if (unlikely(rc != X86EMUL_CONTINUE)) 678 return rc; 679 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, 680 size, &ctxt->exception); 681 if (unlikely(rc != X86EMUL_CONTINUE)) 682 return rc; 683 fc->end += size; 684 } 685 *dest = fc->data[ctxt->_eip - fc->start]; 686 ctxt->_eip++; 687 return X86EMUL_CONTINUE; 688 } 689 690 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, 691 void *dest, unsigned size) 692 { 693 int rc; 694 695 /* x86 instructions are limited to 15 bytes. */ 696 if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) 697 return X86EMUL_UNHANDLEABLE; 698 while (size--) { 699 rc = do_insn_fetch_byte(ctxt, dest++); 700 if (rc != X86EMUL_CONTINUE) 701 return rc; 702 } 703 return X86EMUL_CONTINUE; 704 } 705 706 /* Fetch next part of the instruction being emulated. */ 707 #define insn_fetch(_type, _ctxt) \ 708 ({ unsigned long _x; \ 709 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ 710 if (rc != X86EMUL_CONTINUE) \ 711 goto done; \ 712 (_type)_x; \ 713 }) 714 715 #define insn_fetch_arr(_arr, _size, _ctxt) \ 716 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ 717 if (rc != X86EMUL_CONTINUE) \ 718 goto done; \ 719 }) 720 721 /* 722 * Given the 'reg' portion of a ModRM byte, and a register block, return a 723 * pointer into the block that addresses the relevant register. 724 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 725 */ 726 static void *decode_register(u8 modrm_reg, unsigned long *regs, 727 int highbyte_regs) 728 { 729 void *p; 730 731 p = ®s[modrm_reg]; 732 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 733 p = (unsigned char *)®s[modrm_reg & 3] + 1; 734 return p; 735 } 736 737 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 738 struct segmented_address addr, 739 u16 *size, unsigned long *address, int op_bytes) 740 { 741 int rc; 742 743 if (op_bytes == 2) 744 op_bytes = 3; 745 *address = 0; 746 rc = segmented_read_std(ctxt, addr, size, 2); 747 if (rc != X86EMUL_CONTINUE) 748 return rc; 749 addr.ea += 2; 750 rc = segmented_read_std(ctxt, addr, address, op_bytes); 751 return rc; 752 } 753 754 static int test_cc(unsigned int condition, unsigned int flags) 755 { 756 int rc = 0; 757 758 switch ((condition & 15) >> 1) { 759 case 0: /* o */ 760 rc |= (flags & EFLG_OF); 761 break; 762 case 1: /* b/c/nae */ 763 rc |= (flags & EFLG_CF); 764 break; 765 case 2: /* z/e */ 766 rc |= (flags & EFLG_ZF); 767 break; 768 case 3: /* be/na */ 769 rc |= (flags & (EFLG_CF|EFLG_ZF)); 770 break; 771 case 4: /* s */ 772 rc |= (flags & EFLG_SF); 773 break; 774 case 5: /* p/pe */ 775 rc |= (flags & EFLG_PF); 776 break; 777 case 7: /* le/ng */ 778 rc |= (flags & EFLG_ZF); 779 /* fall through */ 780 case 6: /* l/nge */ 781 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); 782 break; 783 } 784 785 /* Odd condition identifiers (lsb == 1) have inverted sense. */ 786 return (!!rc ^ (condition & 1)); 787 } 788 789 static void fetch_register_operand(struct operand *op) 790 { 791 switch (op->bytes) { 792 case 1: 793 op->val = *(u8 *)op->addr.reg; 794 break; 795 case 2: 796 op->val = *(u16 *)op->addr.reg; 797 break; 798 case 4: 799 op->val = *(u32 *)op->addr.reg; 800 break; 801 case 8: 802 op->val = *(u64 *)op->addr.reg; 803 break; 804 } 805 } 806 807 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 808 { 809 ctxt->ops->get_fpu(ctxt); 810 switch (reg) { 811 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; 812 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; 813 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; 814 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; 815 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; 816 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; 817 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; 818 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; 819 #ifdef CONFIG_X86_64 820 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; 821 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; 822 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; 823 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; 824 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; 825 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; 826 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; 827 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; 828 #endif 829 default: BUG(); 830 } 831 ctxt->ops->put_fpu(ctxt); 832 } 833 834 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 835 int reg) 836 { 837 ctxt->ops->get_fpu(ctxt); 838 switch (reg) { 839 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; 840 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; 841 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; 842 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; 843 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; 844 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; 845 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; 846 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; 847 #ifdef CONFIG_X86_64 848 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; 849 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; 850 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; 851 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; 852 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; 853 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; 854 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; 855 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; 856 #endif 857 default: BUG(); 858 } 859 ctxt->ops->put_fpu(ctxt); 860 } 861 862 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 863 struct operand *op) 864 { 865 unsigned reg = ctxt->modrm_reg; 866 int highbyte_regs = ctxt->rex_prefix == 0; 867 868 if (!(ctxt->d & ModRM)) 869 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 870 871 if (ctxt->d & Sse) { 872 op->type = OP_XMM; 873 op->bytes = 16; 874 op->addr.xmm = reg; 875 read_sse_reg(ctxt, &op->vec_val, reg); 876 return; 877 } 878 879 op->type = OP_REG; 880 if (ctxt->d & ByteOp) { 881 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs); 882 op->bytes = 1; 883 } else { 884 op->addr.reg = decode_register(reg, ctxt->regs, 0); 885 op->bytes = ctxt->op_bytes; 886 } 887 fetch_register_operand(op); 888 op->orig_val = op->val; 889 } 890 891 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 892 struct operand *op) 893 { 894 u8 sib; 895 int index_reg = 0, base_reg = 0, scale; 896 int rc = X86EMUL_CONTINUE; 897 ulong modrm_ea = 0; 898 899 if (ctxt->rex_prefix) { 900 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ 901 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ 902 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ 903 } 904 905 ctxt->modrm = insn_fetch(u8, ctxt); 906 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; 907 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 908 ctxt->modrm_rm |= (ctxt->modrm & 0x07); 909 ctxt->modrm_seg = VCPU_SREG_DS; 910 911 if (ctxt->modrm_mod == 3) { 912 op->type = OP_REG; 913 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 914 op->addr.reg = decode_register(ctxt->modrm_rm, 915 ctxt->regs, ctxt->d & ByteOp); 916 if (ctxt->d & Sse) { 917 op->type = OP_XMM; 918 op->bytes = 16; 919 op->addr.xmm = ctxt->modrm_rm; 920 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 921 return rc; 922 } 923 fetch_register_operand(op); 924 return rc; 925 } 926 927 op->type = OP_MEM; 928 929 if (ctxt->ad_bytes == 2) { 930 unsigned bx = ctxt->regs[VCPU_REGS_RBX]; 931 unsigned bp = ctxt->regs[VCPU_REGS_RBP]; 932 unsigned si = ctxt->regs[VCPU_REGS_RSI]; 933 unsigned di = ctxt->regs[VCPU_REGS_RDI]; 934 935 /* 16-bit ModR/M decode. */ 936 switch (ctxt->modrm_mod) { 937 case 0: 938 if (ctxt->modrm_rm == 6) 939 modrm_ea += insn_fetch(u16, ctxt); 940 break; 941 case 1: 942 modrm_ea += insn_fetch(s8, ctxt); 943 break; 944 case 2: 945 modrm_ea += insn_fetch(u16, ctxt); 946 break; 947 } 948 switch (ctxt->modrm_rm) { 949 case 0: 950 modrm_ea += bx + si; 951 break; 952 case 1: 953 modrm_ea += bx + di; 954 break; 955 case 2: 956 modrm_ea += bp + si; 957 break; 958 case 3: 959 modrm_ea += bp + di; 960 break; 961 case 4: 962 modrm_ea += si; 963 break; 964 case 5: 965 modrm_ea += di; 966 break; 967 case 6: 968 if (ctxt->modrm_mod != 0) 969 modrm_ea += bp; 970 break; 971 case 7: 972 modrm_ea += bx; 973 break; 974 } 975 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 976 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 977 ctxt->modrm_seg = VCPU_SREG_SS; 978 modrm_ea = (u16)modrm_ea; 979 } else { 980 /* 32/64-bit ModR/M decode. */ 981 if ((ctxt->modrm_rm & 7) == 4) { 982 sib = insn_fetch(u8, ctxt); 983 index_reg |= (sib >> 3) & 7; 984 base_reg |= sib & 7; 985 scale = sib >> 6; 986 987 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 988 modrm_ea += insn_fetch(s32, ctxt); 989 else 990 modrm_ea += ctxt->regs[base_reg]; 991 if (index_reg != 4) 992 modrm_ea += ctxt->regs[index_reg] << scale; 993 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 994 if (ctxt->mode == X86EMUL_MODE_PROT64) 995 ctxt->rip_relative = 1; 996 } else 997 modrm_ea += ctxt->regs[ctxt->modrm_rm]; 998 switch (ctxt->modrm_mod) { 999 case 0: 1000 if (ctxt->modrm_rm == 5) 1001 modrm_ea += insn_fetch(s32, ctxt); 1002 break; 1003 case 1: 1004 modrm_ea += insn_fetch(s8, ctxt); 1005 break; 1006 case 2: 1007 modrm_ea += insn_fetch(s32, ctxt); 1008 break; 1009 } 1010 } 1011 op->addr.mem.ea = modrm_ea; 1012 done: 1013 return rc; 1014 } 1015 1016 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1017 struct operand *op) 1018 { 1019 int rc = X86EMUL_CONTINUE; 1020 1021 op->type = OP_MEM; 1022 switch (ctxt->ad_bytes) { 1023 case 2: 1024 op->addr.mem.ea = insn_fetch(u16, ctxt); 1025 break; 1026 case 4: 1027 op->addr.mem.ea = insn_fetch(u32, ctxt); 1028 break; 1029 case 8: 1030 op->addr.mem.ea = insn_fetch(u64, ctxt); 1031 break; 1032 } 1033 done: 1034 return rc; 1035 } 1036 1037 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1038 { 1039 long sv = 0, mask; 1040 1041 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1042 mask = ~(ctxt->dst.bytes * 8 - 1); 1043 1044 if (ctxt->src.bytes == 2) 1045 sv = (s16)ctxt->src.val & (s16)mask; 1046 else if (ctxt->src.bytes == 4) 1047 sv = (s32)ctxt->src.val & (s32)mask; 1048 1049 ctxt->dst.addr.mem.ea += (sv >> 3); 1050 } 1051 1052 /* only subword offset */ 1053 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1054 } 1055 1056 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1057 unsigned long addr, void *dest, unsigned size) 1058 { 1059 int rc; 1060 struct read_cache *mc = &ctxt->mem_read; 1061 1062 while (size) { 1063 int n = min(size, 8u); 1064 size -= n; 1065 if (mc->pos < mc->end) 1066 goto read_cached; 1067 1068 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n, 1069 &ctxt->exception); 1070 if (rc != X86EMUL_CONTINUE) 1071 return rc; 1072 mc->end += n; 1073 1074 read_cached: 1075 memcpy(dest, mc->data + mc->pos, n); 1076 mc->pos += n; 1077 dest += n; 1078 addr += n; 1079 } 1080 return X86EMUL_CONTINUE; 1081 } 1082 1083 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1084 struct segmented_address addr, 1085 void *data, 1086 unsigned size) 1087 { 1088 int rc; 1089 ulong linear; 1090 1091 rc = linearize(ctxt, addr, size, false, &linear); 1092 if (rc != X86EMUL_CONTINUE) 1093 return rc; 1094 return read_emulated(ctxt, linear, data, size); 1095 } 1096 1097 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1098 struct segmented_address addr, 1099 const void *data, 1100 unsigned size) 1101 { 1102 int rc; 1103 ulong linear; 1104 1105 rc = linearize(ctxt, addr, size, true, &linear); 1106 if (rc != X86EMUL_CONTINUE) 1107 return rc; 1108 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1109 &ctxt->exception); 1110 } 1111 1112 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1113 struct segmented_address addr, 1114 const void *orig_data, const void *data, 1115 unsigned size) 1116 { 1117 int rc; 1118 ulong linear; 1119 1120 rc = linearize(ctxt, addr, size, true, &linear); 1121 if (rc != X86EMUL_CONTINUE) 1122 return rc; 1123 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1124 size, &ctxt->exception); 1125 } 1126 1127 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1128 unsigned int size, unsigned short port, 1129 void *dest) 1130 { 1131 struct read_cache *rc = &ctxt->io_read; 1132 1133 if (rc->pos == rc->end) { /* refill pio read ahead */ 1134 unsigned int in_page, n; 1135 unsigned int count = ctxt->rep_prefix ? 1136 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1; 1137 in_page = (ctxt->eflags & EFLG_DF) ? 1138 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) : 1139 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]); 1140 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, 1141 count); 1142 if (n == 0) 1143 n = 1; 1144 rc->pos = rc->end = 0; 1145 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1146 return 0; 1147 rc->end = n * size; 1148 } 1149 1150 memcpy(dest, rc->data + rc->pos, size); 1151 rc->pos += size; 1152 return 1; 1153 } 1154 1155 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1156 u16 index, struct desc_struct *desc) 1157 { 1158 struct desc_ptr dt; 1159 ulong addr; 1160 1161 ctxt->ops->get_idt(ctxt, &dt); 1162 1163 if (dt.size < index * 8 + 7) 1164 return emulate_gp(ctxt, index << 3 | 0x2); 1165 1166 addr = dt.address + index * 8; 1167 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1168 &ctxt->exception); 1169 } 1170 1171 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1172 u16 selector, struct desc_ptr *dt) 1173 { 1174 struct x86_emulate_ops *ops = ctxt->ops; 1175 1176 if (selector & 1 << 2) { 1177 struct desc_struct desc; 1178 u16 sel; 1179 1180 memset (dt, 0, sizeof *dt); 1181 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) 1182 return; 1183 1184 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1185 dt->address = get_desc_base(&desc); 1186 } else 1187 ops->get_gdt(ctxt, dt); 1188 } 1189 1190 /* allowed just for 8 bytes segments */ 1191 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1192 u16 selector, struct desc_struct *desc) 1193 { 1194 struct desc_ptr dt; 1195 u16 index = selector >> 3; 1196 ulong addr; 1197 1198 get_descriptor_table_ptr(ctxt, selector, &dt); 1199 1200 if (dt.size < index * 8 + 7) 1201 return emulate_gp(ctxt, selector & 0xfffc); 1202 1203 addr = dt.address + index * 8; 1204 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1205 &ctxt->exception); 1206 } 1207 1208 /* allowed just for 8 bytes segments */ 1209 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1210 u16 selector, struct desc_struct *desc) 1211 { 1212 struct desc_ptr dt; 1213 u16 index = selector >> 3; 1214 ulong addr; 1215 1216 get_descriptor_table_ptr(ctxt, selector, &dt); 1217 1218 if (dt.size < index * 8 + 7) 1219 return emulate_gp(ctxt, selector & 0xfffc); 1220 1221 addr = dt.address + index * 8; 1222 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1223 &ctxt->exception); 1224 } 1225 1226 /* Does not support long mode */ 1227 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1228 u16 selector, int seg) 1229 { 1230 struct desc_struct seg_desc; 1231 u8 dpl, rpl, cpl; 1232 unsigned err_vec = GP_VECTOR; 1233 u32 err_code = 0; 1234 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1235 int ret; 1236 1237 memset(&seg_desc, 0, sizeof seg_desc); 1238 1239 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) 1240 || ctxt->mode == X86EMUL_MODE_REAL) { 1241 /* set real mode segment descriptor */ 1242 set_desc_base(&seg_desc, selector << 4); 1243 set_desc_limit(&seg_desc, 0xffff); 1244 seg_desc.type = 3; 1245 seg_desc.p = 1; 1246 seg_desc.s = 1; 1247 if (ctxt->mode == X86EMUL_MODE_VM86) 1248 seg_desc.dpl = 3; 1249 goto load; 1250 } 1251 1252 /* NULL selector is not valid for TR, CS and SS */ 1253 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) 1254 && null_selector) 1255 goto exception; 1256 1257 /* TR should be in GDT only */ 1258 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1259 goto exception; 1260 1261 if (null_selector) /* for NULL selector skip all following checks */ 1262 goto load; 1263 1264 ret = read_segment_descriptor(ctxt, selector, &seg_desc); 1265 if (ret != X86EMUL_CONTINUE) 1266 return ret; 1267 1268 err_code = selector & 0xfffc; 1269 err_vec = GP_VECTOR; 1270 1271 /* can't load system descriptor into segment selecor */ 1272 if (seg <= VCPU_SREG_GS && !seg_desc.s) 1273 goto exception; 1274 1275 if (!seg_desc.p) { 1276 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1277 goto exception; 1278 } 1279 1280 rpl = selector & 3; 1281 dpl = seg_desc.dpl; 1282 cpl = ctxt->ops->cpl(ctxt); 1283 1284 switch (seg) { 1285 case VCPU_SREG_SS: 1286 /* 1287 * segment is not a writable data segment or segment 1288 * selector's RPL != CPL or segment selector's RPL != CPL 1289 */ 1290 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1291 goto exception; 1292 break; 1293 case VCPU_SREG_CS: 1294 if (!(seg_desc.type & 8)) 1295 goto exception; 1296 1297 if (seg_desc.type & 4) { 1298 /* conforming */ 1299 if (dpl > cpl) 1300 goto exception; 1301 } else { 1302 /* nonconforming */ 1303 if (rpl > cpl || dpl != cpl) 1304 goto exception; 1305 } 1306 /* CS(RPL) <- CPL */ 1307 selector = (selector & 0xfffc) | cpl; 1308 break; 1309 case VCPU_SREG_TR: 1310 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1311 goto exception; 1312 break; 1313 case VCPU_SREG_LDTR: 1314 if (seg_desc.s || seg_desc.type != 2) 1315 goto exception; 1316 break; 1317 default: /* DS, ES, FS, or GS */ 1318 /* 1319 * segment is not a data or readable code segment or 1320 * ((segment is a data or nonconforming code segment) 1321 * and (both RPL and CPL > DPL)) 1322 */ 1323 if ((seg_desc.type & 0xa) == 0x8 || 1324 (((seg_desc.type & 0xc) != 0xc) && 1325 (rpl > dpl && cpl > dpl))) 1326 goto exception; 1327 break; 1328 } 1329 1330 if (seg_desc.s) { 1331 /* mark segment as accessed */ 1332 seg_desc.type |= 1; 1333 ret = write_segment_descriptor(ctxt, selector, &seg_desc); 1334 if (ret != X86EMUL_CONTINUE) 1335 return ret; 1336 } 1337 load: 1338 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); 1339 return X86EMUL_CONTINUE; 1340 exception: 1341 emulate_exception(ctxt, err_vec, err_code, true); 1342 return X86EMUL_PROPAGATE_FAULT; 1343 } 1344 1345 static void write_register_operand(struct operand *op) 1346 { 1347 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 1348 switch (op->bytes) { 1349 case 1: 1350 *(u8 *)op->addr.reg = (u8)op->val; 1351 break; 1352 case 2: 1353 *(u16 *)op->addr.reg = (u16)op->val; 1354 break; 1355 case 4: 1356 *op->addr.reg = (u32)op->val; 1357 break; /* 64b: zero-extend */ 1358 case 8: 1359 *op->addr.reg = op->val; 1360 break; 1361 } 1362 } 1363 1364 static int writeback(struct x86_emulate_ctxt *ctxt) 1365 { 1366 int rc; 1367 1368 switch (ctxt->dst.type) { 1369 case OP_REG: 1370 write_register_operand(&ctxt->dst); 1371 break; 1372 case OP_MEM: 1373 if (ctxt->lock_prefix) 1374 rc = segmented_cmpxchg(ctxt, 1375 ctxt->dst.addr.mem, 1376 &ctxt->dst.orig_val, 1377 &ctxt->dst.val, 1378 ctxt->dst.bytes); 1379 else 1380 rc = segmented_write(ctxt, 1381 ctxt->dst.addr.mem, 1382 &ctxt->dst.val, 1383 ctxt->dst.bytes); 1384 if (rc != X86EMUL_CONTINUE) 1385 return rc; 1386 break; 1387 case OP_XMM: 1388 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); 1389 break; 1390 case OP_NONE: 1391 /* no writeback */ 1392 break; 1393 default: 1394 break; 1395 } 1396 return X86EMUL_CONTINUE; 1397 } 1398 1399 static int em_push(struct x86_emulate_ctxt *ctxt) 1400 { 1401 struct segmented_address addr; 1402 1403 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes); 1404 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); 1405 addr.seg = VCPU_SREG_SS; 1406 1407 /* Disable writeback. */ 1408 ctxt->dst.type = OP_NONE; 1409 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes); 1410 } 1411 1412 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1413 void *dest, int len) 1414 { 1415 int rc; 1416 struct segmented_address addr; 1417 1418 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); 1419 addr.seg = VCPU_SREG_SS; 1420 rc = segmented_read(ctxt, addr, dest, len); 1421 if (rc != X86EMUL_CONTINUE) 1422 return rc; 1423 1424 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); 1425 return rc; 1426 } 1427 1428 static int em_pop(struct x86_emulate_ctxt *ctxt) 1429 { 1430 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1431 } 1432 1433 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1434 void *dest, int len) 1435 { 1436 int rc; 1437 unsigned long val, change_mask; 1438 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 1439 int cpl = ctxt->ops->cpl(ctxt); 1440 1441 rc = emulate_pop(ctxt, &val, len); 1442 if (rc != X86EMUL_CONTINUE) 1443 return rc; 1444 1445 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF 1446 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; 1447 1448 switch(ctxt->mode) { 1449 case X86EMUL_MODE_PROT64: 1450 case X86EMUL_MODE_PROT32: 1451 case X86EMUL_MODE_PROT16: 1452 if (cpl == 0) 1453 change_mask |= EFLG_IOPL; 1454 if (cpl <= iopl) 1455 change_mask |= EFLG_IF; 1456 break; 1457 case X86EMUL_MODE_VM86: 1458 if (iopl < 3) 1459 return emulate_gp(ctxt, 0); 1460 change_mask |= EFLG_IF; 1461 break; 1462 default: /* real mode */ 1463 change_mask |= (EFLG_IOPL | EFLG_IF); 1464 break; 1465 } 1466 1467 *(unsigned long *)dest = 1468 (ctxt->eflags & ~change_mask) | (val & change_mask); 1469 1470 return rc; 1471 } 1472 1473 static int em_popf(struct x86_emulate_ctxt *ctxt) 1474 { 1475 ctxt->dst.type = OP_REG; 1476 ctxt->dst.addr.reg = &ctxt->eflags; 1477 ctxt->dst.bytes = ctxt->op_bytes; 1478 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1479 } 1480 1481 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1482 { 1483 int seg = ctxt->src2.val; 1484 1485 ctxt->src.val = get_segment_selector(ctxt, seg); 1486 1487 return em_push(ctxt); 1488 } 1489 1490 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1491 { 1492 int seg = ctxt->src2.val; 1493 unsigned long selector; 1494 int rc; 1495 1496 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); 1497 if (rc != X86EMUL_CONTINUE) 1498 return rc; 1499 1500 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1501 return rc; 1502 } 1503 1504 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1505 { 1506 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP]; 1507 int rc = X86EMUL_CONTINUE; 1508 int reg = VCPU_REGS_RAX; 1509 1510 while (reg <= VCPU_REGS_RDI) { 1511 (reg == VCPU_REGS_RSP) ? 1512 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]); 1513 1514 rc = em_push(ctxt); 1515 if (rc != X86EMUL_CONTINUE) 1516 return rc; 1517 1518 ++reg; 1519 } 1520 1521 return rc; 1522 } 1523 1524 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1525 { 1526 ctxt->src.val = (unsigned long)ctxt->eflags; 1527 return em_push(ctxt); 1528 } 1529 1530 static int em_popa(struct x86_emulate_ctxt *ctxt) 1531 { 1532 int rc = X86EMUL_CONTINUE; 1533 int reg = VCPU_REGS_RDI; 1534 1535 while (reg >= VCPU_REGS_RAX) { 1536 if (reg == VCPU_REGS_RSP) { 1537 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], 1538 ctxt->op_bytes); 1539 --reg; 1540 } 1541 1542 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes); 1543 if (rc != X86EMUL_CONTINUE) 1544 break; 1545 --reg; 1546 } 1547 return rc; 1548 } 1549 1550 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1551 { 1552 struct x86_emulate_ops *ops = ctxt->ops; 1553 int rc; 1554 struct desc_ptr dt; 1555 gva_t cs_addr; 1556 gva_t eip_addr; 1557 u16 cs, eip; 1558 1559 /* TODO: Add limit checks */ 1560 ctxt->src.val = ctxt->eflags; 1561 rc = em_push(ctxt); 1562 if (rc != X86EMUL_CONTINUE) 1563 return rc; 1564 1565 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); 1566 1567 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 1568 rc = em_push(ctxt); 1569 if (rc != X86EMUL_CONTINUE) 1570 return rc; 1571 1572 ctxt->src.val = ctxt->_eip; 1573 rc = em_push(ctxt); 1574 if (rc != X86EMUL_CONTINUE) 1575 return rc; 1576 1577 ops->get_idt(ctxt, &dt); 1578 1579 eip_addr = dt.address + (irq << 2); 1580 cs_addr = dt.address + (irq << 2) + 2; 1581 1582 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 1583 if (rc != X86EMUL_CONTINUE) 1584 return rc; 1585 1586 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 1587 if (rc != X86EMUL_CONTINUE) 1588 return rc; 1589 1590 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 1591 if (rc != X86EMUL_CONTINUE) 1592 return rc; 1593 1594 ctxt->_eip = eip; 1595 1596 return rc; 1597 } 1598 1599 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 1600 { 1601 switch(ctxt->mode) { 1602 case X86EMUL_MODE_REAL: 1603 return emulate_int_real(ctxt, irq); 1604 case X86EMUL_MODE_VM86: 1605 case X86EMUL_MODE_PROT16: 1606 case X86EMUL_MODE_PROT32: 1607 case X86EMUL_MODE_PROT64: 1608 default: 1609 /* Protected mode interrupts unimplemented yet */ 1610 return X86EMUL_UNHANDLEABLE; 1611 } 1612 } 1613 1614 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 1615 { 1616 int rc = X86EMUL_CONTINUE; 1617 unsigned long temp_eip = 0; 1618 unsigned long temp_eflags = 0; 1619 unsigned long cs = 0; 1620 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | 1621 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | 1622 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ 1623 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; 1624 1625 /* TODO: Add stack limit check */ 1626 1627 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 1628 1629 if (rc != X86EMUL_CONTINUE) 1630 return rc; 1631 1632 if (temp_eip & ~0xffff) 1633 return emulate_gp(ctxt, 0); 1634 1635 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 1636 1637 if (rc != X86EMUL_CONTINUE) 1638 return rc; 1639 1640 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 1641 1642 if (rc != X86EMUL_CONTINUE) 1643 return rc; 1644 1645 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 1646 1647 if (rc != X86EMUL_CONTINUE) 1648 return rc; 1649 1650 ctxt->_eip = temp_eip; 1651 1652 1653 if (ctxt->op_bytes == 4) 1654 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 1655 else if (ctxt->op_bytes == 2) { 1656 ctxt->eflags &= ~0xffff; 1657 ctxt->eflags |= temp_eflags; 1658 } 1659 1660 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 1661 ctxt->eflags |= EFLG_RESERVED_ONE_MASK; 1662 1663 return rc; 1664 } 1665 1666 static int em_iret(struct x86_emulate_ctxt *ctxt) 1667 { 1668 switch(ctxt->mode) { 1669 case X86EMUL_MODE_REAL: 1670 return emulate_iret_real(ctxt); 1671 case X86EMUL_MODE_VM86: 1672 case X86EMUL_MODE_PROT16: 1673 case X86EMUL_MODE_PROT32: 1674 case X86EMUL_MODE_PROT64: 1675 default: 1676 /* iret from protected mode unimplemented yet */ 1677 return X86EMUL_UNHANDLEABLE; 1678 } 1679 } 1680 1681 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 1682 { 1683 int rc; 1684 unsigned short sel; 1685 1686 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 1687 1688 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); 1689 if (rc != X86EMUL_CONTINUE) 1690 return rc; 1691 1692 ctxt->_eip = 0; 1693 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 1694 return X86EMUL_CONTINUE; 1695 } 1696 1697 static int em_grp2(struct x86_emulate_ctxt *ctxt) 1698 { 1699 switch (ctxt->modrm_reg) { 1700 case 0: /* rol */ 1701 emulate_2op_SrcB(ctxt, "rol"); 1702 break; 1703 case 1: /* ror */ 1704 emulate_2op_SrcB(ctxt, "ror"); 1705 break; 1706 case 2: /* rcl */ 1707 emulate_2op_SrcB(ctxt, "rcl"); 1708 break; 1709 case 3: /* rcr */ 1710 emulate_2op_SrcB(ctxt, "rcr"); 1711 break; 1712 case 4: /* sal/shl */ 1713 case 6: /* sal/shl */ 1714 emulate_2op_SrcB(ctxt, "sal"); 1715 break; 1716 case 5: /* shr */ 1717 emulate_2op_SrcB(ctxt, "shr"); 1718 break; 1719 case 7: /* sar */ 1720 emulate_2op_SrcB(ctxt, "sar"); 1721 break; 1722 } 1723 return X86EMUL_CONTINUE; 1724 } 1725 1726 static int em_not(struct x86_emulate_ctxt *ctxt) 1727 { 1728 ctxt->dst.val = ~ctxt->dst.val; 1729 return X86EMUL_CONTINUE; 1730 } 1731 1732 static int em_neg(struct x86_emulate_ctxt *ctxt) 1733 { 1734 emulate_1op(ctxt, "neg"); 1735 return X86EMUL_CONTINUE; 1736 } 1737 1738 static int em_mul_ex(struct x86_emulate_ctxt *ctxt) 1739 { 1740 u8 ex = 0; 1741 1742 emulate_1op_rax_rdx(ctxt, "mul", ex); 1743 return X86EMUL_CONTINUE; 1744 } 1745 1746 static int em_imul_ex(struct x86_emulate_ctxt *ctxt) 1747 { 1748 u8 ex = 0; 1749 1750 emulate_1op_rax_rdx(ctxt, "imul", ex); 1751 return X86EMUL_CONTINUE; 1752 } 1753 1754 static int em_div_ex(struct x86_emulate_ctxt *ctxt) 1755 { 1756 u8 de = 0; 1757 1758 emulate_1op_rax_rdx(ctxt, "div", de); 1759 if (de) 1760 return emulate_de(ctxt); 1761 return X86EMUL_CONTINUE; 1762 } 1763 1764 static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) 1765 { 1766 u8 de = 0; 1767 1768 emulate_1op_rax_rdx(ctxt, "idiv", de); 1769 if (de) 1770 return emulate_de(ctxt); 1771 return X86EMUL_CONTINUE; 1772 } 1773 1774 static int em_grp45(struct x86_emulate_ctxt *ctxt) 1775 { 1776 int rc = X86EMUL_CONTINUE; 1777 1778 switch (ctxt->modrm_reg) { 1779 case 0: /* inc */ 1780 emulate_1op(ctxt, "inc"); 1781 break; 1782 case 1: /* dec */ 1783 emulate_1op(ctxt, "dec"); 1784 break; 1785 case 2: /* call near abs */ { 1786 long int old_eip; 1787 old_eip = ctxt->_eip; 1788 ctxt->_eip = ctxt->src.val; 1789 ctxt->src.val = old_eip; 1790 rc = em_push(ctxt); 1791 break; 1792 } 1793 case 4: /* jmp abs */ 1794 ctxt->_eip = ctxt->src.val; 1795 break; 1796 case 5: /* jmp far */ 1797 rc = em_jmp_far(ctxt); 1798 break; 1799 case 6: /* push */ 1800 rc = em_push(ctxt); 1801 break; 1802 } 1803 return rc; 1804 } 1805 1806 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 1807 { 1808 u64 old = ctxt->dst.orig_val64; 1809 1810 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) || 1811 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) { 1812 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0); 1813 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32); 1814 ctxt->eflags &= ~EFLG_ZF; 1815 } else { 1816 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) | 1817 (u32) ctxt->regs[VCPU_REGS_RBX]; 1818 1819 ctxt->eflags |= EFLG_ZF; 1820 } 1821 return X86EMUL_CONTINUE; 1822 } 1823 1824 static int em_ret(struct x86_emulate_ctxt *ctxt) 1825 { 1826 ctxt->dst.type = OP_REG; 1827 ctxt->dst.addr.reg = &ctxt->_eip; 1828 ctxt->dst.bytes = ctxt->op_bytes; 1829 return em_pop(ctxt); 1830 } 1831 1832 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 1833 { 1834 int rc; 1835 unsigned long cs; 1836 1837 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); 1838 if (rc != X86EMUL_CONTINUE) 1839 return rc; 1840 if (ctxt->op_bytes == 4) 1841 ctxt->_eip = (u32)ctxt->_eip; 1842 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 1843 if (rc != X86EMUL_CONTINUE) 1844 return rc; 1845 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 1846 return rc; 1847 } 1848 1849 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 1850 { 1851 /* Save real source value, then compare EAX against destination. */ 1852 ctxt->src.orig_val = ctxt->src.val; 1853 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX]; 1854 emulate_2op_SrcV(ctxt, "cmp"); 1855 1856 if (ctxt->eflags & EFLG_ZF) { 1857 /* Success: write back to memory. */ 1858 ctxt->dst.val = ctxt->src.orig_val; 1859 } else { 1860 /* Failure: write the value we saw to EAX. */ 1861 ctxt->dst.type = OP_REG; 1862 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX]; 1863 } 1864 return X86EMUL_CONTINUE; 1865 } 1866 1867 static int em_lseg(struct x86_emulate_ctxt *ctxt) 1868 { 1869 int seg = ctxt->src2.val; 1870 unsigned short sel; 1871 int rc; 1872 1873 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 1874 1875 rc = load_segment_descriptor(ctxt, sel, seg); 1876 if (rc != X86EMUL_CONTINUE) 1877 return rc; 1878 1879 ctxt->dst.val = ctxt->src.val; 1880 return rc; 1881 } 1882 1883 static void 1884 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 1885 struct desc_struct *cs, struct desc_struct *ss) 1886 { 1887 u16 selector; 1888 1889 memset(cs, 0, sizeof(struct desc_struct)); 1890 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS); 1891 memset(ss, 0, sizeof(struct desc_struct)); 1892 1893 cs->l = 0; /* will be adjusted later */ 1894 set_desc_base(cs, 0); /* flat segment */ 1895 cs->g = 1; /* 4kb granularity */ 1896 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 1897 cs->type = 0x0b; /* Read, Execute, Accessed */ 1898 cs->s = 1; 1899 cs->dpl = 0; /* will be adjusted later */ 1900 cs->p = 1; 1901 cs->d = 1; 1902 1903 set_desc_base(ss, 0); /* flat segment */ 1904 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 1905 ss->g = 1; /* 4kb granularity */ 1906 ss->s = 1; 1907 ss->type = 0x03; /* Read/Write, Accessed */ 1908 ss->d = 1; /* 32bit stack segment */ 1909 ss->dpl = 0; 1910 ss->p = 1; 1911 } 1912 1913 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 1914 { 1915 u32 eax, ebx, ecx, edx; 1916 1917 eax = ecx = 0; 1918 return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx) 1919 && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 1920 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 1921 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 1922 } 1923 1924 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 1925 { 1926 struct x86_emulate_ops *ops = ctxt->ops; 1927 u32 eax, ebx, ecx, edx; 1928 1929 /* 1930 * syscall should always be enabled in longmode - so only become 1931 * vendor specific (cpuid) if other modes are active... 1932 */ 1933 if (ctxt->mode == X86EMUL_MODE_PROT64) 1934 return true; 1935 1936 eax = 0x00000000; 1937 ecx = 0x00000000; 1938 if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) { 1939 /* 1940 * Intel ("GenuineIntel") 1941 * remark: Intel CPUs only support "syscall" in 64bit 1942 * longmode. Also an 64bit guest with a 1943 * 32bit compat-app running will #UD !! While this 1944 * behaviour can be fixed (by emulating) into AMD 1945 * response - CPUs of AMD can't behave like Intel. 1946 */ 1947 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 1948 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 1949 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 1950 return false; 1951 1952 /* AMD ("AuthenticAMD") */ 1953 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 1954 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 1955 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 1956 return true; 1957 1958 /* AMD ("AMDisbetter!") */ 1959 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 1960 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 1961 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 1962 return true; 1963 } 1964 1965 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 1966 return false; 1967 } 1968 1969 static int em_syscall(struct x86_emulate_ctxt *ctxt) 1970 { 1971 struct x86_emulate_ops *ops = ctxt->ops; 1972 struct desc_struct cs, ss; 1973 u64 msr_data; 1974 u16 cs_sel, ss_sel; 1975 u64 efer = 0; 1976 1977 /* syscall is not available in real mode */ 1978 if (ctxt->mode == X86EMUL_MODE_REAL || 1979 ctxt->mode == X86EMUL_MODE_VM86) 1980 return emulate_ud(ctxt); 1981 1982 if (!(em_syscall_is_enabled(ctxt))) 1983 return emulate_ud(ctxt); 1984 1985 ops->get_msr(ctxt, MSR_EFER, &efer); 1986 setup_syscalls_segments(ctxt, &cs, &ss); 1987 1988 if (!(efer & EFER_SCE)) 1989 return emulate_ud(ctxt); 1990 1991 ops->get_msr(ctxt, MSR_STAR, &msr_data); 1992 msr_data >>= 32; 1993 cs_sel = (u16)(msr_data & 0xfffc); 1994 ss_sel = (u16)(msr_data + 8); 1995 1996 if (efer & EFER_LMA) { 1997 cs.d = 0; 1998 cs.l = 1; 1999 } 2000 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2001 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2002 2003 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip; 2004 if (efer & EFER_LMA) { 2005 #ifdef CONFIG_X86_64 2006 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; 2007 2008 ops->get_msr(ctxt, 2009 ctxt->mode == X86EMUL_MODE_PROT64 ? 2010 MSR_LSTAR : MSR_CSTAR, &msr_data); 2011 ctxt->_eip = msr_data; 2012 2013 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2014 ctxt->eflags &= ~(msr_data | EFLG_RF); 2015 #endif 2016 } else { 2017 /* legacy mode */ 2018 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2019 ctxt->_eip = (u32)msr_data; 2020 2021 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2022 } 2023 2024 return X86EMUL_CONTINUE; 2025 } 2026 2027 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2028 { 2029 struct x86_emulate_ops *ops = ctxt->ops; 2030 struct desc_struct cs, ss; 2031 u64 msr_data; 2032 u16 cs_sel, ss_sel; 2033 u64 efer = 0; 2034 2035 ops->get_msr(ctxt, MSR_EFER, &efer); 2036 /* inject #GP if in real mode */ 2037 if (ctxt->mode == X86EMUL_MODE_REAL) 2038 return emulate_gp(ctxt, 0); 2039 2040 /* 2041 * Not recognized on AMD in compat mode (but is recognized in legacy 2042 * mode). 2043 */ 2044 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) 2045 && !vendor_intel(ctxt)) 2046 return emulate_ud(ctxt); 2047 2048 /* XXX sysenter/sysexit have not been tested in 64bit mode. 2049 * Therefore, we inject an #UD. 2050 */ 2051 if (ctxt->mode == X86EMUL_MODE_PROT64) 2052 return emulate_ud(ctxt); 2053 2054 setup_syscalls_segments(ctxt, &cs, &ss); 2055 2056 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2057 switch (ctxt->mode) { 2058 case X86EMUL_MODE_PROT32: 2059 if ((msr_data & 0xfffc) == 0x0) 2060 return emulate_gp(ctxt, 0); 2061 break; 2062 case X86EMUL_MODE_PROT64: 2063 if (msr_data == 0x0) 2064 return emulate_gp(ctxt, 0); 2065 break; 2066 } 2067 2068 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2069 cs_sel = (u16)msr_data; 2070 cs_sel &= ~SELECTOR_RPL_MASK; 2071 ss_sel = cs_sel + 8; 2072 ss_sel &= ~SELECTOR_RPL_MASK; 2073 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { 2074 cs.d = 0; 2075 cs.l = 1; 2076 } 2077 2078 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2079 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2080 2081 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2082 ctxt->_eip = msr_data; 2083 2084 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2085 ctxt->regs[VCPU_REGS_RSP] = msr_data; 2086 2087 return X86EMUL_CONTINUE; 2088 } 2089 2090 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2091 { 2092 struct x86_emulate_ops *ops = ctxt->ops; 2093 struct desc_struct cs, ss; 2094 u64 msr_data; 2095 int usermode; 2096 u16 cs_sel = 0, ss_sel = 0; 2097 2098 /* inject #GP if in real mode or Virtual 8086 mode */ 2099 if (ctxt->mode == X86EMUL_MODE_REAL || 2100 ctxt->mode == X86EMUL_MODE_VM86) 2101 return emulate_gp(ctxt, 0); 2102 2103 setup_syscalls_segments(ctxt, &cs, &ss); 2104 2105 if ((ctxt->rex_prefix & 0x8) != 0x0) 2106 usermode = X86EMUL_MODE_PROT64; 2107 else 2108 usermode = X86EMUL_MODE_PROT32; 2109 2110 cs.dpl = 3; 2111 ss.dpl = 3; 2112 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2113 switch (usermode) { 2114 case X86EMUL_MODE_PROT32: 2115 cs_sel = (u16)(msr_data + 16); 2116 if ((msr_data & 0xfffc) == 0x0) 2117 return emulate_gp(ctxt, 0); 2118 ss_sel = (u16)(msr_data + 24); 2119 break; 2120 case X86EMUL_MODE_PROT64: 2121 cs_sel = (u16)(msr_data + 32); 2122 if (msr_data == 0x0) 2123 return emulate_gp(ctxt, 0); 2124 ss_sel = cs_sel + 8; 2125 cs.d = 0; 2126 cs.l = 1; 2127 break; 2128 } 2129 cs_sel |= SELECTOR_RPL_MASK; 2130 ss_sel |= SELECTOR_RPL_MASK; 2131 2132 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2133 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2134 2135 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX]; 2136 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX]; 2137 2138 return X86EMUL_CONTINUE; 2139 } 2140 2141 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2142 { 2143 int iopl; 2144 if (ctxt->mode == X86EMUL_MODE_REAL) 2145 return false; 2146 if (ctxt->mode == X86EMUL_MODE_VM86) 2147 return true; 2148 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 2149 return ctxt->ops->cpl(ctxt) > iopl; 2150 } 2151 2152 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2153 u16 port, u16 len) 2154 { 2155 struct x86_emulate_ops *ops = ctxt->ops; 2156 struct desc_struct tr_seg; 2157 u32 base3; 2158 int r; 2159 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2160 unsigned mask = (1 << len) - 1; 2161 unsigned long base; 2162 2163 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2164 if (!tr_seg.p) 2165 return false; 2166 if (desc_limit_scaled(&tr_seg) < 103) 2167 return false; 2168 base = get_desc_base(&tr_seg); 2169 #ifdef CONFIG_X86_64 2170 base |= ((u64)base3) << 32; 2171 #endif 2172 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2173 if (r != X86EMUL_CONTINUE) 2174 return false; 2175 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2176 return false; 2177 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2178 if (r != X86EMUL_CONTINUE) 2179 return false; 2180 if ((perm >> bit_idx) & mask) 2181 return false; 2182 return true; 2183 } 2184 2185 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2186 u16 port, u16 len) 2187 { 2188 if (ctxt->perm_ok) 2189 return true; 2190 2191 if (emulator_bad_iopl(ctxt)) 2192 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2193 return false; 2194 2195 ctxt->perm_ok = true; 2196 2197 return true; 2198 } 2199 2200 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2201 struct tss_segment_16 *tss) 2202 { 2203 tss->ip = ctxt->_eip; 2204 tss->flag = ctxt->eflags; 2205 tss->ax = ctxt->regs[VCPU_REGS_RAX]; 2206 tss->cx = ctxt->regs[VCPU_REGS_RCX]; 2207 tss->dx = ctxt->regs[VCPU_REGS_RDX]; 2208 tss->bx = ctxt->regs[VCPU_REGS_RBX]; 2209 tss->sp = ctxt->regs[VCPU_REGS_RSP]; 2210 tss->bp = ctxt->regs[VCPU_REGS_RBP]; 2211 tss->si = ctxt->regs[VCPU_REGS_RSI]; 2212 tss->di = ctxt->regs[VCPU_REGS_RDI]; 2213 2214 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2215 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2216 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2217 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2218 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2219 } 2220 2221 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2222 struct tss_segment_16 *tss) 2223 { 2224 int ret; 2225 2226 ctxt->_eip = tss->ip; 2227 ctxt->eflags = tss->flag | 2; 2228 ctxt->regs[VCPU_REGS_RAX] = tss->ax; 2229 ctxt->regs[VCPU_REGS_RCX] = tss->cx; 2230 ctxt->regs[VCPU_REGS_RDX] = tss->dx; 2231 ctxt->regs[VCPU_REGS_RBX] = tss->bx; 2232 ctxt->regs[VCPU_REGS_RSP] = tss->sp; 2233 ctxt->regs[VCPU_REGS_RBP] = tss->bp; 2234 ctxt->regs[VCPU_REGS_RSI] = tss->si; 2235 ctxt->regs[VCPU_REGS_RDI] = tss->di; 2236 2237 /* 2238 * SDM says that segment selectors are loaded before segment 2239 * descriptors 2240 */ 2241 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2242 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2243 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2244 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2245 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2246 2247 /* 2248 * Now load segment descriptors. If fault happenes at this stage 2249 * it is handled in a context of new task 2250 */ 2251 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); 2252 if (ret != X86EMUL_CONTINUE) 2253 return ret; 2254 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2255 if (ret != X86EMUL_CONTINUE) 2256 return ret; 2257 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2258 if (ret != X86EMUL_CONTINUE) 2259 return ret; 2260 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2261 if (ret != X86EMUL_CONTINUE) 2262 return ret; 2263 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2264 if (ret != X86EMUL_CONTINUE) 2265 return ret; 2266 2267 return X86EMUL_CONTINUE; 2268 } 2269 2270 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2271 u16 tss_selector, u16 old_tss_sel, 2272 ulong old_tss_base, struct desc_struct *new_desc) 2273 { 2274 struct x86_emulate_ops *ops = ctxt->ops; 2275 struct tss_segment_16 tss_seg; 2276 int ret; 2277 u32 new_tss_base = get_desc_base(new_desc); 2278 2279 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2280 &ctxt->exception); 2281 if (ret != X86EMUL_CONTINUE) 2282 /* FIXME: need to provide precise fault address */ 2283 return ret; 2284 2285 save_state_to_tss16(ctxt, &tss_seg); 2286 2287 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2288 &ctxt->exception); 2289 if (ret != X86EMUL_CONTINUE) 2290 /* FIXME: need to provide precise fault address */ 2291 return ret; 2292 2293 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2294 &ctxt->exception); 2295 if (ret != X86EMUL_CONTINUE) 2296 /* FIXME: need to provide precise fault address */ 2297 return ret; 2298 2299 if (old_tss_sel != 0xffff) { 2300 tss_seg.prev_task_link = old_tss_sel; 2301 2302 ret = ops->write_std(ctxt, new_tss_base, 2303 &tss_seg.prev_task_link, 2304 sizeof tss_seg.prev_task_link, 2305 &ctxt->exception); 2306 if (ret != X86EMUL_CONTINUE) 2307 /* FIXME: need to provide precise fault address */ 2308 return ret; 2309 } 2310 2311 return load_state_from_tss16(ctxt, &tss_seg); 2312 } 2313 2314 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2315 struct tss_segment_32 *tss) 2316 { 2317 tss->cr3 = ctxt->ops->get_cr(ctxt, 3); 2318 tss->eip = ctxt->_eip; 2319 tss->eflags = ctxt->eflags; 2320 tss->eax = ctxt->regs[VCPU_REGS_RAX]; 2321 tss->ecx = ctxt->regs[VCPU_REGS_RCX]; 2322 tss->edx = ctxt->regs[VCPU_REGS_RDX]; 2323 tss->ebx = ctxt->regs[VCPU_REGS_RBX]; 2324 tss->esp = ctxt->regs[VCPU_REGS_RSP]; 2325 tss->ebp = ctxt->regs[VCPU_REGS_RBP]; 2326 tss->esi = ctxt->regs[VCPU_REGS_RSI]; 2327 tss->edi = ctxt->regs[VCPU_REGS_RDI]; 2328 2329 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2330 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2331 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2332 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2333 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2334 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2335 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2336 } 2337 2338 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2339 struct tss_segment_32 *tss) 2340 { 2341 int ret; 2342 2343 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2344 return emulate_gp(ctxt, 0); 2345 ctxt->_eip = tss->eip; 2346 ctxt->eflags = tss->eflags | 2; 2347 2348 /* General purpose registers */ 2349 ctxt->regs[VCPU_REGS_RAX] = tss->eax; 2350 ctxt->regs[VCPU_REGS_RCX] = tss->ecx; 2351 ctxt->regs[VCPU_REGS_RDX] = tss->edx; 2352 ctxt->regs[VCPU_REGS_RBX] = tss->ebx; 2353 ctxt->regs[VCPU_REGS_RSP] = tss->esp; 2354 ctxt->regs[VCPU_REGS_RBP] = tss->ebp; 2355 ctxt->regs[VCPU_REGS_RSI] = tss->esi; 2356 ctxt->regs[VCPU_REGS_RDI] = tss->edi; 2357 2358 /* 2359 * SDM says that segment selectors are loaded before segment 2360 * descriptors 2361 */ 2362 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2363 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2364 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2365 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2366 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2367 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2368 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2369 2370 /* 2371 * If we're switching between Protected Mode and VM86, we need to make 2372 * sure to update the mode before loading the segment descriptors so 2373 * that the selectors are interpreted correctly. 2374 * 2375 * Need to get rflags to the vcpu struct immediately because it 2376 * influences the CPL which is checked at least when loading the segment 2377 * descriptors and when pushing an error code to the new kernel stack. 2378 * 2379 * TODO Introduce a separate ctxt->ops->set_cpl callback 2380 */ 2381 if (ctxt->eflags & X86_EFLAGS_VM) 2382 ctxt->mode = X86EMUL_MODE_VM86; 2383 else 2384 ctxt->mode = X86EMUL_MODE_PROT32; 2385 2386 ctxt->ops->set_rflags(ctxt, ctxt->eflags); 2387 2388 /* 2389 * Now load segment descriptors. If fault happenes at this stage 2390 * it is handled in a context of new task 2391 */ 2392 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2393 if (ret != X86EMUL_CONTINUE) 2394 return ret; 2395 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2396 if (ret != X86EMUL_CONTINUE) 2397 return ret; 2398 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2399 if (ret != X86EMUL_CONTINUE) 2400 return ret; 2401 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2402 if (ret != X86EMUL_CONTINUE) 2403 return ret; 2404 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2405 if (ret != X86EMUL_CONTINUE) 2406 return ret; 2407 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); 2408 if (ret != X86EMUL_CONTINUE) 2409 return ret; 2410 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); 2411 if (ret != X86EMUL_CONTINUE) 2412 return ret; 2413 2414 return X86EMUL_CONTINUE; 2415 } 2416 2417 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 2418 u16 tss_selector, u16 old_tss_sel, 2419 ulong old_tss_base, struct desc_struct *new_desc) 2420 { 2421 struct x86_emulate_ops *ops = ctxt->ops; 2422 struct tss_segment_32 tss_seg; 2423 int ret; 2424 u32 new_tss_base = get_desc_base(new_desc); 2425 2426 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2427 &ctxt->exception); 2428 if (ret != X86EMUL_CONTINUE) 2429 /* FIXME: need to provide precise fault address */ 2430 return ret; 2431 2432 save_state_to_tss32(ctxt, &tss_seg); 2433 2434 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2435 &ctxt->exception); 2436 if (ret != X86EMUL_CONTINUE) 2437 /* FIXME: need to provide precise fault address */ 2438 return ret; 2439 2440 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2441 &ctxt->exception); 2442 if (ret != X86EMUL_CONTINUE) 2443 /* FIXME: need to provide precise fault address */ 2444 return ret; 2445 2446 if (old_tss_sel != 0xffff) { 2447 tss_seg.prev_task_link = old_tss_sel; 2448 2449 ret = ops->write_std(ctxt, new_tss_base, 2450 &tss_seg.prev_task_link, 2451 sizeof tss_seg.prev_task_link, 2452 &ctxt->exception); 2453 if (ret != X86EMUL_CONTINUE) 2454 /* FIXME: need to provide precise fault address */ 2455 return ret; 2456 } 2457 2458 return load_state_from_tss32(ctxt, &tss_seg); 2459 } 2460 2461 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2462 u16 tss_selector, int idt_index, int reason, 2463 bool has_error_code, u32 error_code) 2464 { 2465 struct x86_emulate_ops *ops = ctxt->ops; 2466 struct desc_struct curr_tss_desc, next_tss_desc; 2467 int ret; 2468 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2469 ulong old_tss_base = 2470 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2471 u32 desc_limit; 2472 2473 /* FIXME: old_tss_base == ~0 ? */ 2474 2475 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2476 if (ret != X86EMUL_CONTINUE) 2477 return ret; 2478 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2479 if (ret != X86EMUL_CONTINUE) 2480 return ret; 2481 2482 /* FIXME: check that next_tss_desc is tss */ 2483 2484 /* 2485 * Check privileges. The three cases are task switch caused by... 2486 * 2487 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2488 * 2. Exception/IRQ/iret: No check is performed 2489 * 3. jmp/call to TSS: Check agains DPL of the TSS 2490 */ 2491 if (reason == TASK_SWITCH_GATE) { 2492 if (idt_index != -1) { 2493 /* Software interrupts */ 2494 struct desc_struct task_gate_desc; 2495 int dpl; 2496 2497 ret = read_interrupt_descriptor(ctxt, idt_index, 2498 &task_gate_desc); 2499 if (ret != X86EMUL_CONTINUE) 2500 return ret; 2501 2502 dpl = task_gate_desc.dpl; 2503 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2504 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2505 } 2506 } else if (reason != TASK_SWITCH_IRET) { 2507 int dpl = next_tss_desc.dpl; 2508 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2509 return emulate_gp(ctxt, tss_selector); 2510 } 2511 2512 2513 desc_limit = desc_limit_scaled(&next_tss_desc); 2514 if (!next_tss_desc.p || 2515 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2516 desc_limit < 0x2b)) { 2517 emulate_ts(ctxt, tss_selector & 0xfffc); 2518 return X86EMUL_PROPAGATE_FAULT; 2519 } 2520 2521 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2522 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2523 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2524 } 2525 2526 if (reason == TASK_SWITCH_IRET) 2527 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2528 2529 /* set back link to prev task only if NT bit is set in eflags 2530 note that old_tss_sel is not used afetr this point */ 2531 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2532 old_tss_sel = 0xffff; 2533 2534 if (next_tss_desc.type & 8) 2535 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 2536 old_tss_base, &next_tss_desc); 2537 else 2538 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 2539 old_tss_base, &next_tss_desc); 2540 if (ret != X86EMUL_CONTINUE) 2541 return ret; 2542 2543 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2544 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2545 2546 if (reason != TASK_SWITCH_IRET) { 2547 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2548 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2549 } 2550 2551 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2552 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2553 2554 if (has_error_code) { 2555 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2556 ctxt->lock_prefix = 0; 2557 ctxt->src.val = (unsigned long) error_code; 2558 ret = em_push(ctxt); 2559 } 2560 2561 return ret; 2562 } 2563 2564 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2565 u16 tss_selector, int idt_index, int reason, 2566 bool has_error_code, u32 error_code) 2567 { 2568 int rc; 2569 2570 ctxt->_eip = ctxt->eip; 2571 ctxt->dst.type = OP_NONE; 2572 2573 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2574 has_error_code, error_code); 2575 2576 if (rc == X86EMUL_CONTINUE) 2577 ctxt->eip = ctxt->_eip; 2578 2579 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2580 } 2581 2582 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, 2583 int reg, struct operand *op) 2584 { 2585 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; 2586 2587 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes); 2588 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]); 2589 op->addr.mem.seg = seg; 2590 } 2591 2592 static int em_das(struct x86_emulate_ctxt *ctxt) 2593 { 2594 u8 al, old_al; 2595 bool af, cf, old_cf; 2596 2597 cf = ctxt->eflags & X86_EFLAGS_CF; 2598 al = ctxt->dst.val; 2599 2600 old_al = al; 2601 old_cf = cf; 2602 cf = false; 2603 af = ctxt->eflags & X86_EFLAGS_AF; 2604 if ((al & 0x0f) > 9 || af) { 2605 al -= 6; 2606 cf = old_cf | (al >= 250); 2607 af = true; 2608 } else { 2609 af = false; 2610 } 2611 if (old_al > 0x99 || old_cf) { 2612 al -= 0x60; 2613 cf = true; 2614 } 2615 2616 ctxt->dst.val = al; 2617 /* Set PF, ZF, SF */ 2618 ctxt->src.type = OP_IMM; 2619 ctxt->src.val = 0; 2620 ctxt->src.bytes = 1; 2621 emulate_2op_SrcV(ctxt, "or"); 2622 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 2623 if (cf) 2624 ctxt->eflags |= X86_EFLAGS_CF; 2625 if (af) 2626 ctxt->eflags |= X86_EFLAGS_AF; 2627 return X86EMUL_CONTINUE; 2628 } 2629 2630 static int em_call(struct x86_emulate_ctxt *ctxt) 2631 { 2632 long rel = ctxt->src.val; 2633 2634 ctxt->src.val = (unsigned long)ctxt->_eip; 2635 jmp_rel(ctxt, rel); 2636 return em_push(ctxt); 2637 } 2638 2639 static int em_call_far(struct x86_emulate_ctxt *ctxt) 2640 { 2641 u16 sel, old_cs; 2642 ulong old_eip; 2643 int rc; 2644 2645 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2646 old_eip = ctxt->_eip; 2647 2648 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2649 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) 2650 return X86EMUL_CONTINUE; 2651 2652 ctxt->_eip = 0; 2653 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 2654 2655 ctxt->src.val = old_cs; 2656 rc = em_push(ctxt); 2657 if (rc != X86EMUL_CONTINUE) 2658 return rc; 2659 2660 ctxt->src.val = old_eip; 2661 return em_push(ctxt); 2662 } 2663 2664 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 2665 { 2666 int rc; 2667 2668 ctxt->dst.type = OP_REG; 2669 ctxt->dst.addr.reg = &ctxt->_eip; 2670 ctxt->dst.bytes = ctxt->op_bytes; 2671 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 2672 if (rc != X86EMUL_CONTINUE) 2673 return rc; 2674 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); 2675 return X86EMUL_CONTINUE; 2676 } 2677 2678 static int em_add(struct x86_emulate_ctxt *ctxt) 2679 { 2680 emulate_2op_SrcV(ctxt, "add"); 2681 return X86EMUL_CONTINUE; 2682 } 2683 2684 static int em_or(struct x86_emulate_ctxt *ctxt) 2685 { 2686 emulate_2op_SrcV(ctxt, "or"); 2687 return X86EMUL_CONTINUE; 2688 } 2689 2690 static int em_adc(struct x86_emulate_ctxt *ctxt) 2691 { 2692 emulate_2op_SrcV(ctxt, "adc"); 2693 return X86EMUL_CONTINUE; 2694 } 2695 2696 static int em_sbb(struct x86_emulate_ctxt *ctxt) 2697 { 2698 emulate_2op_SrcV(ctxt, "sbb"); 2699 return X86EMUL_CONTINUE; 2700 } 2701 2702 static int em_and(struct x86_emulate_ctxt *ctxt) 2703 { 2704 emulate_2op_SrcV(ctxt, "and"); 2705 return X86EMUL_CONTINUE; 2706 } 2707 2708 static int em_sub(struct x86_emulate_ctxt *ctxt) 2709 { 2710 emulate_2op_SrcV(ctxt, "sub"); 2711 return X86EMUL_CONTINUE; 2712 } 2713 2714 static int em_xor(struct x86_emulate_ctxt *ctxt) 2715 { 2716 emulate_2op_SrcV(ctxt, "xor"); 2717 return X86EMUL_CONTINUE; 2718 } 2719 2720 static int em_cmp(struct x86_emulate_ctxt *ctxt) 2721 { 2722 emulate_2op_SrcV(ctxt, "cmp"); 2723 /* Disable writeback. */ 2724 ctxt->dst.type = OP_NONE; 2725 return X86EMUL_CONTINUE; 2726 } 2727 2728 static int em_test(struct x86_emulate_ctxt *ctxt) 2729 { 2730 emulate_2op_SrcV(ctxt, "test"); 2731 /* Disable writeback. */ 2732 ctxt->dst.type = OP_NONE; 2733 return X86EMUL_CONTINUE; 2734 } 2735 2736 static int em_xchg(struct x86_emulate_ctxt *ctxt) 2737 { 2738 /* Write back the register source. */ 2739 ctxt->src.val = ctxt->dst.val; 2740 write_register_operand(&ctxt->src); 2741 2742 /* Write back the memory destination with implicit LOCK prefix. */ 2743 ctxt->dst.val = ctxt->src.orig_val; 2744 ctxt->lock_prefix = 1; 2745 return X86EMUL_CONTINUE; 2746 } 2747 2748 static int em_imul(struct x86_emulate_ctxt *ctxt) 2749 { 2750 emulate_2op_SrcV_nobyte(ctxt, "imul"); 2751 return X86EMUL_CONTINUE; 2752 } 2753 2754 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 2755 { 2756 ctxt->dst.val = ctxt->src2.val; 2757 return em_imul(ctxt); 2758 } 2759 2760 static int em_cwd(struct x86_emulate_ctxt *ctxt) 2761 { 2762 ctxt->dst.type = OP_REG; 2763 ctxt->dst.bytes = ctxt->src.bytes; 2764 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX]; 2765 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 2766 2767 return X86EMUL_CONTINUE; 2768 } 2769 2770 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 2771 { 2772 u64 tsc = 0; 2773 2774 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 2775 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc; 2776 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32; 2777 return X86EMUL_CONTINUE; 2778 } 2779 2780 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 2781 { 2782 u64 pmc; 2783 2784 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc)) 2785 return emulate_gp(ctxt, 0); 2786 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc; 2787 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32; 2788 return X86EMUL_CONTINUE; 2789 } 2790 2791 static int em_mov(struct x86_emulate_ctxt *ctxt) 2792 { 2793 ctxt->dst.val = ctxt->src.val; 2794 return X86EMUL_CONTINUE; 2795 } 2796 2797 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 2798 { 2799 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 2800 return emulate_gp(ctxt, 0); 2801 2802 /* Disable writeback. */ 2803 ctxt->dst.type = OP_NONE; 2804 return X86EMUL_CONTINUE; 2805 } 2806 2807 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 2808 { 2809 unsigned long val; 2810 2811 if (ctxt->mode == X86EMUL_MODE_PROT64) 2812 val = ctxt->src.val & ~0ULL; 2813 else 2814 val = ctxt->src.val & ~0U; 2815 2816 /* #UD condition is already handled. */ 2817 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 2818 return emulate_gp(ctxt, 0); 2819 2820 /* Disable writeback. */ 2821 ctxt->dst.type = OP_NONE; 2822 return X86EMUL_CONTINUE; 2823 } 2824 2825 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 2826 { 2827 u64 msr_data; 2828 2829 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX] 2830 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32); 2831 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) 2832 return emulate_gp(ctxt, 0); 2833 2834 return X86EMUL_CONTINUE; 2835 } 2836 2837 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 2838 { 2839 u64 msr_data; 2840 2841 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) 2842 return emulate_gp(ctxt, 0); 2843 2844 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data; 2845 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32; 2846 return X86EMUL_CONTINUE; 2847 } 2848 2849 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 2850 { 2851 if (ctxt->modrm_reg > VCPU_SREG_GS) 2852 return emulate_ud(ctxt); 2853 2854 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 2855 return X86EMUL_CONTINUE; 2856 } 2857 2858 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 2859 { 2860 u16 sel = ctxt->src.val; 2861 2862 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 2863 return emulate_ud(ctxt); 2864 2865 if (ctxt->modrm_reg == VCPU_SREG_SS) 2866 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 2867 2868 /* Disable writeback. */ 2869 ctxt->dst.type = OP_NONE; 2870 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 2871 } 2872 2873 static int em_movdqu(struct x86_emulate_ctxt *ctxt) 2874 { 2875 memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes); 2876 return X86EMUL_CONTINUE; 2877 } 2878 2879 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 2880 { 2881 int rc; 2882 ulong linear; 2883 2884 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 2885 if (rc == X86EMUL_CONTINUE) 2886 ctxt->ops->invlpg(ctxt, linear); 2887 /* Disable writeback. */ 2888 ctxt->dst.type = OP_NONE; 2889 return X86EMUL_CONTINUE; 2890 } 2891 2892 static int em_clts(struct x86_emulate_ctxt *ctxt) 2893 { 2894 ulong cr0; 2895 2896 cr0 = ctxt->ops->get_cr(ctxt, 0); 2897 cr0 &= ~X86_CR0_TS; 2898 ctxt->ops->set_cr(ctxt, 0, cr0); 2899 return X86EMUL_CONTINUE; 2900 } 2901 2902 static int em_vmcall(struct x86_emulate_ctxt *ctxt) 2903 { 2904 int rc; 2905 2906 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) 2907 return X86EMUL_UNHANDLEABLE; 2908 2909 rc = ctxt->ops->fix_hypercall(ctxt); 2910 if (rc != X86EMUL_CONTINUE) 2911 return rc; 2912 2913 /* Let the processor re-execute the fixed hypercall */ 2914 ctxt->_eip = ctxt->eip; 2915 /* Disable writeback. */ 2916 ctxt->dst.type = OP_NONE; 2917 return X86EMUL_CONTINUE; 2918 } 2919 2920 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 2921 { 2922 struct desc_ptr desc_ptr; 2923 int rc; 2924 2925 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 2926 &desc_ptr.size, &desc_ptr.address, 2927 ctxt->op_bytes); 2928 if (rc != X86EMUL_CONTINUE) 2929 return rc; 2930 ctxt->ops->set_gdt(ctxt, &desc_ptr); 2931 /* Disable writeback. */ 2932 ctxt->dst.type = OP_NONE; 2933 return X86EMUL_CONTINUE; 2934 } 2935 2936 static int em_vmmcall(struct x86_emulate_ctxt *ctxt) 2937 { 2938 int rc; 2939 2940 rc = ctxt->ops->fix_hypercall(ctxt); 2941 2942 /* Disable writeback. */ 2943 ctxt->dst.type = OP_NONE; 2944 return rc; 2945 } 2946 2947 static int em_lidt(struct x86_emulate_ctxt *ctxt) 2948 { 2949 struct desc_ptr desc_ptr; 2950 int rc; 2951 2952 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 2953 &desc_ptr.size, &desc_ptr.address, 2954 ctxt->op_bytes); 2955 if (rc != X86EMUL_CONTINUE) 2956 return rc; 2957 ctxt->ops->set_idt(ctxt, &desc_ptr); 2958 /* Disable writeback. */ 2959 ctxt->dst.type = OP_NONE; 2960 return X86EMUL_CONTINUE; 2961 } 2962 2963 static int em_smsw(struct x86_emulate_ctxt *ctxt) 2964 { 2965 ctxt->dst.bytes = 2; 2966 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 2967 return X86EMUL_CONTINUE; 2968 } 2969 2970 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 2971 { 2972 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 2973 | (ctxt->src.val & 0x0f)); 2974 ctxt->dst.type = OP_NONE; 2975 return X86EMUL_CONTINUE; 2976 } 2977 2978 static int em_loop(struct x86_emulate_ctxt *ctxt) 2979 { 2980 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); 2981 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) && 2982 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 2983 jmp_rel(ctxt, ctxt->src.val); 2984 2985 return X86EMUL_CONTINUE; 2986 } 2987 2988 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 2989 { 2990 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) 2991 jmp_rel(ctxt, ctxt->src.val); 2992 2993 return X86EMUL_CONTINUE; 2994 } 2995 2996 static int em_in(struct x86_emulate_ctxt *ctxt) 2997 { 2998 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 2999 &ctxt->dst.val)) 3000 return X86EMUL_IO_NEEDED; 3001 3002 return X86EMUL_CONTINUE; 3003 } 3004 3005 static int em_out(struct x86_emulate_ctxt *ctxt) 3006 { 3007 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3008 &ctxt->src.val, 1); 3009 /* Disable writeback. */ 3010 ctxt->dst.type = OP_NONE; 3011 return X86EMUL_CONTINUE; 3012 } 3013 3014 static int em_cli(struct x86_emulate_ctxt *ctxt) 3015 { 3016 if (emulator_bad_iopl(ctxt)) 3017 return emulate_gp(ctxt, 0); 3018 3019 ctxt->eflags &= ~X86_EFLAGS_IF; 3020 return X86EMUL_CONTINUE; 3021 } 3022 3023 static int em_sti(struct x86_emulate_ctxt *ctxt) 3024 { 3025 if (emulator_bad_iopl(ctxt)) 3026 return emulate_gp(ctxt, 0); 3027 3028 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3029 ctxt->eflags |= X86_EFLAGS_IF; 3030 return X86EMUL_CONTINUE; 3031 } 3032 3033 static int em_bt(struct x86_emulate_ctxt *ctxt) 3034 { 3035 /* Disable writeback. */ 3036 ctxt->dst.type = OP_NONE; 3037 /* only subword offset */ 3038 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 3039 3040 emulate_2op_SrcV_nobyte(ctxt, "bt"); 3041 return X86EMUL_CONTINUE; 3042 } 3043 3044 static int em_bts(struct x86_emulate_ctxt *ctxt) 3045 { 3046 emulate_2op_SrcV_nobyte(ctxt, "bts"); 3047 return X86EMUL_CONTINUE; 3048 } 3049 3050 static int em_btr(struct x86_emulate_ctxt *ctxt) 3051 { 3052 emulate_2op_SrcV_nobyte(ctxt, "btr"); 3053 return X86EMUL_CONTINUE; 3054 } 3055 3056 static int em_btc(struct x86_emulate_ctxt *ctxt) 3057 { 3058 emulate_2op_SrcV_nobyte(ctxt, "btc"); 3059 return X86EMUL_CONTINUE; 3060 } 3061 3062 static int em_bsf(struct x86_emulate_ctxt *ctxt) 3063 { 3064 u8 zf; 3065 3066 __asm__ ("bsf %2, %0; setz %1" 3067 : "=r"(ctxt->dst.val), "=q"(zf) 3068 : "r"(ctxt->src.val)); 3069 3070 ctxt->eflags &= ~X86_EFLAGS_ZF; 3071 if (zf) { 3072 ctxt->eflags |= X86_EFLAGS_ZF; 3073 /* Disable writeback. */ 3074 ctxt->dst.type = OP_NONE; 3075 } 3076 return X86EMUL_CONTINUE; 3077 } 3078 3079 static int em_bsr(struct x86_emulate_ctxt *ctxt) 3080 { 3081 u8 zf; 3082 3083 __asm__ ("bsr %2, %0; setz %1" 3084 : "=r"(ctxt->dst.val), "=q"(zf) 3085 : "r"(ctxt->src.val)); 3086 3087 ctxt->eflags &= ~X86_EFLAGS_ZF; 3088 if (zf) { 3089 ctxt->eflags |= X86_EFLAGS_ZF; 3090 /* Disable writeback. */ 3091 ctxt->dst.type = OP_NONE; 3092 } 3093 return X86EMUL_CONTINUE; 3094 } 3095 3096 static bool valid_cr(int nr) 3097 { 3098 switch (nr) { 3099 case 0: 3100 case 2 ... 4: 3101 case 8: 3102 return true; 3103 default: 3104 return false; 3105 } 3106 } 3107 3108 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 3109 { 3110 if (!valid_cr(ctxt->modrm_reg)) 3111 return emulate_ud(ctxt); 3112 3113 return X86EMUL_CONTINUE; 3114 } 3115 3116 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 3117 { 3118 u64 new_val = ctxt->src.val64; 3119 int cr = ctxt->modrm_reg; 3120 u64 efer = 0; 3121 3122 static u64 cr_reserved_bits[] = { 3123 0xffffffff00000000ULL, 3124 0, 0, 0, /* CR3 checked later */ 3125 CR4_RESERVED_BITS, 3126 0, 0, 0, 3127 CR8_RESERVED_BITS, 3128 }; 3129 3130 if (!valid_cr(cr)) 3131 return emulate_ud(ctxt); 3132 3133 if (new_val & cr_reserved_bits[cr]) 3134 return emulate_gp(ctxt, 0); 3135 3136 switch (cr) { 3137 case 0: { 3138 u64 cr4; 3139 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 3140 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 3141 return emulate_gp(ctxt, 0); 3142 3143 cr4 = ctxt->ops->get_cr(ctxt, 4); 3144 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3145 3146 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 3147 !(cr4 & X86_CR4_PAE)) 3148 return emulate_gp(ctxt, 0); 3149 3150 break; 3151 } 3152 case 3: { 3153 u64 rsvd = 0; 3154 3155 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3156 if (efer & EFER_LMA) 3157 rsvd = CR3_L_MODE_RESERVED_BITS; 3158 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) 3159 rsvd = CR3_PAE_RESERVED_BITS; 3160 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) 3161 rsvd = CR3_NONPAE_RESERVED_BITS; 3162 3163 if (new_val & rsvd) 3164 return emulate_gp(ctxt, 0); 3165 3166 break; 3167 } 3168 case 4: { 3169 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3170 3171 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 3172 return emulate_gp(ctxt, 0); 3173 3174 break; 3175 } 3176 } 3177 3178 return X86EMUL_CONTINUE; 3179 } 3180 3181 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3182 { 3183 unsigned long dr7; 3184 3185 ctxt->ops->get_dr(ctxt, 7, &dr7); 3186 3187 /* Check if DR7.Global_Enable is set */ 3188 return dr7 & (1 << 13); 3189 } 3190 3191 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3192 { 3193 int dr = ctxt->modrm_reg; 3194 u64 cr4; 3195 3196 if (dr > 7) 3197 return emulate_ud(ctxt); 3198 3199 cr4 = ctxt->ops->get_cr(ctxt, 4); 3200 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3201 return emulate_ud(ctxt); 3202 3203 if (check_dr7_gd(ctxt)) 3204 return emulate_db(ctxt); 3205 3206 return X86EMUL_CONTINUE; 3207 } 3208 3209 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3210 { 3211 u64 new_val = ctxt->src.val64; 3212 int dr = ctxt->modrm_reg; 3213 3214 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3215 return emulate_gp(ctxt, 0); 3216 3217 return check_dr_read(ctxt); 3218 } 3219 3220 static int check_svme(struct x86_emulate_ctxt *ctxt) 3221 { 3222 u64 efer; 3223 3224 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3225 3226 if (!(efer & EFER_SVME)) 3227 return emulate_ud(ctxt); 3228 3229 return X86EMUL_CONTINUE; 3230 } 3231 3232 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3233 { 3234 u64 rax = ctxt->regs[VCPU_REGS_RAX]; 3235 3236 /* Valid physical address? */ 3237 if (rax & 0xffff000000000000ULL) 3238 return emulate_gp(ctxt, 0); 3239 3240 return check_svme(ctxt); 3241 } 3242 3243 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3244 { 3245 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3246 3247 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3248 return emulate_ud(ctxt); 3249 3250 return X86EMUL_CONTINUE; 3251 } 3252 3253 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3254 { 3255 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3256 u64 rcx = ctxt->regs[VCPU_REGS_RCX]; 3257 3258 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3259 (rcx > 3)) 3260 return emulate_gp(ctxt, 0); 3261 3262 return X86EMUL_CONTINUE; 3263 } 3264 3265 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3266 { 3267 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3268 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3269 return emulate_gp(ctxt, 0); 3270 3271 return X86EMUL_CONTINUE; 3272 } 3273 3274 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3275 { 3276 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3277 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3278 return emulate_gp(ctxt, 0); 3279 3280 return X86EMUL_CONTINUE; 3281 } 3282 3283 #define D(_y) { .flags = (_y) } 3284 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } 3285 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ 3286 .check_perm = (_p) } 3287 #define N D(0) 3288 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3289 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) } 3290 #define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) } 3291 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3292 #define II(_f, _e, _i) \ 3293 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } 3294 #define IIP(_f, _e, _i, _p) \ 3295 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ 3296 .check_perm = (_p) } 3297 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3298 3299 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3300 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3301 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3302 #define I2bvIP(_f, _e, _i, _p) \ 3303 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3304 3305 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3306 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3307 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3308 3309 static struct opcode group7_rm1[] = { 3310 DI(SrcNone | ModRM | Priv, monitor), 3311 DI(SrcNone | ModRM | Priv, mwait), 3312 N, N, N, N, N, N, 3313 }; 3314 3315 static struct opcode group7_rm3[] = { 3316 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa), 3317 II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall), 3318 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa), 3319 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa), 3320 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme), 3321 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme), 3322 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme), 3323 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme), 3324 }; 3325 3326 static struct opcode group7_rm7[] = { 3327 N, 3328 DIP(SrcNone | ModRM, rdtscp, check_rdtsc), 3329 N, N, N, N, N, N, 3330 }; 3331 3332 static struct opcode group1[] = { 3333 I(Lock, em_add), 3334 I(Lock | PageTable, em_or), 3335 I(Lock, em_adc), 3336 I(Lock, em_sbb), 3337 I(Lock | PageTable, em_and), 3338 I(Lock, em_sub), 3339 I(Lock, em_xor), 3340 I(0, em_cmp), 3341 }; 3342 3343 static struct opcode group1A[] = { 3344 I(DstMem | SrcNone | ModRM | Mov | Stack, em_pop), N, N, N, N, N, N, N, 3345 }; 3346 3347 static struct opcode group3[] = { 3348 I(DstMem | SrcImm | ModRM, em_test), 3349 I(DstMem | SrcImm | ModRM, em_test), 3350 I(DstMem | SrcNone | ModRM | Lock, em_not), 3351 I(DstMem | SrcNone | ModRM | Lock, em_neg), 3352 I(SrcMem | ModRM, em_mul_ex), 3353 I(SrcMem | ModRM, em_imul_ex), 3354 I(SrcMem | ModRM, em_div_ex), 3355 I(SrcMem | ModRM, em_idiv_ex), 3356 }; 3357 3358 static struct opcode group4[] = { 3359 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), 3360 I(ByteOp | DstMem | SrcNone | ModRM | Lock, em_grp45), 3361 N, N, N, N, N, N, 3362 }; 3363 3364 static struct opcode group5[] = { 3365 I(DstMem | SrcNone | ModRM | Lock, em_grp45), 3366 I(DstMem | SrcNone | ModRM | Lock, em_grp45), 3367 I(SrcMem | ModRM | Stack, em_grp45), 3368 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far), 3369 I(SrcMem | ModRM | Stack, em_grp45), 3370 I(SrcMemFAddr | ModRM | ImplicitOps, em_grp45), 3371 I(SrcMem | ModRM | Stack, em_grp45), N, 3372 }; 3373 3374 static struct opcode group6[] = { 3375 DI(ModRM | Prot, sldt), 3376 DI(ModRM | Prot, str), 3377 DI(ModRM | Prot | Priv, lldt), 3378 DI(ModRM | Prot | Priv, ltr), 3379 N, N, N, N, 3380 }; 3381 3382 static struct group_dual group7 = { { 3383 DI(ModRM | Mov | DstMem | Priv, sgdt), 3384 DI(ModRM | Mov | DstMem | Priv, sidt), 3385 II(ModRM | SrcMem | Priv, em_lgdt, lgdt), 3386 II(ModRM | SrcMem | Priv, em_lidt, lidt), 3387 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, 3388 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), 3389 II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 3390 }, { 3391 I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall), 3392 EXT(0, group7_rm1), 3393 N, EXT(0, group7_rm3), 3394 II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N, 3395 II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7), 3396 } }; 3397 3398 static struct opcode group8[] = { 3399 N, N, N, N, 3400 I(DstMem | SrcImmByte | ModRM, em_bt), 3401 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_bts), 3402 I(DstMem | SrcImmByte | ModRM | Lock, em_btr), 3403 I(DstMem | SrcImmByte | ModRM | Lock | PageTable, em_btc), 3404 }; 3405 3406 static struct group_dual group9 = { { 3407 N, I(DstMem64 | ModRM | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 3408 }, { 3409 N, N, N, N, N, N, N, N, 3410 } }; 3411 3412 static struct opcode group11[] = { 3413 I(DstMem | SrcImm | ModRM | Mov | PageTable, em_mov), 3414 X7(D(Undefined)), 3415 }; 3416 3417 static struct gprefix pfx_0f_6f_0f_7f = { 3418 N, N, N, I(Sse, em_movdqu), 3419 }; 3420 3421 static struct opcode opcode_table[256] = { 3422 /* 0x00 - 0x07 */ 3423 I6ALU(Lock, em_add), 3424 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 3425 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 3426 /* 0x08 - 0x0F */ 3427 I6ALU(Lock | PageTable, em_or), 3428 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 3429 N, 3430 /* 0x10 - 0x17 */ 3431 I6ALU(Lock, em_adc), 3432 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 3433 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 3434 /* 0x18 - 0x1F */ 3435 I6ALU(Lock, em_sbb), 3436 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 3437 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 3438 /* 0x20 - 0x27 */ 3439 I6ALU(Lock | PageTable, em_and), N, N, 3440 /* 0x28 - 0x2F */ 3441 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 3442 /* 0x30 - 0x37 */ 3443 I6ALU(Lock, em_xor), N, N, 3444 /* 0x38 - 0x3F */ 3445 I6ALU(0, em_cmp), N, N, 3446 /* 0x40 - 0x4F */ 3447 X16(D(DstReg)), 3448 /* 0x50 - 0x57 */ 3449 X8(I(SrcReg | Stack, em_push)), 3450 /* 0x58 - 0x5F */ 3451 X8(I(DstReg | Stack, em_pop)), 3452 /* 0x60 - 0x67 */ 3453 I(ImplicitOps | Stack | No64, em_pusha), 3454 I(ImplicitOps | Stack | No64, em_popa), 3455 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , 3456 N, N, N, N, 3457 /* 0x68 - 0x6F */ 3458 I(SrcImm | Mov | Stack, em_push), 3459 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 3460 I(SrcImmByte | Mov | Stack, em_push), 3461 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 3462 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */ 3463 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 3464 /* 0x70 - 0x7F */ 3465 X16(D(SrcImmByte)), 3466 /* 0x80 - 0x87 */ 3467 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1), 3468 G(DstMem | SrcImm | ModRM | Group, group1), 3469 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1), 3470 G(DstMem | SrcImmByte | ModRM | Group, group1), 3471 I2bv(DstMem | SrcReg | ModRM, em_test), 3472 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 3473 /* 0x88 - 0x8F */ 3474 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 3475 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 3476 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 3477 D(ModRM | SrcMem | NoAccess | DstReg), 3478 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 3479 G(0, group1A), 3480 /* 0x90 - 0x97 */ 3481 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 3482 /* 0x98 - 0x9F */ 3483 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 3484 I(SrcImmFAddr | No64, em_call_far), N, 3485 II(ImplicitOps | Stack, em_pushf, pushf), 3486 II(ImplicitOps | Stack, em_popf, popf), N, N, 3487 /* 0xA0 - 0xA7 */ 3488 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 3489 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 3490 I2bv(SrcSI | DstDI | Mov | String, em_mov), 3491 I2bv(SrcSI | DstDI | String, em_cmp), 3492 /* 0xA8 - 0xAF */ 3493 I2bv(DstAcc | SrcImm, em_test), 3494 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 3495 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 3496 I2bv(SrcAcc | DstDI | String, em_cmp), 3497 /* 0xB0 - 0xB7 */ 3498 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 3499 /* 0xB8 - 0xBF */ 3500 X8(I(DstReg | SrcImm | Mov, em_mov)), 3501 /* 0xC0 - 0xC7 */ 3502 D2bv(DstMem | SrcImmByte | ModRM), 3503 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), 3504 I(ImplicitOps | Stack, em_ret), 3505 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 3506 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 3507 G(ByteOp, group11), G(0, group11), 3508 /* 0xC8 - 0xCF */ 3509 N, N, N, I(ImplicitOps | Stack, em_ret_far), 3510 D(ImplicitOps), DI(SrcImmByte, intn), 3511 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 3512 /* 0xD0 - 0xD7 */ 3513 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), 3514 N, N, N, N, 3515 /* 0xD8 - 0xDF */ 3516 N, N, N, N, N, N, N, N, 3517 /* 0xE0 - 0xE7 */ 3518 X3(I(SrcImmByte, em_loop)), 3519 I(SrcImmByte, em_jcxz), 3520 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 3521 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 3522 /* 0xE8 - 0xEF */ 3523 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), 3524 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), 3525 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 3526 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 3527 /* 0xF0 - 0xF7 */ 3528 N, DI(ImplicitOps, icebp), N, N, 3529 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 3530 G(ByteOp, group3), G(0, group3), 3531 /* 0xF8 - 0xFF */ 3532 D(ImplicitOps), D(ImplicitOps), 3533 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 3534 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 3535 }; 3536 3537 static struct opcode twobyte_table[256] = { 3538 /* 0x00 - 0x0F */ 3539 G(0, group6), GD(0, &group7), N, N, 3540 N, I(ImplicitOps | VendorSpecific, em_syscall), 3541 II(ImplicitOps | Priv, em_clts, clts), N, 3542 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 3543 N, D(ImplicitOps | ModRM), N, N, 3544 /* 0x10 - 0x1F */ 3545 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, 3546 /* 0x20 - 0x2F */ 3547 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), 3548 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), 3549 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), 3550 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), 3551 N, N, N, N, 3552 N, N, N, N, N, N, N, N, 3553 /* 0x30 - 0x3F */ 3554 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 3555 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 3556 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 3557 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 3558 I(ImplicitOps | VendorSpecific, em_sysenter), 3559 I(ImplicitOps | Priv | VendorSpecific, em_sysexit), 3560 N, N, 3561 N, N, N, N, N, N, N, N, 3562 /* 0x40 - 0x4F */ 3563 X16(D(DstReg | SrcMem | ModRM | Mov)), 3564 /* 0x50 - 0x5F */ 3565 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3566 /* 0x60 - 0x6F */ 3567 N, N, N, N, 3568 N, N, N, N, 3569 N, N, N, N, 3570 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 3571 /* 0x70 - 0x7F */ 3572 N, N, N, N, 3573 N, N, N, N, 3574 N, N, N, N, 3575 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 3576 /* 0x80 - 0x8F */ 3577 X16(D(SrcImm)), 3578 /* 0x90 - 0x9F */ 3579 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 3580 /* 0xA0 - 0xA7 */ 3581 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 3582 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt), 3583 D(DstMem | SrcReg | Src2ImmByte | ModRM), 3584 D(DstMem | SrcReg | Src2CL | ModRM), N, N, 3585 /* 0xA8 - 0xAF */ 3586 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 3587 DI(ImplicitOps, rsm), 3588 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 3589 D(DstMem | SrcReg | Src2ImmByte | ModRM), 3590 D(DstMem | SrcReg | Src2CL | ModRM), 3591 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), 3592 /* 0xB0 - 0xB7 */ 3593 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), 3594 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 3595 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 3596 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 3597 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 3598 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3599 /* 0xB8 - 0xBF */ 3600 N, N, 3601 G(BitOp, group8), 3602 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 3603 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr), 3604 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3605 /* 0xC0 - 0xCF */ 3606 D2bv(DstMem | SrcReg | ModRM | Lock), 3607 N, D(DstMem | SrcReg | ModRM | Mov), 3608 N, N, N, GD(0, &group9), 3609 N, N, N, N, N, N, N, N, 3610 /* 0xD0 - 0xDF */ 3611 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3612 /* 0xE0 - 0xEF */ 3613 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3614 /* 0xF0 - 0xFF */ 3615 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 3616 }; 3617 3618 #undef D 3619 #undef N 3620 #undef G 3621 #undef GD 3622 #undef I 3623 #undef GP 3624 #undef EXT 3625 3626 #undef D2bv 3627 #undef D2bvIP 3628 #undef I2bv 3629 #undef I2bvIP 3630 #undef I6ALU 3631 3632 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 3633 { 3634 unsigned size; 3635 3636 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3637 if (size == 8) 3638 size = 4; 3639 return size; 3640 } 3641 3642 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 3643 unsigned size, bool sign_extension) 3644 { 3645 int rc = X86EMUL_CONTINUE; 3646 3647 op->type = OP_IMM; 3648 op->bytes = size; 3649 op->addr.mem.ea = ctxt->_eip; 3650 /* NB. Immediates are sign-extended as necessary. */ 3651 switch (op->bytes) { 3652 case 1: 3653 op->val = insn_fetch(s8, ctxt); 3654 break; 3655 case 2: 3656 op->val = insn_fetch(s16, ctxt); 3657 break; 3658 case 4: 3659 op->val = insn_fetch(s32, ctxt); 3660 break; 3661 } 3662 if (!sign_extension) { 3663 switch (op->bytes) { 3664 case 1: 3665 op->val &= 0xff; 3666 break; 3667 case 2: 3668 op->val &= 0xffff; 3669 break; 3670 case 4: 3671 op->val &= 0xffffffff; 3672 break; 3673 } 3674 } 3675 done: 3676 return rc; 3677 } 3678 3679 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 3680 unsigned d) 3681 { 3682 int rc = X86EMUL_CONTINUE; 3683 3684 switch (d) { 3685 case OpReg: 3686 decode_register_operand(ctxt, op); 3687 break; 3688 case OpImmUByte: 3689 rc = decode_imm(ctxt, op, 1, false); 3690 break; 3691 case OpMem: 3692 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3693 mem_common: 3694 *op = ctxt->memop; 3695 ctxt->memopp = op; 3696 if ((ctxt->d & BitOp) && op == &ctxt->dst) 3697 fetch_bit_operand(ctxt); 3698 op->orig_val = op->val; 3699 break; 3700 case OpMem64: 3701 ctxt->memop.bytes = 8; 3702 goto mem_common; 3703 case OpAcc: 3704 op->type = OP_REG; 3705 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3706 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX]; 3707 fetch_register_operand(op); 3708 op->orig_val = op->val; 3709 break; 3710 case OpDI: 3711 op->type = OP_MEM; 3712 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3713 op->addr.mem.ea = 3714 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]); 3715 op->addr.mem.seg = VCPU_SREG_ES; 3716 op->val = 0; 3717 break; 3718 case OpDX: 3719 op->type = OP_REG; 3720 op->bytes = 2; 3721 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX]; 3722 fetch_register_operand(op); 3723 break; 3724 case OpCL: 3725 op->bytes = 1; 3726 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff; 3727 break; 3728 case OpImmByte: 3729 rc = decode_imm(ctxt, op, 1, true); 3730 break; 3731 case OpOne: 3732 op->bytes = 1; 3733 op->val = 1; 3734 break; 3735 case OpImm: 3736 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 3737 break; 3738 case OpMem8: 3739 ctxt->memop.bytes = 1; 3740 goto mem_common; 3741 case OpMem16: 3742 ctxt->memop.bytes = 2; 3743 goto mem_common; 3744 case OpMem32: 3745 ctxt->memop.bytes = 4; 3746 goto mem_common; 3747 case OpImmU16: 3748 rc = decode_imm(ctxt, op, 2, false); 3749 break; 3750 case OpImmU: 3751 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 3752 break; 3753 case OpSI: 3754 op->type = OP_MEM; 3755 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3756 op->addr.mem.ea = 3757 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]); 3758 op->addr.mem.seg = seg_override(ctxt); 3759 op->val = 0; 3760 break; 3761 case OpImmFAddr: 3762 op->type = OP_IMM; 3763 op->addr.mem.ea = ctxt->_eip; 3764 op->bytes = ctxt->op_bytes + 2; 3765 insn_fetch_arr(op->valptr, op->bytes, ctxt); 3766 break; 3767 case OpMemFAddr: 3768 ctxt->memop.bytes = ctxt->op_bytes + 2; 3769 goto mem_common; 3770 case OpES: 3771 op->val = VCPU_SREG_ES; 3772 break; 3773 case OpCS: 3774 op->val = VCPU_SREG_CS; 3775 break; 3776 case OpSS: 3777 op->val = VCPU_SREG_SS; 3778 break; 3779 case OpDS: 3780 op->val = VCPU_SREG_DS; 3781 break; 3782 case OpFS: 3783 op->val = VCPU_SREG_FS; 3784 break; 3785 case OpGS: 3786 op->val = VCPU_SREG_GS; 3787 break; 3788 case OpImplicit: 3789 /* Special instructions do their own operand decoding. */ 3790 default: 3791 op->type = OP_NONE; /* Disable writeback. */ 3792 break; 3793 } 3794 3795 done: 3796 return rc; 3797 } 3798 3799 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 3800 { 3801 int rc = X86EMUL_CONTINUE; 3802 int mode = ctxt->mode; 3803 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 3804 bool op_prefix = false; 3805 struct opcode opcode; 3806 3807 ctxt->memop.type = OP_NONE; 3808 ctxt->memopp = NULL; 3809 ctxt->_eip = ctxt->eip; 3810 ctxt->fetch.start = ctxt->_eip; 3811 ctxt->fetch.end = ctxt->fetch.start + insn_len; 3812 if (insn_len > 0) 3813 memcpy(ctxt->fetch.data, insn, insn_len); 3814 3815 switch (mode) { 3816 case X86EMUL_MODE_REAL: 3817 case X86EMUL_MODE_VM86: 3818 case X86EMUL_MODE_PROT16: 3819 def_op_bytes = def_ad_bytes = 2; 3820 break; 3821 case X86EMUL_MODE_PROT32: 3822 def_op_bytes = def_ad_bytes = 4; 3823 break; 3824 #ifdef CONFIG_X86_64 3825 case X86EMUL_MODE_PROT64: 3826 def_op_bytes = 4; 3827 def_ad_bytes = 8; 3828 break; 3829 #endif 3830 default: 3831 return EMULATION_FAILED; 3832 } 3833 3834 ctxt->op_bytes = def_op_bytes; 3835 ctxt->ad_bytes = def_ad_bytes; 3836 3837 /* Legacy prefixes. */ 3838 for (;;) { 3839 switch (ctxt->b = insn_fetch(u8, ctxt)) { 3840 case 0x66: /* operand-size override */ 3841 op_prefix = true; 3842 /* switch between 2/4 bytes */ 3843 ctxt->op_bytes = def_op_bytes ^ 6; 3844 break; 3845 case 0x67: /* address-size override */ 3846 if (mode == X86EMUL_MODE_PROT64) 3847 /* switch between 4/8 bytes */ 3848 ctxt->ad_bytes = def_ad_bytes ^ 12; 3849 else 3850 /* switch between 2/4 bytes */ 3851 ctxt->ad_bytes = def_ad_bytes ^ 6; 3852 break; 3853 case 0x26: /* ES override */ 3854 case 0x2e: /* CS override */ 3855 case 0x36: /* SS override */ 3856 case 0x3e: /* DS override */ 3857 set_seg_override(ctxt, (ctxt->b >> 3) & 3); 3858 break; 3859 case 0x64: /* FS override */ 3860 case 0x65: /* GS override */ 3861 set_seg_override(ctxt, ctxt->b & 7); 3862 break; 3863 case 0x40 ... 0x4f: /* REX */ 3864 if (mode != X86EMUL_MODE_PROT64) 3865 goto done_prefixes; 3866 ctxt->rex_prefix = ctxt->b; 3867 continue; 3868 case 0xf0: /* LOCK */ 3869 ctxt->lock_prefix = 1; 3870 break; 3871 case 0xf2: /* REPNE/REPNZ */ 3872 case 0xf3: /* REP/REPE/REPZ */ 3873 ctxt->rep_prefix = ctxt->b; 3874 break; 3875 default: 3876 goto done_prefixes; 3877 } 3878 3879 /* Any legacy prefix after a REX prefix nullifies its effect. */ 3880 3881 ctxt->rex_prefix = 0; 3882 } 3883 3884 done_prefixes: 3885 3886 /* REX prefix. */ 3887 if (ctxt->rex_prefix & 8) 3888 ctxt->op_bytes = 8; /* REX.W */ 3889 3890 /* Opcode byte(s). */ 3891 opcode = opcode_table[ctxt->b]; 3892 /* Two-byte opcode? */ 3893 if (ctxt->b == 0x0f) { 3894 ctxt->twobyte = 1; 3895 ctxt->b = insn_fetch(u8, ctxt); 3896 opcode = twobyte_table[ctxt->b]; 3897 } 3898 ctxt->d = opcode.flags; 3899 3900 while (ctxt->d & GroupMask) { 3901 switch (ctxt->d & GroupMask) { 3902 case Group: 3903 ctxt->modrm = insn_fetch(u8, ctxt); 3904 --ctxt->_eip; 3905 goffset = (ctxt->modrm >> 3) & 7; 3906 opcode = opcode.u.group[goffset]; 3907 break; 3908 case GroupDual: 3909 ctxt->modrm = insn_fetch(u8, ctxt); 3910 --ctxt->_eip; 3911 goffset = (ctxt->modrm >> 3) & 7; 3912 if ((ctxt->modrm >> 6) == 3) 3913 opcode = opcode.u.gdual->mod3[goffset]; 3914 else 3915 opcode = opcode.u.gdual->mod012[goffset]; 3916 break; 3917 case RMExt: 3918 goffset = ctxt->modrm & 7; 3919 opcode = opcode.u.group[goffset]; 3920 break; 3921 case Prefix: 3922 if (ctxt->rep_prefix && op_prefix) 3923 return EMULATION_FAILED; 3924 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 3925 switch (simd_prefix) { 3926 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 3927 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 3928 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 3929 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 3930 } 3931 break; 3932 default: 3933 return EMULATION_FAILED; 3934 } 3935 3936 ctxt->d &= ~(u64)GroupMask; 3937 ctxt->d |= opcode.flags; 3938 } 3939 3940 ctxt->execute = opcode.u.execute; 3941 ctxt->check_perm = opcode.check_perm; 3942 ctxt->intercept = opcode.intercept; 3943 3944 /* Unrecognised? */ 3945 if (ctxt->d == 0 || (ctxt->d & Undefined)) 3946 return EMULATION_FAILED; 3947 3948 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) 3949 return EMULATION_FAILED; 3950 3951 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) 3952 ctxt->op_bytes = 8; 3953 3954 if (ctxt->d & Op3264) { 3955 if (mode == X86EMUL_MODE_PROT64) 3956 ctxt->op_bytes = 8; 3957 else 3958 ctxt->op_bytes = 4; 3959 } 3960 3961 if (ctxt->d & Sse) 3962 ctxt->op_bytes = 16; 3963 3964 /* ModRM and SIB bytes. */ 3965 if (ctxt->d & ModRM) { 3966 rc = decode_modrm(ctxt, &ctxt->memop); 3967 if (!ctxt->has_seg_override) 3968 set_seg_override(ctxt, ctxt->modrm_seg); 3969 } else if (ctxt->d & MemAbs) 3970 rc = decode_abs(ctxt, &ctxt->memop); 3971 if (rc != X86EMUL_CONTINUE) 3972 goto done; 3973 3974 if (!ctxt->has_seg_override) 3975 set_seg_override(ctxt, VCPU_SREG_DS); 3976 3977 ctxt->memop.addr.mem.seg = seg_override(ctxt); 3978 3979 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) 3980 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 3981 3982 /* 3983 * Decode and fetch the source operand: register, memory 3984 * or immediate. 3985 */ 3986 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 3987 if (rc != X86EMUL_CONTINUE) 3988 goto done; 3989 3990 /* 3991 * Decode and fetch the second source operand: register, memory 3992 * or immediate. 3993 */ 3994 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 3995 if (rc != X86EMUL_CONTINUE) 3996 goto done; 3997 3998 /* Decode and fetch the destination operand: register or memory. */ 3999 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 4000 4001 done: 4002 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) 4003 ctxt->memopp->addr.mem.ea += ctxt->_eip; 4004 4005 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 4006 } 4007 4008 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 4009 { 4010 return ctxt->d & PageTable; 4011 } 4012 4013 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 4014 { 4015 /* The second termination condition only applies for REPE 4016 * and REPNE. Test if the repeat string operation prefix is 4017 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 4018 * corresponding termination condition according to: 4019 * - if REPE/REPZ and ZF = 0 then done 4020 * - if REPNE/REPNZ and ZF = 1 then done 4021 */ 4022 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 4023 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 4024 && (((ctxt->rep_prefix == REPE_PREFIX) && 4025 ((ctxt->eflags & EFLG_ZF) == 0)) 4026 || ((ctxt->rep_prefix == REPNE_PREFIX) && 4027 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) 4028 return true; 4029 4030 return false; 4031 } 4032 4033 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 4034 { 4035 struct x86_emulate_ops *ops = ctxt->ops; 4036 int rc = X86EMUL_CONTINUE; 4037 int saved_dst_type = ctxt->dst.type; 4038 4039 ctxt->mem_read.pos = 0; 4040 4041 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { 4042 rc = emulate_ud(ctxt); 4043 goto done; 4044 } 4045 4046 /* LOCK prefix is allowed only with some instructions */ 4047 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 4048 rc = emulate_ud(ctxt); 4049 goto done; 4050 } 4051 4052 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 4053 rc = emulate_ud(ctxt); 4054 goto done; 4055 } 4056 4057 if ((ctxt->d & Sse) 4058 && ((ops->get_cr(ctxt, 0) & X86_CR0_EM) 4059 || !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 4060 rc = emulate_ud(ctxt); 4061 goto done; 4062 } 4063 4064 if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 4065 rc = emulate_nm(ctxt); 4066 goto done; 4067 } 4068 4069 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4070 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4071 X86_ICPT_PRE_EXCEPT); 4072 if (rc != X86EMUL_CONTINUE) 4073 goto done; 4074 } 4075 4076 /* Privileged instruction can be executed only in CPL=0 */ 4077 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 4078 rc = emulate_gp(ctxt, 0); 4079 goto done; 4080 } 4081 4082 /* Instruction can only be executed in protected mode */ 4083 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { 4084 rc = emulate_ud(ctxt); 4085 goto done; 4086 } 4087 4088 /* Do instruction specific permission checks */ 4089 if (ctxt->check_perm) { 4090 rc = ctxt->check_perm(ctxt); 4091 if (rc != X86EMUL_CONTINUE) 4092 goto done; 4093 } 4094 4095 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4096 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4097 X86_ICPT_POST_EXCEPT); 4098 if (rc != X86EMUL_CONTINUE) 4099 goto done; 4100 } 4101 4102 if (ctxt->rep_prefix && (ctxt->d & String)) { 4103 /* All REP prefixes have the same first termination condition */ 4104 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) { 4105 ctxt->eip = ctxt->_eip; 4106 goto done; 4107 } 4108 } 4109 4110 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 4111 rc = segmented_read(ctxt, ctxt->src.addr.mem, 4112 ctxt->src.valptr, ctxt->src.bytes); 4113 if (rc != X86EMUL_CONTINUE) 4114 goto done; 4115 ctxt->src.orig_val64 = ctxt->src.val64; 4116 } 4117 4118 if (ctxt->src2.type == OP_MEM) { 4119 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 4120 &ctxt->src2.val, ctxt->src2.bytes); 4121 if (rc != X86EMUL_CONTINUE) 4122 goto done; 4123 } 4124 4125 if ((ctxt->d & DstMask) == ImplicitOps) 4126 goto special_insn; 4127 4128 4129 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 4130 /* optimisation - avoid slow emulated read if Mov */ 4131 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 4132 &ctxt->dst.val, ctxt->dst.bytes); 4133 if (rc != X86EMUL_CONTINUE) 4134 goto done; 4135 } 4136 ctxt->dst.orig_val = ctxt->dst.val; 4137 4138 special_insn: 4139 4140 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4141 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4142 X86_ICPT_POST_MEMACCESS); 4143 if (rc != X86EMUL_CONTINUE) 4144 goto done; 4145 } 4146 4147 if (ctxt->execute) { 4148 rc = ctxt->execute(ctxt); 4149 if (rc != X86EMUL_CONTINUE) 4150 goto done; 4151 goto writeback; 4152 } 4153 4154 if (ctxt->twobyte) 4155 goto twobyte_insn; 4156 4157 switch (ctxt->b) { 4158 case 0x40 ... 0x47: /* inc r16/r32 */ 4159 emulate_1op(ctxt, "inc"); 4160 break; 4161 case 0x48 ... 0x4f: /* dec r16/r32 */ 4162 emulate_1op(ctxt, "dec"); 4163 break; 4164 case 0x63: /* movsxd */ 4165 if (ctxt->mode != X86EMUL_MODE_PROT64) 4166 goto cannot_emulate; 4167 ctxt->dst.val = (s32) ctxt->src.val; 4168 break; 4169 case 0x70 ... 0x7f: /* jcc (short) */ 4170 if (test_cc(ctxt->b, ctxt->eflags)) 4171 jmp_rel(ctxt, ctxt->src.val); 4172 break; 4173 case 0x8d: /* lea r16/r32, m */ 4174 ctxt->dst.val = ctxt->src.addr.mem.ea; 4175 break; 4176 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 4177 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX]) 4178 break; 4179 rc = em_xchg(ctxt); 4180 break; 4181 case 0x98: /* cbw/cwde/cdqe */ 4182 switch (ctxt->op_bytes) { 4183 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 4184 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 4185 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 4186 } 4187 break; 4188 case 0xc0 ... 0xc1: 4189 rc = em_grp2(ctxt); 4190 break; 4191 case 0xcc: /* int3 */ 4192 rc = emulate_int(ctxt, 3); 4193 break; 4194 case 0xcd: /* int n */ 4195 rc = emulate_int(ctxt, ctxt->src.val); 4196 break; 4197 case 0xce: /* into */ 4198 if (ctxt->eflags & EFLG_OF) 4199 rc = emulate_int(ctxt, 4); 4200 break; 4201 case 0xd0 ... 0xd1: /* Grp2 */ 4202 rc = em_grp2(ctxt); 4203 break; 4204 case 0xd2 ... 0xd3: /* Grp2 */ 4205 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX]; 4206 rc = em_grp2(ctxt); 4207 break; 4208 case 0xe9: /* jmp rel */ 4209 case 0xeb: /* jmp rel short */ 4210 jmp_rel(ctxt, ctxt->src.val); 4211 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 4212 break; 4213 case 0xf4: /* hlt */ 4214 ctxt->ops->halt(ctxt); 4215 break; 4216 case 0xf5: /* cmc */ 4217 /* complement carry flag from eflags reg */ 4218 ctxt->eflags ^= EFLG_CF; 4219 break; 4220 case 0xf8: /* clc */ 4221 ctxt->eflags &= ~EFLG_CF; 4222 break; 4223 case 0xf9: /* stc */ 4224 ctxt->eflags |= EFLG_CF; 4225 break; 4226 case 0xfc: /* cld */ 4227 ctxt->eflags &= ~EFLG_DF; 4228 break; 4229 case 0xfd: /* std */ 4230 ctxt->eflags |= EFLG_DF; 4231 break; 4232 default: 4233 goto cannot_emulate; 4234 } 4235 4236 if (rc != X86EMUL_CONTINUE) 4237 goto done; 4238 4239 writeback: 4240 rc = writeback(ctxt); 4241 if (rc != X86EMUL_CONTINUE) 4242 goto done; 4243 4244 /* 4245 * restore dst type in case the decoding will be reused 4246 * (happens for string instruction ) 4247 */ 4248 ctxt->dst.type = saved_dst_type; 4249 4250 if ((ctxt->d & SrcMask) == SrcSI) 4251 string_addr_inc(ctxt, seg_override(ctxt), 4252 VCPU_REGS_RSI, &ctxt->src); 4253 4254 if ((ctxt->d & DstMask) == DstDI) 4255 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, 4256 &ctxt->dst); 4257 4258 if (ctxt->rep_prefix && (ctxt->d & String)) { 4259 struct read_cache *r = &ctxt->io_read; 4260 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); 4261 4262 if (!string_insn_completed(ctxt)) { 4263 /* 4264 * Re-enter guest when pio read ahead buffer is empty 4265 * or, if it is not used, after each 1024 iteration. 4266 */ 4267 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) && 4268 (r->end == 0 || r->end != r->pos)) { 4269 /* 4270 * Reset read cache. Usually happens before 4271 * decode, but since instruction is restarted 4272 * we have to do it here. 4273 */ 4274 ctxt->mem_read.end = 0; 4275 return EMULATION_RESTART; 4276 } 4277 goto done; /* skip rip writeback */ 4278 } 4279 } 4280 4281 ctxt->eip = ctxt->_eip; 4282 4283 done: 4284 if (rc == X86EMUL_PROPAGATE_FAULT) 4285 ctxt->have_exception = true; 4286 if (rc == X86EMUL_INTERCEPTED) 4287 return EMULATION_INTERCEPTED; 4288 4289 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 4290 4291 twobyte_insn: 4292 switch (ctxt->b) { 4293 case 0x09: /* wbinvd */ 4294 (ctxt->ops->wbinvd)(ctxt); 4295 break; 4296 case 0x08: /* invd */ 4297 case 0x0d: /* GrpP (prefetch) */ 4298 case 0x18: /* Grp16 (prefetch/nop) */ 4299 break; 4300 case 0x20: /* mov cr, reg */ 4301 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 4302 break; 4303 case 0x21: /* mov from dr to reg */ 4304 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 4305 break; 4306 case 0x40 ... 0x4f: /* cmov */ 4307 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; 4308 if (!test_cc(ctxt->b, ctxt->eflags)) 4309 ctxt->dst.type = OP_NONE; /* no writeback */ 4310 break; 4311 case 0x80 ... 0x8f: /* jnz rel, etc*/ 4312 if (test_cc(ctxt->b, ctxt->eflags)) 4313 jmp_rel(ctxt, ctxt->src.val); 4314 break; 4315 case 0x90 ... 0x9f: /* setcc r/m8 */ 4316 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 4317 break; 4318 case 0xa4: /* shld imm8, r, r/m */ 4319 case 0xa5: /* shld cl, r, r/m */ 4320 emulate_2op_cl(ctxt, "shld"); 4321 break; 4322 case 0xac: /* shrd imm8, r, r/m */ 4323 case 0xad: /* shrd cl, r, r/m */ 4324 emulate_2op_cl(ctxt, "shrd"); 4325 break; 4326 case 0xae: /* clflush */ 4327 break; 4328 case 0xb6 ... 0xb7: /* movzx */ 4329 ctxt->dst.bytes = ctxt->op_bytes; 4330 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val 4331 : (u16) ctxt->src.val; 4332 break; 4333 case 0xbe ... 0xbf: /* movsx */ 4334 ctxt->dst.bytes = ctxt->op_bytes; 4335 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val : 4336 (s16) ctxt->src.val; 4337 break; 4338 case 0xc0 ... 0xc1: /* xadd */ 4339 emulate_2op_SrcV(ctxt, "add"); 4340 /* Write back the register source. */ 4341 ctxt->src.val = ctxt->dst.orig_val; 4342 write_register_operand(&ctxt->src); 4343 break; 4344 case 0xc3: /* movnti */ 4345 ctxt->dst.bytes = ctxt->op_bytes; 4346 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : 4347 (u64) ctxt->src.val; 4348 break; 4349 default: 4350 goto cannot_emulate; 4351 } 4352 4353 if (rc != X86EMUL_CONTINUE) 4354 goto done; 4355 4356 goto writeback; 4357 4358 cannot_emulate: 4359 return EMULATION_FAILED; 4360 } 4361