1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 21 #include <linux/kvm_host.h> 22 #include "kvm_cache_regs.h" 23 #include "kvm_emulate.h" 24 #include <linux/stringify.h> 25 #include <asm/debugreg.h> 26 #include <asm/nospec-branch.h> 27 #include <asm/ibt.h> 28 29 #include "x86.h" 30 #include "tss.h" 31 #include "mmu.h" 32 #include "pmu.h" 33 34 /* 35 * Operand types 36 */ 37 #define OpNone 0ull 38 #define OpImplicit 1ull /* No generic decode */ 39 #define OpReg 2ull /* Register */ 40 #define OpMem 3ull /* Memory */ 41 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 42 #define OpDI 5ull /* ES:DI/EDI/RDI */ 43 #define OpMem64 6ull /* Memory, 64-bit */ 44 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 45 #define OpDX 8ull /* DX register */ 46 #define OpCL 9ull /* CL register (for shifts) */ 47 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 48 #define OpOne 11ull /* Implied 1 */ 49 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 50 #define OpMem16 13ull /* Memory operand (16-bit). */ 51 #define OpMem32 14ull /* Memory operand (32-bit). */ 52 #define OpImmU 15ull /* Immediate operand, zero extended */ 53 #define OpSI 16ull /* SI/ESI/RSI */ 54 #define OpImmFAddr 17ull /* Immediate far address */ 55 #define OpMemFAddr 18ull /* Far address in memory */ 56 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 57 #define OpES 20ull /* ES */ 58 #define OpCS 21ull /* CS */ 59 #define OpSS 22ull /* SS */ 60 #define OpDS 23ull /* DS */ 61 #define OpFS 24ull /* FS */ 62 #define OpGS 25ull /* GS */ 63 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 64 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 65 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 66 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 67 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 68 69 #define OpBits 5 /* Width of operand field */ 70 #define OpMask ((1ull << OpBits) - 1) 71 72 /* 73 * Opcode effective-address decode tables. 74 * Note that we only emulate instructions that have at least one memory 75 * operand (excluding implicit stack references). We assume that stack 76 * references and instruction fetches will never occur in special memory 77 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 78 * not be handled. 79 */ 80 81 /* Operand sizes: 8-bit operands or specified/overridden size. */ 82 #define ByteOp (1<<0) /* 8-bit operands. */ 83 /* Destination operand type. */ 84 #define DstShift 1 85 #define ImplicitOps (OpImplicit << DstShift) 86 #define DstReg (OpReg << DstShift) 87 #define DstMem (OpMem << DstShift) 88 #define DstAcc (OpAcc << DstShift) 89 #define DstDI (OpDI << DstShift) 90 #define DstMem64 (OpMem64 << DstShift) 91 #define DstMem16 (OpMem16 << DstShift) 92 #define DstImmUByte (OpImmUByte << DstShift) 93 #define DstDX (OpDX << DstShift) 94 #define DstAccLo (OpAccLo << DstShift) 95 #define DstMask (OpMask << DstShift) 96 /* Source operand type. */ 97 #define SrcShift 6 98 #define SrcNone (OpNone << SrcShift) 99 #define SrcReg (OpReg << SrcShift) 100 #define SrcMem (OpMem << SrcShift) 101 #define SrcMem16 (OpMem16 << SrcShift) 102 #define SrcMem32 (OpMem32 << SrcShift) 103 #define SrcImm (OpImm << SrcShift) 104 #define SrcImmByte (OpImmByte << SrcShift) 105 #define SrcOne (OpOne << SrcShift) 106 #define SrcImmUByte (OpImmUByte << SrcShift) 107 #define SrcImmU (OpImmU << SrcShift) 108 #define SrcSI (OpSI << SrcShift) 109 #define SrcXLat (OpXLat << SrcShift) 110 #define SrcImmFAddr (OpImmFAddr << SrcShift) 111 #define SrcMemFAddr (OpMemFAddr << SrcShift) 112 #define SrcAcc (OpAcc << SrcShift) 113 #define SrcImmU16 (OpImmU16 << SrcShift) 114 #define SrcImm64 (OpImm64 << SrcShift) 115 #define SrcDX (OpDX << SrcShift) 116 #define SrcMem8 (OpMem8 << SrcShift) 117 #define SrcAccHi (OpAccHi << SrcShift) 118 #define SrcMask (OpMask << SrcShift) 119 #define BitOp (1<<11) 120 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 121 #define String (1<<13) /* String instruction (rep capable) */ 122 #define Stack (1<<14) /* Stack instruction (push/pop) */ 123 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 124 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 125 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 126 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 127 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 128 #define Escape (5<<15) /* Escape to coprocessor instruction */ 129 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 130 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 131 #define Sse (1<<18) /* SSE Vector instruction */ 132 /* Generic ModRM decode. */ 133 #define ModRM (1<<19) 134 /* Destination is only written; never read. */ 135 #define Mov (1<<20) 136 /* Misc flags */ 137 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 138 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 139 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 140 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 141 #define Undefined (1<<25) /* No Such Instruction */ 142 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 143 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 144 #define No64 (1<<28) 145 #define PageTable (1 << 29) /* instruction used to write page table */ 146 #define NotImpl (1 << 30) /* instruction is not implemented */ 147 /* Source 2 operand type */ 148 #define Src2Shift (31) 149 #define Src2None (OpNone << Src2Shift) 150 #define Src2Mem (OpMem << Src2Shift) 151 #define Src2CL (OpCL << Src2Shift) 152 #define Src2ImmByte (OpImmByte << Src2Shift) 153 #define Src2One (OpOne << Src2Shift) 154 #define Src2Imm (OpImm << Src2Shift) 155 #define Src2ES (OpES << Src2Shift) 156 #define Src2CS (OpCS << Src2Shift) 157 #define Src2SS (OpSS << Src2Shift) 158 #define Src2DS (OpDS << Src2Shift) 159 #define Src2FS (OpFS << Src2Shift) 160 #define Src2GS (OpGS << Src2Shift) 161 #define Src2Mask (OpMask << Src2Shift) 162 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 163 #define AlignMask ((u64)7 << 41) 164 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 165 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 166 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 167 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 168 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 169 #define NoWrite ((u64)1 << 45) /* No writeback */ 170 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 171 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 172 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 173 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 174 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 175 #define NearBranch ((u64)1 << 52) /* Near branches */ 176 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 177 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 178 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 179 #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ 180 181 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 182 183 #define X2(x...) x, x 184 #define X3(x...) X2(x), x 185 #define X4(x...) X2(x), X2(x) 186 #define X5(x...) X4(x), x 187 #define X6(x...) X4(x), X2(x) 188 #define X7(x...) X4(x), X3(x) 189 #define X8(x...) X4(x), X4(x) 190 #define X16(x...) X8(x), X8(x) 191 192 struct opcode { 193 u64 flags; 194 u8 intercept; 195 u8 pad[7]; 196 union { 197 int (*execute)(struct x86_emulate_ctxt *ctxt); 198 const struct opcode *group; 199 const struct group_dual *gdual; 200 const struct gprefix *gprefix; 201 const struct escape *esc; 202 const struct instr_dual *idual; 203 const struct mode_dual *mdual; 204 void (*fastop)(struct fastop *fake); 205 } u; 206 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 207 }; 208 209 struct group_dual { 210 struct opcode mod012[8]; 211 struct opcode mod3[8]; 212 }; 213 214 struct gprefix { 215 struct opcode pfx_no; 216 struct opcode pfx_66; 217 struct opcode pfx_f2; 218 struct opcode pfx_f3; 219 }; 220 221 struct escape { 222 struct opcode op[8]; 223 struct opcode high[64]; 224 }; 225 226 struct instr_dual { 227 struct opcode mod012; 228 struct opcode mod3; 229 }; 230 231 struct mode_dual { 232 struct opcode mode32; 233 struct opcode mode64; 234 }; 235 236 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 237 238 enum x86_transfer_type { 239 X86_TRANSFER_NONE, 240 X86_TRANSFER_CALL_JMP, 241 X86_TRANSFER_RET, 242 X86_TRANSFER_TASK_SWITCH, 243 }; 244 245 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 246 { 247 unsigned long dirty = ctxt->regs_dirty; 248 unsigned reg; 249 250 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS) 251 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 252 } 253 254 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 255 { 256 ctxt->regs_dirty = 0; 257 ctxt->regs_valid = 0; 258 } 259 260 /* 261 * These EFLAGS bits are restored from saved value during emulation, and 262 * any changes are written back to the saved value after emulation. 263 */ 264 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 265 X86_EFLAGS_PF|X86_EFLAGS_CF) 266 267 #ifdef CONFIG_X86_64 268 #define ON64(x) x 269 #else 270 #define ON64(x) 271 #endif 272 273 /* 274 * fastop functions have a special calling convention: 275 * 276 * dst: rax (in/out) 277 * src: rdx (in/out) 278 * src2: rcx (in) 279 * flags: rflags (in/out) 280 * ex: rsi (in:fastop pointer, out:zero if exception) 281 * 282 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 283 * different operand sizes can be reached by calculation, rather than a jump 284 * table (which would be bigger than the code). 285 * 286 * The 16 byte alignment, considering 5 bytes for the RET thunk, 3 for ENDBR 287 * and 1 for the straight line speculation INT3, leaves 7 bytes for the 288 * body of the function. Currently none is larger than 4. 289 */ 290 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); 291 292 #define FASTOP_SIZE 16 293 294 #define __FOP_FUNC(name) \ 295 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 296 ".type " name ", @function \n\t" \ 297 name ":\n\t" \ 298 ASM_ENDBR \ 299 IBT_NOSEAL(name) 300 301 #define FOP_FUNC(name) \ 302 __FOP_FUNC(#name) 303 304 #define __FOP_RET(name) \ 305 "11: " ASM_RET \ 306 ".size " name ", .-" name "\n\t" 307 308 #define FOP_RET(name) \ 309 __FOP_RET(#name) 310 311 #define __FOP_START(op, align) \ 312 extern void em_##op(struct fastop *fake); \ 313 asm(".pushsection .text, \"ax\" \n\t" \ 314 ".global em_" #op " \n\t" \ 315 ".align " __stringify(align) " \n\t" \ 316 "em_" #op ":\n\t" 317 318 #define FOP_START(op) __FOP_START(op, FASTOP_SIZE) 319 320 #define FOP_END \ 321 ".popsection") 322 323 #define __FOPNOP(name) \ 324 __FOP_FUNC(name) \ 325 __FOP_RET(name) 326 327 #define FOPNOP() \ 328 __FOPNOP(__stringify(__UNIQUE_ID(nop))) 329 330 #define FOP1E(op, dst) \ 331 __FOP_FUNC(#op "_" #dst) \ 332 "10: " #op " %" #dst " \n\t" \ 333 __FOP_RET(#op "_" #dst) 334 335 #define FOP1EEX(op, dst) \ 336 FOP1E(op, dst) _ASM_EXTABLE_TYPE_REG(10b, 11b, EX_TYPE_ZERO_REG, %%esi) 337 338 #define FASTOP1(op) \ 339 FOP_START(op) \ 340 FOP1E(op##b, al) \ 341 FOP1E(op##w, ax) \ 342 FOP1E(op##l, eax) \ 343 ON64(FOP1E(op##q, rax)) \ 344 FOP_END 345 346 /* 1-operand, using src2 (for MUL/DIV r/m) */ 347 #define FASTOP1SRC2(op, name) \ 348 FOP_START(name) \ 349 FOP1E(op, cl) \ 350 FOP1E(op, cx) \ 351 FOP1E(op, ecx) \ 352 ON64(FOP1E(op, rcx)) \ 353 FOP_END 354 355 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 356 #define FASTOP1SRC2EX(op, name) \ 357 FOP_START(name) \ 358 FOP1EEX(op, cl) \ 359 FOP1EEX(op, cx) \ 360 FOP1EEX(op, ecx) \ 361 ON64(FOP1EEX(op, rcx)) \ 362 FOP_END 363 364 #define FOP2E(op, dst, src) \ 365 __FOP_FUNC(#op "_" #dst "_" #src) \ 366 #op " %" #src ", %" #dst " \n\t" \ 367 __FOP_RET(#op "_" #dst "_" #src) 368 369 #define FASTOP2(op) \ 370 FOP_START(op) \ 371 FOP2E(op##b, al, dl) \ 372 FOP2E(op##w, ax, dx) \ 373 FOP2E(op##l, eax, edx) \ 374 ON64(FOP2E(op##q, rax, rdx)) \ 375 FOP_END 376 377 /* 2 operand, word only */ 378 #define FASTOP2W(op) \ 379 FOP_START(op) \ 380 FOPNOP() \ 381 FOP2E(op##w, ax, dx) \ 382 FOP2E(op##l, eax, edx) \ 383 ON64(FOP2E(op##q, rax, rdx)) \ 384 FOP_END 385 386 /* 2 operand, src is CL */ 387 #define FASTOP2CL(op) \ 388 FOP_START(op) \ 389 FOP2E(op##b, al, cl) \ 390 FOP2E(op##w, ax, cl) \ 391 FOP2E(op##l, eax, cl) \ 392 ON64(FOP2E(op##q, rax, cl)) \ 393 FOP_END 394 395 /* 2 operand, src and dest are reversed */ 396 #define FASTOP2R(op, name) \ 397 FOP_START(name) \ 398 FOP2E(op##b, dl, al) \ 399 FOP2E(op##w, dx, ax) \ 400 FOP2E(op##l, edx, eax) \ 401 ON64(FOP2E(op##q, rdx, rax)) \ 402 FOP_END 403 404 #define FOP3E(op, dst, src, src2) \ 405 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 406 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\ 407 __FOP_RET(#op "_" #dst "_" #src "_" #src2) 408 409 /* 3-operand, word-only, src2=cl */ 410 #define FASTOP3WCL(op) \ 411 FOP_START(op) \ 412 FOPNOP() \ 413 FOP3E(op##w, ax, dx, cl) \ 414 FOP3E(op##l, eax, edx, cl) \ 415 ON64(FOP3E(op##q, rax, rdx, cl)) \ 416 FOP_END 417 418 /* Special case for SETcc - 1 instruction per cc */ 419 #define FOP_SETCC(op) \ 420 FOP_FUNC(op) \ 421 #op " %al \n\t" \ 422 FOP_RET(op) 423 424 FOP_START(setcc) 425 FOP_SETCC(seto) 426 FOP_SETCC(setno) 427 FOP_SETCC(setc) 428 FOP_SETCC(setnc) 429 FOP_SETCC(setz) 430 FOP_SETCC(setnz) 431 FOP_SETCC(setbe) 432 FOP_SETCC(setnbe) 433 FOP_SETCC(sets) 434 FOP_SETCC(setns) 435 FOP_SETCC(setp) 436 FOP_SETCC(setnp) 437 FOP_SETCC(setl) 438 FOP_SETCC(setnl) 439 FOP_SETCC(setle) 440 FOP_SETCC(setnle) 441 FOP_END; 442 443 FOP_START(salc) 444 FOP_FUNC(salc) 445 "pushf; sbb %al, %al; popf \n\t" 446 FOP_RET(salc) 447 FOP_END; 448 449 /* 450 * XXX: inoutclob user must know where the argument is being expanded. 451 * Using asm goto would allow us to remove _fault. 452 */ 453 #define asm_safe(insn, inoutclob...) \ 454 ({ \ 455 int _fault = 0; \ 456 \ 457 asm volatile("1:" insn "\n" \ 458 "2:\n" \ 459 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \ 460 : [_fault] "+r"(_fault) inoutclob ); \ 461 \ 462 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 463 }) 464 465 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 466 enum x86_intercept intercept, 467 enum x86_intercept_stage stage) 468 { 469 struct x86_instruction_info info = { 470 .intercept = intercept, 471 .rep_prefix = ctxt->rep_prefix, 472 .modrm_mod = ctxt->modrm_mod, 473 .modrm_reg = ctxt->modrm_reg, 474 .modrm_rm = ctxt->modrm_rm, 475 .src_val = ctxt->src.val64, 476 .dst_val = ctxt->dst.val64, 477 .src_bytes = ctxt->src.bytes, 478 .dst_bytes = ctxt->dst.bytes, 479 .ad_bytes = ctxt->ad_bytes, 480 .next_rip = ctxt->eip, 481 }; 482 483 return ctxt->ops->intercept(ctxt, &info, stage); 484 } 485 486 static void assign_masked(ulong *dest, ulong src, ulong mask) 487 { 488 *dest = (*dest & ~mask) | (src & mask); 489 } 490 491 static void assign_register(unsigned long *reg, u64 val, int bytes) 492 { 493 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 494 switch (bytes) { 495 case 1: 496 *(u8 *)reg = (u8)val; 497 break; 498 case 2: 499 *(u16 *)reg = (u16)val; 500 break; 501 case 4: 502 *reg = (u32)val; 503 break; /* 64b: zero-extend */ 504 case 8: 505 *reg = val; 506 break; 507 } 508 } 509 510 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 511 { 512 return (1UL << (ctxt->ad_bytes << 3)) - 1; 513 } 514 515 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 516 { 517 u16 sel; 518 struct desc_struct ss; 519 520 if (ctxt->mode == X86EMUL_MODE_PROT64) 521 return ~0UL; 522 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 523 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 524 } 525 526 static int stack_size(struct x86_emulate_ctxt *ctxt) 527 { 528 return (__fls(stack_mask(ctxt)) + 1) >> 3; 529 } 530 531 /* Access/update address held in a register, based on addressing mode. */ 532 static inline unsigned long 533 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 534 { 535 if (ctxt->ad_bytes == sizeof(unsigned long)) 536 return reg; 537 else 538 return reg & ad_mask(ctxt); 539 } 540 541 static inline unsigned long 542 register_address(struct x86_emulate_ctxt *ctxt, int reg) 543 { 544 return address_mask(ctxt, reg_read(ctxt, reg)); 545 } 546 547 static void masked_increment(ulong *reg, ulong mask, int inc) 548 { 549 assign_masked(reg, *reg + inc, mask); 550 } 551 552 static inline void 553 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 554 { 555 ulong *preg = reg_rmw(ctxt, reg); 556 557 assign_register(preg, *preg + inc, ctxt->ad_bytes); 558 } 559 560 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 561 { 562 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 563 } 564 565 static u32 desc_limit_scaled(struct desc_struct *desc) 566 { 567 u32 limit = get_desc_limit(desc); 568 569 return desc->g ? (limit << 12) | 0xfff : limit; 570 } 571 572 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 573 { 574 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 575 return 0; 576 577 return ctxt->ops->get_cached_segment_base(ctxt, seg); 578 } 579 580 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 581 u32 error, bool valid) 582 { 583 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt)) 584 return X86EMUL_UNHANDLEABLE; 585 586 ctxt->exception.vector = vec; 587 ctxt->exception.error_code = error; 588 ctxt->exception.error_code_valid = valid; 589 return X86EMUL_PROPAGATE_FAULT; 590 } 591 592 static int emulate_db(struct x86_emulate_ctxt *ctxt) 593 { 594 return emulate_exception(ctxt, DB_VECTOR, 0, false); 595 } 596 597 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 598 { 599 return emulate_exception(ctxt, GP_VECTOR, err, true); 600 } 601 602 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 603 { 604 return emulate_exception(ctxt, SS_VECTOR, err, true); 605 } 606 607 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 608 { 609 return emulate_exception(ctxt, UD_VECTOR, 0, false); 610 } 611 612 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 613 { 614 return emulate_exception(ctxt, TS_VECTOR, err, true); 615 } 616 617 static int emulate_de(struct x86_emulate_ctxt *ctxt) 618 { 619 return emulate_exception(ctxt, DE_VECTOR, 0, false); 620 } 621 622 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 623 { 624 return emulate_exception(ctxt, NM_VECTOR, 0, false); 625 } 626 627 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 628 { 629 u16 selector; 630 struct desc_struct desc; 631 632 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 633 return selector; 634 } 635 636 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 637 unsigned seg) 638 { 639 u16 dummy; 640 u32 base3; 641 struct desc_struct desc; 642 643 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 644 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 645 } 646 647 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 648 { 649 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 650 } 651 652 static inline bool emul_is_noncanonical_address(u64 la, 653 struct x86_emulate_ctxt *ctxt) 654 { 655 return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt)); 656 } 657 658 /* 659 * x86 defines three classes of vector instructions: explicitly 660 * aligned, explicitly unaligned, and the rest, which change behaviour 661 * depending on whether they're AVX encoded or not. 662 * 663 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 664 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 665 * 512 bytes of data must be aligned to a 16 byte boundary. 666 */ 667 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 668 { 669 u64 alignment = ctxt->d & AlignMask; 670 671 if (likely(size < 16)) 672 return 1; 673 674 switch (alignment) { 675 case Unaligned: 676 case Avx: 677 return 1; 678 case Aligned16: 679 return 16; 680 case Aligned: 681 default: 682 return size; 683 } 684 } 685 686 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 687 struct segmented_address addr, 688 unsigned *max_size, unsigned size, 689 bool write, bool fetch, 690 enum x86emul_mode mode, ulong *linear) 691 { 692 struct desc_struct desc; 693 bool usable; 694 ulong la; 695 u32 lim; 696 u16 sel; 697 u8 va_bits; 698 699 la = seg_base(ctxt, addr.seg) + addr.ea; 700 *max_size = 0; 701 switch (mode) { 702 case X86EMUL_MODE_PROT64: 703 *linear = la; 704 va_bits = ctxt_virt_addr_bits(ctxt); 705 if (!__is_canonical_address(la, va_bits)) 706 goto bad; 707 708 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 709 if (size > *max_size) 710 goto bad; 711 break; 712 default: 713 *linear = la = (u32)la; 714 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 715 addr.seg); 716 if (!usable) 717 goto bad; 718 /* code segment in protected mode or read-only data segment */ 719 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 720 || !(desc.type & 2)) && write) 721 goto bad; 722 /* unreadable code segment */ 723 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 724 goto bad; 725 lim = desc_limit_scaled(&desc); 726 if (!(desc.type & 8) && (desc.type & 4)) { 727 /* expand-down segment */ 728 if (addr.ea <= lim) 729 goto bad; 730 lim = desc.d ? 0xffffffff : 0xffff; 731 } 732 if (addr.ea > lim) 733 goto bad; 734 if (lim == 0xffffffff) 735 *max_size = ~0u; 736 else { 737 *max_size = (u64)lim + 1 - addr.ea; 738 if (size > *max_size) 739 goto bad; 740 } 741 break; 742 } 743 if (la & (insn_alignment(ctxt, size) - 1)) 744 return emulate_gp(ctxt, 0); 745 return X86EMUL_CONTINUE; 746 bad: 747 if (addr.seg == VCPU_SREG_SS) 748 return emulate_ss(ctxt, 0); 749 else 750 return emulate_gp(ctxt, 0); 751 } 752 753 static int linearize(struct x86_emulate_ctxt *ctxt, 754 struct segmented_address addr, 755 unsigned size, bool write, 756 ulong *linear) 757 { 758 unsigned max_size; 759 return __linearize(ctxt, addr, &max_size, size, write, false, 760 ctxt->mode, linear); 761 } 762 763 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst) 764 { 765 ulong linear; 766 int rc; 767 unsigned max_size; 768 struct segmented_address addr = { .seg = VCPU_SREG_CS, 769 .ea = dst }; 770 771 if (ctxt->op_bytes != sizeof(unsigned long)) 772 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 773 rc = __linearize(ctxt, addr, &max_size, 1, false, true, ctxt->mode, &linear); 774 if (rc == X86EMUL_CONTINUE) 775 ctxt->_eip = addr.ea; 776 return rc; 777 } 778 779 static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt) 780 { 781 u64 efer; 782 struct desc_struct cs; 783 u16 selector; 784 u32 base3; 785 786 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 787 788 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) { 789 /* Real mode. cpu must not have long mode active */ 790 if (efer & EFER_LMA) 791 return X86EMUL_UNHANDLEABLE; 792 ctxt->mode = X86EMUL_MODE_REAL; 793 return X86EMUL_CONTINUE; 794 } 795 796 if (ctxt->eflags & X86_EFLAGS_VM) { 797 /* Protected/VM86 mode. cpu must not have long mode active */ 798 if (efer & EFER_LMA) 799 return X86EMUL_UNHANDLEABLE; 800 ctxt->mode = X86EMUL_MODE_VM86; 801 return X86EMUL_CONTINUE; 802 } 803 804 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS)) 805 return X86EMUL_UNHANDLEABLE; 806 807 if (efer & EFER_LMA) { 808 if (cs.l) { 809 /* Proper long mode */ 810 ctxt->mode = X86EMUL_MODE_PROT64; 811 } else if (cs.d) { 812 /* 32 bit compatibility mode*/ 813 ctxt->mode = X86EMUL_MODE_PROT32; 814 } else { 815 ctxt->mode = X86EMUL_MODE_PROT16; 816 } 817 } else { 818 /* Legacy 32 bit / 16 bit mode */ 819 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 820 } 821 822 return X86EMUL_CONTINUE; 823 } 824 825 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 826 { 827 return assign_eip(ctxt, dst); 828 } 829 830 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst) 831 { 832 int rc = emulator_recalc_and_set_mode(ctxt); 833 834 if (rc != X86EMUL_CONTINUE) 835 return rc; 836 837 return assign_eip(ctxt, dst); 838 } 839 840 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 841 { 842 return assign_eip_near(ctxt, ctxt->_eip + rel); 843 } 844 845 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 846 void *data, unsigned size) 847 { 848 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 849 } 850 851 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 852 ulong linear, void *data, 853 unsigned int size) 854 { 855 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 856 } 857 858 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 859 struct segmented_address addr, 860 void *data, 861 unsigned size) 862 { 863 int rc; 864 ulong linear; 865 866 rc = linearize(ctxt, addr, size, false, &linear); 867 if (rc != X86EMUL_CONTINUE) 868 return rc; 869 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 870 } 871 872 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 873 struct segmented_address addr, 874 void *data, 875 unsigned int size) 876 { 877 int rc; 878 ulong linear; 879 880 rc = linearize(ctxt, addr, size, true, &linear); 881 if (rc != X86EMUL_CONTINUE) 882 return rc; 883 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 884 } 885 886 /* 887 * Prefetch the remaining bytes of the instruction without crossing page 888 * boundary if they are not in fetch_cache yet. 889 */ 890 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 891 { 892 int rc; 893 unsigned size, max_size; 894 unsigned long linear; 895 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 896 struct segmented_address addr = { .seg = VCPU_SREG_CS, 897 .ea = ctxt->eip + cur_size }; 898 899 /* 900 * We do not know exactly how many bytes will be needed, and 901 * __linearize is expensive, so fetch as much as possible. We 902 * just have to avoid going beyond the 15 byte limit, the end 903 * of the segment, or the end of the page. 904 * 905 * __linearize is called with size 0 so that it does not do any 906 * boundary check itself. Instead, we use max_size to check 907 * against op_size. 908 */ 909 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 910 &linear); 911 if (unlikely(rc != X86EMUL_CONTINUE)) 912 return rc; 913 914 size = min_t(unsigned, 15UL ^ cur_size, max_size); 915 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 916 917 /* 918 * One instruction can only straddle two pages, 919 * and one has been loaded at the beginning of 920 * x86_decode_insn. So, if not enough bytes 921 * still, we must have hit the 15-byte boundary. 922 */ 923 if (unlikely(size < op_size)) 924 return emulate_gp(ctxt, 0); 925 926 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 927 size, &ctxt->exception); 928 if (unlikely(rc != X86EMUL_CONTINUE)) 929 return rc; 930 ctxt->fetch.end += size; 931 return X86EMUL_CONTINUE; 932 } 933 934 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 935 unsigned size) 936 { 937 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 938 939 if (unlikely(done_size < size)) 940 return __do_insn_fetch_bytes(ctxt, size - done_size); 941 else 942 return X86EMUL_CONTINUE; 943 } 944 945 /* Fetch next part of the instruction being emulated. */ 946 #define insn_fetch(_type, _ctxt) \ 947 ({ _type _x; \ 948 \ 949 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 950 if (rc != X86EMUL_CONTINUE) \ 951 goto done; \ 952 ctxt->_eip += sizeof(_type); \ 953 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 954 ctxt->fetch.ptr += sizeof(_type); \ 955 _x; \ 956 }) 957 958 #define insn_fetch_arr(_arr, _size, _ctxt) \ 959 ({ \ 960 rc = do_insn_fetch_bytes(_ctxt, _size); \ 961 if (rc != X86EMUL_CONTINUE) \ 962 goto done; \ 963 ctxt->_eip += (_size); \ 964 memcpy(_arr, ctxt->fetch.ptr, _size); \ 965 ctxt->fetch.ptr += (_size); \ 966 }) 967 968 /* 969 * Given the 'reg' portion of a ModRM byte, and a register block, return a 970 * pointer into the block that addresses the relevant register. 971 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 972 */ 973 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 974 int byteop) 975 { 976 void *p; 977 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 978 979 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 980 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 981 else 982 p = reg_rmw(ctxt, modrm_reg); 983 return p; 984 } 985 986 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 987 struct segmented_address addr, 988 u16 *size, unsigned long *address, int op_bytes) 989 { 990 int rc; 991 992 if (op_bytes == 2) 993 op_bytes = 3; 994 *address = 0; 995 rc = segmented_read_std(ctxt, addr, size, 2); 996 if (rc != X86EMUL_CONTINUE) 997 return rc; 998 addr.ea += 2; 999 rc = segmented_read_std(ctxt, addr, address, op_bytes); 1000 return rc; 1001 } 1002 1003 FASTOP2(add); 1004 FASTOP2(or); 1005 FASTOP2(adc); 1006 FASTOP2(sbb); 1007 FASTOP2(and); 1008 FASTOP2(sub); 1009 FASTOP2(xor); 1010 FASTOP2(cmp); 1011 FASTOP2(test); 1012 1013 FASTOP1SRC2(mul, mul_ex); 1014 FASTOP1SRC2(imul, imul_ex); 1015 FASTOP1SRC2EX(div, div_ex); 1016 FASTOP1SRC2EX(idiv, idiv_ex); 1017 1018 FASTOP3WCL(shld); 1019 FASTOP3WCL(shrd); 1020 1021 FASTOP2W(imul); 1022 1023 FASTOP1(not); 1024 FASTOP1(neg); 1025 FASTOP1(inc); 1026 FASTOP1(dec); 1027 1028 FASTOP2CL(rol); 1029 FASTOP2CL(ror); 1030 FASTOP2CL(rcl); 1031 FASTOP2CL(rcr); 1032 FASTOP2CL(shl); 1033 FASTOP2CL(shr); 1034 FASTOP2CL(sar); 1035 1036 FASTOP2W(bsf); 1037 FASTOP2W(bsr); 1038 FASTOP2W(bt); 1039 FASTOP2W(bts); 1040 FASTOP2W(btr); 1041 FASTOP2W(btc); 1042 1043 FASTOP2(xadd); 1044 1045 FASTOP2R(cmp, cmp_r); 1046 1047 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1048 { 1049 /* If src is zero, do not writeback, but update flags */ 1050 if (ctxt->src.val == 0) 1051 ctxt->dst.type = OP_NONE; 1052 return fastop(ctxt, em_bsf); 1053 } 1054 1055 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1056 { 1057 /* If src is zero, do not writeback, but update flags */ 1058 if (ctxt->src.val == 0) 1059 ctxt->dst.type = OP_NONE; 1060 return fastop(ctxt, em_bsr); 1061 } 1062 1063 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1064 { 1065 u8 rc; 1066 void (*fop)(void) = (void *)em_setcc + FASTOP_SIZE * (condition & 0xf); 1067 1068 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1069 asm("push %[flags]; popf; " CALL_NOSPEC 1070 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1071 return rc; 1072 } 1073 1074 static void fetch_register_operand(struct operand *op) 1075 { 1076 switch (op->bytes) { 1077 case 1: 1078 op->val = *(u8 *)op->addr.reg; 1079 break; 1080 case 2: 1081 op->val = *(u16 *)op->addr.reg; 1082 break; 1083 case 4: 1084 op->val = *(u32 *)op->addr.reg; 1085 break; 1086 case 8: 1087 op->val = *(u64 *)op->addr.reg; 1088 break; 1089 } 1090 } 1091 1092 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1093 { 1094 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1095 return emulate_nm(ctxt); 1096 1097 kvm_fpu_get(); 1098 asm volatile("fninit"); 1099 kvm_fpu_put(); 1100 return X86EMUL_CONTINUE; 1101 } 1102 1103 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1104 { 1105 u16 fcw; 1106 1107 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1108 return emulate_nm(ctxt); 1109 1110 kvm_fpu_get(); 1111 asm volatile("fnstcw %0": "+m"(fcw)); 1112 kvm_fpu_put(); 1113 1114 ctxt->dst.val = fcw; 1115 1116 return X86EMUL_CONTINUE; 1117 } 1118 1119 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1120 { 1121 u16 fsw; 1122 1123 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1124 return emulate_nm(ctxt); 1125 1126 kvm_fpu_get(); 1127 asm volatile("fnstsw %0": "+m"(fsw)); 1128 kvm_fpu_put(); 1129 1130 ctxt->dst.val = fsw; 1131 1132 return X86EMUL_CONTINUE; 1133 } 1134 1135 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1136 struct operand *op) 1137 { 1138 unsigned int reg; 1139 1140 if (ctxt->d & ModRM) 1141 reg = ctxt->modrm_reg; 1142 else 1143 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1144 1145 if (ctxt->d & Sse) { 1146 op->type = OP_XMM; 1147 op->bytes = 16; 1148 op->addr.xmm = reg; 1149 kvm_read_sse_reg(reg, &op->vec_val); 1150 return; 1151 } 1152 if (ctxt->d & Mmx) { 1153 reg &= 7; 1154 op->type = OP_MM; 1155 op->bytes = 8; 1156 op->addr.mm = reg; 1157 return; 1158 } 1159 1160 op->type = OP_REG; 1161 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1162 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1163 1164 fetch_register_operand(op); 1165 op->orig_val = op->val; 1166 } 1167 1168 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1169 { 1170 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1171 ctxt->modrm_seg = VCPU_SREG_SS; 1172 } 1173 1174 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1175 struct operand *op) 1176 { 1177 u8 sib; 1178 int index_reg, base_reg, scale; 1179 int rc = X86EMUL_CONTINUE; 1180 ulong modrm_ea = 0; 1181 1182 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1183 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1184 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1185 1186 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1187 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1188 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1189 ctxt->modrm_seg = VCPU_SREG_DS; 1190 1191 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1192 op->type = OP_REG; 1193 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1194 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1195 ctxt->d & ByteOp); 1196 if (ctxt->d & Sse) { 1197 op->type = OP_XMM; 1198 op->bytes = 16; 1199 op->addr.xmm = ctxt->modrm_rm; 1200 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val); 1201 return rc; 1202 } 1203 if (ctxt->d & Mmx) { 1204 op->type = OP_MM; 1205 op->bytes = 8; 1206 op->addr.mm = ctxt->modrm_rm & 7; 1207 return rc; 1208 } 1209 fetch_register_operand(op); 1210 return rc; 1211 } 1212 1213 op->type = OP_MEM; 1214 1215 if (ctxt->ad_bytes == 2) { 1216 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1217 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1218 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1219 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1220 1221 /* 16-bit ModR/M decode. */ 1222 switch (ctxt->modrm_mod) { 1223 case 0: 1224 if (ctxt->modrm_rm == 6) 1225 modrm_ea += insn_fetch(u16, ctxt); 1226 break; 1227 case 1: 1228 modrm_ea += insn_fetch(s8, ctxt); 1229 break; 1230 case 2: 1231 modrm_ea += insn_fetch(u16, ctxt); 1232 break; 1233 } 1234 switch (ctxt->modrm_rm) { 1235 case 0: 1236 modrm_ea += bx + si; 1237 break; 1238 case 1: 1239 modrm_ea += bx + di; 1240 break; 1241 case 2: 1242 modrm_ea += bp + si; 1243 break; 1244 case 3: 1245 modrm_ea += bp + di; 1246 break; 1247 case 4: 1248 modrm_ea += si; 1249 break; 1250 case 5: 1251 modrm_ea += di; 1252 break; 1253 case 6: 1254 if (ctxt->modrm_mod != 0) 1255 modrm_ea += bp; 1256 break; 1257 case 7: 1258 modrm_ea += bx; 1259 break; 1260 } 1261 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1262 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1263 ctxt->modrm_seg = VCPU_SREG_SS; 1264 modrm_ea = (u16)modrm_ea; 1265 } else { 1266 /* 32/64-bit ModR/M decode. */ 1267 if ((ctxt->modrm_rm & 7) == 4) { 1268 sib = insn_fetch(u8, ctxt); 1269 index_reg |= (sib >> 3) & 7; 1270 base_reg |= sib & 7; 1271 scale = sib >> 6; 1272 1273 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1274 modrm_ea += insn_fetch(s32, ctxt); 1275 else { 1276 modrm_ea += reg_read(ctxt, base_reg); 1277 adjust_modrm_seg(ctxt, base_reg); 1278 /* Increment ESP on POP [ESP] */ 1279 if ((ctxt->d & IncSP) && 1280 base_reg == VCPU_REGS_RSP) 1281 modrm_ea += ctxt->op_bytes; 1282 } 1283 if (index_reg != 4) 1284 modrm_ea += reg_read(ctxt, index_reg) << scale; 1285 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1286 modrm_ea += insn_fetch(s32, ctxt); 1287 if (ctxt->mode == X86EMUL_MODE_PROT64) 1288 ctxt->rip_relative = 1; 1289 } else { 1290 base_reg = ctxt->modrm_rm; 1291 modrm_ea += reg_read(ctxt, base_reg); 1292 adjust_modrm_seg(ctxt, base_reg); 1293 } 1294 switch (ctxt->modrm_mod) { 1295 case 1: 1296 modrm_ea += insn_fetch(s8, ctxt); 1297 break; 1298 case 2: 1299 modrm_ea += insn_fetch(s32, ctxt); 1300 break; 1301 } 1302 } 1303 op->addr.mem.ea = modrm_ea; 1304 if (ctxt->ad_bytes != 8) 1305 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1306 1307 done: 1308 return rc; 1309 } 1310 1311 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1312 struct operand *op) 1313 { 1314 int rc = X86EMUL_CONTINUE; 1315 1316 op->type = OP_MEM; 1317 switch (ctxt->ad_bytes) { 1318 case 2: 1319 op->addr.mem.ea = insn_fetch(u16, ctxt); 1320 break; 1321 case 4: 1322 op->addr.mem.ea = insn_fetch(u32, ctxt); 1323 break; 1324 case 8: 1325 op->addr.mem.ea = insn_fetch(u64, ctxt); 1326 break; 1327 } 1328 done: 1329 return rc; 1330 } 1331 1332 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1333 { 1334 long sv = 0, mask; 1335 1336 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1337 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1338 1339 if (ctxt->src.bytes == 2) 1340 sv = (s16)ctxt->src.val & (s16)mask; 1341 else if (ctxt->src.bytes == 4) 1342 sv = (s32)ctxt->src.val & (s32)mask; 1343 else 1344 sv = (s64)ctxt->src.val & (s64)mask; 1345 1346 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1347 ctxt->dst.addr.mem.ea + (sv >> 3)); 1348 } 1349 1350 /* only subword offset */ 1351 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1352 } 1353 1354 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1355 unsigned long addr, void *dest, unsigned size) 1356 { 1357 int rc; 1358 struct read_cache *mc = &ctxt->mem_read; 1359 1360 if (mc->pos < mc->end) 1361 goto read_cached; 1362 1363 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt)) 1364 return X86EMUL_UNHANDLEABLE; 1365 1366 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1367 &ctxt->exception); 1368 if (rc != X86EMUL_CONTINUE) 1369 return rc; 1370 1371 mc->end += size; 1372 1373 read_cached: 1374 memcpy(dest, mc->data + mc->pos, size); 1375 mc->pos += size; 1376 return X86EMUL_CONTINUE; 1377 } 1378 1379 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1380 struct segmented_address addr, 1381 void *data, 1382 unsigned size) 1383 { 1384 int rc; 1385 ulong linear; 1386 1387 rc = linearize(ctxt, addr, size, false, &linear); 1388 if (rc != X86EMUL_CONTINUE) 1389 return rc; 1390 return read_emulated(ctxt, linear, data, size); 1391 } 1392 1393 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1394 struct segmented_address addr, 1395 const void *data, 1396 unsigned size) 1397 { 1398 int rc; 1399 ulong linear; 1400 1401 rc = linearize(ctxt, addr, size, true, &linear); 1402 if (rc != X86EMUL_CONTINUE) 1403 return rc; 1404 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1405 &ctxt->exception); 1406 } 1407 1408 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1409 struct segmented_address addr, 1410 const void *orig_data, const void *data, 1411 unsigned size) 1412 { 1413 int rc; 1414 ulong linear; 1415 1416 rc = linearize(ctxt, addr, size, true, &linear); 1417 if (rc != X86EMUL_CONTINUE) 1418 return rc; 1419 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1420 size, &ctxt->exception); 1421 } 1422 1423 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1424 unsigned int size, unsigned short port, 1425 void *dest) 1426 { 1427 struct read_cache *rc = &ctxt->io_read; 1428 1429 if (rc->pos == rc->end) { /* refill pio read ahead */ 1430 unsigned int in_page, n; 1431 unsigned int count = ctxt->rep_prefix ? 1432 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1433 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1434 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1435 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1436 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1437 if (n == 0) 1438 n = 1; 1439 rc->pos = rc->end = 0; 1440 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1441 return 0; 1442 rc->end = n * size; 1443 } 1444 1445 if (ctxt->rep_prefix && (ctxt->d & String) && 1446 !(ctxt->eflags & X86_EFLAGS_DF)) { 1447 ctxt->dst.data = rc->data + rc->pos; 1448 ctxt->dst.type = OP_MEM_STR; 1449 ctxt->dst.count = (rc->end - rc->pos) / size; 1450 rc->pos = rc->end; 1451 } else { 1452 memcpy(dest, rc->data + rc->pos, size); 1453 rc->pos += size; 1454 } 1455 return 1; 1456 } 1457 1458 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1459 u16 index, struct desc_struct *desc) 1460 { 1461 struct desc_ptr dt; 1462 ulong addr; 1463 1464 ctxt->ops->get_idt(ctxt, &dt); 1465 1466 if (dt.size < index * 8 + 7) 1467 return emulate_gp(ctxt, index << 3 | 0x2); 1468 1469 addr = dt.address + index * 8; 1470 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1471 } 1472 1473 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1474 u16 selector, struct desc_ptr *dt) 1475 { 1476 const struct x86_emulate_ops *ops = ctxt->ops; 1477 u32 base3 = 0; 1478 1479 if (selector & 1 << 2) { 1480 struct desc_struct desc; 1481 u16 sel; 1482 1483 memset(dt, 0, sizeof(*dt)); 1484 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1485 VCPU_SREG_LDTR)) 1486 return; 1487 1488 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1489 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1490 } else 1491 ops->get_gdt(ctxt, dt); 1492 } 1493 1494 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1495 u16 selector, ulong *desc_addr_p) 1496 { 1497 struct desc_ptr dt; 1498 u16 index = selector >> 3; 1499 ulong addr; 1500 1501 get_descriptor_table_ptr(ctxt, selector, &dt); 1502 1503 if (dt.size < index * 8 + 7) 1504 return emulate_gp(ctxt, selector & 0xfffc); 1505 1506 addr = dt.address + index * 8; 1507 1508 #ifdef CONFIG_X86_64 1509 if (addr >> 32 != 0) { 1510 u64 efer = 0; 1511 1512 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1513 if (!(efer & EFER_LMA)) 1514 addr &= (u32)-1; 1515 } 1516 #endif 1517 1518 *desc_addr_p = addr; 1519 return X86EMUL_CONTINUE; 1520 } 1521 1522 /* allowed just for 8 bytes segments */ 1523 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1524 u16 selector, struct desc_struct *desc, 1525 ulong *desc_addr_p) 1526 { 1527 int rc; 1528 1529 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1530 if (rc != X86EMUL_CONTINUE) 1531 return rc; 1532 1533 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1534 } 1535 1536 /* allowed just for 8 bytes segments */ 1537 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1538 u16 selector, struct desc_struct *desc) 1539 { 1540 int rc; 1541 ulong addr; 1542 1543 rc = get_descriptor_ptr(ctxt, selector, &addr); 1544 if (rc != X86EMUL_CONTINUE) 1545 return rc; 1546 1547 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1548 } 1549 1550 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1551 u16 selector, int seg, u8 cpl, 1552 enum x86_transfer_type transfer, 1553 struct desc_struct *desc) 1554 { 1555 struct desc_struct seg_desc, old_desc; 1556 u8 dpl, rpl; 1557 unsigned err_vec = GP_VECTOR; 1558 u32 err_code = 0; 1559 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1560 ulong desc_addr; 1561 int ret; 1562 u16 dummy; 1563 u32 base3 = 0; 1564 1565 memset(&seg_desc, 0, sizeof(seg_desc)); 1566 1567 if (ctxt->mode == X86EMUL_MODE_REAL) { 1568 /* set real mode segment descriptor (keep limit etc. for 1569 * unreal mode) */ 1570 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1571 set_desc_base(&seg_desc, selector << 4); 1572 goto load; 1573 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1574 /* VM86 needs a clean new segment descriptor */ 1575 set_desc_base(&seg_desc, selector << 4); 1576 set_desc_limit(&seg_desc, 0xffff); 1577 seg_desc.type = 3; 1578 seg_desc.p = 1; 1579 seg_desc.s = 1; 1580 seg_desc.dpl = 3; 1581 goto load; 1582 } 1583 1584 rpl = selector & 3; 1585 1586 /* TR should be in GDT only */ 1587 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1588 goto exception; 1589 1590 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1591 if (null_selector) { 1592 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1593 goto exception; 1594 1595 if (seg == VCPU_SREG_SS) { 1596 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1597 goto exception; 1598 1599 /* 1600 * ctxt->ops->set_segment expects the CPL to be in 1601 * SS.DPL, so fake an expand-up 32-bit data segment. 1602 */ 1603 seg_desc.type = 3; 1604 seg_desc.p = 1; 1605 seg_desc.s = 1; 1606 seg_desc.dpl = cpl; 1607 seg_desc.d = 1; 1608 seg_desc.g = 1; 1609 } 1610 1611 /* Skip all following checks */ 1612 goto load; 1613 } 1614 1615 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1616 if (ret != X86EMUL_CONTINUE) 1617 return ret; 1618 1619 err_code = selector & 0xfffc; 1620 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1621 GP_VECTOR; 1622 1623 /* can't load system descriptor into segment selector */ 1624 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1625 if (transfer == X86_TRANSFER_CALL_JMP) 1626 return X86EMUL_UNHANDLEABLE; 1627 goto exception; 1628 } 1629 1630 dpl = seg_desc.dpl; 1631 1632 switch (seg) { 1633 case VCPU_SREG_SS: 1634 /* 1635 * segment is not a writable data segment or segment 1636 * selector's RPL != CPL or segment selector's RPL != CPL 1637 */ 1638 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1639 goto exception; 1640 break; 1641 case VCPU_SREG_CS: 1642 if (!(seg_desc.type & 8)) 1643 goto exception; 1644 1645 if (transfer == X86_TRANSFER_RET) { 1646 /* RET can never return to an inner privilege level. */ 1647 if (rpl < cpl) 1648 goto exception; 1649 /* Outer-privilege level return is not implemented */ 1650 if (rpl > cpl) 1651 return X86EMUL_UNHANDLEABLE; 1652 } 1653 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) { 1654 if (seg_desc.type & 4) { 1655 /* conforming */ 1656 if (dpl > rpl) 1657 goto exception; 1658 } else { 1659 /* nonconforming */ 1660 if (dpl != rpl) 1661 goto exception; 1662 } 1663 } else { /* X86_TRANSFER_CALL_JMP */ 1664 if (seg_desc.type & 4) { 1665 /* conforming */ 1666 if (dpl > cpl) 1667 goto exception; 1668 } else { 1669 /* nonconforming */ 1670 if (rpl > cpl || dpl != cpl) 1671 goto exception; 1672 } 1673 } 1674 /* in long-mode d/b must be clear if l is set */ 1675 if (seg_desc.d && seg_desc.l) { 1676 u64 efer = 0; 1677 1678 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1679 if (efer & EFER_LMA) 1680 goto exception; 1681 } 1682 1683 /* CS(RPL) <- CPL */ 1684 selector = (selector & 0xfffc) | cpl; 1685 break; 1686 case VCPU_SREG_TR: 1687 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1688 goto exception; 1689 break; 1690 case VCPU_SREG_LDTR: 1691 if (seg_desc.s || seg_desc.type != 2) 1692 goto exception; 1693 break; 1694 default: /* DS, ES, FS, or GS */ 1695 /* 1696 * segment is not a data or readable code segment or 1697 * ((segment is a data or nonconforming code segment) 1698 * and (both RPL and CPL > DPL)) 1699 */ 1700 if ((seg_desc.type & 0xa) == 0x8 || 1701 (((seg_desc.type & 0xc) != 0xc) && 1702 (rpl > dpl && cpl > dpl))) 1703 goto exception; 1704 break; 1705 } 1706 1707 if (!seg_desc.p) { 1708 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1709 goto exception; 1710 } 1711 1712 if (seg_desc.s) { 1713 /* mark segment as accessed */ 1714 if (!(seg_desc.type & 1)) { 1715 seg_desc.type |= 1; 1716 ret = write_segment_descriptor(ctxt, selector, 1717 &seg_desc); 1718 if (ret != X86EMUL_CONTINUE) 1719 return ret; 1720 } 1721 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1722 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1723 if (ret != X86EMUL_CONTINUE) 1724 return ret; 1725 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1726 ((u64)base3 << 32), ctxt)) 1727 return emulate_gp(ctxt, err_code); 1728 } 1729 1730 if (seg == VCPU_SREG_TR) { 1731 old_desc = seg_desc; 1732 seg_desc.type |= 2; /* busy */ 1733 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1734 sizeof(seg_desc), &ctxt->exception); 1735 if (ret != X86EMUL_CONTINUE) 1736 return ret; 1737 } 1738 load: 1739 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1740 if (desc) 1741 *desc = seg_desc; 1742 return X86EMUL_CONTINUE; 1743 exception: 1744 return emulate_exception(ctxt, err_vec, err_code, true); 1745 } 1746 1747 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1748 u16 selector, int seg) 1749 { 1750 u8 cpl = ctxt->ops->cpl(ctxt); 1751 1752 /* 1753 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1754 * they can load it at CPL<3 (Intel's manual says only LSS can, 1755 * but it's wrong). 1756 * 1757 * However, the Intel manual says that putting IST=1/DPL=3 in 1758 * an interrupt gate will result in SS=3 (the AMD manual instead 1759 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1760 * and only forbid it here. 1761 */ 1762 if (seg == VCPU_SREG_SS && selector == 3 && 1763 ctxt->mode == X86EMUL_MODE_PROT64) 1764 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1765 1766 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1767 X86_TRANSFER_NONE, NULL); 1768 } 1769 1770 static void write_register_operand(struct operand *op) 1771 { 1772 return assign_register(op->addr.reg, op->val, op->bytes); 1773 } 1774 1775 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1776 { 1777 switch (op->type) { 1778 case OP_REG: 1779 write_register_operand(op); 1780 break; 1781 case OP_MEM: 1782 if (ctxt->lock_prefix) 1783 return segmented_cmpxchg(ctxt, 1784 op->addr.mem, 1785 &op->orig_val, 1786 &op->val, 1787 op->bytes); 1788 else 1789 return segmented_write(ctxt, 1790 op->addr.mem, 1791 &op->val, 1792 op->bytes); 1793 break; 1794 case OP_MEM_STR: 1795 return segmented_write(ctxt, 1796 op->addr.mem, 1797 op->data, 1798 op->bytes * op->count); 1799 break; 1800 case OP_XMM: 1801 kvm_write_sse_reg(op->addr.xmm, &op->vec_val); 1802 break; 1803 case OP_MM: 1804 kvm_write_mmx_reg(op->addr.mm, &op->mm_val); 1805 break; 1806 case OP_NONE: 1807 /* no writeback */ 1808 break; 1809 default: 1810 break; 1811 } 1812 return X86EMUL_CONTINUE; 1813 } 1814 1815 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1816 { 1817 struct segmented_address addr; 1818 1819 rsp_increment(ctxt, -bytes); 1820 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1821 addr.seg = VCPU_SREG_SS; 1822 1823 return segmented_write(ctxt, addr, data, bytes); 1824 } 1825 1826 static int em_push(struct x86_emulate_ctxt *ctxt) 1827 { 1828 /* Disable writeback. */ 1829 ctxt->dst.type = OP_NONE; 1830 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1831 } 1832 1833 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1834 void *dest, int len) 1835 { 1836 int rc; 1837 struct segmented_address addr; 1838 1839 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1840 addr.seg = VCPU_SREG_SS; 1841 rc = segmented_read(ctxt, addr, dest, len); 1842 if (rc != X86EMUL_CONTINUE) 1843 return rc; 1844 1845 rsp_increment(ctxt, len); 1846 return rc; 1847 } 1848 1849 static int em_pop(struct x86_emulate_ctxt *ctxt) 1850 { 1851 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1852 } 1853 1854 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1855 void *dest, int len) 1856 { 1857 int rc; 1858 unsigned long val, change_mask; 1859 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1860 int cpl = ctxt->ops->cpl(ctxt); 1861 1862 rc = emulate_pop(ctxt, &val, len); 1863 if (rc != X86EMUL_CONTINUE) 1864 return rc; 1865 1866 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1867 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1868 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1869 X86_EFLAGS_AC | X86_EFLAGS_ID; 1870 1871 switch(ctxt->mode) { 1872 case X86EMUL_MODE_PROT64: 1873 case X86EMUL_MODE_PROT32: 1874 case X86EMUL_MODE_PROT16: 1875 if (cpl == 0) 1876 change_mask |= X86_EFLAGS_IOPL; 1877 if (cpl <= iopl) 1878 change_mask |= X86_EFLAGS_IF; 1879 break; 1880 case X86EMUL_MODE_VM86: 1881 if (iopl < 3) 1882 return emulate_gp(ctxt, 0); 1883 change_mask |= X86_EFLAGS_IF; 1884 break; 1885 default: /* real mode */ 1886 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1887 break; 1888 } 1889 1890 *(unsigned long *)dest = 1891 (ctxt->eflags & ~change_mask) | (val & change_mask); 1892 1893 return rc; 1894 } 1895 1896 static int em_popf(struct x86_emulate_ctxt *ctxt) 1897 { 1898 ctxt->dst.type = OP_REG; 1899 ctxt->dst.addr.reg = &ctxt->eflags; 1900 ctxt->dst.bytes = ctxt->op_bytes; 1901 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1902 } 1903 1904 static int em_enter(struct x86_emulate_ctxt *ctxt) 1905 { 1906 int rc; 1907 unsigned frame_size = ctxt->src.val; 1908 unsigned nesting_level = ctxt->src2.val & 31; 1909 ulong rbp; 1910 1911 if (nesting_level) 1912 return X86EMUL_UNHANDLEABLE; 1913 1914 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1915 rc = push(ctxt, &rbp, stack_size(ctxt)); 1916 if (rc != X86EMUL_CONTINUE) 1917 return rc; 1918 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1919 stack_mask(ctxt)); 1920 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1921 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1922 stack_mask(ctxt)); 1923 return X86EMUL_CONTINUE; 1924 } 1925 1926 static int em_leave(struct x86_emulate_ctxt *ctxt) 1927 { 1928 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1929 stack_mask(ctxt)); 1930 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1931 } 1932 1933 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1934 { 1935 int seg = ctxt->src2.val; 1936 1937 ctxt->src.val = get_segment_selector(ctxt, seg); 1938 if (ctxt->op_bytes == 4) { 1939 rsp_increment(ctxt, -2); 1940 ctxt->op_bytes = 2; 1941 } 1942 1943 return em_push(ctxt); 1944 } 1945 1946 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1947 { 1948 int seg = ctxt->src2.val; 1949 unsigned long selector; 1950 int rc; 1951 1952 rc = emulate_pop(ctxt, &selector, 2); 1953 if (rc != X86EMUL_CONTINUE) 1954 return rc; 1955 1956 if (seg == VCPU_SREG_SS) 1957 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1958 if (ctxt->op_bytes > 2) 1959 rsp_increment(ctxt, ctxt->op_bytes - 2); 1960 1961 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1962 return rc; 1963 } 1964 1965 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1966 { 1967 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1968 int rc = X86EMUL_CONTINUE; 1969 int reg = VCPU_REGS_RAX; 1970 1971 while (reg <= VCPU_REGS_RDI) { 1972 (reg == VCPU_REGS_RSP) ? 1973 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1974 1975 rc = em_push(ctxt); 1976 if (rc != X86EMUL_CONTINUE) 1977 return rc; 1978 1979 ++reg; 1980 } 1981 1982 return rc; 1983 } 1984 1985 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1986 { 1987 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1988 return em_push(ctxt); 1989 } 1990 1991 static int em_popa(struct x86_emulate_ctxt *ctxt) 1992 { 1993 int rc = X86EMUL_CONTINUE; 1994 int reg = VCPU_REGS_RDI; 1995 u32 val; 1996 1997 while (reg >= VCPU_REGS_RAX) { 1998 if (reg == VCPU_REGS_RSP) { 1999 rsp_increment(ctxt, ctxt->op_bytes); 2000 --reg; 2001 } 2002 2003 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2004 if (rc != X86EMUL_CONTINUE) 2005 break; 2006 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2007 --reg; 2008 } 2009 return rc; 2010 } 2011 2012 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2013 { 2014 const struct x86_emulate_ops *ops = ctxt->ops; 2015 int rc; 2016 struct desc_ptr dt; 2017 gva_t cs_addr; 2018 gva_t eip_addr; 2019 u16 cs, eip; 2020 2021 /* TODO: Add limit checks */ 2022 ctxt->src.val = ctxt->eflags; 2023 rc = em_push(ctxt); 2024 if (rc != X86EMUL_CONTINUE) 2025 return rc; 2026 2027 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2028 2029 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2030 rc = em_push(ctxt); 2031 if (rc != X86EMUL_CONTINUE) 2032 return rc; 2033 2034 ctxt->src.val = ctxt->_eip; 2035 rc = em_push(ctxt); 2036 if (rc != X86EMUL_CONTINUE) 2037 return rc; 2038 2039 ops->get_idt(ctxt, &dt); 2040 2041 eip_addr = dt.address + (irq << 2); 2042 cs_addr = dt.address + (irq << 2) + 2; 2043 2044 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2045 if (rc != X86EMUL_CONTINUE) 2046 return rc; 2047 2048 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2049 if (rc != X86EMUL_CONTINUE) 2050 return rc; 2051 2052 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2053 if (rc != X86EMUL_CONTINUE) 2054 return rc; 2055 2056 ctxt->_eip = eip; 2057 2058 return rc; 2059 } 2060 2061 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2062 { 2063 int rc; 2064 2065 invalidate_registers(ctxt); 2066 rc = __emulate_int_real(ctxt, irq); 2067 if (rc == X86EMUL_CONTINUE) 2068 writeback_registers(ctxt); 2069 return rc; 2070 } 2071 2072 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2073 { 2074 switch(ctxt->mode) { 2075 case X86EMUL_MODE_REAL: 2076 return __emulate_int_real(ctxt, irq); 2077 case X86EMUL_MODE_VM86: 2078 case X86EMUL_MODE_PROT16: 2079 case X86EMUL_MODE_PROT32: 2080 case X86EMUL_MODE_PROT64: 2081 default: 2082 /* Protected mode interrupts unimplemented yet */ 2083 return X86EMUL_UNHANDLEABLE; 2084 } 2085 } 2086 2087 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2088 { 2089 int rc = X86EMUL_CONTINUE; 2090 unsigned long temp_eip = 0; 2091 unsigned long temp_eflags = 0; 2092 unsigned long cs = 0; 2093 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2094 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2095 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2096 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2097 X86_EFLAGS_AC | X86_EFLAGS_ID | 2098 X86_EFLAGS_FIXED; 2099 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2100 X86_EFLAGS_VIP; 2101 2102 /* TODO: Add stack limit check */ 2103 2104 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2105 2106 if (rc != X86EMUL_CONTINUE) 2107 return rc; 2108 2109 if (temp_eip & ~0xffff) 2110 return emulate_gp(ctxt, 0); 2111 2112 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2113 2114 if (rc != X86EMUL_CONTINUE) 2115 return rc; 2116 2117 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2118 2119 if (rc != X86EMUL_CONTINUE) 2120 return rc; 2121 2122 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2123 2124 if (rc != X86EMUL_CONTINUE) 2125 return rc; 2126 2127 ctxt->_eip = temp_eip; 2128 2129 if (ctxt->op_bytes == 4) 2130 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2131 else if (ctxt->op_bytes == 2) { 2132 ctxt->eflags &= ~0xffff; 2133 ctxt->eflags |= temp_eflags; 2134 } 2135 2136 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2137 ctxt->eflags |= X86_EFLAGS_FIXED; 2138 ctxt->ops->set_nmi_mask(ctxt, false); 2139 2140 return rc; 2141 } 2142 2143 static int em_iret(struct x86_emulate_ctxt *ctxt) 2144 { 2145 switch(ctxt->mode) { 2146 case X86EMUL_MODE_REAL: 2147 return emulate_iret_real(ctxt); 2148 case X86EMUL_MODE_VM86: 2149 case X86EMUL_MODE_PROT16: 2150 case X86EMUL_MODE_PROT32: 2151 case X86EMUL_MODE_PROT64: 2152 default: 2153 /* iret from protected mode unimplemented yet */ 2154 return X86EMUL_UNHANDLEABLE; 2155 } 2156 } 2157 2158 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2159 { 2160 int rc; 2161 unsigned short sel; 2162 struct desc_struct new_desc; 2163 u8 cpl = ctxt->ops->cpl(ctxt); 2164 2165 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2166 2167 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2168 X86_TRANSFER_CALL_JMP, 2169 &new_desc); 2170 if (rc != X86EMUL_CONTINUE) 2171 return rc; 2172 2173 rc = assign_eip_far(ctxt, ctxt->src.val); 2174 /* Error handling is not implemented. */ 2175 if (rc != X86EMUL_CONTINUE) 2176 return X86EMUL_UNHANDLEABLE; 2177 2178 return rc; 2179 } 2180 2181 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2182 { 2183 return assign_eip_near(ctxt, ctxt->src.val); 2184 } 2185 2186 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2187 { 2188 int rc; 2189 long int old_eip; 2190 2191 old_eip = ctxt->_eip; 2192 rc = assign_eip_near(ctxt, ctxt->src.val); 2193 if (rc != X86EMUL_CONTINUE) 2194 return rc; 2195 ctxt->src.val = old_eip; 2196 rc = em_push(ctxt); 2197 return rc; 2198 } 2199 2200 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2201 { 2202 u64 old = ctxt->dst.orig_val64; 2203 2204 if (ctxt->dst.bytes == 16) 2205 return X86EMUL_UNHANDLEABLE; 2206 2207 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2208 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2209 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2210 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2211 ctxt->eflags &= ~X86_EFLAGS_ZF; 2212 } else { 2213 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2214 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2215 2216 ctxt->eflags |= X86_EFLAGS_ZF; 2217 } 2218 return X86EMUL_CONTINUE; 2219 } 2220 2221 static int em_ret(struct x86_emulate_ctxt *ctxt) 2222 { 2223 int rc; 2224 unsigned long eip; 2225 2226 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2227 if (rc != X86EMUL_CONTINUE) 2228 return rc; 2229 2230 return assign_eip_near(ctxt, eip); 2231 } 2232 2233 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2234 { 2235 int rc; 2236 unsigned long eip, cs; 2237 int cpl = ctxt->ops->cpl(ctxt); 2238 struct desc_struct new_desc; 2239 2240 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2241 if (rc != X86EMUL_CONTINUE) 2242 return rc; 2243 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2244 if (rc != X86EMUL_CONTINUE) 2245 return rc; 2246 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2247 X86_TRANSFER_RET, 2248 &new_desc); 2249 if (rc != X86EMUL_CONTINUE) 2250 return rc; 2251 rc = assign_eip_far(ctxt, eip); 2252 /* Error handling is not implemented. */ 2253 if (rc != X86EMUL_CONTINUE) 2254 return X86EMUL_UNHANDLEABLE; 2255 2256 return rc; 2257 } 2258 2259 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2260 { 2261 int rc; 2262 2263 rc = em_ret_far(ctxt); 2264 if (rc != X86EMUL_CONTINUE) 2265 return rc; 2266 rsp_increment(ctxt, ctxt->src.val); 2267 return X86EMUL_CONTINUE; 2268 } 2269 2270 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2271 { 2272 /* Save real source value, then compare EAX against destination. */ 2273 ctxt->dst.orig_val = ctxt->dst.val; 2274 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2275 ctxt->src.orig_val = ctxt->src.val; 2276 ctxt->src.val = ctxt->dst.orig_val; 2277 fastop(ctxt, em_cmp); 2278 2279 if (ctxt->eflags & X86_EFLAGS_ZF) { 2280 /* Success: write back to memory; no update of EAX */ 2281 ctxt->src.type = OP_NONE; 2282 ctxt->dst.val = ctxt->src.orig_val; 2283 } else { 2284 /* Failure: write the value we saw to EAX. */ 2285 ctxt->src.type = OP_REG; 2286 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2287 ctxt->src.val = ctxt->dst.orig_val; 2288 /* Create write-cycle to dest by writing the same value */ 2289 ctxt->dst.val = ctxt->dst.orig_val; 2290 } 2291 return X86EMUL_CONTINUE; 2292 } 2293 2294 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2295 { 2296 int seg = ctxt->src2.val; 2297 unsigned short sel; 2298 int rc; 2299 2300 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2301 2302 rc = load_segment_descriptor(ctxt, sel, seg); 2303 if (rc != X86EMUL_CONTINUE) 2304 return rc; 2305 2306 ctxt->dst.val = ctxt->src.val; 2307 return rc; 2308 } 2309 2310 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2311 { 2312 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2313 return emulate_ud(ctxt); 2314 2315 if (ctxt->ops->leave_smm(ctxt)) 2316 ctxt->ops->triple_fault(ctxt); 2317 2318 return emulator_recalc_and_set_mode(ctxt); 2319 } 2320 2321 static void 2322 setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss) 2323 { 2324 cs->l = 0; /* will be adjusted later */ 2325 set_desc_base(cs, 0); /* flat segment */ 2326 cs->g = 1; /* 4kb granularity */ 2327 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2328 cs->type = 0x0b; /* Read, Execute, Accessed */ 2329 cs->s = 1; 2330 cs->dpl = 0; /* will be adjusted later */ 2331 cs->p = 1; 2332 cs->d = 1; 2333 cs->avl = 0; 2334 2335 set_desc_base(ss, 0); /* flat segment */ 2336 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2337 ss->g = 1; /* 4kb granularity */ 2338 ss->s = 1; 2339 ss->type = 0x03; /* Read/Write, Accessed */ 2340 ss->d = 1; /* 32bit stack segment */ 2341 ss->dpl = 0; 2342 ss->p = 1; 2343 ss->l = 0; 2344 ss->avl = 0; 2345 } 2346 2347 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2348 { 2349 u32 eax, ebx, ecx, edx; 2350 2351 eax = ecx = 0; 2352 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2353 return is_guest_vendor_intel(ebx, ecx, edx); 2354 } 2355 2356 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2357 { 2358 const struct x86_emulate_ops *ops = ctxt->ops; 2359 u32 eax, ebx, ecx, edx; 2360 2361 /* 2362 * syscall should always be enabled in longmode - so only become 2363 * vendor specific (cpuid) if other modes are active... 2364 */ 2365 if (ctxt->mode == X86EMUL_MODE_PROT64) 2366 return true; 2367 2368 eax = 0x00000000; 2369 ecx = 0x00000000; 2370 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2371 /* 2372 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a 2373 * 64bit guest with a 32bit compat-app running will #UD !! While this 2374 * behaviour can be fixed (by emulating) into AMD response - CPUs of 2375 * AMD can't behave like Intel. 2376 */ 2377 if (is_guest_vendor_intel(ebx, ecx, edx)) 2378 return false; 2379 2380 if (is_guest_vendor_amd(ebx, ecx, edx) || 2381 is_guest_vendor_hygon(ebx, ecx, edx)) 2382 return true; 2383 2384 /* 2385 * default: (not Intel, not AMD, not Hygon), apply Intel's 2386 * stricter rules... 2387 */ 2388 return false; 2389 } 2390 2391 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2392 { 2393 const struct x86_emulate_ops *ops = ctxt->ops; 2394 struct desc_struct cs, ss; 2395 u64 msr_data; 2396 u16 cs_sel, ss_sel; 2397 u64 efer = 0; 2398 2399 /* syscall is not available in real mode */ 2400 if (ctxt->mode == X86EMUL_MODE_REAL || 2401 ctxt->mode == X86EMUL_MODE_VM86) 2402 return emulate_ud(ctxt); 2403 2404 if (!(em_syscall_is_enabled(ctxt))) 2405 return emulate_ud(ctxt); 2406 2407 ops->get_msr(ctxt, MSR_EFER, &efer); 2408 if (!(efer & EFER_SCE)) 2409 return emulate_ud(ctxt); 2410 2411 setup_syscalls_segments(&cs, &ss); 2412 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2413 msr_data >>= 32; 2414 cs_sel = (u16)(msr_data & 0xfffc); 2415 ss_sel = (u16)(msr_data + 8); 2416 2417 if (efer & EFER_LMA) { 2418 cs.d = 0; 2419 cs.l = 1; 2420 } 2421 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2422 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2423 2424 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2425 if (efer & EFER_LMA) { 2426 #ifdef CONFIG_X86_64 2427 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2428 2429 ops->get_msr(ctxt, 2430 ctxt->mode == X86EMUL_MODE_PROT64 ? 2431 MSR_LSTAR : MSR_CSTAR, &msr_data); 2432 ctxt->_eip = msr_data; 2433 2434 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2435 ctxt->eflags &= ~msr_data; 2436 ctxt->eflags |= X86_EFLAGS_FIXED; 2437 #endif 2438 } else { 2439 /* legacy mode */ 2440 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2441 ctxt->_eip = (u32)msr_data; 2442 2443 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2444 } 2445 2446 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2447 return X86EMUL_CONTINUE; 2448 } 2449 2450 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2451 { 2452 const struct x86_emulate_ops *ops = ctxt->ops; 2453 struct desc_struct cs, ss; 2454 u64 msr_data; 2455 u16 cs_sel, ss_sel; 2456 u64 efer = 0; 2457 2458 ops->get_msr(ctxt, MSR_EFER, &efer); 2459 /* inject #GP if in real mode */ 2460 if (ctxt->mode == X86EMUL_MODE_REAL) 2461 return emulate_gp(ctxt, 0); 2462 2463 /* 2464 * Not recognized on AMD in compat mode (but is recognized in legacy 2465 * mode). 2466 */ 2467 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2468 && !vendor_intel(ctxt)) 2469 return emulate_ud(ctxt); 2470 2471 /* sysenter/sysexit have not been tested in 64bit mode. */ 2472 if (ctxt->mode == X86EMUL_MODE_PROT64) 2473 return X86EMUL_UNHANDLEABLE; 2474 2475 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2476 if ((msr_data & 0xfffc) == 0x0) 2477 return emulate_gp(ctxt, 0); 2478 2479 setup_syscalls_segments(&cs, &ss); 2480 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2481 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2482 ss_sel = cs_sel + 8; 2483 if (efer & EFER_LMA) { 2484 cs.d = 0; 2485 cs.l = 1; 2486 } 2487 2488 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2489 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2490 2491 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2492 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2493 2494 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2495 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2496 (u32)msr_data; 2497 if (efer & EFER_LMA) 2498 ctxt->mode = X86EMUL_MODE_PROT64; 2499 2500 return X86EMUL_CONTINUE; 2501 } 2502 2503 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2504 { 2505 const struct x86_emulate_ops *ops = ctxt->ops; 2506 struct desc_struct cs, ss; 2507 u64 msr_data, rcx, rdx; 2508 int usermode; 2509 u16 cs_sel = 0, ss_sel = 0; 2510 2511 /* inject #GP if in real mode or Virtual 8086 mode */ 2512 if (ctxt->mode == X86EMUL_MODE_REAL || 2513 ctxt->mode == X86EMUL_MODE_VM86) 2514 return emulate_gp(ctxt, 0); 2515 2516 setup_syscalls_segments(&cs, &ss); 2517 2518 if ((ctxt->rex_prefix & 0x8) != 0x0) 2519 usermode = X86EMUL_MODE_PROT64; 2520 else 2521 usermode = X86EMUL_MODE_PROT32; 2522 2523 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2524 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2525 2526 cs.dpl = 3; 2527 ss.dpl = 3; 2528 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2529 switch (usermode) { 2530 case X86EMUL_MODE_PROT32: 2531 cs_sel = (u16)(msr_data + 16); 2532 if ((msr_data & 0xfffc) == 0x0) 2533 return emulate_gp(ctxt, 0); 2534 ss_sel = (u16)(msr_data + 24); 2535 rcx = (u32)rcx; 2536 rdx = (u32)rdx; 2537 break; 2538 case X86EMUL_MODE_PROT64: 2539 cs_sel = (u16)(msr_data + 32); 2540 if (msr_data == 0x0) 2541 return emulate_gp(ctxt, 0); 2542 ss_sel = cs_sel + 8; 2543 cs.d = 0; 2544 cs.l = 1; 2545 if (emul_is_noncanonical_address(rcx, ctxt) || 2546 emul_is_noncanonical_address(rdx, ctxt)) 2547 return emulate_gp(ctxt, 0); 2548 break; 2549 } 2550 cs_sel |= SEGMENT_RPL_MASK; 2551 ss_sel |= SEGMENT_RPL_MASK; 2552 2553 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2554 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2555 2556 ctxt->_eip = rdx; 2557 ctxt->mode = usermode; 2558 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2559 2560 return X86EMUL_CONTINUE; 2561 } 2562 2563 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2564 { 2565 int iopl; 2566 if (ctxt->mode == X86EMUL_MODE_REAL) 2567 return false; 2568 if (ctxt->mode == X86EMUL_MODE_VM86) 2569 return true; 2570 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2571 return ctxt->ops->cpl(ctxt) > iopl; 2572 } 2573 2574 #define VMWARE_PORT_VMPORT (0x5658) 2575 #define VMWARE_PORT_VMRPC (0x5659) 2576 2577 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2578 u16 port, u16 len) 2579 { 2580 const struct x86_emulate_ops *ops = ctxt->ops; 2581 struct desc_struct tr_seg; 2582 u32 base3; 2583 int r; 2584 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2585 unsigned mask = (1 << len) - 1; 2586 unsigned long base; 2587 2588 /* 2589 * VMware allows access to these ports even if denied 2590 * by TSS I/O permission bitmap. Mimic behavior. 2591 */ 2592 if (enable_vmware_backdoor && 2593 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2594 return true; 2595 2596 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2597 if (!tr_seg.p) 2598 return false; 2599 if (desc_limit_scaled(&tr_seg) < 103) 2600 return false; 2601 base = get_desc_base(&tr_seg); 2602 #ifdef CONFIG_X86_64 2603 base |= ((u64)base3) << 32; 2604 #endif 2605 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2606 if (r != X86EMUL_CONTINUE) 2607 return false; 2608 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2609 return false; 2610 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2611 if (r != X86EMUL_CONTINUE) 2612 return false; 2613 if ((perm >> bit_idx) & mask) 2614 return false; 2615 return true; 2616 } 2617 2618 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2619 u16 port, u16 len) 2620 { 2621 if (ctxt->perm_ok) 2622 return true; 2623 2624 if (emulator_bad_iopl(ctxt)) 2625 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2626 return false; 2627 2628 ctxt->perm_ok = true; 2629 2630 return true; 2631 } 2632 2633 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2634 { 2635 /* 2636 * Intel CPUs mask the counter and pointers in quite strange 2637 * manner when ECX is zero due to REP-string optimizations. 2638 */ 2639 #ifdef CONFIG_X86_64 2640 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2641 return; 2642 2643 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2644 2645 switch (ctxt->b) { 2646 case 0xa4: /* movsb */ 2647 case 0xa5: /* movsd/w */ 2648 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2649 fallthrough; 2650 case 0xaa: /* stosb */ 2651 case 0xab: /* stosd/w */ 2652 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2653 } 2654 #endif 2655 } 2656 2657 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2658 struct tss_segment_16 *tss) 2659 { 2660 tss->ip = ctxt->_eip; 2661 tss->flag = ctxt->eflags; 2662 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2663 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2664 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2665 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2666 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2667 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2668 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2669 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2670 2671 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2672 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2673 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2674 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2675 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2676 } 2677 2678 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2679 struct tss_segment_16 *tss) 2680 { 2681 int ret; 2682 u8 cpl; 2683 2684 ctxt->_eip = tss->ip; 2685 ctxt->eflags = tss->flag | 2; 2686 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2687 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2688 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2689 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2690 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2691 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2692 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2693 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2694 2695 /* 2696 * SDM says that segment selectors are loaded before segment 2697 * descriptors 2698 */ 2699 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2700 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2701 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2702 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2703 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2704 2705 cpl = tss->cs & 3; 2706 2707 /* 2708 * Now load segment descriptors. If fault happens at this stage 2709 * it is handled in a context of new task 2710 */ 2711 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 2712 X86_TRANSFER_TASK_SWITCH, NULL); 2713 if (ret != X86EMUL_CONTINUE) 2714 return ret; 2715 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2716 X86_TRANSFER_TASK_SWITCH, NULL); 2717 if (ret != X86EMUL_CONTINUE) 2718 return ret; 2719 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2720 X86_TRANSFER_TASK_SWITCH, NULL); 2721 if (ret != X86EMUL_CONTINUE) 2722 return ret; 2723 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2724 X86_TRANSFER_TASK_SWITCH, NULL); 2725 if (ret != X86EMUL_CONTINUE) 2726 return ret; 2727 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2728 X86_TRANSFER_TASK_SWITCH, NULL); 2729 if (ret != X86EMUL_CONTINUE) 2730 return ret; 2731 2732 return X86EMUL_CONTINUE; 2733 } 2734 2735 static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2736 ulong old_tss_base, struct desc_struct *new_desc) 2737 { 2738 struct tss_segment_16 tss_seg; 2739 int ret; 2740 u32 new_tss_base = get_desc_base(new_desc); 2741 2742 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2743 if (ret != X86EMUL_CONTINUE) 2744 return ret; 2745 2746 save_state_to_tss16(ctxt, &tss_seg); 2747 2748 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2749 if (ret != X86EMUL_CONTINUE) 2750 return ret; 2751 2752 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2753 if (ret != X86EMUL_CONTINUE) 2754 return ret; 2755 2756 if (old_tss_sel != 0xffff) { 2757 tss_seg.prev_task_link = old_tss_sel; 2758 2759 ret = linear_write_system(ctxt, new_tss_base, 2760 &tss_seg.prev_task_link, 2761 sizeof(tss_seg.prev_task_link)); 2762 if (ret != X86EMUL_CONTINUE) 2763 return ret; 2764 } 2765 2766 return load_state_from_tss16(ctxt, &tss_seg); 2767 } 2768 2769 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2770 struct tss_segment_32 *tss) 2771 { 2772 /* CR3 and ldt selector are not saved intentionally */ 2773 tss->eip = ctxt->_eip; 2774 tss->eflags = ctxt->eflags; 2775 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2776 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2777 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2778 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2779 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2780 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2781 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2782 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2783 2784 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2785 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2786 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2787 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2788 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2789 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2790 } 2791 2792 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2793 struct tss_segment_32 *tss) 2794 { 2795 int ret; 2796 u8 cpl; 2797 2798 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2799 return emulate_gp(ctxt, 0); 2800 ctxt->_eip = tss->eip; 2801 ctxt->eflags = tss->eflags | 2; 2802 2803 /* General purpose registers */ 2804 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2805 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2806 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2807 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2808 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2809 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2810 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2811 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2812 2813 /* 2814 * SDM says that segment selectors are loaded before segment 2815 * descriptors. This is important because CPL checks will 2816 * use CS.RPL. 2817 */ 2818 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2819 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2820 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2821 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2822 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2823 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2824 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2825 2826 /* 2827 * If we're switching between Protected Mode and VM86, we need to make 2828 * sure to update the mode before loading the segment descriptors so 2829 * that the selectors are interpreted correctly. 2830 */ 2831 if (ctxt->eflags & X86_EFLAGS_VM) { 2832 ctxt->mode = X86EMUL_MODE_VM86; 2833 cpl = 3; 2834 } else { 2835 ctxt->mode = X86EMUL_MODE_PROT32; 2836 cpl = tss->cs & 3; 2837 } 2838 2839 /* 2840 * Now load segment descriptors. If fault happens at this stage 2841 * it is handled in a context of new task 2842 */ 2843 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 2844 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 2845 if (ret != X86EMUL_CONTINUE) 2846 return ret; 2847 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2848 X86_TRANSFER_TASK_SWITCH, NULL); 2849 if (ret != X86EMUL_CONTINUE) 2850 return ret; 2851 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2852 X86_TRANSFER_TASK_SWITCH, NULL); 2853 if (ret != X86EMUL_CONTINUE) 2854 return ret; 2855 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2856 X86_TRANSFER_TASK_SWITCH, NULL); 2857 if (ret != X86EMUL_CONTINUE) 2858 return ret; 2859 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2860 X86_TRANSFER_TASK_SWITCH, NULL); 2861 if (ret != X86EMUL_CONTINUE) 2862 return ret; 2863 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 2864 X86_TRANSFER_TASK_SWITCH, NULL); 2865 if (ret != X86EMUL_CONTINUE) 2866 return ret; 2867 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 2868 X86_TRANSFER_TASK_SWITCH, NULL); 2869 2870 return ret; 2871 } 2872 2873 static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2874 ulong old_tss_base, struct desc_struct *new_desc) 2875 { 2876 struct tss_segment_32 tss_seg; 2877 int ret; 2878 u32 new_tss_base = get_desc_base(new_desc); 2879 u32 eip_offset = offsetof(struct tss_segment_32, eip); 2880 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 2881 2882 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2883 if (ret != X86EMUL_CONTINUE) 2884 return ret; 2885 2886 save_state_to_tss32(ctxt, &tss_seg); 2887 2888 /* Only GP registers and segment selectors are saved */ 2889 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 2890 ldt_sel_offset - eip_offset); 2891 if (ret != X86EMUL_CONTINUE) 2892 return ret; 2893 2894 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2895 if (ret != X86EMUL_CONTINUE) 2896 return ret; 2897 2898 if (old_tss_sel != 0xffff) { 2899 tss_seg.prev_task_link = old_tss_sel; 2900 2901 ret = linear_write_system(ctxt, new_tss_base, 2902 &tss_seg.prev_task_link, 2903 sizeof(tss_seg.prev_task_link)); 2904 if (ret != X86EMUL_CONTINUE) 2905 return ret; 2906 } 2907 2908 return load_state_from_tss32(ctxt, &tss_seg); 2909 } 2910 2911 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2912 u16 tss_selector, int idt_index, int reason, 2913 bool has_error_code, u32 error_code) 2914 { 2915 const struct x86_emulate_ops *ops = ctxt->ops; 2916 struct desc_struct curr_tss_desc, next_tss_desc; 2917 int ret; 2918 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2919 ulong old_tss_base = 2920 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2921 u32 desc_limit; 2922 ulong desc_addr, dr7; 2923 2924 /* FIXME: old_tss_base == ~0 ? */ 2925 2926 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2927 if (ret != X86EMUL_CONTINUE) 2928 return ret; 2929 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2930 if (ret != X86EMUL_CONTINUE) 2931 return ret; 2932 2933 /* FIXME: check that next_tss_desc is tss */ 2934 2935 /* 2936 * Check privileges. The three cases are task switch caused by... 2937 * 2938 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2939 * 2. Exception/IRQ/iret: No check is performed 2940 * 3. jmp/call to TSS/task-gate: No check is performed since the 2941 * hardware checks it before exiting. 2942 */ 2943 if (reason == TASK_SWITCH_GATE) { 2944 if (idt_index != -1) { 2945 /* Software interrupts */ 2946 struct desc_struct task_gate_desc; 2947 int dpl; 2948 2949 ret = read_interrupt_descriptor(ctxt, idt_index, 2950 &task_gate_desc); 2951 if (ret != X86EMUL_CONTINUE) 2952 return ret; 2953 2954 dpl = task_gate_desc.dpl; 2955 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2956 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2957 } 2958 } 2959 2960 desc_limit = desc_limit_scaled(&next_tss_desc); 2961 if (!next_tss_desc.p || 2962 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2963 desc_limit < 0x2b)) { 2964 return emulate_ts(ctxt, tss_selector & 0xfffc); 2965 } 2966 2967 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2968 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2969 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2970 } 2971 2972 if (reason == TASK_SWITCH_IRET) 2973 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2974 2975 /* set back link to prev task only if NT bit is set in eflags 2976 note that old_tss_sel is not used after this point */ 2977 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2978 old_tss_sel = 0xffff; 2979 2980 if (next_tss_desc.type & 8) 2981 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc); 2982 else 2983 ret = task_switch_16(ctxt, old_tss_sel, 2984 old_tss_base, &next_tss_desc); 2985 if (ret != X86EMUL_CONTINUE) 2986 return ret; 2987 2988 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2989 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2990 2991 if (reason != TASK_SWITCH_IRET) { 2992 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2993 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2994 } 2995 2996 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2997 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2998 2999 if (has_error_code) { 3000 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3001 ctxt->lock_prefix = 0; 3002 ctxt->src.val = (unsigned long) error_code; 3003 ret = em_push(ctxt); 3004 } 3005 3006 ops->get_dr(ctxt, 7, &dr7); 3007 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3008 3009 return ret; 3010 } 3011 3012 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3013 u16 tss_selector, int idt_index, int reason, 3014 bool has_error_code, u32 error_code) 3015 { 3016 int rc; 3017 3018 invalidate_registers(ctxt); 3019 ctxt->_eip = ctxt->eip; 3020 ctxt->dst.type = OP_NONE; 3021 3022 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3023 has_error_code, error_code); 3024 3025 if (rc == X86EMUL_CONTINUE) { 3026 ctxt->eip = ctxt->_eip; 3027 writeback_registers(ctxt); 3028 } 3029 3030 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3031 } 3032 3033 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3034 struct operand *op) 3035 { 3036 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3037 3038 register_address_increment(ctxt, reg, df * op->bytes); 3039 op->addr.mem.ea = register_address(ctxt, reg); 3040 } 3041 3042 static int em_das(struct x86_emulate_ctxt *ctxt) 3043 { 3044 u8 al, old_al; 3045 bool af, cf, old_cf; 3046 3047 cf = ctxt->eflags & X86_EFLAGS_CF; 3048 al = ctxt->dst.val; 3049 3050 old_al = al; 3051 old_cf = cf; 3052 cf = false; 3053 af = ctxt->eflags & X86_EFLAGS_AF; 3054 if ((al & 0x0f) > 9 || af) { 3055 al -= 6; 3056 cf = old_cf | (al >= 250); 3057 af = true; 3058 } else { 3059 af = false; 3060 } 3061 if (old_al > 0x99 || old_cf) { 3062 al -= 0x60; 3063 cf = true; 3064 } 3065 3066 ctxt->dst.val = al; 3067 /* Set PF, ZF, SF */ 3068 ctxt->src.type = OP_IMM; 3069 ctxt->src.val = 0; 3070 ctxt->src.bytes = 1; 3071 fastop(ctxt, em_or); 3072 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3073 if (cf) 3074 ctxt->eflags |= X86_EFLAGS_CF; 3075 if (af) 3076 ctxt->eflags |= X86_EFLAGS_AF; 3077 return X86EMUL_CONTINUE; 3078 } 3079 3080 static int em_aam(struct x86_emulate_ctxt *ctxt) 3081 { 3082 u8 al, ah; 3083 3084 if (ctxt->src.val == 0) 3085 return emulate_de(ctxt); 3086 3087 al = ctxt->dst.val & 0xff; 3088 ah = al / ctxt->src.val; 3089 al %= ctxt->src.val; 3090 3091 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3092 3093 /* Set PF, ZF, SF */ 3094 ctxt->src.type = OP_IMM; 3095 ctxt->src.val = 0; 3096 ctxt->src.bytes = 1; 3097 fastop(ctxt, em_or); 3098 3099 return X86EMUL_CONTINUE; 3100 } 3101 3102 static int em_aad(struct x86_emulate_ctxt *ctxt) 3103 { 3104 u8 al = ctxt->dst.val & 0xff; 3105 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3106 3107 al = (al + (ah * ctxt->src.val)) & 0xff; 3108 3109 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3110 3111 /* Set PF, ZF, SF */ 3112 ctxt->src.type = OP_IMM; 3113 ctxt->src.val = 0; 3114 ctxt->src.bytes = 1; 3115 fastop(ctxt, em_or); 3116 3117 return X86EMUL_CONTINUE; 3118 } 3119 3120 static int em_call(struct x86_emulate_ctxt *ctxt) 3121 { 3122 int rc; 3123 long rel = ctxt->src.val; 3124 3125 ctxt->src.val = (unsigned long)ctxt->_eip; 3126 rc = jmp_rel(ctxt, rel); 3127 if (rc != X86EMUL_CONTINUE) 3128 return rc; 3129 return em_push(ctxt); 3130 } 3131 3132 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3133 { 3134 u16 sel, old_cs; 3135 ulong old_eip; 3136 int rc; 3137 struct desc_struct old_desc, new_desc; 3138 const struct x86_emulate_ops *ops = ctxt->ops; 3139 int cpl = ctxt->ops->cpl(ctxt); 3140 enum x86emul_mode prev_mode = ctxt->mode; 3141 3142 old_eip = ctxt->_eip; 3143 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3144 3145 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3146 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3147 X86_TRANSFER_CALL_JMP, &new_desc); 3148 if (rc != X86EMUL_CONTINUE) 3149 return rc; 3150 3151 rc = assign_eip_far(ctxt, ctxt->src.val); 3152 if (rc != X86EMUL_CONTINUE) 3153 goto fail; 3154 3155 ctxt->src.val = old_cs; 3156 rc = em_push(ctxt); 3157 if (rc != X86EMUL_CONTINUE) 3158 goto fail; 3159 3160 ctxt->src.val = old_eip; 3161 rc = em_push(ctxt); 3162 /* If we failed, we tainted the memory, but the very least we should 3163 restore cs */ 3164 if (rc != X86EMUL_CONTINUE) { 3165 pr_warn_once("faulting far call emulation tainted memory\n"); 3166 goto fail; 3167 } 3168 return rc; 3169 fail: 3170 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3171 ctxt->mode = prev_mode; 3172 return rc; 3173 3174 } 3175 3176 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3177 { 3178 int rc; 3179 unsigned long eip; 3180 3181 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3182 if (rc != X86EMUL_CONTINUE) 3183 return rc; 3184 rc = assign_eip_near(ctxt, eip); 3185 if (rc != X86EMUL_CONTINUE) 3186 return rc; 3187 rsp_increment(ctxt, ctxt->src.val); 3188 return X86EMUL_CONTINUE; 3189 } 3190 3191 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3192 { 3193 /* Write back the register source. */ 3194 ctxt->src.val = ctxt->dst.val; 3195 write_register_operand(&ctxt->src); 3196 3197 /* Write back the memory destination with implicit LOCK prefix. */ 3198 ctxt->dst.val = ctxt->src.orig_val; 3199 ctxt->lock_prefix = 1; 3200 return X86EMUL_CONTINUE; 3201 } 3202 3203 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3204 { 3205 ctxt->dst.val = ctxt->src2.val; 3206 return fastop(ctxt, em_imul); 3207 } 3208 3209 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3210 { 3211 ctxt->dst.type = OP_REG; 3212 ctxt->dst.bytes = ctxt->src.bytes; 3213 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3214 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3215 3216 return X86EMUL_CONTINUE; 3217 } 3218 3219 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3220 { 3221 u64 tsc_aux = 0; 3222 3223 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3224 return emulate_ud(ctxt); 3225 3226 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3227 ctxt->dst.val = tsc_aux; 3228 return X86EMUL_CONTINUE; 3229 } 3230 3231 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3232 { 3233 u64 tsc = 0; 3234 3235 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3236 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3237 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3238 return X86EMUL_CONTINUE; 3239 } 3240 3241 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3242 { 3243 u64 pmc; 3244 3245 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3246 return emulate_gp(ctxt, 0); 3247 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3248 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3249 return X86EMUL_CONTINUE; 3250 } 3251 3252 static int em_mov(struct x86_emulate_ctxt *ctxt) 3253 { 3254 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3255 return X86EMUL_CONTINUE; 3256 } 3257 3258 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3259 { 3260 u16 tmp; 3261 3262 if (!ctxt->ops->guest_has_movbe(ctxt)) 3263 return emulate_ud(ctxt); 3264 3265 switch (ctxt->op_bytes) { 3266 case 2: 3267 /* 3268 * From MOVBE definition: "...When the operand size is 16 bits, 3269 * the upper word of the destination register remains unchanged 3270 * ..." 3271 * 3272 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3273 * rules so we have to do the operation almost per hand. 3274 */ 3275 tmp = (u16)ctxt->src.val; 3276 ctxt->dst.val &= ~0xffffUL; 3277 ctxt->dst.val |= (unsigned long)swab16(tmp); 3278 break; 3279 case 4: 3280 ctxt->dst.val = swab32((u32)ctxt->src.val); 3281 break; 3282 case 8: 3283 ctxt->dst.val = swab64(ctxt->src.val); 3284 break; 3285 default: 3286 BUG(); 3287 } 3288 return X86EMUL_CONTINUE; 3289 } 3290 3291 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3292 { 3293 int cr_num = ctxt->modrm_reg; 3294 int r; 3295 3296 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) 3297 return emulate_gp(ctxt, 0); 3298 3299 /* Disable writeback. */ 3300 ctxt->dst.type = OP_NONE; 3301 3302 if (cr_num == 0) { 3303 /* 3304 * CR0 write might have updated CR0.PE and/or CR0.PG 3305 * which can affect the cpu's execution mode. 3306 */ 3307 r = emulator_recalc_and_set_mode(ctxt); 3308 if (r != X86EMUL_CONTINUE) 3309 return r; 3310 } 3311 3312 return X86EMUL_CONTINUE; 3313 } 3314 3315 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3316 { 3317 unsigned long val; 3318 3319 if (ctxt->mode == X86EMUL_MODE_PROT64) 3320 val = ctxt->src.val & ~0ULL; 3321 else 3322 val = ctxt->src.val & ~0U; 3323 3324 /* #UD condition is already handled. */ 3325 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3326 return emulate_gp(ctxt, 0); 3327 3328 /* Disable writeback. */ 3329 ctxt->dst.type = OP_NONE; 3330 return X86EMUL_CONTINUE; 3331 } 3332 3333 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3334 { 3335 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3336 u64 msr_data; 3337 int r; 3338 3339 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3340 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3341 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data); 3342 3343 if (r == X86EMUL_PROPAGATE_FAULT) 3344 return emulate_gp(ctxt, 0); 3345 3346 return r; 3347 } 3348 3349 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3350 { 3351 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3352 u64 msr_data; 3353 int r; 3354 3355 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data); 3356 3357 if (r == X86EMUL_PROPAGATE_FAULT) 3358 return emulate_gp(ctxt, 0); 3359 3360 if (r == X86EMUL_CONTINUE) { 3361 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3362 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3363 } 3364 return r; 3365 } 3366 3367 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3368 { 3369 if (segment > VCPU_SREG_GS && 3370 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3371 ctxt->ops->cpl(ctxt) > 0) 3372 return emulate_gp(ctxt, 0); 3373 3374 ctxt->dst.val = get_segment_selector(ctxt, segment); 3375 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3376 ctxt->dst.bytes = 2; 3377 return X86EMUL_CONTINUE; 3378 } 3379 3380 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3381 { 3382 if (ctxt->modrm_reg > VCPU_SREG_GS) 3383 return emulate_ud(ctxt); 3384 3385 return em_store_sreg(ctxt, ctxt->modrm_reg); 3386 } 3387 3388 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3389 { 3390 u16 sel = ctxt->src.val; 3391 3392 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3393 return emulate_ud(ctxt); 3394 3395 if (ctxt->modrm_reg == VCPU_SREG_SS) 3396 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3397 3398 /* Disable writeback. */ 3399 ctxt->dst.type = OP_NONE; 3400 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3401 } 3402 3403 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3404 { 3405 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3406 } 3407 3408 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3409 { 3410 u16 sel = ctxt->src.val; 3411 3412 /* Disable writeback. */ 3413 ctxt->dst.type = OP_NONE; 3414 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3415 } 3416 3417 static int em_str(struct x86_emulate_ctxt *ctxt) 3418 { 3419 return em_store_sreg(ctxt, VCPU_SREG_TR); 3420 } 3421 3422 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3423 { 3424 u16 sel = ctxt->src.val; 3425 3426 /* Disable writeback. */ 3427 ctxt->dst.type = OP_NONE; 3428 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3429 } 3430 3431 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3432 { 3433 int rc; 3434 ulong linear; 3435 3436 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3437 if (rc == X86EMUL_CONTINUE) 3438 ctxt->ops->invlpg(ctxt, linear); 3439 /* Disable writeback. */ 3440 ctxt->dst.type = OP_NONE; 3441 return X86EMUL_CONTINUE; 3442 } 3443 3444 static int em_clts(struct x86_emulate_ctxt *ctxt) 3445 { 3446 ulong cr0; 3447 3448 cr0 = ctxt->ops->get_cr(ctxt, 0); 3449 cr0 &= ~X86_CR0_TS; 3450 ctxt->ops->set_cr(ctxt, 0, cr0); 3451 return X86EMUL_CONTINUE; 3452 } 3453 3454 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3455 { 3456 int rc = ctxt->ops->fix_hypercall(ctxt); 3457 3458 if (rc != X86EMUL_CONTINUE) 3459 return rc; 3460 3461 /* Let the processor re-execute the fixed hypercall */ 3462 ctxt->_eip = ctxt->eip; 3463 /* Disable writeback. */ 3464 ctxt->dst.type = OP_NONE; 3465 return X86EMUL_CONTINUE; 3466 } 3467 3468 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3469 void (*get)(struct x86_emulate_ctxt *ctxt, 3470 struct desc_ptr *ptr)) 3471 { 3472 struct desc_ptr desc_ptr; 3473 3474 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3475 ctxt->ops->cpl(ctxt) > 0) 3476 return emulate_gp(ctxt, 0); 3477 3478 if (ctxt->mode == X86EMUL_MODE_PROT64) 3479 ctxt->op_bytes = 8; 3480 get(ctxt, &desc_ptr); 3481 if (ctxt->op_bytes == 2) { 3482 ctxt->op_bytes = 4; 3483 desc_ptr.address &= 0x00ffffff; 3484 } 3485 /* Disable writeback. */ 3486 ctxt->dst.type = OP_NONE; 3487 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3488 &desc_ptr, 2 + ctxt->op_bytes); 3489 } 3490 3491 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3492 { 3493 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3494 } 3495 3496 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3497 { 3498 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3499 } 3500 3501 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3502 { 3503 struct desc_ptr desc_ptr; 3504 int rc; 3505 3506 if (ctxt->mode == X86EMUL_MODE_PROT64) 3507 ctxt->op_bytes = 8; 3508 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3509 &desc_ptr.size, &desc_ptr.address, 3510 ctxt->op_bytes); 3511 if (rc != X86EMUL_CONTINUE) 3512 return rc; 3513 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3514 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3515 return emulate_gp(ctxt, 0); 3516 if (lgdt) 3517 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3518 else 3519 ctxt->ops->set_idt(ctxt, &desc_ptr); 3520 /* Disable writeback. */ 3521 ctxt->dst.type = OP_NONE; 3522 return X86EMUL_CONTINUE; 3523 } 3524 3525 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3526 { 3527 return em_lgdt_lidt(ctxt, true); 3528 } 3529 3530 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3531 { 3532 return em_lgdt_lidt(ctxt, false); 3533 } 3534 3535 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3536 { 3537 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3538 ctxt->ops->cpl(ctxt) > 0) 3539 return emulate_gp(ctxt, 0); 3540 3541 if (ctxt->dst.type == OP_MEM) 3542 ctxt->dst.bytes = 2; 3543 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3544 return X86EMUL_CONTINUE; 3545 } 3546 3547 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3548 { 3549 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3550 | (ctxt->src.val & 0x0f)); 3551 ctxt->dst.type = OP_NONE; 3552 return X86EMUL_CONTINUE; 3553 } 3554 3555 static int em_loop(struct x86_emulate_ctxt *ctxt) 3556 { 3557 int rc = X86EMUL_CONTINUE; 3558 3559 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3560 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3561 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3562 rc = jmp_rel(ctxt, ctxt->src.val); 3563 3564 return rc; 3565 } 3566 3567 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3568 { 3569 int rc = X86EMUL_CONTINUE; 3570 3571 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3572 rc = jmp_rel(ctxt, ctxt->src.val); 3573 3574 return rc; 3575 } 3576 3577 static int em_in(struct x86_emulate_ctxt *ctxt) 3578 { 3579 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3580 &ctxt->dst.val)) 3581 return X86EMUL_IO_NEEDED; 3582 3583 return X86EMUL_CONTINUE; 3584 } 3585 3586 static int em_out(struct x86_emulate_ctxt *ctxt) 3587 { 3588 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3589 &ctxt->src.val, 1); 3590 /* Disable writeback. */ 3591 ctxt->dst.type = OP_NONE; 3592 return X86EMUL_CONTINUE; 3593 } 3594 3595 static int em_cli(struct x86_emulate_ctxt *ctxt) 3596 { 3597 if (emulator_bad_iopl(ctxt)) 3598 return emulate_gp(ctxt, 0); 3599 3600 ctxt->eflags &= ~X86_EFLAGS_IF; 3601 return X86EMUL_CONTINUE; 3602 } 3603 3604 static int em_sti(struct x86_emulate_ctxt *ctxt) 3605 { 3606 if (emulator_bad_iopl(ctxt)) 3607 return emulate_gp(ctxt, 0); 3608 3609 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3610 ctxt->eflags |= X86_EFLAGS_IF; 3611 return X86EMUL_CONTINUE; 3612 } 3613 3614 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3615 { 3616 u32 eax, ebx, ecx, edx; 3617 u64 msr = 0; 3618 3619 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3620 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3621 ctxt->ops->cpl(ctxt)) { 3622 return emulate_gp(ctxt, 0); 3623 } 3624 3625 eax = reg_read(ctxt, VCPU_REGS_RAX); 3626 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3627 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3628 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3629 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3630 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3631 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3632 return X86EMUL_CONTINUE; 3633 } 3634 3635 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3636 { 3637 u32 flags; 3638 3639 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3640 X86_EFLAGS_SF; 3641 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3642 3643 ctxt->eflags &= ~0xffUL; 3644 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3645 return X86EMUL_CONTINUE; 3646 } 3647 3648 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3649 { 3650 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3651 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3652 return X86EMUL_CONTINUE; 3653 } 3654 3655 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3656 { 3657 switch (ctxt->op_bytes) { 3658 #ifdef CONFIG_X86_64 3659 case 8: 3660 asm("bswap %0" : "+r"(ctxt->dst.val)); 3661 break; 3662 #endif 3663 default: 3664 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3665 break; 3666 } 3667 return X86EMUL_CONTINUE; 3668 } 3669 3670 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3671 { 3672 /* emulating clflush regardless of cpuid */ 3673 return X86EMUL_CONTINUE; 3674 } 3675 3676 static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 3677 { 3678 /* emulating clflushopt regardless of cpuid */ 3679 return X86EMUL_CONTINUE; 3680 } 3681 3682 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3683 { 3684 ctxt->dst.val = (s32) ctxt->src.val; 3685 return X86EMUL_CONTINUE; 3686 } 3687 3688 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 3689 { 3690 if (!ctxt->ops->guest_has_fxsr(ctxt)) 3691 return emulate_ud(ctxt); 3692 3693 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 3694 return emulate_nm(ctxt); 3695 3696 /* 3697 * Don't emulate a case that should never be hit, instead of working 3698 * around a lack of fxsave64/fxrstor64 on old compilers. 3699 */ 3700 if (ctxt->mode >= X86EMUL_MODE_PROT64) 3701 return X86EMUL_UNHANDLEABLE; 3702 3703 return X86EMUL_CONTINUE; 3704 } 3705 3706 /* 3707 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 3708 * and restore MXCSR. 3709 */ 3710 static size_t __fxstate_size(int nregs) 3711 { 3712 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 3713 } 3714 3715 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 3716 { 3717 bool cr4_osfxsr; 3718 if (ctxt->mode == X86EMUL_MODE_PROT64) 3719 return __fxstate_size(16); 3720 3721 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 3722 return __fxstate_size(cr4_osfxsr ? 8 : 0); 3723 } 3724 3725 /* 3726 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 3727 * 1) 16 bit mode 3728 * 2) 32 bit mode 3729 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 3730 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 3731 * save and restore 3732 * 3) 64-bit mode with REX.W prefix 3733 * - like (2), but XMM 8-15 are being saved and restored 3734 * 4) 64-bit mode without REX.W prefix 3735 * - like (3), but FIP and FDP are 64 bit 3736 * 3737 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 3738 * desired result. (4) is not emulated. 3739 * 3740 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 3741 * and FPU DS) should match. 3742 */ 3743 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 3744 { 3745 struct fxregs_state fx_state; 3746 int rc; 3747 3748 rc = check_fxsr(ctxt); 3749 if (rc != X86EMUL_CONTINUE) 3750 return rc; 3751 3752 kvm_fpu_get(); 3753 3754 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 3755 3756 kvm_fpu_put(); 3757 3758 if (rc != X86EMUL_CONTINUE) 3759 return rc; 3760 3761 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 3762 fxstate_size(ctxt)); 3763 } 3764 3765 /* 3766 * FXRSTOR might restore XMM registers not provided by the guest. Fill 3767 * in the host registers (via FXSAVE) instead, so they won't be modified. 3768 * (preemption has to stay disabled until FXRSTOR). 3769 * 3770 * Use noinline to keep the stack for other functions called by callers small. 3771 */ 3772 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 3773 const size_t used_size) 3774 { 3775 struct fxregs_state fx_tmp; 3776 int rc; 3777 3778 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 3779 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 3780 __fxstate_size(16) - used_size); 3781 3782 return rc; 3783 } 3784 3785 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 3786 { 3787 struct fxregs_state fx_state; 3788 int rc; 3789 size_t size; 3790 3791 rc = check_fxsr(ctxt); 3792 if (rc != X86EMUL_CONTINUE) 3793 return rc; 3794 3795 size = fxstate_size(ctxt); 3796 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 3797 if (rc != X86EMUL_CONTINUE) 3798 return rc; 3799 3800 kvm_fpu_get(); 3801 3802 if (size < __fxstate_size(16)) { 3803 rc = fxregs_fixup(&fx_state, size); 3804 if (rc != X86EMUL_CONTINUE) 3805 goto out; 3806 } 3807 3808 if (fx_state.mxcsr >> 16) { 3809 rc = emulate_gp(ctxt, 0); 3810 goto out; 3811 } 3812 3813 if (rc == X86EMUL_CONTINUE) 3814 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 3815 3816 out: 3817 kvm_fpu_put(); 3818 3819 return rc; 3820 } 3821 3822 static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 3823 { 3824 u32 eax, ecx, edx; 3825 3826 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE)) 3827 return emulate_ud(ctxt); 3828 3829 eax = reg_read(ctxt, VCPU_REGS_RAX); 3830 edx = reg_read(ctxt, VCPU_REGS_RDX); 3831 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3832 3833 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 3834 return emulate_gp(ctxt, 0); 3835 3836 return X86EMUL_CONTINUE; 3837 } 3838 3839 static bool valid_cr(int nr) 3840 { 3841 switch (nr) { 3842 case 0: 3843 case 2 ... 4: 3844 case 8: 3845 return true; 3846 default: 3847 return false; 3848 } 3849 } 3850 3851 static int check_cr_access(struct x86_emulate_ctxt *ctxt) 3852 { 3853 if (!valid_cr(ctxt->modrm_reg)) 3854 return emulate_ud(ctxt); 3855 3856 return X86EMUL_CONTINUE; 3857 } 3858 3859 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3860 { 3861 unsigned long dr7; 3862 3863 ctxt->ops->get_dr(ctxt, 7, &dr7); 3864 3865 return dr7 & DR7_GD; 3866 } 3867 3868 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3869 { 3870 int dr = ctxt->modrm_reg; 3871 u64 cr4; 3872 3873 if (dr > 7) 3874 return emulate_ud(ctxt); 3875 3876 cr4 = ctxt->ops->get_cr(ctxt, 4); 3877 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3878 return emulate_ud(ctxt); 3879 3880 if (check_dr7_gd(ctxt)) { 3881 ulong dr6; 3882 3883 ctxt->ops->get_dr(ctxt, 6, &dr6); 3884 dr6 &= ~DR_TRAP_BITS; 3885 dr6 |= DR6_BD | DR6_ACTIVE_LOW; 3886 ctxt->ops->set_dr(ctxt, 6, dr6); 3887 return emulate_db(ctxt); 3888 } 3889 3890 return X86EMUL_CONTINUE; 3891 } 3892 3893 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3894 { 3895 u64 new_val = ctxt->src.val64; 3896 int dr = ctxt->modrm_reg; 3897 3898 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3899 return emulate_gp(ctxt, 0); 3900 3901 return check_dr_read(ctxt); 3902 } 3903 3904 static int check_svme(struct x86_emulate_ctxt *ctxt) 3905 { 3906 u64 efer = 0; 3907 3908 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3909 3910 if (!(efer & EFER_SVME)) 3911 return emulate_ud(ctxt); 3912 3913 return X86EMUL_CONTINUE; 3914 } 3915 3916 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3917 { 3918 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3919 3920 /* Valid physical address? */ 3921 if (rax & 0xffff000000000000ULL) 3922 return emulate_gp(ctxt, 0); 3923 3924 return check_svme(ctxt); 3925 } 3926 3927 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3928 { 3929 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3930 3931 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3932 return emulate_gp(ctxt, 0); 3933 3934 return X86EMUL_CONTINUE; 3935 } 3936 3937 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3938 { 3939 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3940 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3941 3942 /* 3943 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 3944 * in Ring3 when CR4.PCE=0. 3945 */ 3946 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 3947 return X86EMUL_CONTINUE; 3948 3949 /* 3950 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE 3951 * check however is unnecessary because CPL is always 0 outside 3952 * protected mode. 3953 */ 3954 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3955 ctxt->ops->check_pmc(ctxt, rcx)) 3956 return emulate_gp(ctxt, 0); 3957 3958 return X86EMUL_CONTINUE; 3959 } 3960 3961 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3962 { 3963 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3964 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3965 return emulate_gp(ctxt, 0); 3966 3967 return X86EMUL_CONTINUE; 3968 } 3969 3970 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3971 { 3972 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3973 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3974 return emulate_gp(ctxt, 0); 3975 3976 return X86EMUL_CONTINUE; 3977 } 3978 3979 #define D(_y) { .flags = (_y) } 3980 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 3981 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 3982 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3983 #define N D(NotImpl) 3984 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3985 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3986 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3987 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 3988 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 3989 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3990 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3991 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 3992 #define II(_f, _e, _i) \ 3993 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 3994 #define IIP(_f, _e, _i, _p) \ 3995 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 3996 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3997 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3998 3999 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4000 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4001 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4002 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4003 #define I2bvIP(_f, _e, _i, _p) \ 4004 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4005 4006 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4007 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4008 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4009 4010 static const struct opcode group7_rm0[] = { 4011 N, 4012 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4013 N, N, N, N, N, N, 4014 }; 4015 4016 static const struct opcode group7_rm1[] = { 4017 DI(SrcNone | Priv, monitor), 4018 DI(SrcNone | Priv, mwait), 4019 N, N, N, N, N, N, 4020 }; 4021 4022 static const struct opcode group7_rm2[] = { 4023 N, 4024 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 4025 N, N, N, N, N, N, 4026 }; 4027 4028 static const struct opcode group7_rm3[] = { 4029 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4030 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4031 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4032 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4033 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4034 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4035 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4036 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4037 }; 4038 4039 static const struct opcode group7_rm7[] = { 4040 N, 4041 DIP(SrcNone, rdtscp, check_rdtsc), 4042 N, N, N, N, N, N, 4043 }; 4044 4045 static const struct opcode group1[] = { 4046 F(Lock, em_add), 4047 F(Lock | PageTable, em_or), 4048 F(Lock, em_adc), 4049 F(Lock, em_sbb), 4050 F(Lock | PageTable, em_and), 4051 F(Lock, em_sub), 4052 F(Lock, em_xor), 4053 F(NoWrite, em_cmp), 4054 }; 4055 4056 static const struct opcode group1A[] = { 4057 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4058 }; 4059 4060 static const struct opcode group2[] = { 4061 F(DstMem | ModRM, em_rol), 4062 F(DstMem | ModRM, em_ror), 4063 F(DstMem | ModRM, em_rcl), 4064 F(DstMem | ModRM, em_rcr), 4065 F(DstMem | ModRM, em_shl), 4066 F(DstMem | ModRM, em_shr), 4067 F(DstMem | ModRM, em_shl), 4068 F(DstMem | ModRM, em_sar), 4069 }; 4070 4071 static const struct opcode group3[] = { 4072 F(DstMem | SrcImm | NoWrite, em_test), 4073 F(DstMem | SrcImm | NoWrite, em_test), 4074 F(DstMem | SrcNone | Lock, em_not), 4075 F(DstMem | SrcNone | Lock, em_neg), 4076 F(DstXacc | Src2Mem, em_mul_ex), 4077 F(DstXacc | Src2Mem, em_imul_ex), 4078 F(DstXacc | Src2Mem, em_div_ex), 4079 F(DstXacc | Src2Mem, em_idiv_ex), 4080 }; 4081 4082 static const struct opcode group4[] = { 4083 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4084 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4085 N, N, N, N, N, N, 4086 }; 4087 4088 static const struct opcode group5[] = { 4089 F(DstMem | SrcNone | Lock, em_inc), 4090 F(DstMem | SrcNone | Lock, em_dec), 4091 I(SrcMem | NearBranch | IsBranch, em_call_near_abs), 4092 I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far), 4093 I(SrcMem | NearBranch | IsBranch, em_jmp_abs), 4094 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), 4095 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4096 }; 4097 4098 static const struct opcode group6[] = { 4099 II(Prot | DstMem, em_sldt, sldt), 4100 II(Prot | DstMem, em_str, str), 4101 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4102 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4103 N, N, N, N, 4104 }; 4105 4106 static const struct group_dual group7 = { { 4107 II(Mov | DstMem, em_sgdt, sgdt), 4108 II(Mov | DstMem, em_sidt, sidt), 4109 II(SrcMem | Priv, em_lgdt, lgdt), 4110 II(SrcMem | Priv, em_lidt, lidt), 4111 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4112 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4113 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4114 }, { 4115 EXT(0, group7_rm0), 4116 EXT(0, group7_rm1), 4117 EXT(0, group7_rm2), 4118 EXT(0, group7_rm3), 4119 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4120 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4121 EXT(0, group7_rm7), 4122 } }; 4123 4124 static const struct opcode group8[] = { 4125 N, N, N, N, 4126 F(DstMem | SrcImmByte | NoWrite, em_bt), 4127 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4128 F(DstMem | SrcImmByte | Lock, em_btr), 4129 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4130 }; 4131 4132 /* 4133 * The "memory" destination is actually always a register, since we come 4134 * from the register case of group9. 4135 */ 4136 static const struct gprefix pfx_0f_c7_7 = { 4137 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4138 }; 4139 4140 4141 static const struct group_dual group9 = { { 4142 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4143 }, { 4144 N, N, N, N, N, N, N, 4145 GP(0, &pfx_0f_c7_7), 4146 } }; 4147 4148 static const struct opcode group11[] = { 4149 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4150 X7(D(Undefined)), 4151 }; 4152 4153 static const struct gprefix pfx_0f_ae_7 = { 4154 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4155 }; 4156 4157 static const struct group_dual group15 = { { 4158 I(ModRM | Aligned16, em_fxsave), 4159 I(ModRM | Aligned16, em_fxrstor), 4160 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4161 }, { 4162 N, N, N, N, N, N, N, N, 4163 } }; 4164 4165 static const struct gprefix pfx_0f_6f_0f_7f = { 4166 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4167 }; 4168 4169 static const struct instr_dual instr_dual_0f_2b = { 4170 I(0, em_mov), N 4171 }; 4172 4173 static const struct gprefix pfx_0f_2b = { 4174 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4175 }; 4176 4177 static const struct gprefix pfx_0f_10_0f_11 = { 4178 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4179 }; 4180 4181 static const struct gprefix pfx_0f_28_0f_29 = { 4182 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4183 }; 4184 4185 static const struct gprefix pfx_0f_e7 = { 4186 N, I(Sse, em_mov), N, N, 4187 }; 4188 4189 static const struct escape escape_d9 = { { 4190 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4191 }, { 4192 /* 0xC0 - 0xC7 */ 4193 N, N, N, N, N, N, N, N, 4194 /* 0xC8 - 0xCF */ 4195 N, N, N, N, N, N, N, N, 4196 /* 0xD0 - 0xC7 */ 4197 N, N, N, N, N, N, N, N, 4198 /* 0xD8 - 0xDF */ 4199 N, N, N, N, N, N, N, N, 4200 /* 0xE0 - 0xE7 */ 4201 N, N, N, N, N, N, N, N, 4202 /* 0xE8 - 0xEF */ 4203 N, N, N, N, N, N, N, N, 4204 /* 0xF0 - 0xF7 */ 4205 N, N, N, N, N, N, N, N, 4206 /* 0xF8 - 0xFF */ 4207 N, N, N, N, N, N, N, N, 4208 } }; 4209 4210 static const struct escape escape_db = { { 4211 N, N, N, N, N, N, N, N, 4212 }, { 4213 /* 0xC0 - 0xC7 */ 4214 N, N, N, N, N, N, N, N, 4215 /* 0xC8 - 0xCF */ 4216 N, N, N, N, N, N, N, N, 4217 /* 0xD0 - 0xC7 */ 4218 N, N, N, N, N, N, N, N, 4219 /* 0xD8 - 0xDF */ 4220 N, N, N, N, N, N, N, N, 4221 /* 0xE0 - 0xE7 */ 4222 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4223 /* 0xE8 - 0xEF */ 4224 N, N, N, N, N, N, N, N, 4225 /* 0xF0 - 0xF7 */ 4226 N, N, N, N, N, N, N, N, 4227 /* 0xF8 - 0xFF */ 4228 N, N, N, N, N, N, N, N, 4229 } }; 4230 4231 static const struct escape escape_dd = { { 4232 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4233 }, { 4234 /* 0xC0 - 0xC7 */ 4235 N, N, N, N, N, N, N, N, 4236 /* 0xC8 - 0xCF */ 4237 N, N, N, N, N, N, N, N, 4238 /* 0xD0 - 0xC7 */ 4239 N, N, N, N, N, N, N, N, 4240 /* 0xD8 - 0xDF */ 4241 N, N, N, N, N, N, N, N, 4242 /* 0xE0 - 0xE7 */ 4243 N, N, N, N, N, N, N, N, 4244 /* 0xE8 - 0xEF */ 4245 N, N, N, N, N, N, N, N, 4246 /* 0xF0 - 0xF7 */ 4247 N, N, N, N, N, N, N, N, 4248 /* 0xF8 - 0xFF */ 4249 N, N, N, N, N, N, N, N, 4250 } }; 4251 4252 static const struct instr_dual instr_dual_0f_c3 = { 4253 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4254 }; 4255 4256 static const struct mode_dual mode_dual_63 = { 4257 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4258 }; 4259 4260 static const struct instr_dual instr_dual_8d = { 4261 D(DstReg | SrcMem | ModRM | NoAccess), N 4262 }; 4263 4264 static const struct opcode opcode_table[256] = { 4265 /* 0x00 - 0x07 */ 4266 F6ALU(Lock, em_add), 4267 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4268 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4269 /* 0x08 - 0x0F */ 4270 F6ALU(Lock | PageTable, em_or), 4271 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4272 N, 4273 /* 0x10 - 0x17 */ 4274 F6ALU(Lock, em_adc), 4275 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4276 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4277 /* 0x18 - 0x1F */ 4278 F6ALU(Lock, em_sbb), 4279 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4280 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4281 /* 0x20 - 0x27 */ 4282 F6ALU(Lock | PageTable, em_and), N, N, 4283 /* 0x28 - 0x2F */ 4284 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4285 /* 0x30 - 0x37 */ 4286 F6ALU(Lock, em_xor), N, N, 4287 /* 0x38 - 0x3F */ 4288 F6ALU(NoWrite, em_cmp), N, N, 4289 /* 0x40 - 0x4F */ 4290 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4291 /* 0x50 - 0x57 */ 4292 X8(I(SrcReg | Stack, em_push)), 4293 /* 0x58 - 0x5F */ 4294 X8(I(DstReg | Stack, em_pop)), 4295 /* 0x60 - 0x67 */ 4296 I(ImplicitOps | Stack | No64, em_pusha), 4297 I(ImplicitOps | Stack | No64, em_popa), 4298 N, MD(ModRM, &mode_dual_63), 4299 N, N, N, N, 4300 /* 0x68 - 0x6F */ 4301 I(SrcImm | Mov | Stack, em_push), 4302 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4303 I(SrcImmByte | Mov | Stack, em_push), 4304 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4305 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4306 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4307 /* 0x70 - 0x7F */ 4308 X16(D(SrcImmByte | NearBranch | IsBranch)), 4309 /* 0x80 - 0x87 */ 4310 G(ByteOp | DstMem | SrcImm, group1), 4311 G(DstMem | SrcImm, group1), 4312 G(ByteOp | DstMem | SrcImm | No64, group1), 4313 G(DstMem | SrcImmByte, group1), 4314 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4315 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4316 /* 0x88 - 0x8F */ 4317 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4318 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4319 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4320 ID(0, &instr_dual_8d), 4321 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4322 G(0, group1A), 4323 /* 0x90 - 0x97 */ 4324 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4325 /* 0x98 - 0x9F */ 4326 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4327 I(SrcImmFAddr | No64 | IsBranch, em_call_far), N, 4328 II(ImplicitOps | Stack, em_pushf, pushf), 4329 II(ImplicitOps | Stack, em_popf, popf), 4330 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4331 /* 0xA0 - 0xA7 */ 4332 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4333 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4334 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4335 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4336 /* 0xA8 - 0xAF */ 4337 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4338 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4339 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4340 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4341 /* 0xB0 - 0xB7 */ 4342 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4343 /* 0xB8 - 0xBF */ 4344 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4345 /* 0xC0 - 0xC7 */ 4346 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4347 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch, em_ret_near_imm), 4348 I(ImplicitOps | NearBranch | IsBranch, em_ret), 4349 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4350 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4351 G(ByteOp, group11), G(0, group11), 4352 /* 0xC8 - 0xCF */ 4353 I(Stack | SrcImmU16 | Src2ImmByte | IsBranch, em_enter), 4354 I(Stack | IsBranch, em_leave), 4355 I(ImplicitOps | SrcImmU16 | IsBranch, em_ret_far_imm), 4356 I(ImplicitOps | IsBranch, em_ret_far), 4357 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch, intn), 4358 D(ImplicitOps | No64 | IsBranch), 4359 II(ImplicitOps | IsBranch, em_iret, iret), 4360 /* 0xD0 - 0xD7 */ 4361 G(Src2One | ByteOp, group2), G(Src2One, group2), 4362 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4363 I(DstAcc | SrcImmUByte | No64, em_aam), 4364 I(DstAcc | SrcImmUByte | No64, em_aad), 4365 F(DstAcc | ByteOp | No64, em_salc), 4366 I(DstAcc | SrcXLat | ByteOp, em_mov), 4367 /* 0xD8 - 0xDF */ 4368 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4369 /* 0xE0 - 0xE7 */ 4370 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), 4371 I(SrcImmByte | NearBranch | IsBranch, em_jcxz), 4372 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4373 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4374 /* 0xE8 - 0xEF */ 4375 I(SrcImm | NearBranch | IsBranch, em_call), 4376 D(SrcImm | ImplicitOps | NearBranch | IsBranch), 4377 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), 4378 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), 4379 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4380 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4381 /* 0xF0 - 0xF7 */ 4382 N, DI(ImplicitOps, icebp), N, N, 4383 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4384 G(ByteOp, group3), G(0, group3), 4385 /* 0xF8 - 0xFF */ 4386 D(ImplicitOps), D(ImplicitOps), 4387 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4388 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4389 }; 4390 4391 static const struct opcode twobyte_table[256] = { 4392 /* 0x00 - 0x0F */ 4393 G(0, group6), GD(0, &group7), N, N, 4394 N, I(ImplicitOps | EmulateOnUD | IsBranch, em_syscall), 4395 II(ImplicitOps | Priv, em_clts, clts), N, 4396 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4397 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4398 /* 0x10 - 0x1F */ 4399 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4400 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4401 N, N, N, N, N, N, 4402 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4403 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4404 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4405 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4406 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4407 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4408 /* 0x20 - 0x2F */ 4409 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4410 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4411 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4412 check_cr_access), 4413 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4414 check_dr_write), 4415 N, N, N, N, 4416 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4417 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4418 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4419 N, N, N, N, 4420 /* 0x30 - 0x3F */ 4421 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4422 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4423 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4424 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4425 I(ImplicitOps | EmulateOnUD | IsBranch, em_sysenter), 4426 I(ImplicitOps | Priv | EmulateOnUD | IsBranch, em_sysexit), 4427 N, N, 4428 N, N, N, N, N, N, N, N, 4429 /* 0x40 - 0x4F */ 4430 X16(D(DstReg | SrcMem | ModRM)), 4431 /* 0x50 - 0x5F */ 4432 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4433 /* 0x60 - 0x6F */ 4434 N, N, N, N, 4435 N, N, N, N, 4436 N, N, N, N, 4437 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4438 /* 0x70 - 0x7F */ 4439 N, N, N, N, 4440 N, N, N, N, 4441 N, N, N, N, 4442 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4443 /* 0x80 - 0x8F */ 4444 X16(D(SrcImm | NearBranch | IsBranch)), 4445 /* 0x90 - 0x9F */ 4446 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4447 /* 0xA0 - 0xA7 */ 4448 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4449 II(ImplicitOps, em_cpuid, cpuid), 4450 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4451 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4452 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4453 /* 0xA8 - 0xAF */ 4454 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4455 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4456 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4457 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4458 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4459 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4460 /* 0xB0 - 0xB7 */ 4461 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4462 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4463 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4464 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4465 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4466 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4467 /* 0xB8 - 0xBF */ 4468 N, N, 4469 G(BitOp, group8), 4470 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4471 I(DstReg | SrcMem | ModRM, em_bsf_c), 4472 I(DstReg | SrcMem | ModRM, em_bsr_c), 4473 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4474 /* 0xC0 - 0xC7 */ 4475 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4476 N, ID(0, &instr_dual_0f_c3), 4477 N, N, N, GD(0, &group9), 4478 /* 0xC8 - 0xCF */ 4479 X8(I(DstReg, em_bswap)), 4480 /* 0xD0 - 0xDF */ 4481 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4482 /* 0xE0 - 0xEF */ 4483 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4484 N, N, N, N, N, N, N, N, 4485 /* 0xF0 - 0xFF */ 4486 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4487 }; 4488 4489 static const struct instr_dual instr_dual_0f_38_f0 = { 4490 I(DstReg | SrcMem | Mov, em_movbe), N 4491 }; 4492 4493 static const struct instr_dual instr_dual_0f_38_f1 = { 4494 I(DstMem | SrcReg | Mov, em_movbe), N 4495 }; 4496 4497 static const struct gprefix three_byte_0f_38_f0 = { 4498 ID(0, &instr_dual_0f_38_f0), N, N, N 4499 }; 4500 4501 static const struct gprefix three_byte_0f_38_f1 = { 4502 ID(0, &instr_dual_0f_38_f1), N, N, N 4503 }; 4504 4505 /* 4506 * Insns below are selected by the prefix which indexed by the third opcode 4507 * byte. 4508 */ 4509 static const struct opcode opcode_map_0f_38[256] = { 4510 /* 0x00 - 0x7f */ 4511 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4512 /* 0x80 - 0xef */ 4513 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4514 /* 0xf0 - 0xf1 */ 4515 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4516 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4517 /* 0xf2 - 0xff */ 4518 N, N, X4(N), X8(N) 4519 }; 4520 4521 #undef D 4522 #undef N 4523 #undef G 4524 #undef GD 4525 #undef I 4526 #undef GP 4527 #undef EXT 4528 #undef MD 4529 #undef ID 4530 4531 #undef D2bv 4532 #undef D2bvIP 4533 #undef I2bv 4534 #undef I2bvIP 4535 #undef I6ALU 4536 4537 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4538 { 4539 unsigned size; 4540 4541 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4542 if (size == 8) 4543 size = 4; 4544 return size; 4545 } 4546 4547 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4548 unsigned size, bool sign_extension) 4549 { 4550 int rc = X86EMUL_CONTINUE; 4551 4552 op->type = OP_IMM; 4553 op->bytes = size; 4554 op->addr.mem.ea = ctxt->_eip; 4555 /* NB. Immediates are sign-extended as necessary. */ 4556 switch (op->bytes) { 4557 case 1: 4558 op->val = insn_fetch(s8, ctxt); 4559 break; 4560 case 2: 4561 op->val = insn_fetch(s16, ctxt); 4562 break; 4563 case 4: 4564 op->val = insn_fetch(s32, ctxt); 4565 break; 4566 case 8: 4567 op->val = insn_fetch(s64, ctxt); 4568 break; 4569 } 4570 if (!sign_extension) { 4571 switch (op->bytes) { 4572 case 1: 4573 op->val &= 0xff; 4574 break; 4575 case 2: 4576 op->val &= 0xffff; 4577 break; 4578 case 4: 4579 op->val &= 0xffffffff; 4580 break; 4581 } 4582 } 4583 done: 4584 return rc; 4585 } 4586 4587 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4588 unsigned d) 4589 { 4590 int rc = X86EMUL_CONTINUE; 4591 4592 switch (d) { 4593 case OpReg: 4594 decode_register_operand(ctxt, op); 4595 break; 4596 case OpImmUByte: 4597 rc = decode_imm(ctxt, op, 1, false); 4598 break; 4599 case OpMem: 4600 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4601 mem_common: 4602 *op = ctxt->memop; 4603 ctxt->memopp = op; 4604 if (ctxt->d & BitOp) 4605 fetch_bit_operand(ctxt); 4606 op->orig_val = op->val; 4607 break; 4608 case OpMem64: 4609 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4610 goto mem_common; 4611 case OpAcc: 4612 op->type = OP_REG; 4613 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4614 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4615 fetch_register_operand(op); 4616 op->orig_val = op->val; 4617 break; 4618 case OpAccLo: 4619 op->type = OP_REG; 4620 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4621 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4622 fetch_register_operand(op); 4623 op->orig_val = op->val; 4624 break; 4625 case OpAccHi: 4626 if (ctxt->d & ByteOp) { 4627 op->type = OP_NONE; 4628 break; 4629 } 4630 op->type = OP_REG; 4631 op->bytes = ctxt->op_bytes; 4632 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4633 fetch_register_operand(op); 4634 op->orig_val = op->val; 4635 break; 4636 case OpDI: 4637 op->type = OP_MEM; 4638 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4639 op->addr.mem.ea = 4640 register_address(ctxt, VCPU_REGS_RDI); 4641 op->addr.mem.seg = VCPU_SREG_ES; 4642 op->val = 0; 4643 op->count = 1; 4644 break; 4645 case OpDX: 4646 op->type = OP_REG; 4647 op->bytes = 2; 4648 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4649 fetch_register_operand(op); 4650 break; 4651 case OpCL: 4652 op->type = OP_IMM; 4653 op->bytes = 1; 4654 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4655 break; 4656 case OpImmByte: 4657 rc = decode_imm(ctxt, op, 1, true); 4658 break; 4659 case OpOne: 4660 op->type = OP_IMM; 4661 op->bytes = 1; 4662 op->val = 1; 4663 break; 4664 case OpImm: 4665 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4666 break; 4667 case OpImm64: 4668 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4669 break; 4670 case OpMem8: 4671 ctxt->memop.bytes = 1; 4672 if (ctxt->memop.type == OP_REG) { 4673 ctxt->memop.addr.reg = decode_register(ctxt, 4674 ctxt->modrm_rm, true); 4675 fetch_register_operand(&ctxt->memop); 4676 } 4677 goto mem_common; 4678 case OpMem16: 4679 ctxt->memop.bytes = 2; 4680 goto mem_common; 4681 case OpMem32: 4682 ctxt->memop.bytes = 4; 4683 goto mem_common; 4684 case OpImmU16: 4685 rc = decode_imm(ctxt, op, 2, false); 4686 break; 4687 case OpImmU: 4688 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4689 break; 4690 case OpSI: 4691 op->type = OP_MEM; 4692 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4693 op->addr.mem.ea = 4694 register_address(ctxt, VCPU_REGS_RSI); 4695 op->addr.mem.seg = ctxt->seg_override; 4696 op->val = 0; 4697 op->count = 1; 4698 break; 4699 case OpXLat: 4700 op->type = OP_MEM; 4701 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4702 op->addr.mem.ea = 4703 address_mask(ctxt, 4704 reg_read(ctxt, VCPU_REGS_RBX) + 4705 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4706 op->addr.mem.seg = ctxt->seg_override; 4707 op->val = 0; 4708 break; 4709 case OpImmFAddr: 4710 op->type = OP_IMM; 4711 op->addr.mem.ea = ctxt->_eip; 4712 op->bytes = ctxt->op_bytes + 2; 4713 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4714 break; 4715 case OpMemFAddr: 4716 ctxt->memop.bytes = ctxt->op_bytes + 2; 4717 goto mem_common; 4718 case OpES: 4719 op->type = OP_IMM; 4720 op->val = VCPU_SREG_ES; 4721 break; 4722 case OpCS: 4723 op->type = OP_IMM; 4724 op->val = VCPU_SREG_CS; 4725 break; 4726 case OpSS: 4727 op->type = OP_IMM; 4728 op->val = VCPU_SREG_SS; 4729 break; 4730 case OpDS: 4731 op->type = OP_IMM; 4732 op->val = VCPU_SREG_DS; 4733 break; 4734 case OpFS: 4735 op->type = OP_IMM; 4736 op->val = VCPU_SREG_FS; 4737 break; 4738 case OpGS: 4739 op->type = OP_IMM; 4740 op->val = VCPU_SREG_GS; 4741 break; 4742 case OpImplicit: 4743 /* Special instructions do their own operand decoding. */ 4744 default: 4745 op->type = OP_NONE; /* Disable writeback. */ 4746 break; 4747 } 4748 4749 done: 4750 return rc; 4751 } 4752 4753 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) 4754 { 4755 int rc = X86EMUL_CONTINUE; 4756 int mode = ctxt->mode; 4757 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4758 bool op_prefix = false; 4759 bool has_seg_override = false; 4760 struct opcode opcode; 4761 u16 dummy; 4762 struct desc_struct desc; 4763 4764 ctxt->memop.type = OP_NONE; 4765 ctxt->memopp = NULL; 4766 ctxt->_eip = ctxt->eip; 4767 ctxt->fetch.ptr = ctxt->fetch.data; 4768 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4769 ctxt->opcode_len = 1; 4770 ctxt->intercept = x86_intercept_none; 4771 if (insn_len > 0) 4772 memcpy(ctxt->fetch.data, insn, insn_len); 4773 else { 4774 rc = __do_insn_fetch_bytes(ctxt, 1); 4775 if (rc != X86EMUL_CONTINUE) 4776 goto done; 4777 } 4778 4779 switch (mode) { 4780 case X86EMUL_MODE_REAL: 4781 case X86EMUL_MODE_VM86: 4782 def_op_bytes = def_ad_bytes = 2; 4783 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 4784 if (desc.d) 4785 def_op_bytes = def_ad_bytes = 4; 4786 break; 4787 case X86EMUL_MODE_PROT16: 4788 def_op_bytes = def_ad_bytes = 2; 4789 break; 4790 case X86EMUL_MODE_PROT32: 4791 def_op_bytes = def_ad_bytes = 4; 4792 break; 4793 #ifdef CONFIG_X86_64 4794 case X86EMUL_MODE_PROT64: 4795 def_op_bytes = 4; 4796 def_ad_bytes = 8; 4797 break; 4798 #endif 4799 default: 4800 return EMULATION_FAILED; 4801 } 4802 4803 ctxt->op_bytes = def_op_bytes; 4804 ctxt->ad_bytes = def_ad_bytes; 4805 4806 /* Legacy prefixes. */ 4807 for (;;) { 4808 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4809 case 0x66: /* operand-size override */ 4810 op_prefix = true; 4811 /* switch between 2/4 bytes */ 4812 ctxt->op_bytes = def_op_bytes ^ 6; 4813 break; 4814 case 0x67: /* address-size override */ 4815 if (mode == X86EMUL_MODE_PROT64) 4816 /* switch between 4/8 bytes */ 4817 ctxt->ad_bytes = def_ad_bytes ^ 12; 4818 else 4819 /* switch between 2/4 bytes */ 4820 ctxt->ad_bytes = def_ad_bytes ^ 6; 4821 break; 4822 case 0x26: /* ES override */ 4823 has_seg_override = true; 4824 ctxt->seg_override = VCPU_SREG_ES; 4825 break; 4826 case 0x2e: /* CS override */ 4827 has_seg_override = true; 4828 ctxt->seg_override = VCPU_SREG_CS; 4829 break; 4830 case 0x36: /* SS override */ 4831 has_seg_override = true; 4832 ctxt->seg_override = VCPU_SREG_SS; 4833 break; 4834 case 0x3e: /* DS override */ 4835 has_seg_override = true; 4836 ctxt->seg_override = VCPU_SREG_DS; 4837 break; 4838 case 0x64: /* FS override */ 4839 has_seg_override = true; 4840 ctxt->seg_override = VCPU_SREG_FS; 4841 break; 4842 case 0x65: /* GS override */ 4843 has_seg_override = true; 4844 ctxt->seg_override = VCPU_SREG_GS; 4845 break; 4846 case 0x40 ... 0x4f: /* REX */ 4847 if (mode != X86EMUL_MODE_PROT64) 4848 goto done_prefixes; 4849 ctxt->rex_prefix = ctxt->b; 4850 continue; 4851 case 0xf0: /* LOCK */ 4852 ctxt->lock_prefix = 1; 4853 break; 4854 case 0xf2: /* REPNE/REPNZ */ 4855 case 0xf3: /* REP/REPE/REPZ */ 4856 ctxt->rep_prefix = ctxt->b; 4857 break; 4858 default: 4859 goto done_prefixes; 4860 } 4861 4862 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4863 4864 ctxt->rex_prefix = 0; 4865 } 4866 4867 done_prefixes: 4868 4869 /* REX prefix. */ 4870 if (ctxt->rex_prefix & 8) 4871 ctxt->op_bytes = 8; /* REX.W */ 4872 4873 /* Opcode byte(s). */ 4874 opcode = opcode_table[ctxt->b]; 4875 /* Two-byte opcode? */ 4876 if (ctxt->b == 0x0f) { 4877 ctxt->opcode_len = 2; 4878 ctxt->b = insn_fetch(u8, ctxt); 4879 opcode = twobyte_table[ctxt->b]; 4880 4881 /* 0F_38 opcode map */ 4882 if (ctxt->b == 0x38) { 4883 ctxt->opcode_len = 3; 4884 ctxt->b = insn_fetch(u8, ctxt); 4885 opcode = opcode_map_0f_38[ctxt->b]; 4886 } 4887 } 4888 ctxt->d = opcode.flags; 4889 4890 if (ctxt->d & ModRM) 4891 ctxt->modrm = insn_fetch(u8, ctxt); 4892 4893 /* vex-prefix instructions are not implemented */ 4894 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 4895 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 4896 ctxt->d = NotImpl; 4897 } 4898 4899 while (ctxt->d & GroupMask) { 4900 switch (ctxt->d & GroupMask) { 4901 case Group: 4902 goffset = (ctxt->modrm >> 3) & 7; 4903 opcode = opcode.u.group[goffset]; 4904 break; 4905 case GroupDual: 4906 goffset = (ctxt->modrm >> 3) & 7; 4907 if ((ctxt->modrm >> 6) == 3) 4908 opcode = opcode.u.gdual->mod3[goffset]; 4909 else 4910 opcode = opcode.u.gdual->mod012[goffset]; 4911 break; 4912 case RMExt: 4913 goffset = ctxt->modrm & 7; 4914 opcode = opcode.u.group[goffset]; 4915 break; 4916 case Prefix: 4917 if (ctxt->rep_prefix && op_prefix) 4918 return EMULATION_FAILED; 4919 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4920 switch (simd_prefix) { 4921 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4922 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4923 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4924 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4925 } 4926 break; 4927 case Escape: 4928 if (ctxt->modrm > 0xbf) { 4929 size_t size = ARRAY_SIZE(opcode.u.esc->high); 4930 u32 index = array_index_nospec( 4931 ctxt->modrm - 0xc0, size); 4932 4933 opcode = opcode.u.esc->high[index]; 4934 } else { 4935 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4936 } 4937 break; 4938 case InstrDual: 4939 if ((ctxt->modrm >> 6) == 3) 4940 opcode = opcode.u.idual->mod3; 4941 else 4942 opcode = opcode.u.idual->mod012; 4943 break; 4944 case ModeDual: 4945 if (ctxt->mode == X86EMUL_MODE_PROT64) 4946 opcode = opcode.u.mdual->mode64; 4947 else 4948 opcode = opcode.u.mdual->mode32; 4949 break; 4950 default: 4951 return EMULATION_FAILED; 4952 } 4953 4954 ctxt->d &= ~(u64)GroupMask; 4955 ctxt->d |= opcode.flags; 4956 } 4957 4958 ctxt->is_branch = opcode.flags & IsBranch; 4959 4960 /* Unrecognised? */ 4961 if (ctxt->d == 0) 4962 return EMULATION_FAILED; 4963 4964 ctxt->execute = opcode.u.execute; 4965 4966 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) && 4967 likely(!(ctxt->d & EmulateOnUD))) 4968 return EMULATION_FAILED; 4969 4970 if (unlikely(ctxt->d & 4971 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 4972 No16))) { 4973 /* 4974 * These are copied unconditionally here, and checked unconditionally 4975 * in x86_emulate_insn. 4976 */ 4977 ctxt->check_perm = opcode.check_perm; 4978 ctxt->intercept = opcode.intercept; 4979 4980 if (ctxt->d & NotImpl) 4981 return EMULATION_FAILED; 4982 4983 if (mode == X86EMUL_MODE_PROT64) { 4984 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 4985 ctxt->op_bytes = 8; 4986 else if (ctxt->d & NearBranch) 4987 ctxt->op_bytes = 8; 4988 } 4989 4990 if (ctxt->d & Op3264) { 4991 if (mode == X86EMUL_MODE_PROT64) 4992 ctxt->op_bytes = 8; 4993 else 4994 ctxt->op_bytes = 4; 4995 } 4996 4997 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 4998 ctxt->op_bytes = 4; 4999 5000 if (ctxt->d & Sse) 5001 ctxt->op_bytes = 16; 5002 else if (ctxt->d & Mmx) 5003 ctxt->op_bytes = 8; 5004 } 5005 5006 /* ModRM and SIB bytes. */ 5007 if (ctxt->d & ModRM) { 5008 rc = decode_modrm(ctxt, &ctxt->memop); 5009 if (!has_seg_override) { 5010 has_seg_override = true; 5011 ctxt->seg_override = ctxt->modrm_seg; 5012 } 5013 } else if (ctxt->d & MemAbs) 5014 rc = decode_abs(ctxt, &ctxt->memop); 5015 if (rc != X86EMUL_CONTINUE) 5016 goto done; 5017 5018 if (!has_seg_override) 5019 ctxt->seg_override = VCPU_SREG_DS; 5020 5021 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5022 5023 /* 5024 * Decode and fetch the source operand: register, memory 5025 * or immediate. 5026 */ 5027 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5028 if (rc != X86EMUL_CONTINUE) 5029 goto done; 5030 5031 /* 5032 * Decode and fetch the second source operand: register, memory 5033 * or immediate. 5034 */ 5035 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5036 if (rc != X86EMUL_CONTINUE) 5037 goto done; 5038 5039 /* Decode and fetch the destination operand: register or memory. */ 5040 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5041 5042 if (ctxt->rip_relative && likely(ctxt->memopp)) 5043 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5044 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5045 5046 done: 5047 if (rc == X86EMUL_PROPAGATE_FAULT) 5048 ctxt->have_exception = true; 5049 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5050 } 5051 5052 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5053 { 5054 return ctxt->d & PageTable; 5055 } 5056 5057 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5058 { 5059 /* The second termination condition only applies for REPE 5060 * and REPNE. Test if the repeat string operation prefix is 5061 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5062 * corresponding termination condition according to: 5063 * - if REPE/REPZ and ZF = 0 then done 5064 * - if REPNE/REPNZ and ZF = 1 then done 5065 */ 5066 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5067 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5068 && (((ctxt->rep_prefix == REPE_PREFIX) && 5069 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5070 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5071 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5072 return true; 5073 5074 return false; 5075 } 5076 5077 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5078 { 5079 int rc; 5080 5081 kvm_fpu_get(); 5082 rc = asm_safe("fwait"); 5083 kvm_fpu_put(); 5084 5085 if (unlikely(rc != X86EMUL_CONTINUE)) 5086 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5087 5088 return X86EMUL_CONTINUE; 5089 } 5090 5091 static void fetch_possible_mmx_operand(struct operand *op) 5092 { 5093 if (op->type == OP_MM) 5094 kvm_read_mmx_reg(op->addr.mm, &op->mm_val); 5095 } 5096 5097 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop) 5098 { 5099 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5100 5101 if (!(ctxt->d & ByteOp)) 5102 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5103 5104 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5105 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5106 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5107 : "c"(ctxt->src2.val)); 5108 5109 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5110 if (!fop) /* exception is returned in fop variable */ 5111 return emulate_de(ctxt); 5112 return X86EMUL_CONTINUE; 5113 } 5114 5115 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5116 { 5117 /* Clear fields that are set conditionally but read without a guard. */ 5118 ctxt->rip_relative = false; 5119 ctxt->rex_prefix = 0; 5120 ctxt->lock_prefix = 0; 5121 ctxt->rep_prefix = 0; 5122 ctxt->regs_valid = 0; 5123 ctxt->regs_dirty = 0; 5124 5125 ctxt->io_read.pos = 0; 5126 ctxt->io_read.end = 0; 5127 ctxt->mem_read.end = 0; 5128 } 5129 5130 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5131 { 5132 const struct x86_emulate_ops *ops = ctxt->ops; 5133 int rc = X86EMUL_CONTINUE; 5134 int saved_dst_type = ctxt->dst.type; 5135 unsigned emul_flags; 5136 5137 ctxt->mem_read.pos = 0; 5138 5139 /* LOCK prefix is allowed only with some instructions */ 5140 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5141 rc = emulate_ud(ctxt); 5142 goto done; 5143 } 5144 5145 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5146 rc = emulate_ud(ctxt); 5147 goto done; 5148 } 5149 5150 emul_flags = ctxt->ops->get_hflags(ctxt); 5151 if (unlikely(ctxt->d & 5152 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5153 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5154 (ctxt->d & Undefined)) { 5155 rc = emulate_ud(ctxt); 5156 goto done; 5157 } 5158 5159 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5160 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5161 rc = emulate_ud(ctxt); 5162 goto done; 5163 } 5164 5165 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5166 rc = emulate_nm(ctxt); 5167 goto done; 5168 } 5169 5170 if (ctxt->d & Mmx) { 5171 rc = flush_pending_x87_faults(ctxt); 5172 if (rc != X86EMUL_CONTINUE) 5173 goto done; 5174 /* 5175 * Now that we know the fpu is exception safe, we can fetch 5176 * operands from it. 5177 */ 5178 fetch_possible_mmx_operand(&ctxt->src); 5179 fetch_possible_mmx_operand(&ctxt->src2); 5180 if (!(ctxt->d & Mov)) 5181 fetch_possible_mmx_operand(&ctxt->dst); 5182 } 5183 5184 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5185 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5186 X86_ICPT_PRE_EXCEPT); 5187 if (rc != X86EMUL_CONTINUE) 5188 goto done; 5189 } 5190 5191 /* Instruction can only be executed in protected mode */ 5192 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5193 rc = emulate_ud(ctxt); 5194 goto done; 5195 } 5196 5197 /* Privileged instruction can be executed only in CPL=0 */ 5198 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5199 if (ctxt->d & PrivUD) 5200 rc = emulate_ud(ctxt); 5201 else 5202 rc = emulate_gp(ctxt, 0); 5203 goto done; 5204 } 5205 5206 /* Do instruction specific permission checks */ 5207 if (ctxt->d & CheckPerm) { 5208 rc = ctxt->check_perm(ctxt); 5209 if (rc != X86EMUL_CONTINUE) 5210 goto done; 5211 } 5212 5213 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5214 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5215 X86_ICPT_POST_EXCEPT); 5216 if (rc != X86EMUL_CONTINUE) 5217 goto done; 5218 } 5219 5220 if (ctxt->rep_prefix && (ctxt->d & String)) { 5221 /* All REP prefixes have the same first termination condition */ 5222 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5223 string_registers_quirk(ctxt); 5224 ctxt->eip = ctxt->_eip; 5225 ctxt->eflags &= ~X86_EFLAGS_RF; 5226 goto done; 5227 } 5228 } 5229 } 5230 5231 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5232 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5233 ctxt->src.valptr, ctxt->src.bytes); 5234 if (rc != X86EMUL_CONTINUE) 5235 goto done; 5236 ctxt->src.orig_val64 = ctxt->src.val64; 5237 } 5238 5239 if (ctxt->src2.type == OP_MEM) { 5240 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5241 &ctxt->src2.val, ctxt->src2.bytes); 5242 if (rc != X86EMUL_CONTINUE) 5243 goto done; 5244 } 5245 5246 if ((ctxt->d & DstMask) == ImplicitOps) 5247 goto special_insn; 5248 5249 5250 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5251 /* optimisation - avoid slow emulated read if Mov */ 5252 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5253 &ctxt->dst.val, ctxt->dst.bytes); 5254 if (rc != X86EMUL_CONTINUE) { 5255 if (!(ctxt->d & NoWrite) && 5256 rc == X86EMUL_PROPAGATE_FAULT && 5257 ctxt->exception.vector == PF_VECTOR) 5258 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5259 goto done; 5260 } 5261 } 5262 /* Copy full 64-bit value for CMPXCHG8B. */ 5263 ctxt->dst.orig_val64 = ctxt->dst.val64; 5264 5265 special_insn: 5266 5267 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5268 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5269 X86_ICPT_POST_MEMACCESS); 5270 if (rc != X86EMUL_CONTINUE) 5271 goto done; 5272 } 5273 5274 if (ctxt->rep_prefix && (ctxt->d & String)) 5275 ctxt->eflags |= X86_EFLAGS_RF; 5276 else 5277 ctxt->eflags &= ~X86_EFLAGS_RF; 5278 5279 if (ctxt->execute) { 5280 if (ctxt->d & Fastop) 5281 rc = fastop(ctxt, ctxt->fop); 5282 else 5283 rc = ctxt->execute(ctxt); 5284 if (rc != X86EMUL_CONTINUE) 5285 goto done; 5286 goto writeback; 5287 } 5288 5289 if (ctxt->opcode_len == 2) 5290 goto twobyte_insn; 5291 else if (ctxt->opcode_len == 3) 5292 goto threebyte_insn; 5293 5294 switch (ctxt->b) { 5295 case 0x70 ... 0x7f: /* jcc (short) */ 5296 if (test_cc(ctxt->b, ctxt->eflags)) 5297 rc = jmp_rel(ctxt, ctxt->src.val); 5298 break; 5299 case 0x8d: /* lea r16/r32, m */ 5300 ctxt->dst.val = ctxt->src.addr.mem.ea; 5301 break; 5302 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5303 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5304 ctxt->dst.type = OP_NONE; 5305 else 5306 rc = em_xchg(ctxt); 5307 break; 5308 case 0x98: /* cbw/cwde/cdqe */ 5309 switch (ctxt->op_bytes) { 5310 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5311 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5312 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5313 } 5314 break; 5315 case 0xcc: /* int3 */ 5316 rc = emulate_int(ctxt, 3); 5317 break; 5318 case 0xcd: /* int n */ 5319 rc = emulate_int(ctxt, ctxt->src.val); 5320 break; 5321 case 0xce: /* into */ 5322 if (ctxt->eflags & X86_EFLAGS_OF) 5323 rc = emulate_int(ctxt, 4); 5324 break; 5325 case 0xe9: /* jmp rel */ 5326 case 0xeb: /* jmp rel short */ 5327 rc = jmp_rel(ctxt, ctxt->src.val); 5328 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5329 break; 5330 case 0xf4: /* hlt */ 5331 ctxt->ops->halt(ctxt); 5332 break; 5333 case 0xf5: /* cmc */ 5334 /* complement carry flag from eflags reg */ 5335 ctxt->eflags ^= X86_EFLAGS_CF; 5336 break; 5337 case 0xf8: /* clc */ 5338 ctxt->eflags &= ~X86_EFLAGS_CF; 5339 break; 5340 case 0xf9: /* stc */ 5341 ctxt->eflags |= X86_EFLAGS_CF; 5342 break; 5343 case 0xfc: /* cld */ 5344 ctxt->eflags &= ~X86_EFLAGS_DF; 5345 break; 5346 case 0xfd: /* std */ 5347 ctxt->eflags |= X86_EFLAGS_DF; 5348 break; 5349 default: 5350 goto cannot_emulate; 5351 } 5352 5353 if (rc != X86EMUL_CONTINUE) 5354 goto done; 5355 5356 writeback: 5357 if (ctxt->d & SrcWrite) { 5358 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5359 rc = writeback(ctxt, &ctxt->src); 5360 if (rc != X86EMUL_CONTINUE) 5361 goto done; 5362 } 5363 if (!(ctxt->d & NoWrite)) { 5364 rc = writeback(ctxt, &ctxt->dst); 5365 if (rc != X86EMUL_CONTINUE) 5366 goto done; 5367 } 5368 5369 /* 5370 * restore dst type in case the decoding will be reused 5371 * (happens for string instruction ) 5372 */ 5373 ctxt->dst.type = saved_dst_type; 5374 5375 if ((ctxt->d & SrcMask) == SrcSI) 5376 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5377 5378 if ((ctxt->d & DstMask) == DstDI) 5379 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5380 5381 if (ctxt->rep_prefix && (ctxt->d & String)) { 5382 unsigned int count; 5383 struct read_cache *r = &ctxt->io_read; 5384 if ((ctxt->d & SrcMask) == SrcSI) 5385 count = ctxt->src.count; 5386 else 5387 count = ctxt->dst.count; 5388 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5389 5390 if (!string_insn_completed(ctxt)) { 5391 /* 5392 * Re-enter guest when pio read ahead buffer is empty 5393 * or, if it is not used, after each 1024 iteration. 5394 */ 5395 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5396 (r->end == 0 || r->end != r->pos)) { 5397 /* 5398 * Reset read cache. Usually happens before 5399 * decode, but since instruction is restarted 5400 * we have to do it here. 5401 */ 5402 ctxt->mem_read.end = 0; 5403 writeback_registers(ctxt); 5404 return EMULATION_RESTART; 5405 } 5406 goto done; /* skip rip writeback */ 5407 } 5408 ctxt->eflags &= ~X86_EFLAGS_RF; 5409 } 5410 5411 ctxt->eip = ctxt->_eip; 5412 if (ctxt->mode != X86EMUL_MODE_PROT64) 5413 ctxt->eip = (u32)ctxt->_eip; 5414 5415 done: 5416 if (rc == X86EMUL_PROPAGATE_FAULT) { 5417 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt)) 5418 return EMULATION_FAILED; 5419 ctxt->have_exception = true; 5420 } 5421 if (rc == X86EMUL_INTERCEPTED) 5422 return EMULATION_INTERCEPTED; 5423 5424 if (rc == X86EMUL_CONTINUE) 5425 writeback_registers(ctxt); 5426 5427 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5428 5429 twobyte_insn: 5430 switch (ctxt->b) { 5431 case 0x09: /* wbinvd */ 5432 (ctxt->ops->wbinvd)(ctxt); 5433 break; 5434 case 0x08: /* invd */ 5435 case 0x0d: /* GrpP (prefetch) */ 5436 case 0x18: /* Grp16 (prefetch/nop) */ 5437 case 0x1f: /* nop */ 5438 break; 5439 case 0x20: /* mov cr, reg */ 5440 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5441 break; 5442 case 0x21: /* mov from dr to reg */ 5443 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5444 break; 5445 case 0x40 ... 0x4f: /* cmov */ 5446 if (test_cc(ctxt->b, ctxt->eflags)) 5447 ctxt->dst.val = ctxt->src.val; 5448 else if (ctxt->op_bytes != 4) 5449 ctxt->dst.type = OP_NONE; /* no writeback */ 5450 break; 5451 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5452 if (test_cc(ctxt->b, ctxt->eflags)) 5453 rc = jmp_rel(ctxt, ctxt->src.val); 5454 break; 5455 case 0x90 ... 0x9f: /* setcc r/m8 */ 5456 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5457 break; 5458 case 0xb6 ... 0xb7: /* movzx */ 5459 ctxt->dst.bytes = ctxt->op_bytes; 5460 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5461 : (u16) ctxt->src.val; 5462 break; 5463 case 0xbe ... 0xbf: /* movsx */ 5464 ctxt->dst.bytes = ctxt->op_bytes; 5465 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5466 (s16) ctxt->src.val; 5467 break; 5468 default: 5469 goto cannot_emulate; 5470 } 5471 5472 threebyte_insn: 5473 5474 if (rc != X86EMUL_CONTINUE) 5475 goto done; 5476 5477 goto writeback; 5478 5479 cannot_emulate: 5480 return EMULATION_FAILED; 5481 } 5482 5483 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5484 { 5485 invalidate_registers(ctxt); 5486 } 5487 5488 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5489 { 5490 writeback_registers(ctxt); 5491 } 5492 5493 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5494 { 5495 if (ctxt->rep_prefix && (ctxt->d & String)) 5496 return false; 5497 5498 if (ctxt->d & TwoMemOp) 5499 return false; 5500 5501 return true; 5502 } 5503