xref: /openbmc/linux/arch/x86/kvm/emulate.c (revision 83a530e1)
1 /******************************************************************************
2  * emulate.c
3  *
4  * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5  *
6  * Copyright (c) 2005 Keir Fraser
7  *
8  * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9  * privileged instructions:
10  *
11  * Copyright (C) 2006 Qumranet
12  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13  *
14  *   Avi Kivity <avi@qumranet.com>
15  *   Yaniv Kamay <yaniv@qumranet.com>
16  *
17  * This work is licensed under the terms of the GNU GPL, version 2.  See
18  * the COPYING file in the top-level directory.
19  *
20  * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21  */
22 
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <asm/kvm_emulate.h>
26 #include <linux/stringify.h>
27 #include <asm/debugreg.h>
28 #include <asm/nospec-branch.h>
29 
30 #include "x86.h"
31 #include "tss.h"
32 #include "mmu.h"
33 #include "pmu.h"
34 
35 /*
36  * Operand types
37  */
38 #define OpNone             0ull
39 #define OpImplicit         1ull  /* No generic decode */
40 #define OpReg              2ull  /* Register */
41 #define OpMem              3ull  /* Memory */
42 #define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
43 #define OpDI               5ull  /* ES:DI/EDI/RDI */
44 #define OpMem64            6ull  /* Memory, 64-bit */
45 #define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
46 #define OpDX               8ull  /* DX register */
47 #define OpCL               9ull  /* CL register (for shifts) */
48 #define OpImmByte         10ull  /* 8-bit sign extended immediate */
49 #define OpOne             11ull  /* Implied 1 */
50 #define OpImm             12ull  /* Sign extended up to 32-bit immediate */
51 #define OpMem16           13ull  /* Memory operand (16-bit). */
52 #define OpMem32           14ull  /* Memory operand (32-bit). */
53 #define OpImmU            15ull  /* Immediate operand, zero extended */
54 #define OpSI              16ull  /* SI/ESI/RSI */
55 #define OpImmFAddr        17ull  /* Immediate far address */
56 #define OpMemFAddr        18ull  /* Far address in memory */
57 #define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
58 #define OpES              20ull  /* ES */
59 #define OpCS              21ull  /* CS */
60 #define OpSS              22ull  /* SS */
61 #define OpDS              23ull  /* DS */
62 #define OpFS              24ull  /* FS */
63 #define OpGS              25ull  /* GS */
64 #define OpMem8            26ull  /* 8-bit zero extended memory operand */
65 #define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
66 #define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
67 #define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
68 #define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
69 
70 #define OpBits             5  /* Width of operand field */
71 #define OpMask             ((1ull << OpBits) - 1)
72 
73 /*
74  * Opcode effective-address decode tables.
75  * Note that we only emulate instructions that have at least one memory
76  * operand (excluding implicit stack references). We assume that stack
77  * references and instruction fetches will never occur in special memory
78  * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
79  * not be handled.
80  */
81 
82 /* Operand sizes: 8-bit operands or specified/overridden size. */
83 #define ByteOp      (1<<0)	/* 8-bit operands. */
84 /* Destination operand type. */
85 #define DstShift    1
86 #define ImplicitOps (OpImplicit << DstShift)
87 #define DstReg      (OpReg << DstShift)
88 #define DstMem      (OpMem << DstShift)
89 #define DstAcc      (OpAcc << DstShift)
90 #define DstDI       (OpDI << DstShift)
91 #define DstMem64    (OpMem64 << DstShift)
92 #define DstMem16    (OpMem16 << DstShift)
93 #define DstImmUByte (OpImmUByte << DstShift)
94 #define DstDX       (OpDX << DstShift)
95 #define DstAccLo    (OpAccLo << DstShift)
96 #define DstMask     (OpMask << DstShift)
97 /* Source operand type. */
98 #define SrcShift    6
99 #define SrcNone     (OpNone << SrcShift)
100 #define SrcReg      (OpReg << SrcShift)
101 #define SrcMem      (OpMem << SrcShift)
102 #define SrcMem16    (OpMem16 << SrcShift)
103 #define SrcMem32    (OpMem32 << SrcShift)
104 #define SrcImm      (OpImm << SrcShift)
105 #define SrcImmByte  (OpImmByte << SrcShift)
106 #define SrcOne      (OpOne << SrcShift)
107 #define SrcImmUByte (OpImmUByte << SrcShift)
108 #define SrcImmU     (OpImmU << SrcShift)
109 #define SrcSI       (OpSI << SrcShift)
110 #define SrcXLat     (OpXLat << SrcShift)
111 #define SrcImmFAddr (OpImmFAddr << SrcShift)
112 #define SrcMemFAddr (OpMemFAddr << SrcShift)
113 #define SrcAcc      (OpAcc << SrcShift)
114 #define SrcImmU16   (OpImmU16 << SrcShift)
115 #define SrcImm64    (OpImm64 << SrcShift)
116 #define SrcDX       (OpDX << SrcShift)
117 #define SrcMem8     (OpMem8 << SrcShift)
118 #define SrcAccHi    (OpAccHi << SrcShift)
119 #define SrcMask     (OpMask << SrcShift)
120 #define BitOp       (1<<11)
121 #define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
122 #define String      (1<<13)     /* String instruction (rep capable) */
123 #define Stack       (1<<14)     /* Stack instruction (push/pop) */
124 #define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
125 #define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
126 #define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
127 #define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
128 #define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
129 #define Escape      (5<<15)     /* Escape to coprocessor instruction */
130 #define InstrDual   (6<<15)     /* Alternate instruction decoding of mod == 3 */
131 #define ModeDual    (7<<15)     /* Different instruction for 32/64 bit */
132 #define Sse         (1<<18)     /* SSE Vector instruction */
133 /* Generic ModRM decode. */
134 #define ModRM       (1<<19)
135 /* Destination is only written; never read. */
136 #define Mov         (1<<20)
137 /* Misc flags */
138 #define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
139 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
140 #define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
141 #define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
142 #define Undefined   (1<<25) /* No Such Instruction */
143 #define Lock        (1<<26) /* lock prefix is allowed for the instruction */
144 #define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
145 #define No64	    (1<<28)
146 #define PageTable   (1 << 29)   /* instruction used to write page table */
147 #define NotImpl     (1 << 30)   /* instruction is not implemented */
148 /* Source 2 operand type */
149 #define Src2Shift   (31)
150 #define Src2None    (OpNone << Src2Shift)
151 #define Src2Mem     (OpMem << Src2Shift)
152 #define Src2CL      (OpCL << Src2Shift)
153 #define Src2ImmByte (OpImmByte << Src2Shift)
154 #define Src2One     (OpOne << Src2Shift)
155 #define Src2Imm     (OpImm << Src2Shift)
156 #define Src2ES      (OpES << Src2Shift)
157 #define Src2CS      (OpCS << Src2Shift)
158 #define Src2SS      (OpSS << Src2Shift)
159 #define Src2DS      (OpDS << Src2Shift)
160 #define Src2FS      (OpFS << Src2Shift)
161 #define Src2GS      (OpGS << Src2Shift)
162 #define Src2Mask    (OpMask << Src2Shift)
163 #define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
164 #define AlignMask   ((u64)7 << 41)
165 #define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
166 #define Unaligned   ((u64)2 << 41)  /* Explicitly unaligned (e.g. MOVDQU) */
167 #define Avx         ((u64)3 << 41)  /* Advanced Vector Extensions */
168 #define Aligned16   ((u64)4 << 41)  /* Aligned to 16 byte boundary (e.g. FXSAVE) */
169 #define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
170 #define NoWrite     ((u64)1 << 45)  /* No writeback */
171 #define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
172 #define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
173 #define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
174 #define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
175 #define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
176 #define NearBranch  ((u64)1 << 52)  /* Near branches */
177 #define No16	    ((u64)1 << 53)  /* No 16 bit operand */
178 #define IncSP       ((u64)1 << 54)  /* SP is incremented before ModRM calc */
179 #define TwoMemOp    ((u64)1 << 55)  /* Instruction has two memory operand */
180 
181 #define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
182 
183 #define X2(x...) x, x
184 #define X3(x...) X2(x), x
185 #define X4(x...) X2(x), X2(x)
186 #define X5(x...) X4(x), x
187 #define X6(x...) X4(x), X2(x)
188 #define X7(x...) X4(x), X3(x)
189 #define X8(x...) X4(x), X4(x)
190 #define X16(x...) X8(x), X8(x)
191 
192 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
193 #define FASTOP_SIZE 8
194 
195 /*
196  * fastop functions have a special calling convention:
197  *
198  * dst:    rax        (in/out)
199  * src:    rdx        (in/out)
200  * src2:   rcx        (in)
201  * flags:  rflags     (in/out)
202  * ex:     rsi        (in:fastop pointer, out:zero if exception)
203  *
204  * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
205  * different operand sizes can be reached by calculation, rather than a jump
206  * table (which would be bigger than the code).
207  *
208  * fastop functions are declared as taking a never-defined fastop parameter,
209  * so they can't be called from C directly.
210  */
211 
212 struct fastop;
213 
214 struct opcode {
215 	u64 flags : 56;
216 	u64 intercept : 8;
217 	union {
218 		int (*execute)(struct x86_emulate_ctxt *ctxt);
219 		const struct opcode *group;
220 		const struct group_dual *gdual;
221 		const struct gprefix *gprefix;
222 		const struct escape *esc;
223 		const struct instr_dual *idual;
224 		const struct mode_dual *mdual;
225 		void (*fastop)(struct fastop *fake);
226 	} u;
227 	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
228 };
229 
230 struct group_dual {
231 	struct opcode mod012[8];
232 	struct opcode mod3[8];
233 };
234 
235 struct gprefix {
236 	struct opcode pfx_no;
237 	struct opcode pfx_66;
238 	struct opcode pfx_f2;
239 	struct opcode pfx_f3;
240 };
241 
242 struct escape {
243 	struct opcode op[8];
244 	struct opcode high[64];
245 };
246 
247 struct instr_dual {
248 	struct opcode mod012;
249 	struct opcode mod3;
250 };
251 
252 struct mode_dual {
253 	struct opcode mode32;
254 	struct opcode mode64;
255 };
256 
257 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
258 
259 enum x86_transfer_type {
260 	X86_TRANSFER_NONE,
261 	X86_TRANSFER_CALL_JMP,
262 	X86_TRANSFER_RET,
263 	X86_TRANSFER_TASK_SWITCH,
264 };
265 
266 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
267 {
268 	if (!(ctxt->regs_valid & (1 << nr))) {
269 		ctxt->regs_valid |= 1 << nr;
270 		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
271 	}
272 	return ctxt->_regs[nr];
273 }
274 
275 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
276 {
277 	ctxt->regs_valid |= 1 << nr;
278 	ctxt->regs_dirty |= 1 << nr;
279 	return &ctxt->_regs[nr];
280 }
281 
282 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
283 {
284 	reg_read(ctxt, nr);
285 	return reg_write(ctxt, nr);
286 }
287 
288 static void writeback_registers(struct x86_emulate_ctxt *ctxt)
289 {
290 	unsigned reg;
291 
292 	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
293 		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
294 }
295 
296 static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
297 {
298 	ctxt->regs_dirty = 0;
299 	ctxt->regs_valid = 0;
300 }
301 
302 /*
303  * These EFLAGS bits are restored from saved value during emulation, and
304  * any changes are written back to the saved value after emulation.
305  */
306 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
307 		     X86_EFLAGS_PF|X86_EFLAGS_CF)
308 
309 #ifdef CONFIG_X86_64
310 #define ON64(x) x
311 #else
312 #define ON64(x)
313 #endif
314 
315 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
316 
317 #define FOP_FUNC(name) \
318 	".align " __stringify(FASTOP_SIZE) " \n\t" \
319 	".type " name ", @function \n\t" \
320 	name ":\n\t"
321 
322 #define FOP_RET   "ret \n\t"
323 
324 #define FOP_START(op) \
325 	extern void em_##op(struct fastop *fake); \
326 	asm(".pushsection .text, \"ax\" \n\t" \
327 	    ".global em_" #op " \n\t" \
328 	    FOP_FUNC("em_" #op)
329 
330 #define FOP_END \
331 	    ".popsection")
332 
333 #define FOPNOP() \
334 	FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
335 	FOP_RET
336 
337 #define FOP1E(op,  dst) \
338 	FOP_FUNC(#op "_" #dst) \
339 	"10: " #op " %" #dst " \n\t" FOP_RET
340 
341 #define FOP1EEX(op,  dst) \
342 	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
343 
344 #define FASTOP1(op) \
345 	FOP_START(op) \
346 	FOP1E(op##b, al) \
347 	FOP1E(op##w, ax) \
348 	FOP1E(op##l, eax) \
349 	ON64(FOP1E(op##q, rax))	\
350 	FOP_END
351 
352 /* 1-operand, using src2 (for MUL/DIV r/m) */
353 #define FASTOP1SRC2(op, name) \
354 	FOP_START(name) \
355 	FOP1E(op, cl) \
356 	FOP1E(op, cx) \
357 	FOP1E(op, ecx) \
358 	ON64(FOP1E(op, rcx)) \
359 	FOP_END
360 
361 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
362 #define FASTOP1SRC2EX(op, name) \
363 	FOP_START(name) \
364 	FOP1EEX(op, cl) \
365 	FOP1EEX(op, cx) \
366 	FOP1EEX(op, ecx) \
367 	ON64(FOP1EEX(op, rcx)) \
368 	FOP_END
369 
370 #define FOP2E(op,  dst, src)	   \
371 	FOP_FUNC(#op "_" #dst "_" #src) \
372 	#op " %" #src ", %" #dst " \n\t" FOP_RET
373 
374 #define FASTOP2(op) \
375 	FOP_START(op) \
376 	FOP2E(op##b, al, dl) \
377 	FOP2E(op##w, ax, dx) \
378 	FOP2E(op##l, eax, edx) \
379 	ON64(FOP2E(op##q, rax, rdx)) \
380 	FOP_END
381 
382 /* 2 operand, word only */
383 #define FASTOP2W(op) \
384 	FOP_START(op) \
385 	FOPNOP() \
386 	FOP2E(op##w, ax, dx) \
387 	FOP2E(op##l, eax, edx) \
388 	ON64(FOP2E(op##q, rax, rdx)) \
389 	FOP_END
390 
391 /* 2 operand, src is CL */
392 #define FASTOP2CL(op) \
393 	FOP_START(op) \
394 	FOP2E(op##b, al, cl) \
395 	FOP2E(op##w, ax, cl) \
396 	FOP2E(op##l, eax, cl) \
397 	ON64(FOP2E(op##q, rax, cl)) \
398 	FOP_END
399 
400 /* 2 operand, src and dest are reversed */
401 #define FASTOP2R(op, name) \
402 	FOP_START(name) \
403 	FOP2E(op##b, dl, al) \
404 	FOP2E(op##w, dx, ax) \
405 	FOP2E(op##l, edx, eax) \
406 	ON64(FOP2E(op##q, rdx, rax)) \
407 	FOP_END
408 
409 #define FOP3E(op,  dst, src, src2) \
410 	FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
411 	#op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
412 
413 /* 3-operand, word-only, src2=cl */
414 #define FASTOP3WCL(op) \
415 	FOP_START(op) \
416 	FOPNOP() \
417 	FOP3E(op##w, ax, dx, cl) \
418 	FOP3E(op##l, eax, edx, cl) \
419 	ON64(FOP3E(op##q, rax, rdx, cl)) \
420 	FOP_END
421 
422 /* Special case for SETcc - 1 instruction per cc */
423 #define FOP_SETCC(op) \
424 	".align 4 \n\t" \
425 	".type " #op ", @function \n\t" \
426 	#op ": \n\t" \
427 	#op " %al \n\t" \
428 	FOP_RET
429 
430 asm(".pushsection .fixup, \"ax\"\n"
431     ".global kvm_fastop_exception \n"
432     "kvm_fastop_exception: xor %esi, %esi; ret\n"
433     ".popsection");
434 
435 FOP_START(setcc)
436 FOP_SETCC(seto)
437 FOP_SETCC(setno)
438 FOP_SETCC(setc)
439 FOP_SETCC(setnc)
440 FOP_SETCC(setz)
441 FOP_SETCC(setnz)
442 FOP_SETCC(setbe)
443 FOP_SETCC(setnbe)
444 FOP_SETCC(sets)
445 FOP_SETCC(setns)
446 FOP_SETCC(setp)
447 FOP_SETCC(setnp)
448 FOP_SETCC(setl)
449 FOP_SETCC(setnl)
450 FOP_SETCC(setle)
451 FOP_SETCC(setnle)
452 FOP_END;
453 
454 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
455 FOP_END;
456 
457 /*
458  * XXX: inoutclob user must know where the argument is being expanded.
459  *      Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
460  */
461 #define asm_safe(insn, inoutclob...) \
462 ({ \
463 	int _fault = 0; \
464  \
465 	asm volatile("1:" insn "\n" \
466 	             "2:\n" \
467 	             ".pushsection .fixup, \"ax\"\n" \
468 	             "3: movl $1, %[_fault]\n" \
469 	             "   jmp  2b\n" \
470 	             ".popsection\n" \
471 	             _ASM_EXTABLE(1b, 3b) \
472 	             : [_fault] "+qm"(_fault) inoutclob ); \
473  \
474 	_fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
475 })
476 
477 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
478 				    enum x86_intercept intercept,
479 				    enum x86_intercept_stage stage)
480 {
481 	struct x86_instruction_info info = {
482 		.intercept  = intercept,
483 		.rep_prefix = ctxt->rep_prefix,
484 		.modrm_mod  = ctxt->modrm_mod,
485 		.modrm_reg  = ctxt->modrm_reg,
486 		.modrm_rm   = ctxt->modrm_rm,
487 		.src_val    = ctxt->src.val64,
488 		.dst_val    = ctxt->dst.val64,
489 		.src_bytes  = ctxt->src.bytes,
490 		.dst_bytes  = ctxt->dst.bytes,
491 		.ad_bytes   = ctxt->ad_bytes,
492 		.next_rip   = ctxt->eip,
493 	};
494 
495 	return ctxt->ops->intercept(ctxt, &info, stage);
496 }
497 
498 static void assign_masked(ulong *dest, ulong src, ulong mask)
499 {
500 	*dest = (*dest & ~mask) | (src & mask);
501 }
502 
503 static void assign_register(unsigned long *reg, u64 val, int bytes)
504 {
505 	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
506 	switch (bytes) {
507 	case 1:
508 		*(u8 *)reg = (u8)val;
509 		break;
510 	case 2:
511 		*(u16 *)reg = (u16)val;
512 		break;
513 	case 4:
514 		*reg = (u32)val;
515 		break;	/* 64b: zero-extend */
516 	case 8:
517 		*reg = val;
518 		break;
519 	}
520 }
521 
522 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
523 {
524 	return (1UL << (ctxt->ad_bytes << 3)) - 1;
525 }
526 
527 static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
528 {
529 	u16 sel;
530 	struct desc_struct ss;
531 
532 	if (ctxt->mode == X86EMUL_MODE_PROT64)
533 		return ~0UL;
534 	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
535 	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
536 }
537 
538 static int stack_size(struct x86_emulate_ctxt *ctxt)
539 {
540 	return (__fls(stack_mask(ctxt)) + 1) >> 3;
541 }
542 
543 /* Access/update address held in a register, based on addressing mode. */
544 static inline unsigned long
545 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
546 {
547 	if (ctxt->ad_bytes == sizeof(unsigned long))
548 		return reg;
549 	else
550 		return reg & ad_mask(ctxt);
551 }
552 
553 static inline unsigned long
554 register_address(struct x86_emulate_ctxt *ctxt, int reg)
555 {
556 	return address_mask(ctxt, reg_read(ctxt, reg));
557 }
558 
559 static void masked_increment(ulong *reg, ulong mask, int inc)
560 {
561 	assign_masked(reg, *reg + inc, mask);
562 }
563 
564 static inline void
565 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
566 {
567 	ulong *preg = reg_rmw(ctxt, reg);
568 
569 	assign_register(preg, *preg + inc, ctxt->ad_bytes);
570 }
571 
572 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
573 {
574 	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
575 }
576 
577 static u32 desc_limit_scaled(struct desc_struct *desc)
578 {
579 	u32 limit = get_desc_limit(desc);
580 
581 	return desc->g ? (limit << 12) | 0xfff : limit;
582 }
583 
584 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
585 {
586 	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
587 		return 0;
588 
589 	return ctxt->ops->get_cached_segment_base(ctxt, seg);
590 }
591 
592 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
593 			     u32 error, bool valid)
594 {
595 	WARN_ON(vec > 0x1f);
596 	ctxt->exception.vector = vec;
597 	ctxt->exception.error_code = error;
598 	ctxt->exception.error_code_valid = valid;
599 	return X86EMUL_PROPAGATE_FAULT;
600 }
601 
602 static int emulate_db(struct x86_emulate_ctxt *ctxt)
603 {
604 	return emulate_exception(ctxt, DB_VECTOR, 0, false);
605 }
606 
607 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
608 {
609 	return emulate_exception(ctxt, GP_VECTOR, err, true);
610 }
611 
612 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
613 {
614 	return emulate_exception(ctxt, SS_VECTOR, err, true);
615 }
616 
617 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
618 {
619 	return emulate_exception(ctxt, UD_VECTOR, 0, false);
620 }
621 
622 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
623 {
624 	return emulate_exception(ctxt, TS_VECTOR, err, true);
625 }
626 
627 static int emulate_de(struct x86_emulate_ctxt *ctxt)
628 {
629 	return emulate_exception(ctxt, DE_VECTOR, 0, false);
630 }
631 
632 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
633 {
634 	return emulate_exception(ctxt, NM_VECTOR, 0, false);
635 }
636 
637 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
638 {
639 	u16 selector;
640 	struct desc_struct desc;
641 
642 	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
643 	return selector;
644 }
645 
646 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
647 				 unsigned seg)
648 {
649 	u16 dummy;
650 	u32 base3;
651 	struct desc_struct desc;
652 
653 	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
654 	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
655 }
656 
657 /*
658  * x86 defines three classes of vector instructions: explicitly
659  * aligned, explicitly unaligned, and the rest, which change behaviour
660  * depending on whether they're AVX encoded or not.
661  *
662  * Also included is CMPXCHG16B which is not a vector instruction, yet it is
663  * subject to the same check.  FXSAVE and FXRSTOR are checked here too as their
664  * 512 bytes of data must be aligned to a 16 byte boundary.
665  */
666 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
667 {
668 	u64 alignment = ctxt->d & AlignMask;
669 
670 	if (likely(size < 16))
671 		return 1;
672 
673 	switch (alignment) {
674 	case Unaligned:
675 	case Avx:
676 		return 1;
677 	case Aligned16:
678 		return 16;
679 	case Aligned:
680 	default:
681 		return size;
682 	}
683 }
684 
685 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
686 				       struct segmented_address addr,
687 				       unsigned *max_size, unsigned size,
688 				       bool write, bool fetch,
689 				       enum x86emul_mode mode, ulong *linear)
690 {
691 	struct desc_struct desc;
692 	bool usable;
693 	ulong la;
694 	u32 lim;
695 	u16 sel;
696 	u8  va_bits;
697 
698 	la = seg_base(ctxt, addr.seg) + addr.ea;
699 	*max_size = 0;
700 	switch (mode) {
701 	case X86EMUL_MODE_PROT64:
702 		*linear = la;
703 		va_bits = ctxt_virt_addr_bits(ctxt);
704 		if (get_canonical(la, va_bits) != la)
705 			goto bad;
706 
707 		*max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
708 		if (size > *max_size)
709 			goto bad;
710 		break;
711 	default:
712 		*linear = la = (u32)la;
713 		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
714 						addr.seg);
715 		if (!usable)
716 			goto bad;
717 		/* code segment in protected mode or read-only data segment */
718 		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
719 					|| !(desc.type & 2)) && write)
720 			goto bad;
721 		/* unreadable code segment */
722 		if (!fetch && (desc.type & 8) && !(desc.type & 2))
723 			goto bad;
724 		lim = desc_limit_scaled(&desc);
725 		if (!(desc.type & 8) && (desc.type & 4)) {
726 			/* expand-down segment */
727 			if (addr.ea <= lim)
728 				goto bad;
729 			lim = desc.d ? 0xffffffff : 0xffff;
730 		}
731 		if (addr.ea > lim)
732 			goto bad;
733 		if (lim == 0xffffffff)
734 			*max_size = ~0u;
735 		else {
736 			*max_size = (u64)lim + 1 - addr.ea;
737 			if (size > *max_size)
738 				goto bad;
739 		}
740 		break;
741 	}
742 	if (la & (insn_alignment(ctxt, size) - 1))
743 		return emulate_gp(ctxt, 0);
744 	return X86EMUL_CONTINUE;
745 bad:
746 	if (addr.seg == VCPU_SREG_SS)
747 		return emulate_ss(ctxt, 0);
748 	else
749 		return emulate_gp(ctxt, 0);
750 }
751 
752 static int linearize(struct x86_emulate_ctxt *ctxt,
753 		     struct segmented_address addr,
754 		     unsigned size, bool write,
755 		     ulong *linear)
756 {
757 	unsigned max_size;
758 	return __linearize(ctxt, addr, &max_size, size, write, false,
759 			   ctxt->mode, linear);
760 }
761 
762 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
763 			     enum x86emul_mode mode)
764 {
765 	ulong linear;
766 	int rc;
767 	unsigned max_size;
768 	struct segmented_address addr = { .seg = VCPU_SREG_CS,
769 					   .ea = dst };
770 
771 	if (ctxt->op_bytes != sizeof(unsigned long))
772 		addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
773 	rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
774 	if (rc == X86EMUL_CONTINUE)
775 		ctxt->_eip = addr.ea;
776 	return rc;
777 }
778 
779 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
780 {
781 	return assign_eip(ctxt, dst, ctxt->mode);
782 }
783 
784 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
785 			  const struct desc_struct *cs_desc)
786 {
787 	enum x86emul_mode mode = ctxt->mode;
788 	int rc;
789 
790 #ifdef CONFIG_X86_64
791 	if (ctxt->mode >= X86EMUL_MODE_PROT16) {
792 		if (cs_desc->l) {
793 			u64 efer = 0;
794 
795 			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
796 			if (efer & EFER_LMA)
797 				mode = X86EMUL_MODE_PROT64;
798 		} else
799 			mode = X86EMUL_MODE_PROT32; /* temporary value */
800 	}
801 #endif
802 	if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
803 		mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
804 	rc = assign_eip(ctxt, dst, mode);
805 	if (rc == X86EMUL_CONTINUE)
806 		ctxt->mode = mode;
807 	return rc;
808 }
809 
810 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
811 {
812 	return assign_eip_near(ctxt, ctxt->_eip + rel);
813 }
814 
815 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
816 			      struct segmented_address addr,
817 			      void *data,
818 			      unsigned size)
819 {
820 	int rc;
821 	ulong linear;
822 
823 	rc = linearize(ctxt, addr, size, false, &linear);
824 	if (rc != X86EMUL_CONTINUE)
825 		return rc;
826 	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
827 }
828 
829 static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
830 			       struct segmented_address addr,
831 			       void *data,
832 			       unsigned int size)
833 {
834 	int rc;
835 	ulong linear;
836 
837 	rc = linearize(ctxt, addr, size, true, &linear);
838 	if (rc != X86EMUL_CONTINUE)
839 		return rc;
840 	return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
841 }
842 
843 /*
844  * Prefetch the remaining bytes of the instruction without crossing page
845  * boundary if they are not in fetch_cache yet.
846  */
847 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
848 {
849 	int rc;
850 	unsigned size, max_size;
851 	unsigned long linear;
852 	int cur_size = ctxt->fetch.end - ctxt->fetch.data;
853 	struct segmented_address addr = { .seg = VCPU_SREG_CS,
854 					   .ea = ctxt->eip + cur_size };
855 
856 	/*
857 	 * We do not know exactly how many bytes will be needed, and
858 	 * __linearize is expensive, so fetch as much as possible.  We
859 	 * just have to avoid going beyond the 15 byte limit, the end
860 	 * of the segment, or the end of the page.
861 	 *
862 	 * __linearize is called with size 0 so that it does not do any
863 	 * boundary check itself.  Instead, we use max_size to check
864 	 * against op_size.
865 	 */
866 	rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
867 			 &linear);
868 	if (unlikely(rc != X86EMUL_CONTINUE))
869 		return rc;
870 
871 	size = min_t(unsigned, 15UL ^ cur_size, max_size);
872 	size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
873 
874 	/*
875 	 * One instruction can only straddle two pages,
876 	 * and one has been loaded at the beginning of
877 	 * x86_decode_insn.  So, if not enough bytes
878 	 * still, we must have hit the 15-byte boundary.
879 	 */
880 	if (unlikely(size < op_size))
881 		return emulate_gp(ctxt, 0);
882 
883 	rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
884 			      size, &ctxt->exception);
885 	if (unlikely(rc != X86EMUL_CONTINUE))
886 		return rc;
887 	ctxt->fetch.end += size;
888 	return X86EMUL_CONTINUE;
889 }
890 
891 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
892 					       unsigned size)
893 {
894 	unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;
895 
896 	if (unlikely(done_size < size))
897 		return __do_insn_fetch_bytes(ctxt, size - done_size);
898 	else
899 		return X86EMUL_CONTINUE;
900 }
901 
902 /* Fetch next part of the instruction being emulated. */
903 #define insn_fetch(_type, _ctxt)					\
904 ({	_type _x;							\
905 									\
906 	rc = do_insn_fetch_bytes(_ctxt, sizeof(_type));			\
907 	if (rc != X86EMUL_CONTINUE)					\
908 		goto done;						\
909 	ctxt->_eip += sizeof(_type);					\
910 	memcpy(&_x, ctxt->fetch.ptr, sizeof(_type));			\
911 	ctxt->fetch.ptr += sizeof(_type);				\
912 	_x;								\
913 })
914 
915 #define insn_fetch_arr(_arr, _size, _ctxt)				\
916 ({									\
917 	rc = do_insn_fetch_bytes(_ctxt, _size);				\
918 	if (rc != X86EMUL_CONTINUE)					\
919 		goto done;						\
920 	ctxt->_eip += (_size);						\
921 	memcpy(_arr, ctxt->fetch.ptr, _size);				\
922 	ctxt->fetch.ptr += (_size);					\
923 })
924 
925 /*
926  * Given the 'reg' portion of a ModRM byte, and a register block, return a
927  * pointer into the block that addresses the relevant register.
928  * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
929  */
930 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
931 			     int byteop)
932 {
933 	void *p;
934 	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
935 
936 	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
937 		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
938 	else
939 		p = reg_rmw(ctxt, modrm_reg);
940 	return p;
941 }
942 
943 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
944 			   struct segmented_address addr,
945 			   u16 *size, unsigned long *address, int op_bytes)
946 {
947 	int rc;
948 
949 	if (op_bytes == 2)
950 		op_bytes = 3;
951 	*address = 0;
952 	rc = segmented_read_std(ctxt, addr, size, 2);
953 	if (rc != X86EMUL_CONTINUE)
954 		return rc;
955 	addr.ea += 2;
956 	rc = segmented_read_std(ctxt, addr, address, op_bytes);
957 	return rc;
958 }
959 
960 FASTOP2(add);
961 FASTOP2(or);
962 FASTOP2(adc);
963 FASTOP2(sbb);
964 FASTOP2(and);
965 FASTOP2(sub);
966 FASTOP2(xor);
967 FASTOP2(cmp);
968 FASTOP2(test);
969 
970 FASTOP1SRC2(mul, mul_ex);
971 FASTOP1SRC2(imul, imul_ex);
972 FASTOP1SRC2EX(div, div_ex);
973 FASTOP1SRC2EX(idiv, idiv_ex);
974 
975 FASTOP3WCL(shld);
976 FASTOP3WCL(shrd);
977 
978 FASTOP2W(imul);
979 
980 FASTOP1(not);
981 FASTOP1(neg);
982 FASTOP1(inc);
983 FASTOP1(dec);
984 
985 FASTOP2CL(rol);
986 FASTOP2CL(ror);
987 FASTOP2CL(rcl);
988 FASTOP2CL(rcr);
989 FASTOP2CL(shl);
990 FASTOP2CL(shr);
991 FASTOP2CL(sar);
992 
993 FASTOP2W(bsf);
994 FASTOP2W(bsr);
995 FASTOP2W(bt);
996 FASTOP2W(bts);
997 FASTOP2W(btr);
998 FASTOP2W(btc);
999 
1000 FASTOP2(xadd);
1001 
1002 FASTOP2R(cmp, cmp_r);
1003 
1004 static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
1005 {
1006 	/* If src is zero, do not writeback, but update flags */
1007 	if (ctxt->src.val == 0)
1008 		ctxt->dst.type = OP_NONE;
1009 	return fastop(ctxt, em_bsf);
1010 }
1011 
1012 static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
1013 {
1014 	/* If src is zero, do not writeback, but update flags */
1015 	if (ctxt->src.val == 0)
1016 		ctxt->dst.type = OP_NONE;
1017 	return fastop(ctxt, em_bsr);
1018 }
1019 
1020 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1021 {
1022 	u8 rc;
1023 	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1024 
1025 	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1026 	asm("push %[flags]; popf; " CALL_NOSPEC
1027 	    : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
1028 	return rc;
1029 }
1030 
1031 static void fetch_register_operand(struct operand *op)
1032 {
1033 	switch (op->bytes) {
1034 	case 1:
1035 		op->val = *(u8 *)op->addr.reg;
1036 		break;
1037 	case 2:
1038 		op->val = *(u16 *)op->addr.reg;
1039 		break;
1040 	case 4:
1041 		op->val = *(u32 *)op->addr.reg;
1042 		break;
1043 	case 8:
1044 		op->val = *(u64 *)op->addr.reg;
1045 		break;
1046 	}
1047 }
1048 
1049 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
1050 {
1051 	switch (reg) {
1052 	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
1053 	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
1054 	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
1055 	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
1056 	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
1057 	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
1058 	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
1059 	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
1060 #ifdef CONFIG_X86_64
1061 	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
1062 	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
1063 	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
1064 	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
1065 	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
1066 	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
1067 	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
1068 	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
1069 #endif
1070 	default: BUG();
1071 	}
1072 }
1073 
1074 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
1075 			  int reg)
1076 {
1077 	switch (reg) {
1078 	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
1079 	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
1080 	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
1081 	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
1082 	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
1083 	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
1084 	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
1085 	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
1086 #ifdef CONFIG_X86_64
1087 	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
1088 	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
1089 	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
1090 	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
1091 	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
1092 	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
1093 	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
1094 	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
1095 #endif
1096 	default: BUG();
1097 	}
1098 }
1099 
1100 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1101 {
1102 	switch (reg) {
1103 	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
1104 	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
1105 	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
1106 	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
1107 	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
1108 	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
1109 	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
1110 	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
1111 	default: BUG();
1112 	}
1113 }
1114 
1115 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
1116 {
1117 	switch (reg) {
1118 	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
1119 	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
1120 	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
1121 	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
1122 	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
1123 	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
1124 	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
1125 	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
1126 	default: BUG();
1127 	}
1128 }
1129 
1130 static int em_fninit(struct x86_emulate_ctxt *ctxt)
1131 {
1132 	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1133 		return emulate_nm(ctxt);
1134 
1135 	asm volatile("fninit");
1136 	return X86EMUL_CONTINUE;
1137 }
1138 
1139 static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
1140 {
1141 	u16 fcw;
1142 
1143 	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1144 		return emulate_nm(ctxt);
1145 
1146 	asm volatile("fnstcw %0": "+m"(fcw));
1147 
1148 	ctxt->dst.val = fcw;
1149 
1150 	return X86EMUL_CONTINUE;
1151 }
1152 
1153 static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
1154 {
1155 	u16 fsw;
1156 
1157 	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
1158 		return emulate_nm(ctxt);
1159 
1160 	asm volatile("fnstsw %0": "+m"(fsw));
1161 
1162 	ctxt->dst.val = fsw;
1163 
1164 	return X86EMUL_CONTINUE;
1165 }
1166 
1167 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1168 				    struct operand *op)
1169 {
1170 	unsigned reg = ctxt->modrm_reg;
1171 
1172 	if (!(ctxt->d & ModRM))
1173 		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
1174 
1175 	if (ctxt->d & Sse) {
1176 		op->type = OP_XMM;
1177 		op->bytes = 16;
1178 		op->addr.xmm = reg;
1179 		read_sse_reg(ctxt, &op->vec_val, reg);
1180 		return;
1181 	}
1182 	if (ctxt->d & Mmx) {
1183 		reg &= 7;
1184 		op->type = OP_MM;
1185 		op->bytes = 8;
1186 		op->addr.mm = reg;
1187 		return;
1188 	}
1189 
1190 	op->type = OP_REG;
1191 	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1192 	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);
1193 
1194 	fetch_register_operand(op);
1195 	op->orig_val = op->val;
1196 }
1197 
1198 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
1199 {
1200 	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
1201 		ctxt->modrm_seg = VCPU_SREG_SS;
1202 }
1203 
1204 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1205 			struct operand *op)
1206 {
1207 	u8 sib;
1208 	int index_reg, base_reg, scale;
1209 	int rc = X86EMUL_CONTINUE;
1210 	ulong modrm_ea = 0;
1211 
1212 	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
1213 	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
1214 	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1215 
1216 	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1217 	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
1218 	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1219 	ctxt->modrm_seg = VCPU_SREG_DS;
1220 
1221 	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1222 		op->type = OP_REG;
1223 		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1224 		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1225 				ctxt->d & ByteOp);
1226 		if (ctxt->d & Sse) {
1227 			op->type = OP_XMM;
1228 			op->bytes = 16;
1229 			op->addr.xmm = ctxt->modrm_rm;
1230 			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
1231 			return rc;
1232 		}
1233 		if (ctxt->d & Mmx) {
1234 			op->type = OP_MM;
1235 			op->bytes = 8;
1236 			op->addr.mm = ctxt->modrm_rm & 7;
1237 			return rc;
1238 		}
1239 		fetch_register_operand(op);
1240 		return rc;
1241 	}
1242 
1243 	op->type = OP_MEM;
1244 
1245 	if (ctxt->ad_bytes == 2) {
1246 		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
1247 		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
1248 		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
1249 		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1250 
1251 		/* 16-bit ModR/M decode. */
1252 		switch (ctxt->modrm_mod) {
1253 		case 0:
1254 			if (ctxt->modrm_rm == 6)
1255 				modrm_ea += insn_fetch(u16, ctxt);
1256 			break;
1257 		case 1:
1258 			modrm_ea += insn_fetch(s8, ctxt);
1259 			break;
1260 		case 2:
1261 			modrm_ea += insn_fetch(u16, ctxt);
1262 			break;
1263 		}
1264 		switch (ctxt->modrm_rm) {
1265 		case 0:
1266 			modrm_ea += bx + si;
1267 			break;
1268 		case 1:
1269 			modrm_ea += bx + di;
1270 			break;
1271 		case 2:
1272 			modrm_ea += bp + si;
1273 			break;
1274 		case 3:
1275 			modrm_ea += bp + di;
1276 			break;
1277 		case 4:
1278 			modrm_ea += si;
1279 			break;
1280 		case 5:
1281 			modrm_ea += di;
1282 			break;
1283 		case 6:
1284 			if (ctxt->modrm_mod != 0)
1285 				modrm_ea += bp;
1286 			break;
1287 		case 7:
1288 			modrm_ea += bx;
1289 			break;
1290 		}
1291 		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
1292 		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
1293 			ctxt->modrm_seg = VCPU_SREG_SS;
1294 		modrm_ea = (u16)modrm_ea;
1295 	} else {
1296 		/* 32/64-bit ModR/M decode. */
1297 		if ((ctxt->modrm_rm & 7) == 4) {
1298 			sib = insn_fetch(u8, ctxt);
1299 			index_reg |= (sib >> 3) & 7;
1300 			base_reg |= sib & 7;
1301 			scale = sib >> 6;
1302 
1303 			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1304 				modrm_ea += insn_fetch(s32, ctxt);
1305 			else {
1306 				modrm_ea += reg_read(ctxt, base_reg);
1307 				adjust_modrm_seg(ctxt, base_reg);
1308 				/* Increment ESP on POP [ESP] */
1309 				if ((ctxt->d & IncSP) &&
1310 				    base_reg == VCPU_REGS_RSP)
1311 					modrm_ea += ctxt->op_bytes;
1312 			}
1313 			if (index_reg != 4)
1314 				modrm_ea += reg_read(ctxt, index_reg) << scale;
1315 		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1316 			modrm_ea += insn_fetch(s32, ctxt);
1317 			if (ctxt->mode == X86EMUL_MODE_PROT64)
1318 				ctxt->rip_relative = 1;
1319 		} else {
1320 			base_reg = ctxt->modrm_rm;
1321 			modrm_ea += reg_read(ctxt, base_reg);
1322 			adjust_modrm_seg(ctxt, base_reg);
1323 		}
1324 		switch (ctxt->modrm_mod) {
1325 		case 1:
1326 			modrm_ea += insn_fetch(s8, ctxt);
1327 			break;
1328 		case 2:
1329 			modrm_ea += insn_fetch(s32, ctxt);
1330 			break;
1331 		}
1332 	}
1333 	op->addr.mem.ea = modrm_ea;
1334 	if (ctxt->ad_bytes != 8)
1335 		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
1336 
1337 done:
1338 	return rc;
1339 }
1340 
1341 static int decode_abs(struct x86_emulate_ctxt *ctxt,
1342 		      struct operand *op)
1343 {
1344 	int rc = X86EMUL_CONTINUE;
1345 
1346 	op->type = OP_MEM;
1347 	switch (ctxt->ad_bytes) {
1348 	case 2:
1349 		op->addr.mem.ea = insn_fetch(u16, ctxt);
1350 		break;
1351 	case 4:
1352 		op->addr.mem.ea = insn_fetch(u32, ctxt);
1353 		break;
1354 	case 8:
1355 		op->addr.mem.ea = insn_fetch(u64, ctxt);
1356 		break;
1357 	}
1358 done:
1359 	return rc;
1360 }
1361 
1362 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1363 {
1364 	long sv = 0, mask;
1365 
1366 	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1367 		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1368 
1369 		if (ctxt->src.bytes == 2)
1370 			sv = (s16)ctxt->src.val & (s16)mask;
1371 		else if (ctxt->src.bytes == 4)
1372 			sv = (s32)ctxt->src.val & (s32)mask;
1373 		else
1374 			sv = (s64)ctxt->src.val & (s64)mask;
1375 
1376 		ctxt->dst.addr.mem.ea = address_mask(ctxt,
1377 					   ctxt->dst.addr.mem.ea + (sv >> 3));
1378 	}
1379 
1380 	/* only subword offset */
1381 	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1382 }
1383 
1384 static int read_emulated(struct x86_emulate_ctxt *ctxt,
1385 			 unsigned long addr, void *dest, unsigned size)
1386 {
1387 	int rc;
1388 	struct read_cache *mc = &ctxt->mem_read;
1389 
1390 	if (mc->pos < mc->end)
1391 		goto read_cached;
1392 
1393 	WARN_ON((mc->end + size) >= sizeof(mc->data));
1394 
1395 	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
1396 				      &ctxt->exception);
1397 	if (rc != X86EMUL_CONTINUE)
1398 		return rc;
1399 
1400 	mc->end += size;
1401 
1402 read_cached:
1403 	memcpy(dest, mc->data + mc->pos, size);
1404 	mc->pos += size;
1405 	return X86EMUL_CONTINUE;
1406 }
1407 
1408 static int segmented_read(struct x86_emulate_ctxt *ctxt,
1409 			  struct segmented_address addr,
1410 			  void *data,
1411 			  unsigned size)
1412 {
1413 	int rc;
1414 	ulong linear;
1415 
1416 	rc = linearize(ctxt, addr, size, false, &linear);
1417 	if (rc != X86EMUL_CONTINUE)
1418 		return rc;
1419 	return read_emulated(ctxt, linear, data, size);
1420 }
1421 
1422 static int segmented_write(struct x86_emulate_ctxt *ctxt,
1423 			   struct segmented_address addr,
1424 			   const void *data,
1425 			   unsigned size)
1426 {
1427 	int rc;
1428 	ulong linear;
1429 
1430 	rc = linearize(ctxt, addr, size, true, &linear);
1431 	if (rc != X86EMUL_CONTINUE)
1432 		return rc;
1433 	return ctxt->ops->write_emulated(ctxt, linear, data, size,
1434 					 &ctxt->exception);
1435 }
1436 
1437 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
1438 			     struct segmented_address addr,
1439 			     const void *orig_data, const void *data,
1440 			     unsigned size)
1441 {
1442 	int rc;
1443 	ulong linear;
1444 
1445 	rc = linearize(ctxt, addr, size, true, &linear);
1446 	if (rc != X86EMUL_CONTINUE)
1447 		return rc;
1448 	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
1449 					   size, &ctxt->exception);
1450 }
1451 
1452 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
1453 			   unsigned int size, unsigned short port,
1454 			   void *dest)
1455 {
1456 	struct read_cache *rc = &ctxt->io_read;
1457 
1458 	if (rc->pos == rc->end) { /* refill pio read ahead */
1459 		unsigned int in_page, n;
1460 		unsigned int count = ctxt->rep_prefix ?
1461 			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1462 		in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1463 			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
1464 			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1465 		n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1466 		if (n == 0)
1467 			n = 1;
1468 		rc->pos = rc->end = 0;
1469 		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1470 			return 0;
1471 		rc->end = n * size;
1472 	}
1473 
1474 	if (ctxt->rep_prefix && (ctxt->d & String) &&
1475 	    !(ctxt->eflags & X86_EFLAGS_DF)) {
1476 		ctxt->dst.data = rc->data + rc->pos;
1477 		ctxt->dst.type = OP_MEM_STR;
1478 		ctxt->dst.count = (rc->end - rc->pos) / size;
1479 		rc->pos = rc->end;
1480 	} else {
1481 		memcpy(dest, rc->data + rc->pos, size);
1482 		rc->pos += size;
1483 	}
1484 	return 1;
1485 }
1486 
1487 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
1488 				     u16 index, struct desc_struct *desc)
1489 {
1490 	struct desc_ptr dt;
1491 	ulong addr;
1492 
1493 	ctxt->ops->get_idt(ctxt, &dt);
1494 
1495 	if (dt.size < index * 8 + 7)
1496 		return emulate_gp(ctxt, index << 3 | 0x2);
1497 
1498 	addr = dt.address + index * 8;
1499 	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
1500 				   &ctxt->exception);
1501 }
1502 
1503 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1504 				     u16 selector, struct desc_ptr *dt)
1505 {
1506 	const struct x86_emulate_ops *ops = ctxt->ops;
1507 	u32 base3 = 0;
1508 
1509 	if (selector & 1 << 2) {
1510 		struct desc_struct desc;
1511 		u16 sel;
1512 
1513 		memset (dt, 0, sizeof *dt);
1514 		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
1515 				      VCPU_SREG_LDTR))
1516 			return;
1517 
1518 		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1519 		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1520 	} else
1521 		ops->get_gdt(ctxt, dt);
1522 }
1523 
1524 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
1525 			      u16 selector, ulong *desc_addr_p)
1526 {
1527 	struct desc_ptr dt;
1528 	u16 index = selector >> 3;
1529 	ulong addr;
1530 
1531 	get_descriptor_table_ptr(ctxt, selector, &dt);
1532 
1533 	if (dt.size < index * 8 + 7)
1534 		return emulate_gp(ctxt, selector & 0xfffc);
1535 
1536 	addr = dt.address + index * 8;
1537 
1538 #ifdef CONFIG_X86_64
1539 	if (addr >> 32 != 0) {
1540 		u64 efer = 0;
1541 
1542 		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1543 		if (!(efer & EFER_LMA))
1544 			addr &= (u32)-1;
1545 	}
1546 #endif
1547 
1548 	*desc_addr_p = addr;
1549 	return X86EMUL_CONTINUE;
1550 }
1551 
1552 /* allowed just for 8 bytes segments */
1553 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1554 				   u16 selector, struct desc_struct *desc,
1555 				   ulong *desc_addr_p)
1556 {
1557 	int rc;
1558 
1559 	rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
1560 	if (rc != X86EMUL_CONTINUE)
1561 		return rc;
1562 
1563 	return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1564 				   &ctxt->exception);
1565 }
1566 
1567 /* allowed just for 8 bytes segments */
1568 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1569 				    u16 selector, struct desc_struct *desc)
1570 {
1571 	int rc;
1572 	ulong addr;
1573 
1574 	rc = get_descriptor_ptr(ctxt, selector, &addr);
1575 	if (rc != X86EMUL_CONTINUE)
1576 		return rc;
1577 
1578 	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
1579 				    &ctxt->exception);
1580 }
1581 
1582 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1583 				     u16 selector, int seg, u8 cpl,
1584 				     enum x86_transfer_type transfer,
1585 				     struct desc_struct *desc)
1586 {
1587 	struct desc_struct seg_desc, old_desc;
1588 	u8 dpl, rpl;
1589 	unsigned err_vec = GP_VECTOR;
1590 	u32 err_code = 0;
1591 	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1592 	ulong desc_addr;
1593 	int ret;
1594 	u16 dummy;
1595 	u32 base3 = 0;
1596 
1597 	memset(&seg_desc, 0, sizeof seg_desc);
1598 
1599 	if (ctxt->mode == X86EMUL_MODE_REAL) {
1600 		/* set real mode segment descriptor (keep limit etc. for
1601 		 * unreal mode) */
1602 		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1603 		set_desc_base(&seg_desc, selector << 4);
1604 		goto load;
1605 	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
1606 		/* VM86 needs a clean new segment descriptor */
1607 		set_desc_base(&seg_desc, selector << 4);
1608 		set_desc_limit(&seg_desc, 0xffff);
1609 		seg_desc.type = 3;
1610 		seg_desc.p = 1;
1611 		seg_desc.s = 1;
1612 		seg_desc.dpl = 3;
1613 		goto load;
1614 	}
1615 
1616 	rpl = selector & 3;
1617 
1618 	/* TR should be in GDT only */
1619 	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1620 		goto exception;
1621 
1622 	/* NULL selector is not valid for TR, CS and (except for long mode) SS */
1623 	if (null_selector) {
1624 		if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
1625 			goto exception;
1626 
1627 		if (seg == VCPU_SREG_SS) {
1628 			if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
1629 				goto exception;
1630 
1631 			/*
1632 			 * ctxt->ops->set_segment expects the CPL to be in
1633 			 * SS.DPL, so fake an expand-up 32-bit data segment.
1634 			 */
1635 			seg_desc.type = 3;
1636 			seg_desc.p = 1;
1637 			seg_desc.s = 1;
1638 			seg_desc.dpl = cpl;
1639 			seg_desc.d = 1;
1640 			seg_desc.g = 1;
1641 		}
1642 
1643 		/* Skip all following checks */
1644 		goto load;
1645 	}
1646 
1647 	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1648 	if (ret != X86EMUL_CONTINUE)
1649 		return ret;
1650 
1651 	err_code = selector & 0xfffc;
1652 	err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
1653 							   GP_VECTOR;
1654 
1655 	/* can't load system descriptor into segment selector */
1656 	if (seg <= VCPU_SREG_GS && !seg_desc.s) {
1657 		if (transfer == X86_TRANSFER_CALL_JMP)
1658 			return X86EMUL_UNHANDLEABLE;
1659 		goto exception;
1660 	}
1661 
1662 	if (!seg_desc.p) {
1663 		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1664 		goto exception;
1665 	}
1666 
1667 	dpl = seg_desc.dpl;
1668 
1669 	switch (seg) {
1670 	case VCPU_SREG_SS:
1671 		/*
1672 		 * segment is not a writable data segment or segment
1673 		 * selector's RPL != CPL or segment selector's RPL != CPL
1674 		 */
1675 		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1676 			goto exception;
1677 		break;
1678 	case VCPU_SREG_CS:
1679 		if (!(seg_desc.type & 8))
1680 			goto exception;
1681 
1682 		if (seg_desc.type & 4) {
1683 			/* conforming */
1684 			if (dpl > cpl)
1685 				goto exception;
1686 		} else {
1687 			/* nonconforming */
1688 			if (rpl > cpl || dpl != cpl)
1689 				goto exception;
1690 		}
1691 		/* in long-mode d/b must be clear if l is set */
1692 		if (seg_desc.d && seg_desc.l) {
1693 			u64 efer = 0;
1694 
1695 			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1696 			if (efer & EFER_LMA)
1697 				goto exception;
1698 		}
1699 
1700 		/* CS(RPL) <- CPL */
1701 		selector = (selector & 0xfffc) | cpl;
1702 		break;
1703 	case VCPU_SREG_TR:
1704 		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1705 			goto exception;
1706 		old_desc = seg_desc;
1707 		seg_desc.type |= 2; /* busy */
1708 		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
1709 						  sizeof(seg_desc), &ctxt->exception);
1710 		if (ret != X86EMUL_CONTINUE)
1711 			return ret;
1712 		break;
1713 	case VCPU_SREG_LDTR:
1714 		if (seg_desc.s || seg_desc.type != 2)
1715 			goto exception;
1716 		break;
1717 	default: /*  DS, ES, FS, or GS */
1718 		/*
1719 		 * segment is not a data or readable code segment or
1720 		 * ((segment is a data or nonconforming code segment)
1721 		 * and (both RPL and CPL > DPL))
1722 		 */
1723 		if ((seg_desc.type & 0xa) == 0x8 ||
1724 		    (((seg_desc.type & 0xc) != 0xc) &&
1725 		     (rpl > dpl && cpl > dpl)))
1726 			goto exception;
1727 		break;
1728 	}
1729 
1730 	if (seg_desc.s) {
1731 		/* mark segment as accessed */
1732 		if (!(seg_desc.type & 1)) {
1733 			seg_desc.type |= 1;
1734 			ret = write_segment_descriptor(ctxt, selector,
1735 						       &seg_desc);
1736 			if (ret != X86EMUL_CONTINUE)
1737 				return ret;
1738 		}
1739 	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1740 		ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
1741 				sizeof(base3), &ctxt->exception);
1742 		if (ret != X86EMUL_CONTINUE)
1743 			return ret;
1744 		if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
1745 				((u64)base3 << 32), ctxt))
1746 			return emulate_gp(ctxt, 0);
1747 	}
1748 load:
1749 	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1750 	if (desc)
1751 		*desc = seg_desc;
1752 	return X86EMUL_CONTINUE;
1753 exception:
1754 	return emulate_exception(ctxt, err_vec, err_code, true);
1755 }
1756 
1757 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1758 				   u16 selector, int seg)
1759 {
1760 	u8 cpl = ctxt->ops->cpl(ctxt);
1761 
1762 	/*
1763 	 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
1764 	 * they can load it at CPL<3 (Intel's manual says only LSS can,
1765 	 * but it's wrong).
1766 	 *
1767 	 * However, the Intel manual says that putting IST=1/DPL=3 in
1768 	 * an interrupt gate will result in SS=3 (the AMD manual instead
1769 	 * says it doesn't), so allow SS=3 in __load_segment_descriptor
1770 	 * and only forbid it here.
1771 	 */
1772 	if (seg == VCPU_SREG_SS && selector == 3 &&
1773 	    ctxt->mode == X86EMUL_MODE_PROT64)
1774 		return emulate_exception(ctxt, GP_VECTOR, 0, true);
1775 
1776 	return __load_segment_descriptor(ctxt, selector, seg, cpl,
1777 					 X86_TRANSFER_NONE, NULL);
1778 }
1779 
1780 static void write_register_operand(struct operand *op)
1781 {
1782 	return assign_register(op->addr.reg, op->val, op->bytes);
1783 }
1784 
1785 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1786 {
1787 	switch (op->type) {
1788 	case OP_REG:
1789 		write_register_operand(op);
1790 		break;
1791 	case OP_MEM:
1792 		if (ctxt->lock_prefix)
1793 			return segmented_cmpxchg(ctxt,
1794 						 op->addr.mem,
1795 						 &op->orig_val,
1796 						 &op->val,
1797 						 op->bytes);
1798 		else
1799 			return segmented_write(ctxt,
1800 					       op->addr.mem,
1801 					       &op->val,
1802 					       op->bytes);
1803 		break;
1804 	case OP_MEM_STR:
1805 		return segmented_write(ctxt,
1806 				       op->addr.mem,
1807 				       op->data,
1808 				       op->bytes * op->count);
1809 		break;
1810 	case OP_XMM:
1811 		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
1812 		break;
1813 	case OP_MM:
1814 		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
1815 		break;
1816 	case OP_NONE:
1817 		/* no writeback */
1818 		break;
1819 	default:
1820 		break;
1821 	}
1822 	return X86EMUL_CONTINUE;
1823 }
1824 
1825 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1826 {
1827 	struct segmented_address addr;
1828 
1829 	rsp_increment(ctxt, -bytes);
1830 	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1831 	addr.seg = VCPU_SREG_SS;
1832 
1833 	return segmented_write(ctxt, addr, data, bytes);
1834 }
1835 
1836 static int em_push(struct x86_emulate_ctxt *ctxt)
1837 {
1838 	/* Disable writeback. */
1839 	ctxt->dst.type = OP_NONE;
1840 	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1841 }
1842 
1843 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1844 		       void *dest, int len)
1845 {
1846 	int rc;
1847 	struct segmented_address addr;
1848 
1849 	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1850 	addr.seg = VCPU_SREG_SS;
1851 	rc = segmented_read(ctxt, addr, dest, len);
1852 	if (rc != X86EMUL_CONTINUE)
1853 		return rc;
1854 
1855 	rsp_increment(ctxt, len);
1856 	return rc;
1857 }
1858 
1859 static int em_pop(struct x86_emulate_ctxt *ctxt)
1860 {
1861 	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1862 }
1863 
1864 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1865 			void *dest, int len)
1866 {
1867 	int rc;
1868 	unsigned long val, change_mask;
1869 	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1870 	int cpl = ctxt->ops->cpl(ctxt);
1871 
1872 	rc = emulate_pop(ctxt, &val, len);
1873 	if (rc != X86EMUL_CONTINUE)
1874 		return rc;
1875 
1876 	change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
1877 		      X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
1878 		      X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
1879 		      X86_EFLAGS_AC | X86_EFLAGS_ID;
1880 
1881 	switch(ctxt->mode) {
1882 	case X86EMUL_MODE_PROT64:
1883 	case X86EMUL_MODE_PROT32:
1884 	case X86EMUL_MODE_PROT16:
1885 		if (cpl == 0)
1886 			change_mask |= X86_EFLAGS_IOPL;
1887 		if (cpl <= iopl)
1888 			change_mask |= X86_EFLAGS_IF;
1889 		break;
1890 	case X86EMUL_MODE_VM86:
1891 		if (iopl < 3)
1892 			return emulate_gp(ctxt, 0);
1893 		change_mask |= X86_EFLAGS_IF;
1894 		break;
1895 	default: /* real mode */
1896 		change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1897 		break;
1898 	}
1899 
1900 	*(unsigned long *)dest =
1901 		(ctxt->eflags & ~change_mask) | (val & change_mask);
1902 
1903 	return rc;
1904 }
1905 
1906 static int em_popf(struct x86_emulate_ctxt *ctxt)
1907 {
1908 	ctxt->dst.type = OP_REG;
1909 	ctxt->dst.addr.reg = &ctxt->eflags;
1910 	ctxt->dst.bytes = ctxt->op_bytes;
1911 	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1912 }
1913 
1914 static int em_enter(struct x86_emulate_ctxt *ctxt)
1915 {
1916 	int rc;
1917 	unsigned frame_size = ctxt->src.val;
1918 	unsigned nesting_level = ctxt->src2.val & 31;
1919 	ulong rbp;
1920 
1921 	if (nesting_level)
1922 		return X86EMUL_UNHANDLEABLE;
1923 
1924 	rbp = reg_read(ctxt, VCPU_REGS_RBP);
1925 	rc = push(ctxt, &rbp, stack_size(ctxt));
1926 	if (rc != X86EMUL_CONTINUE)
1927 		return rc;
1928 	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
1929 		      stack_mask(ctxt));
1930 	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
1931 		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
1932 		      stack_mask(ctxt));
1933 	return X86EMUL_CONTINUE;
1934 }
1935 
1936 static int em_leave(struct x86_emulate_ctxt *ctxt)
1937 {
1938 	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
1939 		      stack_mask(ctxt));
1940 	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
1941 }
1942 
1943 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1944 {
1945 	int seg = ctxt->src2.val;
1946 
1947 	ctxt->src.val = get_segment_selector(ctxt, seg);
1948 	if (ctxt->op_bytes == 4) {
1949 		rsp_increment(ctxt, -2);
1950 		ctxt->op_bytes = 2;
1951 	}
1952 
1953 	return em_push(ctxt);
1954 }
1955 
1956 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1957 {
1958 	int seg = ctxt->src2.val;
1959 	unsigned long selector;
1960 	int rc;
1961 
1962 	rc = emulate_pop(ctxt, &selector, 2);
1963 	if (rc != X86EMUL_CONTINUE)
1964 		return rc;
1965 
1966 	if (ctxt->modrm_reg == VCPU_SREG_SS)
1967 		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1968 	if (ctxt->op_bytes > 2)
1969 		rsp_increment(ctxt, ctxt->op_bytes - 2);
1970 
1971 	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1972 	return rc;
1973 }
1974 
1975 static int em_pusha(struct x86_emulate_ctxt *ctxt)
1976 {
1977 	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1978 	int rc = X86EMUL_CONTINUE;
1979 	int reg = VCPU_REGS_RAX;
1980 
1981 	while (reg <= VCPU_REGS_RDI) {
1982 		(reg == VCPU_REGS_RSP) ?
1983 		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1984 
1985 		rc = em_push(ctxt);
1986 		if (rc != X86EMUL_CONTINUE)
1987 			return rc;
1988 
1989 		++reg;
1990 	}
1991 
1992 	return rc;
1993 }
1994 
1995 static int em_pushf(struct x86_emulate_ctxt *ctxt)
1996 {
1997 	ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
1998 	return em_push(ctxt);
1999 }
2000 
2001 static int em_popa(struct x86_emulate_ctxt *ctxt)
2002 {
2003 	int rc = X86EMUL_CONTINUE;
2004 	int reg = VCPU_REGS_RDI;
2005 	u32 val;
2006 
2007 	while (reg >= VCPU_REGS_RAX) {
2008 		if (reg == VCPU_REGS_RSP) {
2009 			rsp_increment(ctxt, ctxt->op_bytes);
2010 			--reg;
2011 		}
2012 
2013 		rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2014 		if (rc != X86EMUL_CONTINUE)
2015 			break;
2016 		assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2017 		--reg;
2018 	}
2019 	return rc;
2020 }
2021 
2022 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2023 {
2024 	const struct x86_emulate_ops *ops = ctxt->ops;
2025 	int rc;
2026 	struct desc_ptr dt;
2027 	gva_t cs_addr;
2028 	gva_t eip_addr;
2029 	u16 cs, eip;
2030 
2031 	/* TODO: Add limit checks */
2032 	ctxt->src.val = ctxt->eflags;
2033 	rc = em_push(ctxt);
2034 	if (rc != X86EMUL_CONTINUE)
2035 		return rc;
2036 
2037 	ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2038 
2039 	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2040 	rc = em_push(ctxt);
2041 	if (rc != X86EMUL_CONTINUE)
2042 		return rc;
2043 
2044 	ctxt->src.val = ctxt->_eip;
2045 	rc = em_push(ctxt);
2046 	if (rc != X86EMUL_CONTINUE)
2047 		return rc;
2048 
2049 	ops->get_idt(ctxt, &dt);
2050 
2051 	eip_addr = dt.address + (irq << 2);
2052 	cs_addr = dt.address + (irq << 2) + 2;
2053 
2054 	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
2055 	if (rc != X86EMUL_CONTINUE)
2056 		return rc;
2057 
2058 	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
2059 	if (rc != X86EMUL_CONTINUE)
2060 		return rc;
2061 
2062 	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2063 	if (rc != X86EMUL_CONTINUE)
2064 		return rc;
2065 
2066 	ctxt->_eip = eip;
2067 
2068 	return rc;
2069 }
2070 
2071 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2072 {
2073 	int rc;
2074 
2075 	invalidate_registers(ctxt);
2076 	rc = __emulate_int_real(ctxt, irq);
2077 	if (rc == X86EMUL_CONTINUE)
2078 		writeback_registers(ctxt);
2079 	return rc;
2080 }
2081 
2082 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2083 {
2084 	switch(ctxt->mode) {
2085 	case X86EMUL_MODE_REAL:
2086 		return __emulate_int_real(ctxt, irq);
2087 	case X86EMUL_MODE_VM86:
2088 	case X86EMUL_MODE_PROT16:
2089 	case X86EMUL_MODE_PROT32:
2090 	case X86EMUL_MODE_PROT64:
2091 	default:
2092 		/* Protected mode interrupts unimplemented yet */
2093 		return X86EMUL_UNHANDLEABLE;
2094 	}
2095 }
2096 
2097 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2098 {
2099 	int rc = X86EMUL_CONTINUE;
2100 	unsigned long temp_eip = 0;
2101 	unsigned long temp_eflags = 0;
2102 	unsigned long cs = 0;
2103 	unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
2104 			     X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
2105 			     X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
2106 			     X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
2107 			     X86_EFLAGS_AC | X86_EFLAGS_ID |
2108 			     X86_EFLAGS_FIXED;
2109 	unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
2110 				  X86_EFLAGS_VIP;
2111 
2112 	/* TODO: Add stack limit check */
2113 
2114 	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2115 
2116 	if (rc != X86EMUL_CONTINUE)
2117 		return rc;
2118 
2119 	if (temp_eip & ~0xffff)
2120 		return emulate_gp(ctxt, 0);
2121 
2122 	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2123 
2124 	if (rc != X86EMUL_CONTINUE)
2125 		return rc;
2126 
2127 	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2128 
2129 	if (rc != X86EMUL_CONTINUE)
2130 		return rc;
2131 
2132 	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2133 
2134 	if (rc != X86EMUL_CONTINUE)
2135 		return rc;
2136 
2137 	ctxt->_eip = temp_eip;
2138 
2139 	if (ctxt->op_bytes == 4)
2140 		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2141 	else if (ctxt->op_bytes == 2) {
2142 		ctxt->eflags &= ~0xffff;
2143 		ctxt->eflags |= temp_eflags;
2144 	}
2145 
2146 	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
2147 	ctxt->eflags |= X86_EFLAGS_FIXED;
2148 	ctxt->ops->set_nmi_mask(ctxt, false);
2149 
2150 	return rc;
2151 }
2152 
2153 static int em_iret(struct x86_emulate_ctxt *ctxt)
2154 {
2155 	switch(ctxt->mode) {
2156 	case X86EMUL_MODE_REAL:
2157 		return emulate_iret_real(ctxt);
2158 	case X86EMUL_MODE_VM86:
2159 	case X86EMUL_MODE_PROT16:
2160 	case X86EMUL_MODE_PROT32:
2161 	case X86EMUL_MODE_PROT64:
2162 	default:
2163 		/* iret from protected mode unimplemented yet */
2164 		return X86EMUL_UNHANDLEABLE;
2165 	}
2166 }
2167 
2168 static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
2169 {
2170 	int rc;
2171 	unsigned short sel;
2172 	struct desc_struct new_desc;
2173 	u8 cpl = ctxt->ops->cpl(ctxt);
2174 
2175 	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2176 
2177 	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
2178 				       X86_TRANSFER_CALL_JMP,
2179 				       &new_desc);
2180 	if (rc != X86EMUL_CONTINUE)
2181 		return rc;
2182 
2183 	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2184 	/* Error handling is not implemented. */
2185 	if (rc != X86EMUL_CONTINUE)
2186 		return X86EMUL_UNHANDLEABLE;
2187 
2188 	return rc;
2189 }
2190 
2191 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2192 {
2193 	return assign_eip_near(ctxt, ctxt->src.val);
2194 }
2195 
2196 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
2197 {
2198 	int rc;
2199 	long int old_eip;
2200 
2201 	old_eip = ctxt->_eip;
2202 	rc = assign_eip_near(ctxt, ctxt->src.val);
2203 	if (rc != X86EMUL_CONTINUE)
2204 		return rc;
2205 	ctxt->src.val = old_eip;
2206 	rc = em_push(ctxt);
2207 	return rc;
2208 }
2209 
2210 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2211 {
2212 	u64 old = ctxt->dst.orig_val64;
2213 
2214 	if (ctxt->dst.bytes == 16)
2215 		return X86EMUL_UNHANDLEABLE;
2216 
2217 	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
2218 	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
2219 		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
2220 		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2221 		ctxt->eflags &= ~X86_EFLAGS_ZF;
2222 	} else {
2223 		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
2224 			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2225 
2226 		ctxt->eflags |= X86_EFLAGS_ZF;
2227 	}
2228 	return X86EMUL_CONTINUE;
2229 }
2230 
2231 static int em_ret(struct x86_emulate_ctxt *ctxt)
2232 {
2233 	int rc;
2234 	unsigned long eip;
2235 
2236 	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2237 	if (rc != X86EMUL_CONTINUE)
2238 		return rc;
2239 
2240 	return assign_eip_near(ctxt, eip);
2241 }
2242 
2243 static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2244 {
2245 	int rc;
2246 	unsigned long eip, cs;
2247 	int cpl = ctxt->ops->cpl(ctxt);
2248 	struct desc_struct new_desc;
2249 
2250 	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2251 	if (rc != X86EMUL_CONTINUE)
2252 		return rc;
2253 	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2254 	if (rc != X86EMUL_CONTINUE)
2255 		return rc;
2256 	/* Outer-privilege level return is not implemented */
2257 	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
2258 		return X86EMUL_UNHANDLEABLE;
2259 	rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
2260 				       X86_TRANSFER_RET,
2261 				       &new_desc);
2262 	if (rc != X86EMUL_CONTINUE)
2263 		return rc;
2264 	rc = assign_eip_far(ctxt, eip, &new_desc);
2265 	/* Error handling is not implemented. */
2266 	if (rc != X86EMUL_CONTINUE)
2267 		return X86EMUL_UNHANDLEABLE;
2268 
2269 	return rc;
2270 }
2271 
2272 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
2273 {
2274         int rc;
2275 
2276         rc = em_ret_far(ctxt);
2277         if (rc != X86EMUL_CONTINUE)
2278                 return rc;
2279         rsp_increment(ctxt, ctxt->src.val);
2280         return X86EMUL_CONTINUE;
2281 }
2282 
2283 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
2284 {
2285 	/* Save real source value, then compare EAX against destination. */
2286 	ctxt->dst.orig_val = ctxt->dst.val;
2287 	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2288 	ctxt->src.orig_val = ctxt->src.val;
2289 	ctxt->src.val = ctxt->dst.orig_val;
2290 	fastop(ctxt, em_cmp);
2291 
2292 	if (ctxt->eflags & X86_EFLAGS_ZF) {
2293 		/* Success: write back to memory; no update of EAX */
2294 		ctxt->src.type = OP_NONE;
2295 		ctxt->dst.val = ctxt->src.orig_val;
2296 	} else {
2297 		/* Failure: write the value we saw to EAX. */
2298 		ctxt->src.type = OP_REG;
2299 		ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2300 		ctxt->src.val = ctxt->dst.orig_val;
2301 		/* Create write-cycle to dest by writing the same value */
2302 		ctxt->dst.val = ctxt->dst.orig_val;
2303 	}
2304 	return X86EMUL_CONTINUE;
2305 }
2306 
2307 static int em_lseg(struct x86_emulate_ctxt *ctxt)
2308 {
2309 	int seg = ctxt->src2.val;
2310 	unsigned short sel;
2311 	int rc;
2312 
2313 	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2314 
2315 	rc = load_segment_descriptor(ctxt, sel, seg);
2316 	if (rc != X86EMUL_CONTINUE)
2317 		return rc;
2318 
2319 	ctxt->dst.val = ctxt->src.val;
2320 	return rc;
2321 }
2322 
2323 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
2324 {
2325 	u32 eax, ebx, ecx, edx;
2326 
2327 	eax = 0x80000001;
2328 	ecx = 0;
2329 	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2330 	return edx & bit(X86_FEATURE_LM);
2331 }
2332 
2333 #define GET_SMSTATE(type, smbase, offset)				  \
2334 	({								  \
2335 	 type __val;							  \
2336 	 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val,      \
2337 				      sizeof(__val));			  \
2338 	 if (r != X86EMUL_CONTINUE)					  \
2339 		 return X86EMUL_UNHANDLEABLE;				  \
2340 	 __val;								  \
2341 	})
2342 
2343 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
2344 {
2345 	desc->g    = (flags >> 23) & 1;
2346 	desc->d    = (flags >> 22) & 1;
2347 	desc->l    = (flags >> 21) & 1;
2348 	desc->avl  = (flags >> 20) & 1;
2349 	desc->p    = (flags >> 15) & 1;
2350 	desc->dpl  = (flags >> 13) & 3;
2351 	desc->s    = (flags >> 12) & 1;
2352 	desc->type = (flags >>  8) & 15;
2353 }
2354 
2355 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2356 {
2357 	struct desc_struct desc;
2358 	int offset;
2359 	u16 selector;
2360 
2361 	selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);
2362 
2363 	if (n < 3)
2364 		offset = 0x7f84 + n * 12;
2365 	else
2366 		offset = 0x7f2c + (n - 3) * 12;
2367 
2368 	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
2369 	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
2370 	rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
2371 	ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
2372 	return X86EMUL_CONTINUE;
2373 }
2374 
2375 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
2376 {
2377 	struct desc_struct desc;
2378 	int offset;
2379 	u16 selector;
2380 	u32 base3;
2381 
2382 	offset = 0x7e00 + n * 16;
2383 
2384 	selector =                GET_SMSTATE(u16, smbase, offset);
2385 	rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
2386 	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
2387 	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
2388 	base3 =                   GET_SMSTATE(u32, smbase, offset + 12);
2389 
2390 	ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
2391 	return X86EMUL_CONTINUE;
2392 }
2393 
2394 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2395 				    u64 cr0, u64 cr3, u64 cr4)
2396 {
2397 	int bad;
2398 	u64 pcid;
2399 
2400 	/* In order to later set CR4.PCIDE, CR3[11:0] must be zero.  */
2401 	pcid = 0;
2402 	if (cr4 & X86_CR4_PCIDE) {
2403 		pcid = cr3 & 0xfff;
2404 		cr3 &= ~0xfff;
2405 	}
2406 
2407 	bad = ctxt->ops->set_cr(ctxt, 3, cr3);
2408 	if (bad)
2409 		return X86EMUL_UNHANDLEABLE;
2410 
2411 	/*
2412 	 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
2413 	 * Then enable protected mode.	However, PCID cannot be enabled
2414 	 * if EFER.LMA=0, so set it separately.
2415 	 */
2416 	bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2417 	if (bad)
2418 		return X86EMUL_UNHANDLEABLE;
2419 
2420 	bad = ctxt->ops->set_cr(ctxt, 0, cr0);
2421 	if (bad)
2422 		return X86EMUL_UNHANDLEABLE;
2423 
2424 	if (cr4 & X86_CR4_PCIDE) {
2425 		bad = ctxt->ops->set_cr(ctxt, 4, cr4);
2426 		if (bad)
2427 			return X86EMUL_UNHANDLEABLE;
2428 		if (pcid) {
2429 			bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
2430 			if (bad)
2431 				return X86EMUL_UNHANDLEABLE;
2432 		}
2433 
2434 	}
2435 
2436 	return X86EMUL_CONTINUE;
2437 }
2438 
2439 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
2440 {
2441 	struct desc_struct desc;
2442 	struct desc_ptr dt;
2443 	u16 selector;
2444 	u32 val, cr0, cr3, cr4;
2445 	int i;
2446 
2447 	cr0 =                      GET_SMSTATE(u32, smbase, 0x7ffc);
2448 	cr3 =                      GET_SMSTATE(u32, smbase, 0x7ff8);
2449 	ctxt->eflags =             GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
2450 	ctxt->_eip =               GET_SMSTATE(u32, smbase, 0x7ff0);
2451 
2452 	for (i = 0; i < 8; i++)
2453 		*reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);
2454 
2455 	val = GET_SMSTATE(u32, smbase, 0x7fcc);
2456 	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2457 	val = GET_SMSTATE(u32, smbase, 0x7fc8);
2458 	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2459 
2460 	selector =                 GET_SMSTATE(u32, smbase, 0x7fc4);
2461 	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f64));
2462 	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f60));
2463 	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f5c));
2464 	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);
2465 
2466 	selector =                 GET_SMSTATE(u32, smbase, 0x7fc0);
2467 	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f80));
2468 	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f7c));
2469 	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f78));
2470 	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);
2471 
2472 	dt.address =               GET_SMSTATE(u32, smbase, 0x7f74);
2473 	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f70);
2474 	ctxt->ops->set_gdt(ctxt, &dt);
2475 
2476 	dt.address =               GET_SMSTATE(u32, smbase, 0x7f58);
2477 	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f54);
2478 	ctxt->ops->set_idt(ctxt, &dt);
2479 
2480 	for (i = 0; i < 6; i++) {
2481 		int r = rsm_load_seg_32(ctxt, smbase, i);
2482 		if (r != X86EMUL_CONTINUE)
2483 			return r;
2484 	}
2485 
2486 	cr4 = GET_SMSTATE(u32, smbase, 0x7f14);
2487 
2488 	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));
2489 
2490 	return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2491 }
2492 
2493 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
2494 {
2495 	struct desc_struct desc;
2496 	struct desc_ptr dt;
2497 	u64 val, cr0, cr3, cr4;
2498 	u32 base3;
2499 	u16 selector;
2500 	int i, r;
2501 
2502 	for (i = 0; i < 16; i++)
2503 		*reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);
2504 
2505 	ctxt->_eip   = GET_SMSTATE(u64, smbase, 0x7f78);
2506 	ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;
2507 
2508 	val = GET_SMSTATE(u32, smbase, 0x7f68);
2509 	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
2510 	val = GET_SMSTATE(u32, smbase, 0x7f60);
2511 	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);
2512 
2513 	cr0 =                       GET_SMSTATE(u64, smbase, 0x7f58);
2514 	cr3 =                       GET_SMSTATE(u64, smbase, 0x7f50);
2515 	cr4 =                       GET_SMSTATE(u64, smbase, 0x7f48);
2516 	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
2517 	val =                       GET_SMSTATE(u64, smbase, 0x7ed0);
2518 	ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);
2519 
2520 	selector =                  GET_SMSTATE(u32, smbase, 0x7e90);
2521 	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e92) << 8);
2522 	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e94));
2523 	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e98));
2524 	base3 =                     GET_SMSTATE(u32, smbase, 0x7e9c);
2525 	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);
2526 
2527 	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e84);
2528 	dt.address =                GET_SMSTATE(u64, smbase, 0x7e88);
2529 	ctxt->ops->set_idt(ctxt, &dt);
2530 
2531 	selector =                  GET_SMSTATE(u32, smbase, 0x7e70);
2532 	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e72) << 8);
2533 	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e74));
2534 	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e78));
2535 	base3 =                     GET_SMSTATE(u32, smbase, 0x7e7c);
2536 	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);
2537 
2538 	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e64);
2539 	dt.address =                GET_SMSTATE(u64, smbase, 0x7e68);
2540 	ctxt->ops->set_gdt(ctxt, &dt);
2541 
2542 	r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2543 	if (r != X86EMUL_CONTINUE)
2544 		return r;
2545 
2546 	for (i = 0; i < 6; i++) {
2547 		r = rsm_load_seg_64(ctxt, smbase, i);
2548 		if (r != X86EMUL_CONTINUE)
2549 			return r;
2550 	}
2551 
2552 	return X86EMUL_CONTINUE;
2553 }
2554 
2555 static int em_rsm(struct x86_emulate_ctxt *ctxt)
2556 {
2557 	unsigned long cr0, cr4, efer;
2558 	u64 smbase;
2559 	int ret;
2560 
2561 	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
2562 		return emulate_ud(ctxt);
2563 
2564 	/*
2565 	 * Get back to real mode, to prepare a safe state in which to load
2566 	 * CR0/CR3/CR4/EFER.  It's all a bit more complicated if the vCPU
2567 	 * supports long mode.
2568 	 */
2569 	cr4 = ctxt->ops->get_cr(ctxt, 4);
2570 	if (emulator_has_longmode(ctxt)) {
2571 		struct desc_struct cs_desc;
2572 
2573 		/* Zero CR4.PCIDE before CR0.PG.  */
2574 		if (cr4 & X86_CR4_PCIDE) {
2575 			ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
2576 			cr4 &= ~X86_CR4_PCIDE;
2577 		}
2578 
2579 		/* A 32-bit code segment is required to clear EFER.LMA.  */
2580 		memset(&cs_desc, 0, sizeof(cs_desc));
2581 		cs_desc.type = 0xb;
2582 		cs_desc.s = cs_desc.g = cs_desc.p = 1;
2583 		ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
2584 	}
2585 
2586 	/* For the 64-bit case, this will clear EFER.LMA.  */
2587 	cr0 = ctxt->ops->get_cr(ctxt, 0);
2588 	if (cr0 & X86_CR0_PE)
2589 		ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2590 
2591 	/* Now clear CR4.PAE (which must be done before clearing EFER.LME).  */
2592 	if (cr4 & X86_CR4_PAE)
2593 		ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2594 
2595 	/* And finally go back to 32-bit mode.  */
2596 	efer = 0;
2597 	ctxt->ops->set_msr(ctxt, MSR_EFER, efer);
2598 
2599 	smbase = ctxt->ops->get_smbase(ctxt);
2600 
2601 	/*
2602 	 * Give pre_leave_smm() a chance to make ISA-specific changes to the
2603 	 * vCPU state (e.g. enter guest mode) before loading state from the SMM
2604 	 * state-save area.
2605 	 */
2606 	if (ctxt->ops->pre_leave_smm(ctxt, smbase))
2607 		return X86EMUL_UNHANDLEABLE;
2608 
2609 	if (emulator_has_longmode(ctxt))
2610 		ret = rsm_load_state_64(ctxt, smbase + 0x8000);
2611 	else
2612 		ret = rsm_load_state_32(ctxt, smbase + 0x8000);
2613 
2614 	if (ret != X86EMUL_CONTINUE) {
2615 		/* FIXME: should triple fault */
2616 		return X86EMUL_UNHANDLEABLE;
2617 	}
2618 
2619 	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2620 		ctxt->ops->set_nmi_mask(ctxt, false);
2621 
2622 	ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
2623 		~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
2624 	return X86EMUL_CONTINUE;
2625 }
2626 
2627 static void
2628 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2629 			struct desc_struct *cs, struct desc_struct *ss)
2630 {
2631 	cs->l = 0;		/* will be adjusted later */
2632 	set_desc_base(cs, 0);	/* flat segment */
2633 	cs->g = 1;		/* 4kb granularity */
2634 	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2635 	cs->type = 0x0b;	/* Read, Execute, Accessed */
2636 	cs->s = 1;
2637 	cs->dpl = 0;		/* will be adjusted later */
2638 	cs->p = 1;
2639 	cs->d = 1;
2640 	cs->avl = 0;
2641 
2642 	set_desc_base(ss, 0);	/* flat segment */
2643 	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2644 	ss->g = 1;		/* 4kb granularity */
2645 	ss->s = 1;
2646 	ss->type = 0x03;	/* Read/Write, Accessed */
2647 	ss->d = 1;		/* 32bit stack segment */
2648 	ss->dpl = 0;
2649 	ss->p = 1;
2650 	ss->l = 0;
2651 	ss->avl = 0;
2652 }
2653 
2654 static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
2655 {
2656 	u32 eax, ebx, ecx, edx;
2657 
2658 	eax = ecx = 0;
2659 	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2660 	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2661 		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
2662 		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
2663 }
2664 
2665 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
2666 {
2667 	const struct x86_emulate_ops *ops = ctxt->ops;
2668 	u32 eax, ebx, ecx, edx;
2669 
2670 	/*
2671 	 * syscall should always be enabled in longmode - so only become
2672 	 * vendor specific (cpuid) if other modes are active...
2673 	 */
2674 	if (ctxt->mode == X86EMUL_MODE_PROT64)
2675 		return true;
2676 
2677 	eax = 0x00000000;
2678 	ecx = 0x00000000;
2679 	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2680 	/*
2681 	 * Intel ("GenuineIntel")
2682 	 * remark: Intel CPUs only support "syscall" in 64bit
2683 	 * longmode. Also an 64bit guest with a
2684 	 * 32bit compat-app running will #UD !! While this
2685 	 * behaviour can be fixed (by emulating) into AMD
2686 	 * response - CPUs of AMD can't behave like Intel.
2687 	 */
2688 	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
2689 	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
2690 	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
2691 		return false;
2692 
2693 	/* AMD ("AuthenticAMD") */
2694 	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
2695 	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
2696 	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
2697 		return true;
2698 
2699 	/* AMD ("AMDisbetter!") */
2700 	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
2701 	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
2702 	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
2703 		return true;
2704 
2705 	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
2706 	return false;
2707 }
2708 
2709 static int em_syscall(struct x86_emulate_ctxt *ctxt)
2710 {
2711 	const struct x86_emulate_ops *ops = ctxt->ops;
2712 	struct desc_struct cs, ss;
2713 	u64 msr_data;
2714 	u16 cs_sel, ss_sel;
2715 	u64 efer = 0;
2716 
2717 	/* syscall is not available in real mode */
2718 	if (ctxt->mode == X86EMUL_MODE_REAL ||
2719 	    ctxt->mode == X86EMUL_MODE_VM86)
2720 		return emulate_ud(ctxt);
2721 
2722 	if (!(em_syscall_is_enabled(ctxt)))
2723 		return emulate_ud(ctxt);
2724 
2725 	ops->get_msr(ctxt, MSR_EFER, &efer);
2726 	setup_syscalls_segments(ctxt, &cs, &ss);
2727 
2728 	if (!(efer & EFER_SCE))
2729 		return emulate_ud(ctxt);
2730 
2731 	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2732 	msr_data >>= 32;
2733 	cs_sel = (u16)(msr_data & 0xfffc);
2734 	ss_sel = (u16)(msr_data + 8);
2735 
2736 	if (efer & EFER_LMA) {
2737 		cs.d = 0;
2738 		cs.l = 1;
2739 	}
2740 	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2741 	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2742 
2743 	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2744 	if (efer & EFER_LMA) {
2745 #ifdef CONFIG_X86_64
2746 		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2747 
2748 		ops->get_msr(ctxt,
2749 			     ctxt->mode == X86EMUL_MODE_PROT64 ?
2750 			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2751 		ctxt->_eip = msr_data;
2752 
2753 		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2754 		ctxt->eflags &= ~msr_data;
2755 		ctxt->eflags |= X86_EFLAGS_FIXED;
2756 #endif
2757 	} else {
2758 		/* legacy mode */
2759 		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2760 		ctxt->_eip = (u32)msr_data;
2761 
2762 		ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2763 	}
2764 
2765 	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
2766 	return X86EMUL_CONTINUE;
2767 }
2768 
2769 static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2770 {
2771 	const struct x86_emulate_ops *ops = ctxt->ops;
2772 	struct desc_struct cs, ss;
2773 	u64 msr_data;
2774 	u16 cs_sel, ss_sel;
2775 	u64 efer = 0;
2776 
2777 	ops->get_msr(ctxt, MSR_EFER, &efer);
2778 	/* inject #GP if in real mode */
2779 	if (ctxt->mode == X86EMUL_MODE_REAL)
2780 		return emulate_gp(ctxt, 0);
2781 
2782 	/*
2783 	 * Not recognized on AMD in compat mode (but is recognized in legacy
2784 	 * mode).
2785 	 */
2786 	if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2787 	    && !vendor_intel(ctxt))
2788 		return emulate_ud(ctxt);
2789 
2790 	/* sysenter/sysexit have not been tested in 64bit mode. */
2791 	if (ctxt->mode == X86EMUL_MODE_PROT64)
2792 		return X86EMUL_UNHANDLEABLE;
2793 
2794 	setup_syscalls_segments(ctxt, &cs, &ss);
2795 
2796 	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2797 	if ((msr_data & 0xfffc) == 0x0)
2798 		return emulate_gp(ctxt, 0);
2799 
2800 	ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2801 	cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2802 	ss_sel = cs_sel + 8;
2803 	if (efer & EFER_LMA) {
2804 		cs.d = 0;
2805 		cs.l = 1;
2806 	}
2807 
2808 	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2809 	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2810 
2811 	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2812 	ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2813 
2814 	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2815 	*reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
2816 							      (u32)msr_data;
2817 
2818 	return X86EMUL_CONTINUE;
2819 }
2820 
2821 static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2822 {
2823 	const struct x86_emulate_ops *ops = ctxt->ops;
2824 	struct desc_struct cs, ss;
2825 	u64 msr_data, rcx, rdx;
2826 	int usermode;
2827 	u16 cs_sel = 0, ss_sel = 0;
2828 
2829 	/* inject #GP if in real mode or Virtual 8086 mode */
2830 	if (ctxt->mode == X86EMUL_MODE_REAL ||
2831 	    ctxt->mode == X86EMUL_MODE_VM86)
2832 		return emulate_gp(ctxt, 0);
2833 
2834 	setup_syscalls_segments(ctxt, &cs, &ss);
2835 
2836 	if ((ctxt->rex_prefix & 0x8) != 0x0)
2837 		usermode = X86EMUL_MODE_PROT64;
2838 	else
2839 		usermode = X86EMUL_MODE_PROT32;
2840 
2841 	rcx = reg_read(ctxt, VCPU_REGS_RCX);
2842 	rdx = reg_read(ctxt, VCPU_REGS_RDX);
2843 
2844 	cs.dpl = 3;
2845 	ss.dpl = 3;
2846 	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2847 	switch (usermode) {
2848 	case X86EMUL_MODE_PROT32:
2849 		cs_sel = (u16)(msr_data + 16);
2850 		if ((msr_data & 0xfffc) == 0x0)
2851 			return emulate_gp(ctxt, 0);
2852 		ss_sel = (u16)(msr_data + 24);
2853 		rcx = (u32)rcx;
2854 		rdx = (u32)rdx;
2855 		break;
2856 	case X86EMUL_MODE_PROT64:
2857 		cs_sel = (u16)(msr_data + 32);
2858 		if (msr_data == 0x0)
2859 			return emulate_gp(ctxt, 0);
2860 		ss_sel = cs_sel + 8;
2861 		cs.d = 0;
2862 		cs.l = 1;
2863 		if (emul_is_noncanonical_address(rcx, ctxt) ||
2864 		    emul_is_noncanonical_address(rdx, ctxt))
2865 			return emulate_gp(ctxt, 0);
2866 		break;
2867 	}
2868 	cs_sel |= SEGMENT_RPL_MASK;
2869 	ss_sel |= SEGMENT_RPL_MASK;
2870 
2871 	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
2872 	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2873 
2874 	ctxt->_eip = rdx;
2875 	*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2876 
2877 	return X86EMUL_CONTINUE;
2878 }
2879 
2880 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2881 {
2882 	int iopl;
2883 	if (ctxt->mode == X86EMUL_MODE_REAL)
2884 		return false;
2885 	if (ctxt->mode == X86EMUL_MODE_VM86)
2886 		return true;
2887 	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2888 	return ctxt->ops->cpl(ctxt) > iopl;
2889 }
2890 
2891 #define VMWARE_PORT_VMPORT	(0x5658)
2892 #define VMWARE_PORT_VMRPC	(0x5659)
2893 
2894 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
2895 					    u16 port, u16 len)
2896 {
2897 	const struct x86_emulate_ops *ops = ctxt->ops;
2898 	struct desc_struct tr_seg;
2899 	u32 base3;
2900 	int r;
2901 	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2902 	unsigned mask = (1 << len) - 1;
2903 	unsigned long base;
2904 
2905 	/*
2906 	 * VMware allows access to these ports even if denied
2907 	 * by TSS I/O permission bitmap. Mimic behavior.
2908 	 */
2909 	if (enable_vmware_backdoor &&
2910 	    ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
2911 		return true;
2912 
2913 	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2914 	if (!tr_seg.p)
2915 		return false;
2916 	if (desc_limit_scaled(&tr_seg) < 103)
2917 		return false;
2918 	base = get_desc_base(&tr_seg);
2919 #ifdef CONFIG_X86_64
2920 	base |= ((u64)base3) << 32;
2921 #endif
2922 	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2923 	if (r != X86EMUL_CONTINUE)
2924 		return false;
2925 	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2926 		return false;
2927 	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2928 	if (r != X86EMUL_CONTINUE)
2929 		return false;
2930 	if ((perm >> bit_idx) & mask)
2931 		return false;
2932 	return true;
2933 }
2934 
2935 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
2936 				 u16 port, u16 len)
2937 {
2938 	if (ctxt->perm_ok)
2939 		return true;
2940 
2941 	if (emulator_bad_iopl(ctxt))
2942 		if (!emulator_io_port_access_allowed(ctxt, port, len))
2943 			return false;
2944 
2945 	ctxt->perm_ok = true;
2946 
2947 	return true;
2948 }
2949 
2950 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
2951 {
2952 	/*
2953 	 * Intel CPUs mask the counter and pointers in quite strange
2954 	 * manner when ECX is zero due to REP-string optimizations.
2955 	 */
2956 #ifdef CONFIG_X86_64
2957 	if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
2958 		return;
2959 
2960 	*reg_write(ctxt, VCPU_REGS_RCX) = 0;
2961 
2962 	switch (ctxt->b) {
2963 	case 0xa4:	/* movsb */
2964 	case 0xa5:	/* movsd/w */
2965 		*reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
2966 		/* fall through */
2967 	case 0xaa:	/* stosb */
2968 	case 0xab:	/* stosd/w */
2969 		*reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
2970 	}
2971 #endif
2972 }
2973 
2974 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
2975 				struct tss_segment_16 *tss)
2976 {
2977 	tss->ip = ctxt->_eip;
2978 	tss->flag = ctxt->eflags;
2979 	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
2980 	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
2981 	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
2982 	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
2983 	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
2984 	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
2985 	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
2986 	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2987 
2988 	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
2989 	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2990 	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
2991 	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
2992 	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2993 }
2994 
2995 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
2996 				 struct tss_segment_16 *tss)
2997 {
2998 	int ret;
2999 	u8 cpl;
3000 
3001 	ctxt->_eip = tss->ip;
3002 	ctxt->eflags = tss->flag | 2;
3003 	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
3004 	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
3005 	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
3006 	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
3007 	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
3008 	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
3009 	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
3010 	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
3011 
3012 	/*
3013 	 * SDM says that segment selectors are loaded before segment
3014 	 * descriptors
3015 	 */
3016 	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
3017 	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3018 	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3019 	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3020 	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3021 
3022 	cpl = tss->cs & 3;
3023 
3024 	/*
3025 	 * Now load segment descriptors. If fault happens at this stage
3026 	 * it is handled in a context of new task
3027 	 */
3028 	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3029 					X86_TRANSFER_TASK_SWITCH, NULL);
3030 	if (ret != X86EMUL_CONTINUE)
3031 		return ret;
3032 	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3033 					X86_TRANSFER_TASK_SWITCH, NULL);
3034 	if (ret != X86EMUL_CONTINUE)
3035 		return ret;
3036 	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3037 					X86_TRANSFER_TASK_SWITCH, NULL);
3038 	if (ret != X86EMUL_CONTINUE)
3039 		return ret;
3040 	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3041 					X86_TRANSFER_TASK_SWITCH, NULL);
3042 	if (ret != X86EMUL_CONTINUE)
3043 		return ret;
3044 	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3045 					X86_TRANSFER_TASK_SWITCH, NULL);
3046 	if (ret != X86EMUL_CONTINUE)
3047 		return ret;
3048 
3049 	return X86EMUL_CONTINUE;
3050 }
3051 
3052 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
3053 			  u16 tss_selector, u16 old_tss_sel,
3054 			  ulong old_tss_base, struct desc_struct *new_desc)
3055 {
3056 	const struct x86_emulate_ops *ops = ctxt->ops;
3057 	struct tss_segment_16 tss_seg;
3058 	int ret;
3059 	u32 new_tss_base = get_desc_base(new_desc);
3060 
3061 	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3062 			    &ctxt->exception);
3063 	if (ret != X86EMUL_CONTINUE)
3064 		return ret;
3065 
3066 	save_state_to_tss16(ctxt, &tss_seg);
3067 
3068 	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3069 			     &ctxt->exception);
3070 	if (ret != X86EMUL_CONTINUE)
3071 		return ret;
3072 
3073 	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3074 			    &ctxt->exception);
3075 	if (ret != X86EMUL_CONTINUE)
3076 		return ret;
3077 
3078 	if (old_tss_sel != 0xffff) {
3079 		tss_seg.prev_task_link = old_tss_sel;
3080 
3081 		ret = ops->write_std(ctxt, new_tss_base,
3082 				     &tss_seg.prev_task_link,
3083 				     sizeof tss_seg.prev_task_link,
3084 				     &ctxt->exception);
3085 		if (ret != X86EMUL_CONTINUE)
3086 			return ret;
3087 	}
3088 
3089 	return load_state_from_tss16(ctxt, &tss_seg);
3090 }
3091 
3092 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
3093 				struct tss_segment_32 *tss)
3094 {
3095 	/* CR3 and ldt selector are not saved intentionally */
3096 	tss->eip = ctxt->_eip;
3097 	tss->eflags = ctxt->eflags;
3098 	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
3099 	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
3100 	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
3101 	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
3102 	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
3103 	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
3104 	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
3105 	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
3106 
3107 	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
3108 	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
3109 	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
3110 	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
3111 	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
3112 	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
3113 }
3114 
3115 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
3116 				 struct tss_segment_32 *tss)
3117 {
3118 	int ret;
3119 	u8 cpl;
3120 
3121 	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
3122 		return emulate_gp(ctxt, 0);
3123 	ctxt->_eip = tss->eip;
3124 	ctxt->eflags = tss->eflags | 2;
3125 
3126 	/* General purpose registers */
3127 	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
3128 	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
3129 	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
3130 	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
3131 	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
3132 	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
3133 	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
3134 	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
3135 
3136 	/*
3137 	 * SDM says that segment selectors are loaded before segment
3138 	 * descriptors.  This is important because CPL checks will
3139 	 * use CS.RPL.
3140 	 */
3141 	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
3142 	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
3143 	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
3144 	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
3145 	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3146 	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
3147 	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
3148 
3149 	/*
3150 	 * If we're switching between Protected Mode and VM86, we need to make
3151 	 * sure to update the mode before loading the segment descriptors so
3152 	 * that the selectors are interpreted correctly.
3153 	 */
3154 	if (ctxt->eflags & X86_EFLAGS_VM) {
3155 		ctxt->mode = X86EMUL_MODE_VM86;
3156 		cpl = 3;
3157 	} else {
3158 		ctxt->mode = X86EMUL_MODE_PROT32;
3159 		cpl = tss->cs & 3;
3160 	}
3161 
3162 	/*
3163 	 * Now load segment descriptors. If fault happenes at this stage
3164 	 * it is handled in a context of new task
3165 	 */
3166 	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3167 					cpl, X86_TRANSFER_TASK_SWITCH, NULL);
3168 	if (ret != X86EMUL_CONTINUE)
3169 		return ret;
3170 	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3171 					X86_TRANSFER_TASK_SWITCH, NULL);
3172 	if (ret != X86EMUL_CONTINUE)
3173 		return ret;
3174 	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3175 					X86_TRANSFER_TASK_SWITCH, NULL);
3176 	if (ret != X86EMUL_CONTINUE)
3177 		return ret;
3178 	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3179 					X86_TRANSFER_TASK_SWITCH, NULL);
3180 	if (ret != X86EMUL_CONTINUE)
3181 		return ret;
3182 	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3183 					X86_TRANSFER_TASK_SWITCH, NULL);
3184 	if (ret != X86EMUL_CONTINUE)
3185 		return ret;
3186 	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3187 					X86_TRANSFER_TASK_SWITCH, NULL);
3188 	if (ret != X86EMUL_CONTINUE)
3189 		return ret;
3190 	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3191 					X86_TRANSFER_TASK_SWITCH, NULL);
3192 
3193 	return ret;
3194 }
3195 
3196 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
3197 			  u16 tss_selector, u16 old_tss_sel,
3198 			  ulong old_tss_base, struct desc_struct *new_desc)
3199 {
3200 	const struct x86_emulate_ops *ops = ctxt->ops;
3201 	struct tss_segment_32 tss_seg;
3202 	int ret;
3203 	u32 new_tss_base = get_desc_base(new_desc);
3204 	u32 eip_offset = offsetof(struct tss_segment_32, eip);
3205 	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
3206 
3207 	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3208 			    &ctxt->exception);
3209 	if (ret != X86EMUL_CONTINUE)
3210 		return ret;
3211 
3212 	save_state_to_tss32(ctxt, &tss_seg);
3213 
3214 	/* Only GP registers and segment selectors are saved */
3215 	ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
3216 			     ldt_sel_offset - eip_offset, &ctxt->exception);
3217 	if (ret != X86EMUL_CONTINUE)
3218 		return ret;
3219 
3220 	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3221 			    &ctxt->exception);
3222 	if (ret != X86EMUL_CONTINUE)
3223 		return ret;
3224 
3225 	if (old_tss_sel != 0xffff) {
3226 		tss_seg.prev_task_link = old_tss_sel;
3227 
3228 		ret = ops->write_std(ctxt, new_tss_base,
3229 				     &tss_seg.prev_task_link,
3230 				     sizeof tss_seg.prev_task_link,
3231 				     &ctxt->exception);
3232 		if (ret != X86EMUL_CONTINUE)
3233 			return ret;
3234 	}
3235 
3236 	return load_state_from_tss32(ctxt, &tss_seg);
3237 }
3238 
3239 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
3240 				   u16 tss_selector, int idt_index, int reason,
3241 				   bool has_error_code, u32 error_code)
3242 {
3243 	const struct x86_emulate_ops *ops = ctxt->ops;
3244 	struct desc_struct curr_tss_desc, next_tss_desc;
3245 	int ret;
3246 	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
3247 	ulong old_tss_base =
3248 		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
3249 	u32 desc_limit;
3250 	ulong desc_addr, dr7;
3251 
3252 	/* FIXME: old_tss_base == ~0 ? */
3253 
3254 	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
3255 	if (ret != X86EMUL_CONTINUE)
3256 		return ret;
3257 	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
3258 	if (ret != X86EMUL_CONTINUE)
3259 		return ret;
3260 
3261 	/* FIXME: check that next_tss_desc is tss */
3262 
3263 	/*
3264 	 * Check privileges. The three cases are task switch caused by...
3265 	 *
3266 	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
3267 	 * 2. Exception/IRQ/iret: No check is performed
3268 	 * 3. jmp/call to TSS/task-gate: No check is performed since the
3269 	 *    hardware checks it before exiting.
3270 	 */
3271 	if (reason == TASK_SWITCH_GATE) {
3272 		if (idt_index != -1) {
3273 			/* Software interrupts */
3274 			struct desc_struct task_gate_desc;
3275 			int dpl;
3276 
3277 			ret = read_interrupt_descriptor(ctxt, idt_index,
3278 							&task_gate_desc);
3279 			if (ret != X86EMUL_CONTINUE)
3280 				return ret;
3281 
3282 			dpl = task_gate_desc.dpl;
3283 			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
3284 				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
3285 		}
3286 	}
3287 
3288 	desc_limit = desc_limit_scaled(&next_tss_desc);
3289 	if (!next_tss_desc.p ||
3290 	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
3291 	     desc_limit < 0x2b)) {
3292 		return emulate_ts(ctxt, tss_selector & 0xfffc);
3293 	}
3294 
3295 	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3296 		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
3297 		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
3298 	}
3299 
3300 	if (reason == TASK_SWITCH_IRET)
3301 		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
3302 
3303 	/* set back link to prev task only if NT bit is set in eflags
3304 	   note that old_tss_sel is not used after this point */
3305 	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
3306 		old_tss_sel = 0xffff;
3307 
3308 	if (next_tss_desc.type & 8)
3309 		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
3310 				     old_tss_base, &next_tss_desc);
3311 	else
3312 		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
3313 				     old_tss_base, &next_tss_desc);
3314 	if (ret != X86EMUL_CONTINUE)
3315 		return ret;
3316 
3317 	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
3318 		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
3319 
3320 	if (reason != TASK_SWITCH_IRET) {
3321 		next_tss_desc.type |= (1 << 1); /* set busy flag */
3322 		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
3323 	}
3324 
3325 	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
3326 	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
3327 
3328 	if (has_error_code) {
3329 		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
3330 		ctxt->lock_prefix = 0;
3331 		ctxt->src.val = (unsigned long) error_code;
3332 		ret = em_push(ctxt);
3333 	}
3334 
3335 	ops->get_dr(ctxt, 7, &dr7);
3336 	ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));
3337 
3338 	return ret;
3339 }
3340 
3341 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
3342 			 u16 tss_selector, int idt_index, int reason,
3343 			 bool has_error_code, u32 error_code)
3344 {
3345 	int rc;
3346 
3347 	invalidate_registers(ctxt);
3348 	ctxt->_eip = ctxt->eip;
3349 	ctxt->dst.type = OP_NONE;
3350 
3351 	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3352 				     has_error_code, error_code);
3353 
3354 	if (rc == X86EMUL_CONTINUE) {
3355 		ctxt->eip = ctxt->_eip;
3356 		writeback_registers(ctxt);
3357 	}
3358 
3359 	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3360 }
3361 
3362 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
3363 		struct operand *op)
3364 {
3365 	int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3366 
3367 	register_address_increment(ctxt, reg, df * op->bytes);
3368 	op->addr.mem.ea = register_address(ctxt, reg);
3369 }
3370 
3371 static int em_das(struct x86_emulate_ctxt *ctxt)
3372 {
3373 	u8 al, old_al;
3374 	bool af, cf, old_cf;
3375 
3376 	cf = ctxt->eflags & X86_EFLAGS_CF;
3377 	al = ctxt->dst.val;
3378 
3379 	old_al = al;
3380 	old_cf = cf;
3381 	cf = false;
3382 	af = ctxt->eflags & X86_EFLAGS_AF;
3383 	if ((al & 0x0f) > 9 || af) {
3384 		al -= 6;
3385 		cf = old_cf | (al >= 250);
3386 		af = true;
3387 	} else {
3388 		af = false;
3389 	}
3390 	if (old_al > 0x99 || old_cf) {
3391 		al -= 0x60;
3392 		cf = true;
3393 	}
3394 
3395 	ctxt->dst.val = al;
3396 	/* Set PF, ZF, SF */
3397 	ctxt->src.type = OP_IMM;
3398 	ctxt->src.val = 0;
3399 	ctxt->src.bytes = 1;
3400 	fastop(ctxt, em_or);
3401 	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
3402 	if (cf)
3403 		ctxt->eflags |= X86_EFLAGS_CF;
3404 	if (af)
3405 		ctxt->eflags |= X86_EFLAGS_AF;
3406 	return X86EMUL_CONTINUE;
3407 }
3408 
3409 static int em_aam(struct x86_emulate_ctxt *ctxt)
3410 {
3411 	u8 al, ah;
3412 
3413 	if (ctxt->src.val == 0)
3414 		return emulate_de(ctxt);
3415 
3416 	al = ctxt->dst.val & 0xff;
3417 	ah = al / ctxt->src.val;
3418 	al %= ctxt->src.val;
3419 
3420 	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);
3421 
3422 	/* Set PF, ZF, SF */
3423 	ctxt->src.type = OP_IMM;
3424 	ctxt->src.val = 0;
3425 	ctxt->src.bytes = 1;
3426 	fastop(ctxt, em_or);
3427 
3428 	return X86EMUL_CONTINUE;
3429 }
3430 
3431 static int em_aad(struct x86_emulate_ctxt *ctxt)
3432 {
3433 	u8 al = ctxt->dst.val & 0xff;
3434 	u8 ah = (ctxt->dst.val >> 8) & 0xff;
3435 
3436 	al = (al + (ah * ctxt->src.val)) & 0xff;
3437 
3438 	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;
3439 
3440 	/* Set PF, ZF, SF */
3441 	ctxt->src.type = OP_IMM;
3442 	ctxt->src.val = 0;
3443 	ctxt->src.bytes = 1;
3444 	fastop(ctxt, em_or);
3445 
3446 	return X86EMUL_CONTINUE;
3447 }
3448 
3449 static int em_call(struct x86_emulate_ctxt *ctxt)
3450 {
3451 	int rc;
3452 	long rel = ctxt->src.val;
3453 
3454 	ctxt->src.val = (unsigned long)ctxt->_eip;
3455 	rc = jmp_rel(ctxt, rel);
3456 	if (rc != X86EMUL_CONTINUE)
3457 		return rc;
3458 	return em_push(ctxt);
3459 }
3460 
3461 static int em_call_far(struct x86_emulate_ctxt *ctxt)
3462 {
3463 	u16 sel, old_cs;
3464 	ulong old_eip;
3465 	int rc;
3466 	struct desc_struct old_desc, new_desc;
3467 	const struct x86_emulate_ops *ops = ctxt->ops;
3468 	int cpl = ctxt->ops->cpl(ctxt);
3469 	enum x86emul_mode prev_mode = ctxt->mode;
3470 
3471 	old_eip = ctxt->_eip;
3472 	ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3473 
3474 	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3475 	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
3476 				       X86_TRANSFER_CALL_JMP, &new_desc);
3477 	if (rc != X86EMUL_CONTINUE)
3478 		return rc;
3479 
3480 	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3481 	if (rc != X86EMUL_CONTINUE)
3482 		goto fail;
3483 
3484 	ctxt->src.val = old_cs;
3485 	rc = em_push(ctxt);
3486 	if (rc != X86EMUL_CONTINUE)
3487 		goto fail;
3488 
3489 	ctxt->src.val = old_eip;
3490 	rc = em_push(ctxt);
3491 	/* If we failed, we tainted the memory, but the very least we should
3492 	   restore cs */
3493 	if (rc != X86EMUL_CONTINUE) {
3494 		pr_warn_once("faulting far call emulation tainted memory\n");
3495 		goto fail;
3496 	}
3497 	return rc;
3498 fail:
3499 	ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3500 	ctxt->mode = prev_mode;
3501 	return rc;
3502 
3503 }
3504 
3505 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
3506 {
3507 	int rc;
3508 	unsigned long eip;
3509 
3510 	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
3511 	if (rc != X86EMUL_CONTINUE)
3512 		return rc;
3513 	rc = assign_eip_near(ctxt, eip);
3514 	if (rc != X86EMUL_CONTINUE)
3515 		return rc;
3516 	rsp_increment(ctxt, ctxt->src.val);
3517 	return X86EMUL_CONTINUE;
3518 }
3519 
3520 static int em_xchg(struct x86_emulate_ctxt *ctxt)
3521 {
3522 	/* Write back the register source. */
3523 	ctxt->src.val = ctxt->dst.val;
3524 	write_register_operand(&ctxt->src);
3525 
3526 	/* Write back the memory destination with implicit LOCK prefix. */
3527 	ctxt->dst.val = ctxt->src.orig_val;
3528 	ctxt->lock_prefix = 1;
3529 	return X86EMUL_CONTINUE;
3530 }
3531 
3532 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
3533 {
3534 	ctxt->dst.val = ctxt->src2.val;
3535 	return fastop(ctxt, em_imul);
3536 }
3537 
3538 static int em_cwd(struct x86_emulate_ctxt *ctxt)
3539 {
3540 	ctxt->dst.type = OP_REG;
3541 	ctxt->dst.bytes = ctxt->src.bytes;
3542 	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3543 	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3544 
3545 	return X86EMUL_CONTINUE;
3546 }
3547 
3548 static int em_rdpid(struct x86_emulate_ctxt *ctxt)
3549 {
3550 	u64 tsc_aux = 0;
3551 
3552 	if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
3553 		return emulate_gp(ctxt, 0);
3554 	ctxt->dst.val = tsc_aux;
3555 	return X86EMUL_CONTINUE;
3556 }
3557 
3558 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
3559 {
3560 	u64 tsc = 0;
3561 
3562 	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3563 	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
3564 	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3565 	return X86EMUL_CONTINUE;
3566 }
3567 
3568 static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
3569 {
3570 	u64 pmc;
3571 
3572 	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3573 		return emulate_gp(ctxt, 0);
3574 	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
3575 	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3576 	return X86EMUL_CONTINUE;
3577 }
3578 
3579 static int em_mov(struct x86_emulate_ctxt *ctxt)
3580 {
3581 	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3582 	return X86EMUL_CONTINUE;
3583 }
3584 
3585 #define FFL(x) bit(X86_FEATURE_##x)
3586 
3587 static int em_movbe(struct x86_emulate_ctxt *ctxt)
3588 {
3589 	u32 ebx, ecx, edx, eax = 1;
3590 	u16 tmp;
3591 
3592 	/*
3593 	 * Check MOVBE is set in the guest-visible CPUID leaf.
3594 	 */
3595 	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
3596 	if (!(ecx & FFL(MOVBE)))
3597 		return emulate_ud(ctxt);
3598 
3599 	switch (ctxt->op_bytes) {
3600 	case 2:
3601 		/*
3602 		 * From MOVBE definition: "...When the operand size is 16 bits,
3603 		 * the upper word of the destination register remains unchanged
3604 		 * ..."
3605 		 *
3606 		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
3607 		 * rules so we have to do the operation almost per hand.
3608 		 */
3609 		tmp = (u16)ctxt->src.val;
3610 		ctxt->dst.val &= ~0xffffUL;
3611 		ctxt->dst.val |= (unsigned long)swab16(tmp);
3612 		break;
3613 	case 4:
3614 		ctxt->dst.val = swab32((u32)ctxt->src.val);
3615 		break;
3616 	case 8:
3617 		ctxt->dst.val = swab64(ctxt->src.val);
3618 		break;
3619 	default:
3620 		BUG();
3621 	}
3622 	return X86EMUL_CONTINUE;
3623 }
3624 
3625 static int em_cr_write(struct x86_emulate_ctxt *ctxt)
3626 {
3627 	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
3628 		return emulate_gp(ctxt, 0);
3629 
3630 	/* Disable writeback. */
3631 	ctxt->dst.type = OP_NONE;
3632 	return X86EMUL_CONTINUE;
3633 }
3634 
3635 static int em_dr_write(struct x86_emulate_ctxt *ctxt)
3636 {
3637 	unsigned long val;
3638 
3639 	if (ctxt->mode == X86EMUL_MODE_PROT64)
3640 		val = ctxt->src.val & ~0ULL;
3641 	else
3642 		val = ctxt->src.val & ~0U;
3643 
3644 	/* #UD condition is already handled. */
3645 	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
3646 		return emulate_gp(ctxt, 0);
3647 
3648 	/* Disable writeback. */
3649 	ctxt->dst.type = OP_NONE;
3650 	return X86EMUL_CONTINUE;
3651 }
3652 
3653 static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
3654 {
3655 	u64 msr_data;
3656 
3657 	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
3658 		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
3659 	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3660 		return emulate_gp(ctxt, 0);
3661 
3662 	return X86EMUL_CONTINUE;
3663 }
3664 
3665 static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
3666 {
3667 	u64 msr_data;
3668 
3669 	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3670 		return emulate_gp(ctxt, 0);
3671 
3672 	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
3673 	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3674 	return X86EMUL_CONTINUE;
3675 }
3676 
3677 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
3678 {
3679 	if (segment > VCPU_SREG_GS &&
3680 	    (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3681 	    ctxt->ops->cpl(ctxt) > 0)
3682 		return emulate_gp(ctxt, 0);
3683 
3684 	ctxt->dst.val = get_segment_selector(ctxt, segment);
3685 	if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
3686 		ctxt->dst.bytes = 2;
3687 	return X86EMUL_CONTINUE;
3688 }
3689 
3690 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
3691 {
3692 	if (ctxt->modrm_reg > VCPU_SREG_GS)
3693 		return emulate_ud(ctxt);
3694 
3695 	return em_store_sreg(ctxt, ctxt->modrm_reg);
3696 }
3697 
3698 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
3699 {
3700 	u16 sel = ctxt->src.val;
3701 
3702 	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3703 		return emulate_ud(ctxt);
3704 
3705 	if (ctxt->modrm_reg == VCPU_SREG_SS)
3706 		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3707 
3708 	/* Disable writeback. */
3709 	ctxt->dst.type = OP_NONE;
3710 	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3711 }
3712 
3713 static int em_sldt(struct x86_emulate_ctxt *ctxt)
3714 {
3715 	return em_store_sreg(ctxt, VCPU_SREG_LDTR);
3716 }
3717 
3718 static int em_lldt(struct x86_emulate_ctxt *ctxt)
3719 {
3720 	u16 sel = ctxt->src.val;
3721 
3722 	/* Disable writeback. */
3723 	ctxt->dst.type = OP_NONE;
3724 	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
3725 }
3726 
3727 static int em_str(struct x86_emulate_ctxt *ctxt)
3728 {
3729 	return em_store_sreg(ctxt, VCPU_SREG_TR);
3730 }
3731 
3732 static int em_ltr(struct x86_emulate_ctxt *ctxt)
3733 {
3734 	u16 sel = ctxt->src.val;
3735 
3736 	/* Disable writeback. */
3737 	ctxt->dst.type = OP_NONE;
3738 	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
3739 }
3740 
3741 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
3742 {
3743 	int rc;
3744 	ulong linear;
3745 
3746 	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3747 	if (rc == X86EMUL_CONTINUE)
3748 		ctxt->ops->invlpg(ctxt, linear);
3749 	/* Disable writeback. */
3750 	ctxt->dst.type = OP_NONE;
3751 	return X86EMUL_CONTINUE;
3752 }
3753 
3754 static int em_clts(struct x86_emulate_ctxt *ctxt)
3755 {
3756 	ulong cr0;
3757 
3758 	cr0 = ctxt->ops->get_cr(ctxt, 0);
3759 	cr0 &= ~X86_CR0_TS;
3760 	ctxt->ops->set_cr(ctxt, 0, cr0);
3761 	return X86EMUL_CONTINUE;
3762 }
3763 
3764 static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3765 {
3766 	int rc = ctxt->ops->fix_hypercall(ctxt);
3767 
3768 	if (rc != X86EMUL_CONTINUE)
3769 		return rc;
3770 
3771 	/* Let the processor re-execute the fixed hypercall */
3772 	ctxt->_eip = ctxt->eip;
3773 	/* Disable writeback. */
3774 	ctxt->dst.type = OP_NONE;
3775 	return X86EMUL_CONTINUE;
3776 }
3777 
3778 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
3779 				  void (*get)(struct x86_emulate_ctxt *ctxt,
3780 					      struct desc_ptr *ptr))
3781 {
3782 	struct desc_ptr desc_ptr;
3783 
3784 	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3785 	    ctxt->ops->cpl(ctxt) > 0)
3786 		return emulate_gp(ctxt, 0);
3787 
3788 	if (ctxt->mode == X86EMUL_MODE_PROT64)
3789 		ctxt->op_bytes = 8;
3790 	get(ctxt, &desc_ptr);
3791 	if (ctxt->op_bytes == 2) {
3792 		ctxt->op_bytes = 4;
3793 		desc_ptr.address &= 0x00ffffff;
3794 	}
3795 	/* Disable writeback. */
3796 	ctxt->dst.type = OP_NONE;
3797 	return segmented_write_std(ctxt, ctxt->dst.addr.mem,
3798 				   &desc_ptr, 2 + ctxt->op_bytes);
3799 }
3800 
3801 static int em_sgdt(struct x86_emulate_ctxt *ctxt)
3802 {
3803 	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
3804 }
3805 
3806 static int em_sidt(struct x86_emulate_ctxt *ctxt)
3807 {
3808 	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
3809 }
3810 
3811 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3812 {
3813 	struct desc_ptr desc_ptr;
3814 	int rc;
3815 
3816 	if (ctxt->mode == X86EMUL_MODE_PROT64)
3817 		ctxt->op_bytes = 8;
3818 	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3819 			     &desc_ptr.size, &desc_ptr.address,
3820 			     ctxt->op_bytes);
3821 	if (rc != X86EMUL_CONTINUE)
3822 		return rc;
3823 	if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3824 	    emul_is_noncanonical_address(desc_ptr.address, ctxt))
3825 		return emulate_gp(ctxt, 0);
3826 	if (lgdt)
3827 		ctxt->ops->set_gdt(ctxt, &desc_ptr);
3828 	else
3829 		ctxt->ops->set_idt(ctxt, &desc_ptr);
3830 	/* Disable writeback. */
3831 	ctxt->dst.type = OP_NONE;
3832 	return X86EMUL_CONTINUE;
3833 }
3834 
3835 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
3836 {
3837 	return em_lgdt_lidt(ctxt, true);
3838 }
3839 
3840 static int em_lidt(struct x86_emulate_ctxt *ctxt)
3841 {
3842 	return em_lgdt_lidt(ctxt, false);
3843 }
3844 
3845 static int em_smsw(struct x86_emulate_ctxt *ctxt)
3846 {
3847 	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
3848 	    ctxt->ops->cpl(ctxt) > 0)
3849 		return emulate_gp(ctxt, 0);
3850 
3851 	if (ctxt->dst.type == OP_MEM)
3852 		ctxt->dst.bytes = 2;
3853 	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3854 	return X86EMUL_CONTINUE;
3855 }
3856 
3857 static int em_lmsw(struct x86_emulate_ctxt *ctxt)
3858 {
3859 	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3860 			  | (ctxt->src.val & 0x0f));
3861 	ctxt->dst.type = OP_NONE;
3862 	return X86EMUL_CONTINUE;
3863 }
3864 
3865 static int em_loop(struct x86_emulate_ctxt *ctxt)
3866 {
3867 	int rc = X86EMUL_CONTINUE;
3868 
3869 	register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3870 	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3871 	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3872 		rc = jmp_rel(ctxt, ctxt->src.val);
3873 
3874 	return rc;
3875 }
3876 
3877 static int em_jcxz(struct x86_emulate_ctxt *ctxt)
3878 {
3879 	int rc = X86EMUL_CONTINUE;
3880 
3881 	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3882 		rc = jmp_rel(ctxt, ctxt->src.val);
3883 
3884 	return rc;
3885 }
3886 
3887 static int em_in(struct x86_emulate_ctxt *ctxt)
3888 {
3889 	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
3890 			     &ctxt->dst.val))
3891 		return X86EMUL_IO_NEEDED;
3892 
3893 	return X86EMUL_CONTINUE;
3894 }
3895 
3896 static int em_out(struct x86_emulate_ctxt *ctxt)
3897 {
3898 	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
3899 				    &ctxt->src.val, 1);
3900 	/* Disable writeback. */
3901 	ctxt->dst.type = OP_NONE;
3902 	return X86EMUL_CONTINUE;
3903 }
3904 
3905 static int em_cli(struct x86_emulate_ctxt *ctxt)
3906 {
3907 	if (emulator_bad_iopl(ctxt))
3908 		return emulate_gp(ctxt, 0);
3909 
3910 	ctxt->eflags &= ~X86_EFLAGS_IF;
3911 	return X86EMUL_CONTINUE;
3912 }
3913 
3914 static int em_sti(struct x86_emulate_ctxt *ctxt)
3915 {
3916 	if (emulator_bad_iopl(ctxt))
3917 		return emulate_gp(ctxt, 0);
3918 
3919 	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3920 	ctxt->eflags |= X86_EFLAGS_IF;
3921 	return X86EMUL_CONTINUE;
3922 }
3923 
3924 static int em_cpuid(struct x86_emulate_ctxt *ctxt)
3925 {
3926 	u32 eax, ebx, ecx, edx;
3927 	u64 msr = 0;
3928 
3929 	ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
3930 	if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3931 	    ctxt->ops->cpl(ctxt)) {
3932 		return emulate_gp(ctxt, 0);
3933 	}
3934 
3935 	eax = reg_read(ctxt, VCPU_REGS_RAX);
3936 	ecx = reg_read(ctxt, VCPU_REGS_RCX);
3937 	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
3938 	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
3939 	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
3940 	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
3941 	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
3942 	return X86EMUL_CONTINUE;
3943 }
3944 
3945 static int em_sahf(struct x86_emulate_ctxt *ctxt)
3946 {
3947 	u32 flags;
3948 
3949 	flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
3950 		X86_EFLAGS_SF;
3951 	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;
3952 
3953 	ctxt->eflags &= ~0xffUL;
3954 	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
3955 	return X86EMUL_CONTINUE;
3956 }
3957 
3958 static int em_lahf(struct x86_emulate_ctxt *ctxt)
3959 {
3960 	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
3961 	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
3962 	return X86EMUL_CONTINUE;
3963 }
3964 
3965 static int em_bswap(struct x86_emulate_ctxt *ctxt)
3966 {
3967 	switch (ctxt->op_bytes) {
3968 #ifdef CONFIG_X86_64
3969 	case 8:
3970 		asm("bswap %0" : "+r"(ctxt->dst.val));
3971 		break;
3972 #endif
3973 	default:
3974 		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
3975 		break;
3976 	}
3977 	return X86EMUL_CONTINUE;
3978 }
3979 
3980 static int em_clflush(struct x86_emulate_ctxt *ctxt)
3981 {
3982 	/* emulating clflush regardless of cpuid */
3983 	return X86EMUL_CONTINUE;
3984 }
3985 
3986 static int em_movsxd(struct x86_emulate_ctxt *ctxt)
3987 {
3988 	ctxt->dst.val = (s32) ctxt->src.val;
3989 	return X86EMUL_CONTINUE;
3990 }
3991 
3992 static int check_fxsr(struct x86_emulate_ctxt *ctxt)
3993 {
3994 	u32 eax = 1, ebx, ecx = 0, edx;
3995 
3996 	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
3997 	if (!(edx & FFL(FXSR)))
3998 		return emulate_ud(ctxt);
3999 
4000 	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
4001 		return emulate_nm(ctxt);
4002 
4003 	/*
4004 	 * Don't emulate a case that should never be hit, instead of working
4005 	 * around a lack of fxsave64/fxrstor64 on old compilers.
4006 	 */
4007 	if (ctxt->mode >= X86EMUL_MODE_PROT64)
4008 		return X86EMUL_UNHANDLEABLE;
4009 
4010 	return X86EMUL_CONTINUE;
4011 }
4012 
4013 /*
4014  * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
4015  * and restore MXCSR.
4016  */
4017 static size_t __fxstate_size(int nregs)
4018 {
4019 	return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
4020 }
4021 
4022 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
4023 {
4024 	bool cr4_osfxsr;
4025 	if (ctxt->mode == X86EMUL_MODE_PROT64)
4026 		return __fxstate_size(16);
4027 
4028 	cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
4029 	return __fxstate_size(cr4_osfxsr ? 8 : 0);
4030 }
4031 
4032 /*
4033  * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
4034  *  1) 16 bit mode
4035  *  2) 32 bit mode
4036  *     - like (1), but FIP and FDP (foo) are only 16 bit.  At least Intel CPUs
4037  *       preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
4038  *       save and restore
4039  *  3) 64-bit mode with REX.W prefix
4040  *     - like (2), but XMM 8-15 are being saved and restored
4041  *  4) 64-bit mode without REX.W prefix
4042  *     - like (3), but FIP and FDP are 64 bit
4043  *
4044  * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
4045  * desired result.  (4) is not emulated.
4046  *
4047  * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
4048  * and FPU DS) should match.
4049  */
4050 static int em_fxsave(struct x86_emulate_ctxt *ctxt)
4051 {
4052 	struct fxregs_state fx_state;
4053 	int rc;
4054 
4055 	rc = check_fxsr(ctxt);
4056 	if (rc != X86EMUL_CONTINUE)
4057 		return rc;
4058 
4059 	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));
4060 
4061 	if (rc != X86EMUL_CONTINUE)
4062 		return rc;
4063 
4064 	return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
4065 		                   fxstate_size(ctxt));
4066 }
4067 
4068 /*
4069  * FXRSTOR might restore XMM registers not provided by the guest. Fill
4070  * in the host registers (via FXSAVE) instead, so they won't be modified.
4071  * (preemption has to stay disabled until FXRSTOR).
4072  *
4073  * Use noinline to keep the stack for other functions called by callers small.
4074  */
4075 static noinline int fxregs_fixup(struct fxregs_state *fx_state,
4076 				 const size_t used_size)
4077 {
4078 	struct fxregs_state fx_tmp;
4079 	int rc;
4080 
4081 	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
4082 	memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
4083 	       __fxstate_size(16) - used_size);
4084 
4085 	return rc;
4086 }
4087 
4088 static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
4089 {
4090 	struct fxregs_state fx_state;
4091 	int rc;
4092 	size_t size;
4093 
4094 	rc = check_fxsr(ctxt);
4095 	if (rc != X86EMUL_CONTINUE)
4096 		return rc;
4097 
4098 	size = fxstate_size(ctxt);
4099 	rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
4100 	if (rc != X86EMUL_CONTINUE)
4101 		return rc;
4102 
4103 	if (size < __fxstate_size(16)) {
4104 		rc = fxregs_fixup(&fx_state, size);
4105 		if (rc != X86EMUL_CONTINUE)
4106 			goto out;
4107 	}
4108 
4109 	if (fx_state.mxcsr >> 16) {
4110 		rc = emulate_gp(ctxt, 0);
4111 		goto out;
4112 	}
4113 
4114 	if (rc == X86EMUL_CONTINUE)
4115 		rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));
4116 
4117 out:
4118 	return rc;
4119 }
4120 
4121 static bool valid_cr(int nr)
4122 {
4123 	switch (nr) {
4124 	case 0:
4125 	case 2 ... 4:
4126 	case 8:
4127 		return true;
4128 	default:
4129 		return false;
4130 	}
4131 }
4132 
4133 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
4134 {
4135 	if (!valid_cr(ctxt->modrm_reg))
4136 		return emulate_ud(ctxt);
4137 
4138 	return X86EMUL_CONTINUE;
4139 }
4140 
4141 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
4142 {
4143 	u64 new_val = ctxt->src.val64;
4144 	int cr = ctxt->modrm_reg;
4145 	u64 efer = 0;
4146 
4147 	static u64 cr_reserved_bits[] = {
4148 		0xffffffff00000000ULL,
4149 		0, 0, 0, /* CR3 checked later */
4150 		CR4_RESERVED_BITS,
4151 		0, 0, 0,
4152 		CR8_RESERVED_BITS,
4153 	};
4154 
4155 	if (!valid_cr(cr))
4156 		return emulate_ud(ctxt);
4157 
4158 	if (new_val & cr_reserved_bits[cr])
4159 		return emulate_gp(ctxt, 0);
4160 
4161 	switch (cr) {
4162 	case 0: {
4163 		u64 cr4;
4164 		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
4165 		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
4166 			return emulate_gp(ctxt, 0);
4167 
4168 		cr4 = ctxt->ops->get_cr(ctxt, 4);
4169 		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4170 
4171 		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
4172 		    !(cr4 & X86_CR4_PAE))
4173 			return emulate_gp(ctxt, 0);
4174 
4175 		break;
4176 		}
4177 	case 3: {
4178 		u64 rsvd = 0;
4179 
4180 		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4181 		if (efer & EFER_LMA) {
4182 			u64 maxphyaddr;
4183 			u32 eax, ebx, ecx, edx;
4184 
4185 			eax = 0x80000008;
4186 			ecx = 0;
4187 			if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
4188 						 &edx, false))
4189 				maxphyaddr = eax & 0xff;
4190 			else
4191 				maxphyaddr = 36;
4192 			rsvd = rsvd_bits(maxphyaddr, 62);
4193 		}
4194 
4195 		if (new_val & rsvd)
4196 			return emulate_gp(ctxt, 0);
4197 
4198 		break;
4199 		}
4200 	case 4: {
4201 		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4202 
4203 		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
4204 			return emulate_gp(ctxt, 0);
4205 
4206 		break;
4207 		}
4208 	}
4209 
4210 	return X86EMUL_CONTINUE;
4211 }
4212 
4213 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
4214 {
4215 	unsigned long dr7;
4216 
4217 	ctxt->ops->get_dr(ctxt, 7, &dr7);
4218 
4219 	/* Check if DR7.Global_Enable is set */
4220 	return dr7 & (1 << 13);
4221 }
4222 
4223 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
4224 {
4225 	int dr = ctxt->modrm_reg;
4226 	u64 cr4;
4227 
4228 	if (dr > 7)
4229 		return emulate_ud(ctxt);
4230 
4231 	cr4 = ctxt->ops->get_cr(ctxt, 4);
4232 	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
4233 		return emulate_ud(ctxt);
4234 
4235 	if (check_dr7_gd(ctxt)) {
4236 		ulong dr6;
4237 
4238 		ctxt->ops->get_dr(ctxt, 6, &dr6);
4239 		dr6 &= ~15;
4240 		dr6 |= DR6_BD | DR6_RTM;
4241 		ctxt->ops->set_dr(ctxt, 6, dr6);
4242 		return emulate_db(ctxt);
4243 	}
4244 
4245 	return X86EMUL_CONTINUE;
4246 }
4247 
4248 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
4249 {
4250 	u64 new_val = ctxt->src.val64;
4251 	int dr = ctxt->modrm_reg;
4252 
4253 	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
4254 		return emulate_gp(ctxt, 0);
4255 
4256 	return check_dr_read(ctxt);
4257 }
4258 
4259 static int check_svme(struct x86_emulate_ctxt *ctxt)
4260 {
4261 	u64 efer = 0;
4262 
4263 	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4264 
4265 	if (!(efer & EFER_SVME))
4266 		return emulate_ud(ctxt);
4267 
4268 	return X86EMUL_CONTINUE;
4269 }
4270 
4271 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
4272 {
4273 	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
4274 
4275 	/* Valid physical address? */
4276 	if (rax & 0xffff000000000000ULL)
4277 		return emulate_gp(ctxt, 0);
4278 
4279 	return check_svme(ctxt);
4280 }
4281 
4282 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
4283 {
4284 	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4285 
4286 	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
4287 		return emulate_ud(ctxt);
4288 
4289 	return X86EMUL_CONTINUE;
4290 }
4291 
4292 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
4293 {
4294 	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4295 	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
4296 
4297 	/*
4298 	 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
4299 	 * in Ring3 when CR4.PCE=0.
4300 	 */
4301 	if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
4302 		return X86EMUL_CONTINUE;
4303 
4304 	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
4305 	    ctxt->ops->check_pmc(ctxt, rcx))
4306 		return emulate_gp(ctxt, 0);
4307 
4308 	return X86EMUL_CONTINUE;
4309 }
4310 
4311 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
4312 {
4313 	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
4314 	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
4315 		return emulate_gp(ctxt, 0);
4316 
4317 	return X86EMUL_CONTINUE;
4318 }
4319 
4320 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
4321 {
4322 	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
4323 	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
4324 		return emulate_gp(ctxt, 0);
4325 
4326 	return X86EMUL_CONTINUE;
4327 }
4328 
4329 #define D(_y) { .flags = (_y) }
4330 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
4331 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
4332 		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
4333 #define N    D(NotImpl)
4334 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
4335 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
4336 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
4337 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
4338 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
4339 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
4340 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
4341 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
4342 #define II(_f, _e, _i) \
4343 	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
4344 #define IIP(_f, _e, _i, _p) \
4345 	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
4346 	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
4347 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
4348 
4349 #define D2bv(_f)      D((_f) | ByteOp), D(_f)
4350 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
4351 #define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
4352 #define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
4353 #define I2bvIP(_f, _e, _i, _p) \
4354 	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
4355 
4356 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
4357 		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
4358 		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
4359 
4360 static const struct opcode group7_rm0[] = {
4361 	N,
4362 	I(SrcNone | Priv | EmulateOnUD,	em_hypercall),
4363 	N, N, N, N, N, N,
4364 };
4365 
4366 static const struct opcode group7_rm1[] = {
4367 	DI(SrcNone | Priv, monitor),
4368 	DI(SrcNone | Priv, mwait),
4369 	N, N, N, N, N, N,
4370 };
4371 
4372 static const struct opcode group7_rm3[] = {
4373 	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
4374 	II(SrcNone  | Prot | EmulateOnUD,	em_hypercall,	vmmcall),
4375 	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
4376 	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
4377 	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
4378 	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
4379 	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
4380 	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
4381 };
4382 
4383 static const struct opcode group7_rm7[] = {
4384 	N,
4385 	DIP(SrcNone, rdtscp, check_rdtsc),
4386 	N, N, N, N, N, N,
4387 };
4388 
4389 static const struct opcode group1[] = {
4390 	F(Lock, em_add),
4391 	F(Lock | PageTable, em_or),
4392 	F(Lock, em_adc),
4393 	F(Lock, em_sbb),
4394 	F(Lock | PageTable, em_and),
4395 	F(Lock, em_sub),
4396 	F(Lock, em_xor),
4397 	F(NoWrite, em_cmp),
4398 };
4399 
4400 static const struct opcode group1A[] = {
4401 	I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
4402 };
4403 
4404 static const struct opcode group2[] = {
4405 	F(DstMem | ModRM, em_rol),
4406 	F(DstMem | ModRM, em_ror),
4407 	F(DstMem | ModRM, em_rcl),
4408 	F(DstMem | ModRM, em_rcr),
4409 	F(DstMem | ModRM, em_shl),
4410 	F(DstMem | ModRM, em_shr),
4411 	F(DstMem | ModRM, em_shl),
4412 	F(DstMem | ModRM, em_sar),
4413 };
4414 
4415 static const struct opcode group3[] = {
4416 	F(DstMem | SrcImm | NoWrite, em_test),
4417 	F(DstMem | SrcImm | NoWrite, em_test),
4418 	F(DstMem | SrcNone | Lock, em_not),
4419 	F(DstMem | SrcNone | Lock, em_neg),
4420 	F(DstXacc | Src2Mem, em_mul_ex),
4421 	F(DstXacc | Src2Mem, em_imul_ex),
4422 	F(DstXacc | Src2Mem, em_div_ex),
4423 	F(DstXacc | Src2Mem, em_idiv_ex),
4424 };
4425 
4426 static const struct opcode group4[] = {
4427 	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
4428 	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4429 	N, N, N, N, N, N,
4430 };
4431 
4432 static const struct opcode group5[] = {
4433 	F(DstMem | SrcNone | Lock,		em_inc),
4434 	F(DstMem | SrcNone | Lock,		em_dec),
4435 	I(SrcMem | NearBranch,			em_call_near_abs),
4436 	I(SrcMemFAddr | ImplicitOps,		em_call_far),
4437 	I(SrcMem | NearBranch,			em_jmp_abs),
4438 	I(SrcMemFAddr | ImplicitOps,		em_jmp_far),
4439 	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
4440 };
4441 
4442 static const struct opcode group6[] = {
4443 	II(Prot | DstMem,	   em_sldt, sldt),
4444 	II(Prot | DstMem,	   em_str, str),
4445 	II(Prot | Priv | SrcMem16, em_lldt, lldt),
4446 	II(Prot | Priv | SrcMem16, em_ltr, ltr),
4447 	N, N, N, N,
4448 };
4449 
4450 static const struct group_dual group7 = { {
4451 	II(Mov | DstMem,			em_sgdt, sgdt),
4452 	II(Mov | DstMem,			em_sidt, sidt),
4453 	II(SrcMem | Priv,			em_lgdt, lgdt),
4454 	II(SrcMem | Priv,			em_lidt, lidt),
4455 	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
4456 	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
4457 	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
4458 }, {
4459 	EXT(0, group7_rm0),
4460 	EXT(0, group7_rm1),
4461 	N, EXT(0, group7_rm3),
4462 	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
4463 	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
4464 	EXT(0, group7_rm7),
4465 } };
4466 
4467 static const struct opcode group8[] = {
4468 	N, N, N, N,
4469 	F(DstMem | SrcImmByte | NoWrite,		em_bt),
4470 	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
4471 	F(DstMem | SrcImmByte | Lock,			em_btr),
4472 	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
4473 };
4474 
4475 /*
4476  * The "memory" destination is actually always a register, since we come
4477  * from the register case of group9.
4478  */
4479 static const struct gprefix pfx_0f_c7_7 = {
4480 	N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
4481 };
4482 
4483 
4484 static const struct group_dual group9 = { {
4485 	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4486 }, {
4487 	N, N, N, N, N, N, N,
4488 	GP(0, &pfx_0f_c7_7),
4489 } };
4490 
4491 static const struct opcode group11[] = {
4492 	I(DstMem | SrcImm | Mov | PageTable, em_mov),
4493 	X7(D(Undefined)),
4494 };
4495 
4496 static const struct gprefix pfx_0f_ae_7 = {
4497 	I(SrcMem | ByteOp, em_clflush), N, N, N,
4498 };
4499 
4500 static const struct group_dual group15 = { {
4501 	I(ModRM | Aligned16, em_fxsave),
4502 	I(ModRM | Aligned16, em_fxrstor),
4503 	N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4504 }, {
4505 	N, N, N, N, N, N, N, N,
4506 } };
4507 
4508 static const struct gprefix pfx_0f_6f_0f_7f = {
4509 	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4510 };
4511 
4512 static const struct instr_dual instr_dual_0f_2b = {
4513 	I(0, em_mov), N
4514 };
4515 
4516 static const struct gprefix pfx_0f_2b = {
4517 	ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4518 };
4519 
4520 static const struct gprefix pfx_0f_10_0f_11 = {
4521 	I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
4522 };
4523 
4524 static const struct gprefix pfx_0f_28_0f_29 = {
4525 	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4526 };
4527 
4528 static const struct gprefix pfx_0f_e7 = {
4529 	N, I(Sse, em_mov), N, N,
4530 };
4531 
4532 static const struct escape escape_d9 = { {
4533 	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4534 }, {
4535 	/* 0xC0 - 0xC7 */
4536 	N, N, N, N, N, N, N, N,
4537 	/* 0xC8 - 0xCF */
4538 	N, N, N, N, N, N, N, N,
4539 	/* 0xD0 - 0xC7 */
4540 	N, N, N, N, N, N, N, N,
4541 	/* 0xD8 - 0xDF */
4542 	N, N, N, N, N, N, N, N,
4543 	/* 0xE0 - 0xE7 */
4544 	N, N, N, N, N, N, N, N,
4545 	/* 0xE8 - 0xEF */
4546 	N, N, N, N, N, N, N, N,
4547 	/* 0xF0 - 0xF7 */
4548 	N, N, N, N, N, N, N, N,
4549 	/* 0xF8 - 0xFF */
4550 	N, N, N, N, N, N, N, N,
4551 } };
4552 
4553 static const struct escape escape_db = { {
4554 	N, N, N, N, N, N, N, N,
4555 }, {
4556 	/* 0xC0 - 0xC7 */
4557 	N, N, N, N, N, N, N, N,
4558 	/* 0xC8 - 0xCF */
4559 	N, N, N, N, N, N, N, N,
4560 	/* 0xD0 - 0xC7 */
4561 	N, N, N, N, N, N, N, N,
4562 	/* 0xD8 - 0xDF */
4563 	N, N, N, N, N, N, N, N,
4564 	/* 0xE0 - 0xE7 */
4565 	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
4566 	/* 0xE8 - 0xEF */
4567 	N, N, N, N, N, N, N, N,
4568 	/* 0xF0 - 0xF7 */
4569 	N, N, N, N, N, N, N, N,
4570 	/* 0xF8 - 0xFF */
4571 	N, N, N, N, N, N, N, N,
4572 } };
4573 
4574 static const struct escape escape_dd = { {
4575 	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4576 }, {
4577 	/* 0xC0 - 0xC7 */
4578 	N, N, N, N, N, N, N, N,
4579 	/* 0xC8 - 0xCF */
4580 	N, N, N, N, N, N, N, N,
4581 	/* 0xD0 - 0xC7 */
4582 	N, N, N, N, N, N, N, N,
4583 	/* 0xD8 - 0xDF */
4584 	N, N, N, N, N, N, N, N,
4585 	/* 0xE0 - 0xE7 */
4586 	N, N, N, N, N, N, N, N,
4587 	/* 0xE8 - 0xEF */
4588 	N, N, N, N, N, N, N, N,
4589 	/* 0xF0 - 0xF7 */
4590 	N, N, N, N, N, N, N, N,
4591 	/* 0xF8 - 0xFF */
4592 	N, N, N, N, N, N, N, N,
4593 } };
4594 
4595 static const struct instr_dual instr_dual_0f_c3 = {
4596 	I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
4597 };
4598 
4599 static const struct mode_dual mode_dual_63 = {
4600 	N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
4601 };
4602 
4603 static const struct opcode opcode_table[256] = {
4604 	/* 0x00 - 0x07 */
4605 	F6ALU(Lock, em_add),
4606 	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
4607 	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4608 	/* 0x08 - 0x0F */
4609 	F6ALU(Lock | PageTable, em_or),
4610 	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
4611 	N,
4612 	/* 0x10 - 0x17 */
4613 	F6ALU(Lock, em_adc),
4614 	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
4615 	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4616 	/* 0x18 - 0x1F */
4617 	F6ALU(Lock, em_sbb),
4618 	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
4619 	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4620 	/* 0x20 - 0x27 */
4621 	F6ALU(Lock | PageTable, em_and), N, N,
4622 	/* 0x28 - 0x2F */
4623 	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4624 	/* 0x30 - 0x37 */
4625 	F6ALU(Lock, em_xor), N, N,
4626 	/* 0x38 - 0x3F */
4627 	F6ALU(NoWrite, em_cmp), N, N,
4628 	/* 0x40 - 0x4F */
4629 	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4630 	/* 0x50 - 0x57 */
4631 	X8(I(SrcReg | Stack, em_push)),
4632 	/* 0x58 - 0x5F */
4633 	X8(I(DstReg | Stack, em_pop)),
4634 	/* 0x60 - 0x67 */
4635 	I(ImplicitOps | Stack | No64, em_pusha),
4636 	I(ImplicitOps | Stack | No64, em_popa),
4637 	N, MD(ModRM, &mode_dual_63),
4638 	N, N, N, N,
4639 	/* 0x68 - 0x6F */
4640 	I(SrcImm | Mov | Stack, em_push),
4641 	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4642 	I(SrcImmByte | Mov | Stack, em_push),
4643 	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4644 	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4645 	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4646 	/* 0x70 - 0x7F */
4647 	X16(D(SrcImmByte | NearBranch)),
4648 	/* 0x80 - 0x87 */
4649 	G(ByteOp | DstMem | SrcImm, group1),
4650 	G(DstMem | SrcImm, group1),
4651 	G(ByteOp | DstMem | SrcImm | No64, group1),
4652 	G(DstMem | SrcImmByte, group1),
4653 	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4654 	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4655 	/* 0x88 - 0x8F */
4656 	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4657 	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4658 	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4659 	D(ModRM | SrcMem | NoAccess | DstReg),
4660 	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
4661 	G(0, group1A),
4662 	/* 0x90 - 0x97 */
4663 	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4664 	/* 0x98 - 0x9F */
4665 	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4666 	I(SrcImmFAddr | No64, em_call_far), N,
4667 	II(ImplicitOps | Stack, em_pushf, pushf),
4668 	II(ImplicitOps | Stack, em_popf, popf),
4669 	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4670 	/* 0xA0 - 0xA7 */
4671 	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4672 	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4673 	I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
4674 	F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
4675 	/* 0xA8 - 0xAF */
4676 	F2bv(DstAcc | SrcImm | NoWrite, em_test),
4677 	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
4678 	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4679 	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4680 	/* 0xB0 - 0xB7 */
4681 	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4682 	/* 0xB8 - 0xBF */
4683 	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4684 	/* 0xC0 - 0xC7 */
4685 	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4686 	I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
4687 	I(ImplicitOps | NearBranch, em_ret),
4688 	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
4689 	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4690 	G(ByteOp, group11), G(0, group11),
4691 	/* 0xC8 - 0xCF */
4692 	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4693 	I(ImplicitOps | SrcImmU16, em_ret_far_imm),
4694 	I(ImplicitOps, em_ret_far),
4695 	D(ImplicitOps), DI(SrcImmByte, intn),
4696 	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4697 	/* 0xD0 - 0xD7 */
4698 	G(Src2One | ByteOp, group2), G(Src2One, group2),
4699 	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
4700 	I(DstAcc | SrcImmUByte | No64, em_aam),
4701 	I(DstAcc | SrcImmUByte | No64, em_aad),
4702 	F(DstAcc | ByteOp | No64, em_salc),
4703 	I(DstAcc | SrcXLat | ByteOp, em_mov),
4704 	/* 0xD8 - 0xDF */
4705 	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4706 	/* 0xE0 - 0xE7 */
4707 	X3(I(SrcImmByte | NearBranch, em_loop)),
4708 	I(SrcImmByte | NearBranch, em_jcxz),
4709 	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
4710 	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4711 	/* 0xE8 - 0xEF */
4712 	I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
4713 	I(SrcImmFAddr | No64, em_jmp_far),
4714 	D(SrcImmByte | ImplicitOps | NearBranch),
4715 	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
4716 	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4717 	/* 0xF0 - 0xF7 */
4718 	N, DI(ImplicitOps, icebp), N, N,
4719 	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
4720 	G(ByteOp, group3), G(0, group3),
4721 	/* 0xF8 - 0xFF */
4722 	D(ImplicitOps), D(ImplicitOps),
4723 	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4724 	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
4725 };
4726 
4727 static const struct opcode twobyte_table[256] = {
4728 	/* 0x00 - 0x0F */
4729 	G(0, group6), GD(0, &group7), N, N,
4730 	N, I(ImplicitOps | EmulateOnUD, em_syscall),
4731 	II(ImplicitOps | Priv, em_clts, clts), N,
4732 	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4733 	N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4734 	/* 0x10 - 0x1F */
4735 	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
4736 	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
4737 	N, N, N, N, N, N,
4738 	D(ImplicitOps | ModRM | SrcMem | NoAccess),
4739 	N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4740 	/* 0x20 - 0x2F */
4741 	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
4742 	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
4743 	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
4744 						check_cr_write),
4745 	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
4746 						check_dr_write),
4747 	N, N, N, N,
4748 	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
4749 	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4750 	N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4751 	N, N, N, N,
4752 	/* 0x30 - 0x3F */
4753 	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4754 	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4755 	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4756 	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4757 	I(ImplicitOps | EmulateOnUD, em_sysenter),
4758 	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4759 	N, N,
4760 	N, N, N, N, N, N, N, N,
4761 	/* 0x40 - 0x4F */
4762 	X16(D(DstReg | SrcMem | ModRM)),
4763 	/* 0x50 - 0x5F */
4764 	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4765 	/* 0x60 - 0x6F */
4766 	N, N, N, N,
4767 	N, N, N, N,
4768 	N, N, N, N,
4769 	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4770 	/* 0x70 - 0x7F */
4771 	N, N, N, N,
4772 	N, N, N, N,
4773 	N, N, N, N,
4774 	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4775 	/* 0x80 - 0x8F */
4776 	X16(D(SrcImm | NearBranch)),
4777 	/* 0x90 - 0x9F */
4778 	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4779 	/* 0xA0 - 0xA7 */
4780 	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4781 	II(ImplicitOps, em_cpuid, cpuid),
4782 	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4783 	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
4784 	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4785 	/* 0xA8 - 0xAF */
4786 	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4787 	II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4788 	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4789 	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
4790 	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4791 	GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4792 	/* 0xB0 - 0xB7 */
4793 	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4794 	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4795 	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4796 	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
4797 	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4798 	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4799 	/* 0xB8 - 0xBF */
4800 	N, N,
4801 	G(BitOp, group8),
4802 	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4803 	I(DstReg | SrcMem | ModRM, em_bsf_c),
4804 	I(DstReg | SrcMem | ModRM, em_bsr_c),
4805 	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4806 	/* 0xC0 - 0xC7 */
4807 	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4808 	N, ID(0, &instr_dual_0f_c3),
4809 	N, N, N, GD(0, &group9),
4810 	/* 0xC8 - 0xCF */
4811 	X8(I(DstReg, em_bswap)),
4812 	/* 0xD0 - 0xDF */
4813 	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
4814 	/* 0xE0 - 0xEF */
4815 	N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
4816 	N, N, N, N, N, N, N, N,
4817 	/* 0xF0 - 0xFF */
4818 	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
4819 };
4820 
4821 static const struct instr_dual instr_dual_0f_38_f0 = {
4822 	I(DstReg | SrcMem | Mov, em_movbe), N
4823 };
4824 
4825 static const struct instr_dual instr_dual_0f_38_f1 = {
4826 	I(DstMem | SrcReg | Mov, em_movbe), N
4827 };
4828 
4829 static const struct gprefix three_byte_0f_38_f0 = {
4830 	ID(0, &instr_dual_0f_38_f0), N, N, N
4831 };
4832 
4833 static const struct gprefix three_byte_0f_38_f1 = {
4834 	ID(0, &instr_dual_0f_38_f1), N, N, N
4835 };
4836 
4837 /*
4838  * Insns below are selected by the prefix which indexed by the third opcode
4839  * byte.
4840  */
4841 static const struct opcode opcode_map_0f_38[256] = {
4842 	/* 0x00 - 0x7f */
4843 	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4844 	/* 0x80 - 0xef */
4845 	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
4846 	/* 0xf0 - 0xf1 */
4847 	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
4848 	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
4849 	/* 0xf2 - 0xff */
4850 	N, N, X4(N), X8(N)
4851 };
4852 
4853 #undef D
4854 #undef N
4855 #undef G
4856 #undef GD
4857 #undef I
4858 #undef GP
4859 #undef EXT
4860 #undef MD
4861 #undef ID
4862 
4863 #undef D2bv
4864 #undef D2bvIP
4865 #undef I2bv
4866 #undef I2bvIP
4867 #undef I6ALU
4868 
4869 static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4870 {
4871 	unsigned size;
4872 
4873 	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4874 	if (size == 8)
4875 		size = 4;
4876 	return size;
4877 }
4878 
4879 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
4880 		      unsigned size, bool sign_extension)
4881 {
4882 	int rc = X86EMUL_CONTINUE;
4883 
4884 	op->type = OP_IMM;
4885 	op->bytes = size;
4886 	op->addr.mem.ea = ctxt->_eip;
4887 	/* NB. Immediates are sign-extended as necessary. */
4888 	switch (op->bytes) {
4889 	case 1:
4890 		op->val = insn_fetch(s8, ctxt);
4891 		break;
4892 	case 2:
4893 		op->val = insn_fetch(s16, ctxt);
4894 		break;
4895 	case 4:
4896 		op->val = insn_fetch(s32, ctxt);
4897 		break;
4898 	case 8:
4899 		op->val = insn_fetch(s64, ctxt);
4900 		break;
4901 	}
4902 	if (!sign_extension) {
4903 		switch (op->bytes) {
4904 		case 1:
4905 			op->val &= 0xff;
4906 			break;
4907 		case 2:
4908 			op->val &= 0xffff;
4909 			break;
4910 		case 4:
4911 			op->val &= 0xffffffff;
4912 			break;
4913 		}
4914 	}
4915 done:
4916 	return rc;
4917 }
4918 
4919 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
4920 			  unsigned d)
4921 {
4922 	int rc = X86EMUL_CONTINUE;
4923 
4924 	switch (d) {
4925 	case OpReg:
4926 		decode_register_operand(ctxt, op);
4927 		break;
4928 	case OpImmUByte:
4929 		rc = decode_imm(ctxt, op, 1, false);
4930 		break;
4931 	case OpMem:
4932 		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4933 	mem_common:
4934 		*op = ctxt->memop;
4935 		ctxt->memopp = op;
4936 		if (ctxt->d & BitOp)
4937 			fetch_bit_operand(ctxt);
4938 		op->orig_val = op->val;
4939 		break;
4940 	case OpMem64:
4941 		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4942 		goto mem_common;
4943 	case OpAcc:
4944 		op->type = OP_REG;
4945 		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4946 		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4947 		fetch_register_operand(op);
4948 		op->orig_val = op->val;
4949 		break;
4950 	case OpAccLo:
4951 		op->type = OP_REG;
4952 		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
4953 		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4954 		fetch_register_operand(op);
4955 		op->orig_val = op->val;
4956 		break;
4957 	case OpAccHi:
4958 		if (ctxt->d & ByteOp) {
4959 			op->type = OP_NONE;
4960 			break;
4961 		}
4962 		op->type = OP_REG;
4963 		op->bytes = ctxt->op_bytes;
4964 		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4965 		fetch_register_operand(op);
4966 		op->orig_val = op->val;
4967 		break;
4968 	case OpDI:
4969 		op->type = OP_MEM;
4970 		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4971 		op->addr.mem.ea =
4972 			register_address(ctxt, VCPU_REGS_RDI);
4973 		op->addr.mem.seg = VCPU_SREG_ES;
4974 		op->val = 0;
4975 		op->count = 1;
4976 		break;
4977 	case OpDX:
4978 		op->type = OP_REG;
4979 		op->bytes = 2;
4980 		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4981 		fetch_register_operand(op);
4982 		break;
4983 	case OpCL:
4984 		op->type = OP_IMM;
4985 		op->bytes = 1;
4986 		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4987 		break;
4988 	case OpImmByte:
4989 		rc = decode_imm(ctxt, op, 1, true);
4990 		break;
4991 	case OpOne:
4992 		op->type = OP_IMM;
4993 		op->bytes = 1;
4994 		op->val = 1;
4995 		break;
4996 	case OpImm:
4997 		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
4998 		break;
4999 	case OpImm64:
5000 		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
5001 		break;
5002 	case OpMem8:
5003 		ctxt->memop.bytes = 1;
5004 		if (ctxt->memop.type == OP_REG) {
5005 			ctxt->memop.addr.reg = decode_register(ctxt,
5006 					ctxt->modrm_rm, true);
5007 			fetch_register_operand(&ctxt->memop);
5008 		}
5009 		goto mem_common;
5010 	case OpMem16:
5011 		ctxt->memop.bytes = 2;
5012 		goto mem_common;
5013 	case OpMem32:
5014 		ctxt->memop.bytes = 4;
5015 		goto mem_common;
5016 	case OpImmU16:
5017 		rc = decode_imm(ctxt, op, 2, false);
5018 		break;
5019 	case OpImmU:
5020 		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
5021 		break;
5022 	case OpSI:
5023 		op->type = OP_MEM;
5024 		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5025 		op->addr.mem.ea =
5026 			register_address(ctxt, VCPU_REGS_RSI);
5027 		op->addr.mem.seg = ctxt->seg_override;
5028 		op->val = 0;
5029 		op->count = 1;
5030 		break;
5031 	case OpXLat:
5032 		op->type = OP_MEM;
5033 		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
5034 		op->addr.mem.ea =
5035 			address_mask(ctxt,
5036 				reg_read(ctxt, VCPU_REGS_RBX) +
5037 				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
5038 		op->addr.mem.seg = ctxt->seg_override;
5039 		op->val = 0;
5040 		break;
5041 	case OpImmFAddr:
5042 		op->type = OP_IMM;
5043 		op->addr.mem.ea = ctxt->_eip;
5044 		op->bytes = ctxt->op_bytes + 2;
5045 		insn_fetch_arr(op->valptr, op->bytes, ctxt);
5046 		break;
5047 	case OpMemFAddr:
5048 		ctxt->memop.bytes = ctxt->op_bytes + 2;
5049 		goto mem_common;
5050 	case OpES:
5051 		op->type = OP_IMM;
5052 		op->val = VCPU_SREG_ES;
5053 		break;
5054 	case OpCS:
5055 		op->type = OP_IMM;
5056 		op->val = VCPU_SREG_CS;
5057 		break;
5058 	case OpSS:
5059 		op->type = OP_IMM;
5060 		op->val = VCPU_SREG_SS;
5061 		break;
5062 	case OpDS:
5063 		op->type = OP_IMM;
5064 		op->val = VCPU_SREG_DS;
5065 		break;
5066 	case OpFS:
5067 		op->type = OP_IMM;
5068 		op->val = VCPU_SREG_FS;
5069 		break;
5070 	case OpGS:
5071 		op->type = OP_IMM;
5072 		op->val = VCPU_SREG_GS;
5073 		break;
5074 	case OpImplicit:
5075 		/* Special instructions do their own operand decoding. */
5076 	default:
5077 		op->type = OP_NONE; /* Disable writeback. */
5078 		break;
5079 	}
5080 
5081 done:
5082 	return rc;
5083 }
5084 
5085 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
5086 {
5087 	int rc = X86EMUL_CONTINUE;
5088 	int mode = ctxt->mode;
5089 	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
5090 	bool op_prefix = false;
5091 	bool has_seg_override = false;
5092 	struct opcode opcode;
5093 	u16 dummy;
5094 	struct desc_struct desc;
5095 
5096 	ctxt->memop.type = OP_NONE;
5097 	ctxt->memopp = NULL;
5098 	ctxt->_eip = ctxt->eip;
5099 	ctxt->fetch.ptr = ctxt->fetch.data;
5100 	ctxt->fetch.end = ctxt->fetch.data + insn_len;
5101 	ctxt->opcode_len = 1;
5102 	if (insn_len > 0)
5103 		memcpy(ctxt->fetch.data, insn, insn_len);
5104 	else {
5105 		rc = __do_insn_fetch_bytes(ctxt, 1);
5106 		if (rc != X86EMUL_CONTINUE)
5107 			return rc;
5108 	}
5109 
5110 	switch (mode) {
5111 	case X86EMUL_MODE_REAL:
5112 	case X86EMUL_MODE_VM86:
5113 		def_op_bytes = def_ad_bytes = 2;
5114 		ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
5115 		if (desc.d)
5116 			def_op_bytes = def_ad_bytes = 4;
5117 		break;
5118 	case X86EMUL_MODE_PROT16:
5119 		def_op_bytes = def_ad_bytes = 2;
5120 		break;
5121 	case X86EMUL_MODE_PROT32:
5122 		def_op_bytes = def_ad_bytes = 4;
5123 		break;
5124 #ifdef CONFIG_X86_64
5125 	case X86EMUL_MODE_PROT64:
5126 		def_op_bytes = 4;
5127 		def_ad_bytes = 8;
5128 		break;
5129 #endif
5130 	default:
5131 		return EMULATION_FAILED;
5132 	}
5133 
5134 	ctxt->op_bytes = def_op_bytes;
5135 	ctxt->ad_bytes = def_ad_bytes;
5136 
5137 	/* Legacy prefixes. */
5138 	for (;;) {
5139 		switch (ctxt->b = insn_fetch(u8, ctxt)) {
5140 		case 0x66:	/* operand-size override */
5141 			op_prefix = true;
5142 			/* switch between 2/4 bytes */
5143 			ctxt->op_bytes = def_op_bytes ^ 6;
5144 			break;
5145 		case 0x67:	/* address-size override */
5146 			if (mode == X86EMUL_MODE_PROT64)
5147 				/* switch between 4/8 bytes */
5148 				ctxt->ad_bytes = def_ad_bytes ^ 12;
5149 			else
5150 				/* switch between 2/4 bytes */
5151 				ctxt->ad_bytes = def_ad_bytes ^ 6;
5152 			break;
5153 		case 0x26:	/* ES override */
5154 		case 0x2e:	/* CS override */
5155 		case 0x36:	/* SS override */
5156 		case 0x3e:	/* DS override */
5157 			has_seg_override = true;
5158 			ctxt->seg_override = (ctxt->b >> 3) & 3;
5159 			break;
5160 		case 0x64:	/* FS override */
5161 		case 0x65:	/* GS override */
5162 			has_seg_override = true;
5163 			ctxt->seg_override = ctxt->b & 7;
5164 			break;
5165 		case 0x40 ... 0x4f: /* REX */
5166 			if (mode != X86EMUL_MODE_PROT64)
5167 				goto done_prefixes;
5168 			ctxt->rex_prefix = ctxt->b;
5169 			continue;
5170 		case 0xf0:	/* LOCK */
5171 			ctxt->lock_prefix = 1;
5172 			break;
5173 		case 0xf2:	/* REPNE/REPNZ */
5174 		case 0xf3:	/* REP/REPE/REPZ */
5175 			ctxt->rep_prefix = ctxt->b;
5176 			break;
5177 		default:
5178 			goto done_prefixes;
5179 		}
5180 
5181 		/* Any legacy prefix after a REX prefix nullifies its effect. */
5182 
5183 		ctxt->rex_prefix = 0;
5184 	}
5185 
5186 done_prefixes:
5187 
5188 	/* REX prefix. */
5189 	if (ctxt->rex_prefix & 8)
5190 		ctxt->op_bytes = 8;	/* REX.W */
5191 
5192 	/* Opcode byte(s). */
5193 	opcode = opcode_table[ctxt->b];
5194 	/* Two-byte opcode? */
5195 	if (ctxt->b == 0x0f) {
5196 		ctxt->opcode_len = 2;
5197 		ctxt->b = insn_fetch(u8, ctxt);
5198 		opcode = twobyte_table[ctxt->b];
5199 
5200 		/* 0F_38 opcode map */
5201 		if (ctxt->b == 0x38) {
5202 			ctxt->opcode_len = 3;
5203 			ctxt->b = insn_fetch(u8, ctxt);
5204 			opcode = opcode_map_0f_38[ctxt->b];
5205 		}
5206 	}
5207 	ctxt->d = opcode.flags;
5208 
5209 	if (ctxt->d & ModRM)
5210 		ctxt->modrm = insn_fetch(u8, ctxt);
5211 
5212 	/* vex-prefix instructions are not implemented */
5213 	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
5214 	    (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
5215 		ctxt->d = NotImpl;
5216 	}
5217 
5218 	while (ctxt->d & GroupMask) {
5219 		switch (ctxt->d & GroupMask) {
5220 		case Group:
5221 			goffset = (ctxt->modrm >> 3) & 7;
5222 			opcode = opcode.u.group[goffset];
5223 			break;
5224 		case GroupDual:
5225 			goffset = (ctxt->modrm >> 3) & 7;
5226 			if ((ctxt->modrm >> 6) == 3)
5227 				opcode = opcode.u.gdual->mod3[goffset];
5228 			else
5229 				opcode = opcode.u.gdual->mod012[goffset];
5230 			break;
5231 		case RMExt:
5232 			goffset = ctxt->modrm & 7;
5233 			opcode = opcode.u.group[goffset];
5234 			break;
5235 		case Prefix:
5236 			if (ctxt->rep_prefix && op_prefix)
5237 				return EMULATION_FAILED;
5238 			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
5239 			switch (simd_prefix) {
5240 			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
5241 			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
5242 			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
5243 			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
5244 			}
5245 			break;
5246 		case Escape:
5247 			if (ctxt->modrm > 0xbf)
5248 				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
5249 			else
5250 				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
5251 			break;
5252 		case InstrDual:
5253 			if ((ctxt->modrm >> 6) == 3)
5254 				opcode = opcode.u.idual->mod3;
5255 			else
5256 				opcode = opcode.u.idual->mod012;
5257 			break;
5258 		case ModeDual:
5259 			if (ctxt->mode == X86EMUL_MODE_PROT64)
5260 				opcode = opcode.u.mdual->mode64;
5261 			else
5262 				opcode = opcode.u.mdual->mode32;
5263 			break;
5264 		default:
5265 			return EMULATION_FAILED;
5266 		}
5267 
5268 		ctxt->d &= ~(u64)GroupMask;
5269 		ctxt->d |= opcode.flags;
5270 	}
5271 
5272 	/* Unrecognised? */
5273 	if (ctxt->d == 0)
5274 		return EMULATION_FAILED;
5275 
5276 	ctxt->execute = opcode.u.execute;
5277 
5278 	if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
5279 		return EMULATION_FAILED;
5280 
5281 	if (unlikely(ctxt->d &
5282 	    (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
5283 	     No16))) {
5284 		/*
5285 		 * These are copied unconditionally here, and checked unconditionally
5286 		 * in x86_emulate_insn.
5287 		 */
5288 		ctxt->check_perm = opcode.check_perm;
5289 		ctxt->intercept = opcode.intercept;
5290 
5291 		if (ctxt->d & NotImpl)
5292 			return EMULATION_FAILED;
5293 
5294 		if (mode == X86EMUL_MODE_PROT64) {
5295 			if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
5296 				ctxt->op_bytes = 8;
5297 			else if (ctxt->d & NearBranch)
5298 				ctxt->op_bytes = 8;
5299 		}
5300 
5301 		if (ctxt->d & Op3264) {
5302 			if (mode == X86EMUL_MODE_PROT64)
5303 				ctxt->op_bytes = 8;
5304 			else
5305 				ctxt->op_bytes = 4;
5306 		}
5307 
5308 		if ((ctxt->d & No16) && ctxt->op_bytes == 2)
5309 			ctxt->op_bytes = 4;
5310 
5311 		if (ctxt->d & Sse)
5312 			ctxt->op_bytes = 16;
5313 		else if (ctxt->d & Mmx)
5314 			ctxt->op_bytes = 8;
5315 	}
5316 
5317 	/* ModRM and SIB bytes. */
5318 	if (ctxt->d & ModRM) {
5319 		rc = decode_modrm(ctxt, &ctxt->memop);
5320 		if (!has_seg_override) {
5321 			has_seg_override = true;
5322 			ctxt->seg_override = ctxt->modrm_seg;
5323 		}
5324 	} else if (ctxt->d & MemAbs)
5325 		rc = decode_abs(ctxt, &ctxt->memop);
5326 	if (rc != X86EMUL_CONTINUE)
5327 		goto done;
5328 
5329 	if (!has_seg_override)
5330 		ctxt->seg_override = VCPU_SREG_DS;
5331 
5332 	ctxt->memop.addr.mem.seg = ctxt->seg_override;
5333 
5334 	/*
5335 	 * Decode and fetch the source operand: register, memory
5336 	 * or immediate.
5337 	 */
5338 	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5339 	if (rc != X86EMUL_CONTINUE)
5340 		goto done;
5341 
5342 	/*
5343 	 * Decode and fetch the second source operand: register, memory
5344 	 * or immediate.
5345 	 */
5346 	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5347 	if (rc != X86EMUL_CONTINUE)
5348 		goto done;
5349 
5350 	/* Decode and fetch the destination operand: register or memory. */
5351 	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5352 
5353 	if (ctxt->rip_relative && likely(ctxt->memopp))
5354 		ctxt->memopp->addr.mem.ea = address_mask(ctxt,
5355 					ctxt->memopp->addr.mem.ea + ctxt->_eip);
5356 
5357 done:
5358 	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5359 }
5360 
5361 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
5362 {
5363 	return ctxt->d & PageTable;
5364 }
5365 
5366 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
5367 {
5368 	/* The second termination condition only applies for REPE
5369 	 * and REPNE. Test if the repeat string operation prefix is
5370 	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
5371 	 * corresponding termination condition according to:
5372 	 * 	- if REPE/REPZ and ZF = 0 then done
5373 	 * 	- if REPNE/REPNZ and ZF = 1 then done
5374 	 */
5375 	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
5376 	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
5377 	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
5378 		 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5379 		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
5380 		    ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5381 		return true;
5382 
5383 	return false;
5384 }
5385 
5386 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
5387 {
5388 	int rc;
5389 
5390 	rc = asm_safe("fwait");
5391 
5392 	if (unlikely(rc != X86EMUL_CONTINUE))
5393 		return emulate_exception(ctxt, MF_VECTOR, 0, false);
5394 
5395 	return X86EMUL_CONTINUE;
5396 }
5397 
5398 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
5399 				       struct operand *op)
5400 {
5401 	if (op->type == OP_MM)
5402 		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
5403 }
5404 
5405 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
5406 {
5407 	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5408 
5409 	if (!(ctxt->d & ByteOp))
5410 		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5411 
5412 	asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
5413 	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5414 	      [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
5415 	    : "c"(ctxt->src2.val));
5416 
5417 	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5418 	if (!fop) /* exception is returned in fop variable */
5419 		return emulate_de(ctxt);
5420 	return X86EMUL_CONTINUE;
5421 }
5422 
5423 void init_decode_cache(struct x86_emulate_ctxt *ctxt)
5424 {
5425 	memset(&ctxt->rip_relative, 0,
5426 	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
5427 
5428 	ctxt->io_read.pos = 0;
5429 	ctxt->io_read.end = 0;
5430 	ctxt->mem_read.end = 0;
5431 }
5432 
5433 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5434 {
5435 	const struct x86_emulate_ops *ops = ctxt->ops;
5436 	int rc = X86EMUL_CONTINUE;
5437 	int saved_dst_type = ctxt->dst.type;
5438 	unsigned emul_flags;
5439 
5440 	ctxt->mem_read.pos = 0;
5441 
5442 	/* LOCK prefix is allowed only with some instructions */
5443 	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5444 		rc = emulate_ud(ctxt);
5445 		goto done;
5446 	}
5447 
5448 	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5449 		rc = emulate_ud(ctxt);
5450 		goto done;
5451 	}
5452 
5453 	emul_flags = ctxt->ops->get_hflags(ctxt);
5454 	if (unlikely(ctxt->d &
5455 		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
5456 		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
5457 				(ctxt->d & Undefined)) {
5458 			rc = emulate_ud(ctxt);
5459 			goto done;
5460 		}
5461 
5462 		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
5463 		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
5464 			rc = emulate_ud(ctxt);
5465 			goto done;
5466 		}
5467 
5468 		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
5469 			rc = emulate_nm(ctxt);
5470 			goto done;
5471 		}
5472 
5473 		if (ctxt->d & Mmx) {
5474 			rc = flush_pending_x87_faults(ctxt);
5475 			if (rc != X86EMUL_CONTINUE)
5476 				goto done;
5477 			/*
5478 			 * Now that we know the fpu is exception safe, we can fetch
5479 			 * operands from it.
5480 			 */
5481 			fetch_possible_mmx_operand(ctxt, &ctxt->src);
5482 			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
5483 			if (!(ctxt->d & Mov))
5484 				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
5485 		}
5486 
5487 		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
5488 			rc = emulator_check_intercept(ctxt, ctxt->intercept,
5489 						      X86_ICPT_PRE_EXCEPT);
5490 			if (rc != X86EMUL_CONTINUE)
5491 				goto done;
5492 		}
5493 
5494 		/* Instruction can only be executed in protected mode */
5495 		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
5496 			rc = emulate_ud(ctxt);
5497 			goto done;
5498 		}
5499 
5500 		/* Privileged instruction can be executed only in CPL=0 */
5501 		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5502 			if (ctxt->d & PrivUD)
5503 				rc = emulate_ud(ctxt);
5504 			else
5505 				rc = emulate_gp(ctxt, 0);
5506 			goto done;
5507 		}
5508 
5509 		/* Do instruction specific permission checks */
5510 		if (ctxt->d & CheckPerm) {
5511 			rc = ctxt->check_perm(ctxt);
5512 			if (rc != X86EMUL_CONTINUE)
5513 				goto done;
5514 		}
5515 
5516 		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5517 			rc = emulator_check_intercept(ctxt, ctxt->intercept,
5518 						      X86_ICPT_POST_EXCEPT);
5519 			if (rc != X86EMUL_CONTINUE)
5520 				goto done;
5521 		}
5522 
5523 		if (ctxt->rep_prefix && (ctxt->d & String)) {
5524 			/* All REP prefixes have the same first termination condition */
5525 			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5526 				string_registers_quirk(ctxt);
5527 				ctxt->eip = ctxt->_eip;
5528 				ctxt->eflags &= ~X86_EFLAGS_RF;
5529 				goto done;
5530 			}
5531 		}
5532 	}
5533 
5534 	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
5535 		rc = segmented_read(ctxt, ctxt->src.addr.mem,
5536 				    ctxt->src.valptr, ctxt->src.bytes);
5537 		if (rc != X86EMUL_CONTINUE)
5538 			goto done;
5539 		ctxt->src.orig_val64 = ctxt->src.val64;
5540 	}
5541 
5542 	if (ctxt->src2.type == OP_MEM) {
5543 		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
5544 				    &ctxt->src2.val, ctxt->src2.bytes);
5545 		if (rc != X86EMUL_CONTINUE)
5546 			goto done;
5547 	}
5548 
5549 	if ((ctxt->d & DstMask) == ImplicitOps)
5550 		goto special_insn;
5551 
5552 
5553 	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5554 		/* optimisation - avoid slow emulated read if Mov */
5555 		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
5556 				   &ctxt->dst.val, ctxt->dst.bytes);
5557 		if (rc != X86EMUL_CONTINUE) {
5558 			if (!(ctxt->d & NoWrite) &&
5559 			    rc == X86EMUL_PROPAGATE_FAULT &&
5560 			    ctxt->exception.vector == PF_VECTOR)
5561 				ctxt->exception.error_code |= PFERR_WRITE_MASK;
5562 			goto done;
5563 		}
5564 	}
5565 	/* Copy full 64-bit value for CMPXCHG8B.  */
5566 	ctxt->dst.orig_val64 = ctxt->dst.val64;
5567 
5568 special_insn:
5569 
5570 	if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5571 		rc = emulator_check_intercept(ctxt, ctxt->intercept,
5572 					      X86_ICPT_POST_MEMACCESS);
5573 		if (rc != X86EMUL_CONTINUE)
5574 			goto done;
5575 	}
5576 
5577 	if (ctxt->rep_prefix && (ctxt->d & String))
5578 		ctxt->eflags |= X86_EFLAGS_RF;
5579 	else
5580 		ctxt->eflags &= ~X86_EFLAGS_RF;
5581 
5582 	if (ctxt->execute) {
5583 		if (ctxt->d & Fastop) {
5584 			void (*fop)(struct fastop *) = (void *)ctxt->execute;
5585 			rc = fastop(ctxt, fop);
5586 			if (rc != X86EMUL_CONTINUE)
5587 				goto done;
5588 			goto writeback;
5589 		}
5590 		rc = ctxt->execute(ctxt);
5591 		if (rc != X86EMUL_CONTINUE)
5592 			goto done;
5593 		goto writeback;
5594 	}
5595 
5596 	if (ctxt->opcode_len == 2)
5597 		goto twobyte_insn;
5598 	else if (ctxt->opcode_len == 3)
5599 		goto threebyte_insn;
5600 
5601 	switch (ctxt->b) {
5602 	case 0x70 ... 0x7f: /* jcc (short) */
5603 		if (test_cc(ctxt->b, ctxt->eflags))
5604 			rc = jmp_rel(ctxt, ctxt->src.val);
5605 		break;
5606 	case 0x8d: /* lea r16/r32, m */
5607 		ctxt->dst.val = ctxt->src.addr.mem.ea;
5608 		break;
5609 	case 0x90 ... 0x97: /* nop / xchg reg, rax */
5610 		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5611 			ctxt->dst.type = OP_NONE;
5612 		else
5613 			rc = em_xchg(ctxt);
5614 		break;
5615 	case 0x98: /* cbw/cwde/cdqe */
5616 		switch (ctxt->op_bytes) {
5617 		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
5618 		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
5619 		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5620 		}
5621 		break;
5622 	case 0xcc:		/* int3 */
5623 		rc = emulate_int(ctxt, 3);
5624 		break;
5625 	case 0xcd:		/* int n */
5626 		rc = emulate_int(ctxt, ctxt->src.val);
5627 		break;
5628 	case 0xce:		/* into */
5629 		if (ctxt->eflags & X86_EFLAGS_OF)
5630 			rc = emulate_int(ctxt, 4);
5631 		break;
5632 	case 0xe9: /* jmp rel */
5633 	case 0xeb: /* jmp rel short */
5634 		rc = jmp_rel(ctxt, ctxt->src.val);
5635 		ctxt->dst.type = OP_NONE; /* Disable writeback. */
5636 		break;
5637 	case 0xf4:              /* hlt */
5638 		ctxt->ops->halt(ctxt);
5639 		break;
5640 	case 0xf5:	/* cmc */
5641 		/* complement carry flag from eflags reg */
5642 		ctxt->eflags ^= X86_EFLAGS_CF;
5643 		break;
5644 	case 0xf8: /* clc */
5645 		ctxt->eflags &= ~X86_EFLAGS_CF;
5646 		break;
5647 	case 0xf9: /* stc */
5648 		ctxt->eflags |= X86_EFLAGS_CF;
5649 		break;
5650 	case 0xfc: /* cld */
5651 		ctxt->eflags &= ~X86_EFLAGS_DF;
5652 		break;
5653 	case 0xfd: /* std */
5654 		ctxt->eflags |= X86_EFLAGS_DF;
5655 		break;
5656 	default:
5657 		goto cannot_emulate;
5658 	}
5659 
5660 	if (rc != X86EMUL_CONTINUE)
5661 		goto done;
5662 
5663 writeback:
5664 	if (ctxt->d & SrcWrite) {
5665 		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
5666 		rc = writeback(ctxt, &ctxt->src);
5667 		if (rc != X86EMUL_CONTINUE)
5668 			goto done;
5669 	}
5670 	if (!(ctxt->d & NoWrite)) {
5671 		rc = writeback(ctxt, &ctxt->dst);
5672 		if (rc != X86EMUL_CONTINUE)
5673 			goto done;
5674 	}
5675 
5676 	/*
5677 	 * restore dst type in case the decoding will be reused
5678 	 * (happens for string instruction )
5679 	 */
5680 	ctxt->dst.type = saved_dst_type;
5681 
5682 	if ((ctxt->d & SrcMask) == SrcSI)
5683 		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5684 
5685 	if ((ctxt->d & DstMask) == DstDI)
5686 		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5687 
5688 	if (ctxt->rep_prefix && (ctxt->d & String)) {
5689 		unsigned int count;
5690 		struct read_cache *r = &ctxt->io_read;
5691 		if ((ctxt->d & SrcMask) == SrcSI)
5692 			count = ctxt->src.count;
5693 		else
5694 			count = ctxt->dst.count;
5695 		register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5696 
5697 		if (!string_insn_completed(ctxt)) {
5698 			/*
5699 			 * Re-enter guest when pio read ahead buffer is empty
5700 			 * or, if it is not used, after each 1024 iteration.
5701 			 */
5702 			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5703 			    (r->end == 0 || r->end != r->pos)) {
5704 				/*
5705 				 * Reset read cache. Usually happens before
5706 				 * decode, but since instruction is restarted
5707 				 * we have to do it here.
5708 				 */
5709 				ctxt->mem_read.end = 0;
5710 				writeback_registers(ctxt);
5711 				return EMULATION_RESTART;
5712 			}
5713 			goto done; /* skip rip writeback */
5714 		}
5715 		ctxt->eflags &= ~X86_EFLAGS_RF;
5716 	}
5717 
5718 	ctxt->eip = ctxt->_eip;
5719 
5720 done:
5721 	if (rc == X86EMUL_PROPAGATE_FAULT) {
5722 		WARN_ON(ctxt->exception.vector > 0x1f);
5723 		ctxt->have_exception = true;
5724 	}
5725 	if (rc == X86EMUL_INTERCEPTED)
5726 		return EMULATION_INTERCEPTED;
5727 
5728 	if (rc == X86EMUL_CONTINUE)
5729 		writeback_registers(ctxt);
5730 
5731 	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
5732 
5733 twobyte_insn:
5734 	switch (ctxt->b) {
5735 	case 0x09:		/* wbinvd */
5736 		(ctxt->ops->wbinvd)(ctxt);
5737 		break;
5738 	case 0x08:		/* invd */
5739 	case 0x0d:		/* GrpP (prefetch) */
5740 	case 0x18:		/* Grp16 (prefetch/nop) */
5741 	case 0x1f:		/* nop */
5742 		break;
5743 	case 0x20: /* mov cr, reg */
5744 		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5745 		break;
5746 	case 0x21: /* mov from dr to reg */
5747 		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
5748 		break;
5749 	case 0x40 ... 0x4f:	/* cmov */
5750 		if (test_cc(ctxt->b, ctxt->eflags))
5751 			ctxt->dst.val = ctxt->src.val;
5752 		else if (ctxt->op_bytes != 4)
5753 			ctxt->dst.type = OP_NONE; /* no writeback */
5754 		break;
5755 	case 0x80 ... 0x8f: /* jnz rel, etc*/
5756 		if (test_cc(ctxt->b, ctxt->eflags))
5757 			rc = jmp_rel(ctxt, ctxt->src.val);
5758 		break;
5759 	case 0x90 ... 0x9f:     /* setcc r/m8 */
5760 		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5761 		break;
5762 	case 0xb6 ... 0xb7:	/* movzx */
5763 		ctxt->dst.bytes = ctxt->op_bytes;
5764 		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5765 						       : (u16) ctxt->src.val;
5766 		break;
5767 	case 0xbe ... 0xbf:	/* movsx */
5768 		ctxt->dst.bytes = ctxt->op_bytes;
5769 		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5770 							(s16) ctxt->src.val;
5771 		break;
5772 	default:
5773 		goto cannot_emulate;
5774 	}
5775 
5776 threebyte_insn:
5777 
5778 	if (rc != X86EMUL_CONTINUE)
5779 		goto done;
5780 
5781 	goto writeback;
5782 
5783 cannot_emulate:
5784 	return EMULATION_FAILED;
5785 }
5786 
5787 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
5788 {
5789 	invalidate_registers(ctxt);
5790 }
5791 
5792 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
5793 {
5794 	writeback_registers(ctxt);
5795 }
5796 
5797 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
5798 {
5799 	if (ctxt->rep_prefix && (ctxt->d & String))
5800 		return false;
5801 
5802 	if (ctxt->d & TwoMemOp)
5803 		return false;
5804 
5805 	return true;
5806 }
5807