1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 21 #include <linux/kvm_host.h> 22 #include "kvm_cache_regs.h" 23 #include <asm/kvm_emulate.h> 24 #include <linux/stringify.h> 25 #include <asm/debugreg.h> 26 #include <asm/nospec-branch.h> 27 28 #include "x86.h" 29 #include "tss.h" 30 #include "mmu.h" 31 #include "pmu.h" 32 33 /* 34 * Operand types 35 */ 36 #define OpNone 0ull 37 #define OpImplicit 1ull /* No generic decode */ 38 #define OpReg 2ull /* Register */ 39 #define OpMem 3ull /* Memory */ 40 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 41 #define OpDI 5ull /* ES:DI/EDI/RDI */ 42 #define OpMem64 6ull /* Memory, 64-bit */ 43 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 44 #define OpDX 8ull /* DX register */ 45 #define OpCL 9ull /* CL register (for shifts) */ 46 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 47 #define OpOne 11ull /* Implied 1 */ 48 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 49 #define OpMem16 13ull /* Memory operand (16-bit). */ 50 #define OpMem32 14ull /* Memory operand (32-bit). */ 51 #define OpImmU 15ull /* Immediate operand, zero extended */ 52 #define OpSI 16ull /* SI/ESI/RSI */ 53 #define OpImmFAddr 17ull /* Immediate far address */ 54 #define OpMemFAddr 18ull /* Far address in memory */ 55 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 56 #define OpES 20ull /* ES */ 57 #define OpCS 21ull /* CS */ 58 #define OpSS 22ull /* SS */ 59 #define OpDS 23ull /* DS */ 60 #define OpFS 24ull /* FS */ 61 #define OpGS 25ull /* GS */ 62 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 63 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 64 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 65 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 66 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 67 68 #define OpBits 5 /* Width of operand field */ 69 #define OpMask ((1ull << OpBits) - 1) 70 71 /* 72 * Opcode effective-address decode tables. 73 * Note that we only emulate instructions that have at least one memory 74 * operand (excluding implicit stack references). We assume that stack 75 * references and instruction fetches will never occur in special memory 76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 77 * not be handled. 78 */ 79 80 /* Operand sizes: 8-bit operands or specified/overridden size. */ 81 #define ByteOp (1<<0) /* 8-bit operands. */ 82 /* Destination operand type. */ 83 #define DstShift 1 84 #define ImplicitOps (OpImplicit << DstShift) 85 #define DstReg (OpReg << DstShift) 86 #define DstMem (OpMem << DstShift) 87 #define DstAcc (OpAcc << DstShift) 88 #define DstDI (OpDI << DstShift) 89 #define DstMem64 (OpMem64 << DstShift) 90 #define DstMem16 (OpMem16 << DstShift) 91 #define DstImmUByte (OpImmUByte << DstShift) 92 #define DstDX (OpDX << DstShift) 93 #define DstAccLo (OpAccLo << DstShift) 94 #define DstMask (OpMask << DstShift) 95 /* Source operand type. */ 96 #define SrcShift 6 97 #define SrcNone (OpNone << SrcShift) 98 #define SrcReg (OpReg << SrcShift) 99 #define SrcMem (OpMem << SrcShift) 100 #define SrcMem16 (OpMem16 << SrcShift) 101 #define SrcMem32 (OpMem32 << SrcShift) 102 #define SrcImm (OpImm << SrcShift) 103 #define SrcImmByte (OpImmByte << SrcShift) 104 #define SrcOne (OpOne << SrcShift) 105 #define SrcImmUByte (OpImmUByte << SrcShift) 106 #define SrcImmU (OpImmU << SrcShift) 107 #define SrcSI (OpSI << SrcShift) 108 #define SrcXLat (OpXLat << SrcShift) 109 #define SrcImmFAddr (OpImmFAddr << SrcShift) 110 #define SrcMemFAddr (OpMemFAddr << SrcShift) 111 #define SrcAcc (OpAcc << SrcShift) 112 #define SrcImmU16 (OpImmU16 << SrcShift) 113 #define SrcImm64 (OpImm64 << SrcShift) 114 #define SrcDX (OpDX << SrcShift) 115 #define SrcMem8 (OpMem8 << SrcShift) 116 #define SrcAccHi (OpAccHi << SrcShift) 117 #define SrcMask (OpMask << SrcShift) 118 #define BitOp (1<<11) 119 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 120 #define String (1<<13) /* String instruction (rep capable) */ 121 #define Stack (1<<14) /* Stack instruction (push/pop) */ 122 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 123 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 124 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 125 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 126 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 127 #define Escape (5<<15) /* Escape to coprocessor instruction */ 128 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 129 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 130 #define Sse (1<<18) /* SSE Vector instruction */ 131 /* Generic ModRM decode. */ 132 #define ModRM (1<<19) 133 /* Destination is only written; never read. */ 134 #define Mov (1<<20) 135 /* Misc flags */ 136 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 137 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 138 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 139 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 140 #define Undefined (1<<25) /* No Such Instruction */ 141 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 142 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 143 #define No64 (1<<28) 144 #define PageTable (1 << 29) /* instruction used to write page table */ 145 #define NotImpl (1 << 30) /* instruction is not implemented */ 146 /* Source 2 operand type */ 147 #define Src2Shift (31) 148 #define Src2None (OpNone << Src2Shift) 149 #define Src2Mem (OpMem << Src2Shift) 150 #define Src2CL (OpCL << Src2Shift) 151 #define Src2ImmByte (OpImmByte << Src2Shift) 152 #define Src2One (OpOne << Src2Shift) 153 #define Src2Imm (OpImm << Src2Shift) 154 #define Src2ES (OpES << Src2Shift) 155 #define Src2CS (OpCS << Src2Shift) 156 #define Src2SS (OpSS << Src2Shift) 157 #define Src2DS (OpDS << Src2Shift) 158 #define Src2FS (OpFS << Src2Shift) 159 #define Src2GS (OpGS << Src2Shift) 160 #define Src2Mask (OpMask << Src2Shift) 161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 162 #define AlignMask ((u64)7 << 41) 163 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 164 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 165 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 166 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 167 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 168 #define NoWrite ((u64)1 << 45) /* No writeback */ 169 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 170 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 171 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 172 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 173 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 174 #define NearBranch ((u64)1 << 52) /* Near branches */ 175 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 176 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 177 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 178 179 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 180 181 #define X2(x...) x, x 182 #define X3(x...) X2(x), x 183 #define X4(x...) X2(x), X2(x) 184 #define X5(x...) X4(x), x 185 #define X6(x...) X4(x), X2(x) 186 #define X7(x...) X4(x), X3(x) 187 #define X8(x...) X4(x), X4(x) 188 #define X16(x...) X8(x), X8(x) 189 190 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 191 #define FASTOP_SIZE 8 192 193 /* 194 * fastop functions have a special calling convention: 195 * 196 * dst: rax (in/out) 197 * src: rdx (in/out) 198 * src2: rcx (in) 199 * flags: rflags (in/out) 200 * ex: rsi (in:fastop pointer, out:zero if exception) 201 * 202 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 203 * different operand sizes can be reached by calculation, rather than a jump 204 * table (which would be bigger than the code). 205 * 206 * fastop functions are declared as taking a never-defined fastop parameter, 207 * so they can't be called from C directly. 208 */ 209 210 struct fastop; 211 212 struct opcode { 213 u64 flags : 56; 214 u64 intercept : 8; 215 union { 216 int (*execute)(struct x86_emulate_ctxt *ctxt); 217 const struct opcode *group; 218 const struct group_dual *gdual; 219 const struct gprefix *gprefix; 220 const struct escape *esc; 221 const struct instr_dual *idual; 222 const struct mode_dual *mdual; 223 void (*fastop)(struct fastop *fake); 224 } u; 225 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 226 }; 227 228 struct group_dual { 229 struct opcode mod012[8]; 230 struct opcode mod3[8]; 231 }; 232 233 struct gprefix { 234 struct opcode pfx_no; 235 struct opcode pfx_66; 236 struct opcode pfx_f2; 237 struct opcode pfx_f3; 238 }; 239 240 struct escape { 241 struct opcode op[8]; 242 struct opcode high[64]; 243 }; 244 245 struct instr_dual { 246 struct opcode mod012; 247 struct opcode mod3; 248 }; 249 250 struct mode_dual { 251 struct opcode mode32; 252 struct opcode mode64; 253 }; 254 255 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 256 257 enum x86_transfer_type { 258 X86_TRANSFER_NONE, 259 X86_TRANSFER_CALL_JMP, 260 X86_TRANSFER_RET, 261 X86_TRANSFER_TASK_SWITCH, 262 }; 263 264 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 265 { 266 if (!(ctxt->regs_valid & (1 << nr))) { 267 ctxt->regs_valid |= 1 << nr; 268 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 269 } 270 return ctxt->_regs[nr]; 271 } 272 273 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 274 { 275 ctxt->regs_valid |= 1 << nr; 276 ctxt->regs_dirty |= 1 << nr; 277 return &ctxt->_regs[nr]; 278 } 279 280 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 281 { 282 reg_read(ctxt, nr); 283 return reg_write(ctxt, nr); 284 } 285 286 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 287 { 288 unsigned reg; 289 290 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 291 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 292 } 293 294 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 295 { 296 ctxt->regs_dirty = 0; 297 ctxt->regs_valid = 0; 298 } 299 300 /* 301 * These EFLAGS bits are restored from saved value during emulation, and 302 * any changes are written back to the saved value after emulation. 303 */ 304 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 305 X86_EFLAGS_PF|X86_EFLAGS_CF) 306 307 #ifdef CONFIG_X86_64 308 #define ON64(x) x 309 #else 310 #define ON64(x) 311 #endif 312 313 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 314 315 #define FOP_FUNC(name) \ 316 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 317 ".type " name ", @function \n\t" \ 318 name ":\n\t" 319 320 #define FOP_RET "ret \n\t" 321 322 #define FOP_START(op) \ 323 extern void em_##op(struct fastop *fake); \ 324 asm(".pushsection .text, \"ax\" \n\t" \ 325 ".global em_" #op " \n\t" \ 326 FOP_FUNC("em_" #op) 327 328 #define FOP_END \ 329 ".popsection") 330 331 #define FOPNOP() \ 332 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \ 333 FOP_RET 334 335 #define FOP1E(op, dst) \ 336 FOP_FUNC(#op "_" #dst) \ 337 "10: " #op " %" #dst " \n\t" FOP_RET 338 339 #define FOP1EEX(op, dst) \ 340 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 341 342 #define FASTOP1(op) \ 343 FOP_START(op) \ 344 FOP1E(op##b, al) \ 345 FOP1E(op##w, ax) \ 346 FOP1E(op##l, eax) \ 347 ON64(FOP1E(op##q, rax)) \ 348 FOP_END 349 350 /* 1-operand, using src2 (for MUL/DIV r/m) */ 351 #define FASTOP1SRC2(op, name) \ 352 FOP_START(name) \ 353 FOP1E(op, cl) \ 354 FOP1E(op, cx) \ 355 FOP1E(op, ecx) \ 356 ON64(FOP1E(op, rcx)) \ 357 FOP_END 358 359 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 360 #define FASTOP1SRC2EX(op, name) \ 361 FOP_START(name) \ 362 FOP1EEX(op, cl) \ 363 FOP1EEX(op, cx) \ 364 FOP1EEX(op, ecx) \ 365 ON64(FOP1EEX(op, rcx)) \ 366 FOP_END 367 368 #define FOP2E(op, dst, src) \ 369 FOP_FUNC(#op "_" #dst "_" #src) \ 370 #op " %" #src ", %" #dst " \n\t" FOP_RET 371 372 #define FASTOP2(op) \ 373 FOP_START(op) \ 374 FOP2E(op##b, al, dl) \ 375 FOP2E(op##w, ax, dx) \ 376 FOP2E(op##l, eax, edx) \ 377 ON64(FOP2E(op##q, rax, rdx)) \ 378 FOP_END 379 380 /* 2 operand, word only */ 381 #define FASTOP2W(op) \ 382 FOP_START(op) \ 383 FOPNOP() \ 384 FOP2E(op##w, ax, dx) \ 385 FOP2E(op##l, eax, edx) \ 386 ON64(FOP2E(op##q, rax, rdx)) \ 387 FOP_END 388 389 /* 2 operand, src is CL */ 390 #define FASTOP2CL(op) \ 391 FOP_START(op) \ 392 FOP2E(op##b, al, cl) \ 393 FOP2E(op##w, ax, cl) \ 394 FOP2E(op##l, eax, cl) \ 395 ON64(FOP2E(op##q, rax, cl)) \ 396 FOP_END 397 398 /* 2 operand, src and dest are reversed */ 399 #define FASTOP2R(op, name) \ 400 FOP_START(name) \ 401 FOP2E(op##b, dl, al) \ 402 FOP2E(op##w, dx, ax) \ 403 FOP2E(op##l, edx, eax) \ 404 ON64(FOP2E(op##q, rdx, rax)) \ 405 FOP_END 406 407 #define FOP3E(op, dst, src, src2) \ 408 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 409 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 410 411 /* 3-operand, word-only, src2=cl */ 412 #define FASTOP3WCL(op) \ 413 FOP_START(op) \ 414 FOPNOP() \ 415 FOP3E(op##w, ax, dx, cl) \ 416 FOP3E(op##l, eax, edx, cl) \ 417 ON64(FOP3E(op##q, rax, rdx, cl)) \ 418 FOP_END 419 420 /* Special case for SETcc - 1 instruction per cc */ 421 #define FOP_SETCC(op) \ 422 ".align 4 \n\t" \ 423 ".type " #op ", @function \n\t" \ 424 #op ": \n\t" \ 425 #op " %al \n\t" \ 426 FOP_RET 427 428 asm(".pushsection .fixup, \"ax\"\n" 429 ".global kvm_fastop_exception \n" 430 "kvm_fastop_exception: xor %esi, %esi; ret\n" 431 ".popsection"); 432 433 FOP_START(setcc) 434 FOP_SETCC(seto) 435 FOP_SETCC(setno) 436 FOP_SETCC(setc) 437 FOP_SETCC(setnc) 438 FOP_SETCC(setz) 439 FOP_SETCC(setnz) 440 FOP_SETCC(setbe) 441 FOP_SETCC(setnbe) 442 FOP_SETCC(sets) 443 FOP_SETCC(setns) 444 FOP_SETCC(setp) 445 FOP_SETCC(setnp) 446 FOP_SETCC(setl) 447 FOP_SETCC(setnl) 448 FOP_SETCC(setle) 449 FOP_SETCC(setnle) 450 FOP_END; 451 452 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 453 FOP_END; 454 455 /* 456 * XXX: inoutclob user must know where the argument is being expanded. 457 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault. 458 */ 459 #define asm_safe(insn, inoutclob...) \ 460 ({ \ 461 int _fault = 0; \ 462 \ 463 asm volatile("1:" insn "\n" \ 464 "2:\n" \ 465 ".pushsection .fixup, \"ax\"\n" \ 466 "3: movl $1, %[_fault]\n" \ 467 " jmp 2b\n" \ 468 ".popsection\n" \ 469 _ASM_EXTABLE(1b, 3b) \ 470 : [_fault] "+qm"(_fault) inoutclob ); \ 471 \ 472 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 473 }) 474 475 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 476 enum x86_intercept intercept, 477 enum x86_intercept_stage stage) 478 { 479 struct x86_instruction_info info = { 480 .intercept = intercept, 481 .rep_prefix = ctxt->rep_prefix, 482 .modrm_mod = ctxt->modrm_mod, 483 .modrm_reg = ctxt->modrm_reg, 484 .modrm_rm = ctxt->modrm_rm, 485 .src_val = ctxt->src.val64, 486 .dst_val = ctxt->dst.val64, 487 .src_bytes = ctxt->src.bytes, 488 .dst_bytes = ctxt->dst.bytes, 489 .ad_bytes = ctxt->ad_bytes, 490 .next_rip = ctxt->eip, 491 }; 492 493 return ctxt->ops->intercept(ctxt, &info, stage); 494 } 495 496 static void assign_masked(ulong *dest, ulong src, ulong mask) 497 { 498 *dest = (*dest & ~mask) | (src & mask); 499 } 500 501 static void assign_register(unsigned long *reg, u64 val, int bytes) 502 { 503 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 504 switch (bytes) { 505 case 1: 506 *(u8 *)reg = (u8)val; 507 break; 508 case 2: 509 *(u16 *)reg = (u16)val; 510 break; 511 case 4: 512 *reg = (u32)val; 513 break; /* 64b: zero-extend */ 514 case 8: 515 *reg = val; 516 break; 517 } 518 } 519 520 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 521 { 522 return (1UL << (ctxt->ad_bytes << 3)) - 1; 523 } 524 525 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 526 { 527 u16 sel; 528 struct desc_struct ss; 529 530 if (ctxt->mode == X86EMUL_MODE_PROT64) 531 return ~0UL; 532 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 533 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 534 } 535 536 static int stack_size(struct x86_emulate_ctxt *ctxt) 537 { 538 return (__fls(stack_mask(ctxt)) + 1) >> 3; 539 } 540 541 /* Access/update address held in a register, based on addressing mode. */ 542 static inline unsigned long 543 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 544 { 545 if (ctxt->ad_bytes == sizeof(unsigned long)) 546 return reg; 547 else 548 return reg & ad_mask(ctxt); 549 } 550 551 static inline unsigned long 552 register_address(struct x86_emulate_ctxt *ctxt, int reg) 553 { 554 return address_mask(ctxt, reg_read(ctxt, reg)); 555 } 556 557 static void masked_increment(ulong *reg, ulong mask, int inc) 558 { 559 assign_masked(reg, *reg + inc, mask); 560 } 561 562 static inline void 563 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 564 { 565 ulong *preg = reg_rmw(ctxt, reg); 566 567 assign_register(preg, *preg + inc, ctxt->ad_bytes); 568 } 569 570 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 571 { 572 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 573 } 574 575 static u32 desc_limit_scaled(struct desc_struct *desc) 576 { 577 u32 limit = get_desc_limit(desc); 578 579 return desc->g ? (limit << 12) | 0xfff : limit; 580 } 581 582 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 583 { 584 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 585 return 0; 586 587 return ctxt->ops->get_cached_segment_base(ctxt, seg); 588 } 589 590 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 591 u32 error, bool valid) 592 { 593 WARN_ON(vec > 0x1f); 594 ctxt->exception.vector = vec; 595 ctxt->exception.error_code = error; 596 ctxt->exception.error_code_valid = valid; 597 return X86EMUL_PROPAGATE_FAULT; 598 } 599 600 static int emulate_db(struct x86_emulate_ctxt *ctxt) 601 { 602 return emulate_exception(ctxt, DB_VECTOR, 0, false); 603 } 604 605 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 606 { 607 return emulate_exception(ctxt, GP_VECTOR, err, true); 608 } 609 610 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 611 { 612 return emulate_exception(ctxt, SS_VECTOR, err, true); 613 } 614 615 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 616 { 617 return emulate_exception(ctxt, UD_VECTOR, 0, false); 618 } 619 620 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 621 { 622 return emulate_exception(ctxt, TS_VECTOR, err, true); 623 } 624 625 static int emulate_de(struct x86_emulate_ctxt *ctxt) 626 { 627 return emulate_exception(ctxt, DE_VECTOR, 0, false); 628 } 629 630 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 631 { 632 return emulate_exception(ctxt, NM_VECTOR, 0, false); 633 } 634 635 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 636 { 637 u16 selector; 638 struct desc_struct desc; 639 640 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 641 return selector; 642 } 643 644 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 645 unsigned seg) 646 { 647 u16 dummy; 648 u32 base3; 649 struct desc_struct desc; 650 651 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 652 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 653 } 654 655 /* 656 * x86 defines three classes of vector instructions: explicitly 657 * aligned, explicitly unaligned, and the rest, which change behaviour 658 * depending on whether they're AVX encoded or not. 659 * 660 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 661 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 662 * 512 bytes of data must be aligned to a 16 byte boundary. 663 */ 664 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 665 { 666 u64 alignment = ctxt->d & AlignMask; 667 668 if (likely(size < 16)) 669 return 1; 670 671 switch (alignment) { 672 case Unaligned: 673 case Avx: 674 return 1; 675 case Aligned16: 676 return 16; 677 case Aligned: 678 default: 679 return size; 680 } 681 } 682 683 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 684 struct segmented_address addr, 685 unsigned *max_size, unsigned size, 686 bool write, bool fetch, 687 enum x86emul_mode mode, ulong *linear) 688 { 689 struct desc_struct desc; 690 bool usable; 691 ulong la; 692 u32 lim; 693 u16 sel; 694 u8 va_bits; 695 696 la = seg_base(ctxt, addr.seg) + addr.ea; 697 *max_size = 0; 698 switch (mode) { 699 case X86EMUL_MODE_PROT64: 700 *linear = la; 701 va_bits = ctxt_virt_addr_bits(ctxt); 702 if (get_canonical(la, va_bits) != la) 703 goto bad; 704 705 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 706 if (size > *max_size) 707 goto bad; 708 break; 709 default: 710 *linear = la = (u32)la; 711 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 712 addr.seg); 713 if (!usable) 714 goto bad; 715 /* code segment in protected mode or read-only data segment */ 716 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 717 || !(desc.type & 2)) && write) 718 goto bad; 719 /* unreadable code segment */ 720 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 721 goto bad; 722 lim = desc_limit_scaled(&desc); 723 if (!(desc.type & 8) && (desc.type & 4)) { 724 /* expand-down segment */ 725 if (addr.ea <= lim) 726 goto bad; 727 lim = desc.d ? 0xffffffff : 0xffff; 728 } 729 if (addr.ea > lim) 730 goto bad; 731 if (lim == 0xffffffff) 732 *max_size = ~0u; 733 else { 734 *max_size = (u64)lim + 1 - addr.ea; 735 if (size > *max_size) 736 goto bad; 737 } 738 break; 739 } 740 if (la & (insn_alignment(ctxt, size) - 1)) 741 return emulate_gp(ctxt, 0); 742 return X86EMUL_CONTINUE; 743 bad: 744 if (addr.seg == VCPU_SREG_SS) 745 return emulate_ss(ctxt, 0); 746 else 747 return emulate_gp(ctxt, 0); 748 } 749 750 static int linearize(struct x86_emulate_ctxt *ctxt, 751 struct segmented_address addr, 752 unsigned size, bool write, 753 ulong *linear) 754 { 755 unsigned max_size; 756 return __linearize(ctxt, addr, &max_size, size, write, false, 757 ctxt->mode, linear); 758 } 759 760 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, 761 enum x86emul_mode mode) 762 { 763 ulong linear; 764 int rc; 765 unsigned max_size; 766 struct segmented_address addr = { .seg = VCPU_SREG_CS, 767 .ea = dst }; 768 769 if (ctxt->op_bytes != sizeof(unsigned long)) 770 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 771 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); 772 if (rc == X86EMUL_CONTINUE) 773 ctxt->_eip = addr.ea; 774 return rc; 775 } 776 777 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 778 { 779 return assign_eip(ctxt, dst, ctxt->mode); 780 } 781 782 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, 783 const struct desc_struct *cs_desc) 784 { 785 enum x86emul_mode mode = ctxt->mode; 786 int rc; 787 788 #ifdef CONFIG_X86_64 789 if (ctxt->mode >= X86EMUL_MODE_PROT16) { 790 if (cs_desc->l) { 791 u64 efer = 0; 792 793 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 794 if (efer & EFER_LMA) 795 mode = X86EMUL_MODE_PROT64; 796 } else 797 mode = X86EMUL_MODE_PROT32; /* temporary value */ 798 } 799 #endif 800 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) 801 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 802 rc = assign_eip(ctxt, dst, mode); 803 if (rc == X86EMUL_CONTINUE) 804 ctxt->mode = mode; 805 return rc; 806 } 807 808 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 809 { 810 return assign_eip_near(ctxt, ctxt->_eip + rel); 811 } 812 813 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 814 void *data, unsigned size) 815 { 816 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 817 } 818 819 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 820 ulong linear, void *data, 821 unsigned int size) 822 { 823 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 824 } 825 826 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 827 struct segmented_address addr, 828 void *data, 829 unsigned size) 830 { 831 int rc; 832 ulong linear; 833 834 rc = linearize(ctxt, addr, size, false, &linear); 835 if (rc != X86EMUL_CONTINUE) 836 return rc; 837 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 838 } 839 840 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 841 struct segmented_address addr, 842 void *data, 843 unsigned int size) 844 { 845 int rc; 846 ulong linear; 847 848 rc = linearize(ctxt, addr, size, true, &linear); 849 if (rc != X86EMUL_CONTINUE) 850 return rc; 851 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 852 } 853 854 /* 855 * Prefetch the remaining bytes of the instruction without crossing page 856 * boundary if they are not in fetch_cache yet. 857 */ 858 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 859 { 860 int rc; 861 unsigned size, max_size; 862 unsigned long linear; 863 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 864 struct segmented_address addr = { .seg = VCPU_SREG_CS, 865 .ea = ctxt->eip + cur_size }; 866 867 /* 868 * We do not know exactly how many bytes will be needed, and 869 * __linearize is expensive, so fetch as much as possible. We 870 * just have to avoid going beyond the 15 byte limit, the end 871 * of the segment, or the end of the page. 872 * 873 * __linearize is called with size 0 so that it does not do any 874 * boundary check itself. Instead, we use max_size to check 875 * against op_size. 876 */ 877 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 878 &linear); 879 if (unlikely(rc != X86EMUL_CONTINUE)) 880 return rc; 881 882 size = min_t(unsigned, 15UL ^ cur_size, max_size); 883 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 884 885 /* 886 * One instruction can only straddle two pages, 887 * and one has been loaded at the beginning of 888 * x86_decode_insn. So, if not enough bytes 889 * still, we must have hit the 15-byte boundary. 890 */ 891 if (unlikely(size < op_size)) 892 return emulate_gp(ctxt, 0); 893 894 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 895 size, &ctxt->exception); 896 if (unlikely(rc != X86EMUL_CONTINUE)) 897 return rc; 898 ctxt->fetch.end += size; 899 return X86EMUL_CONTINUE; 900 } 901 902 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 903 unsigned size) 904 { 905 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 906 907 if (unlikely(done_size < size)) 908 return __do_insn_fetch_bytes(ctxt, size - done_size); 909 else 910 return X86EMUL_CONTINUE; 911 } 912 913 /* Fetch next part of the instruction being emulated. */ 914 #define insn_fetch(_type, _ctxt) \ 915 ({ _type _x; \ 916 \ 917 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 918 if (rc != X86EMUL_CONTINUE) \ 919 goto done; \ 920 ctxt->_eip += sizeof(_type); \ 921 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 922 ctxt->fetch.ptr += sizeof(_type); \ 923 _x; \ 924 }) 925 926 #define insn_fetch_arr(_arr, _size, _ctxt) \ 927 ({ \ 928 rc = do_insn_fetch_bytes(_ctxt, _size); \ 929 if (rc != X86EMUL_CONTINUE) \ 930 goto done; \ 931 ctxt->_eip += (_size); \ 932 memcpy(_arr, ctxt->fetch.ptr, _size); \ 933 ctxt->fetch.ptr += (_size); \ 934 }) 935 936 /* 937 * Given the 'reg' portion of a ModRM byte, and a register block, return a 938 * pointer into the block that addresses the relevant register. 939 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 940 */ 941 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 942 int byteop) 943 { 944 void *p; 945 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 946 947 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 948 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 949 else 950 p = reg_rmw(ctxt, modrm_reg); 951 return p; 952 } 953 954 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 955 struct segmented_address addr, 956 u16 *size, unsigned long *address, int op_bytes) 957 { 958 int rc; 959 960 if (op_bytes == 2) 961 op_bytes = 3; 962 *address = 0; 963 rc = segmented_read_std(ctxt, addr, size, 2); 964 if (rc != X86EMUL_CONTINUE) 965 return rc; 966 addr.ea += 2; 967 rc = segmented_read_std(ctxt, addr, address, op_bytes); 968 return rc; 969 } 970 971 FASTOP2(add); 972 FASTOP2(or); 973 FASTOP2(adc); 974 FASTOP2(sbb); 975 FASTOP2(and); 976 FASTOP2(sub); 977 FASTOP2(xor); 978 FASTOP2(cmp); 979 FASTOP2(test); 980 981 FASTOP1SRC2(mul, mul_ex); 982 FASTOP1SRC2(imul, imul_ex); 983 FASTOP1SRC2EX(div, div_ex); 984 FASTOP1SRC2EX(idiv, idiv_ex); 985 986 FASTOP3WCL(shld); 987 FASTOP3WCL(shrd); 988 989 FASTOP2W(imul); 990 991 FASTOP1(not); 992 FASTOP1(neg); 993 FASTOP1(inc); 994 FASTOP1(dec); 995 996 FASTOP2CL(rol); 997 FASTOP2CL(ror); 998 FASTOP2CL(rcl); 999 FASTOP2CL(rcr); 1000 FASTOP2CL(shl); 1001 FASTOP2CL(shr); 1002 FASTOP2CL(sar); 1003 1004 FASTOP2W(bsf); 1005 FASTOP2W(bsr); 1006 FASTOP2W(bt); 1007 FASTOP2W(bts); 1008 FASTOP2W(btr); 1009 FASTOP2W(btc); 1010 1011 FASTOP2(xadd); 1012 1013 FASTOP2R(cmp, cmp_r); 1014 1015 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1016 { 1017 /* If src is zero, do not writeback, but update flags */ 1018 if (ctxt->src.val == 0) 1019 ctxt->dst.type = OP_NONE; 1020 return fastop(ctxt, em_bsf); 1021 } 1022 1023 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1024 { 1025 /* If src is zero, do not writeback, but update flags */ 1026 if (ctxt->src.val == 0) 1027 ctxt->dst.type = OP_NONE; 1028 return fastop(ctxt, em_bsr); 1029 } 1030 1031 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1032 { 1033 u8 rc; 1034 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 1035 1036 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1037 asm("push %[flags]; popf; " CALL_NOSPEC 1038 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1039 return rc; 1040 } 1041 1042 static void fetch_register_operand(struct operand *op) 1043 { 1044 switch (op->bytes) { 1045 case 1: 1046 op->val = *(u8 *)op->addr.reg; 1047 break; 1048 case 2: 1049 op->val = *(u16 *)op->addr.reg; 1050 break; 1051 case 4: 1052 op->val = *(u32 *)op->addr.reg; 1053 break; 1054 case 8: 1055 op->val = *(u64 *)op->addr.reg; 1056 break; 1057 } 1058 } 1059 1060 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 1061 { 1062 switch (reg) { 1063 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 1064 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 1065 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 1066 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 1067 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 1068 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 1069 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 1070 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1071 #ifdef CONFIG_X86_64 1072 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1073 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1074 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1075 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1076 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1077 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1078 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1079 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1080 #endif 1081 default: BUG(); 1082 } 1083 } 1084 1085 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 1086 int reg) 1087 { 1088 switch (reg) { 1089 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1090 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1091 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1092 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1093 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1094 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1095 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1096 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1097 #ifdef CONFIG_X86_64 1098 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1099 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1100 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1101 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1102 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1103 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1104 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1105 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1106 #endif 1107 default: BUG(); 1108 } 1109 } 1110 1111 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1112 { 1113 switch (reg) { 1114 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1115 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1116 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1117 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1118 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1119 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1120 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1121 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1122 default: BUG(); 1123 } 1124 } 1125 1126 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1127 { 1128 switch (reg) { 1129 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1130 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1131 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1132 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1133 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1134 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1135 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1136 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1137 default: BUG(); 1138 } 1139 } 1140 1141 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1142 { 1143 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1144 return emulate_nm(ctxt); 1145 1146 asm volatile("fninit"); 1147 return X86EMUL_CONTINUE; 1148 } 1149 1150 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1151 { 1152 u16 fcw; 1153 1154 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1155 return emulate_nm(ctxt); 1156 1157 asm volatile("fnstcw %0": "+m"(fcw)); 1158 1159 ctxt->dst.val = fcw; 1160 1161 return X86EMUL_CONTINUE; 1162 } 1163 1164 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1165 { 1166 u16 fsw; 1167 1168 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1169 return emulate_nm(ctxt); 1170 1171 asm volatile("fnstsw %0": "+m"(fsw)); 1172 1173 ctxt->dst.val = fsw; 1174 1175 return X86EMUL_CONTINUE; 1176 } 1177 1178 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1179 struct operand *op) 1180 { 1181 unsigned reg = ctxt->modrm_reg; 1182 1183 if (!(ctxt->d & ModRM)) 1184 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1185 1186 if (ctxt->d & Sse) { 1187 op->type = OP_XMM; 1188 op->bytes = 16; 1189 op->addr.xmm = reg; 1190 read_sse_reg(ctxt, &op->vec_val, reg); 1191 return; 1192 } 1193 if (ctxt->d & Mmx) { 1194 reg &= 7; 1195 op->type = OP_MM; 1196 op->bytes = 8; 1197 op->addr.mm = reg; 1198 return; 1199 } 1200 1201 op->type = OP_REG; 1202 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1203 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1204 1205 fetch_register_operand(op); 1206 op->orig_val = op->val; 1207 } 1208 1209 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1210 { 1211 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1212 ctxt->modrm_seg = VCPU_SREG_SS; 1213 } 1214 1215 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1216 struct operand *op) 1217 { 1218 u8 sib; 1219 int index_reg, base_reg, scale; 1220 int rc = X86EMUL_CONTINUE; 1221 ulong modrm_ea = 0; 1222 1223 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1224 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1225 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1226 1227 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1228 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1229 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1230 ctxt->modrm_seg = VCPU_SREG_DS; 1231 1232 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1233 op->type = OP_REG; 1234 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1235 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1236 ctxt->d & ByteOp); 1237 if (ctxt->d & Sse) { 1238 op->type = OP_XMM; 1239 op->bytes = 16; 1240 op->addr.xmm = ctxt->modrm_rm; 1241 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1242 return rc; 1243 } 1244 if (ctxt->d & Mmx) { 1245 op->type = OP_MM; 1246 op->bytes = 8; 1247 op->addr.mm = ctxt->modrm_rm & 7; 1248 return rc; 1249 } 1250 fetch_register_operand(op); 1251 return rc; 1252 } 1253 1254 op->type = OP_MEM; 1255 1256 if (ctxt->ad_bytes == 2) { 1257 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1258 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1259 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1260 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1261 1262 /* 16-bit ModR/M decode. */ 1263 switch (ctxt->modrm_mod) { 1264 case 0: 1265 if (ctxt->modrm_rm == 6) 1266 modrm_ea += insn_fetch(u16, ctxt); 1267 break; 1268 case 1: 1269 modrm_ea += insn_fetch(s8, ctxt); 1270 break; 1271 case 2: 1272 modrm_ea += insn_fetch(u16, ctxt); 1273 break; 1274 } 1275 switch (ctxt->modrm_rm) { 1276 case 0: 1277 modrm_ea += bx + si; 1278 break; 1279 case 1: 1280 modrm_ea += bx + di; 1281 break; 1282 case 2: 1283 modrm_ea += bp + si; 1284 break; 1285 case 3: 1286 modrm_ea += bp + di; 1287 break; 1288 case 4: 1289 modrm_ea += si; 1290 break; 1291 case 5: 1292 modrm_ea += di; 1293 break; 1294 case 6: 1295 if (ctxt->modrm_mod != 0) 1296 modrm_ea += bp; 1297 break; 1298 case 7: 1299 modrm_ea += bx; 1300 break; 1301 } 1302 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1303 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1304 ctxt->modrm_seg = VCPU_SREG_SS; 1305 modrm_ea = (u16)modrm_ea; 1306 } else { 1307 /* 32/64-bit ModR/M decode. */ 1308 if ((ctxt->modrm_rm & 7) == 4) { 1309 sib = insn_fetch(u8, ctxt); 1310 index_reg |= (sib >> 3) & 7; 1311 base_reg |= sib & 7; 1312 scale = sib >> 6; 1313 1314 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1315 modrm_ea += insn_fetch(s32, ctxt); 1316 else { 1317 modrm_ea += reg_read(ctxt, base_reg); 1318 adjust_modrm_seg(ctxt, base_reg); 1319 /* Increment ESP on POP [ESP] */ 1320 if ((ctxt->d & IncSP) && 1321 base_reg == VCPU_REGS_RSP) 1322 modrm_ea += ctxt->op_bytes; 1323 } 1324 if (index_reg != 4) 1325 modrm_ea += reg_read(ctxt, index_reg) << scale; 1326 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1327 modrm_ea += insn_fetch(s32, ctxt); 1328 if (ctxt->mode == X86EMUL_MODE_PROT64) 1329 ctxt->rip_relative = 1; 1330 } else { 1331 base_reg = ctxt->modrm_rm; 1332 modrm_ea += reg_read(ctxt, base_reg); 1333 adjust_modrm_seg(ctxt, base_reg); 1334 } 1335 switch (ctxt->modrm_mod) { 1336 case 1: 1337 modrm_ea += insn_fetch(s8, ctxt); 1338 break; 1339 case 2: 1340 modrm_ea += insn_fetch(s32, ctxt); 1341 break; 1342 } 1343 } 1344 op->addr.mem.ea = modrm_ea; 1345 if (ctxt->ad_bytes != 8) 1346 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1347 1348 done: 1349 return rc; 1350 } 1351 1352 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1353 struct operand *op) 1354 { 1355 int rc = X86EMUL_CONTINUE; 1356 1357 op->type = OP_MEM; 1358 switch (ctxt->ad_bytes) { 1359 case 2: 1360 op->addr.mem.ea = insn_fetch(u16, ctxt); 1361 break; 1362 case 4: 1363 op->addr.mem.ea = insn_fetch(u32, ctxt); 1364 break; 1365 case 8: 1366 op->addr.mem.ea = insn_fetch(u64, ctxt); 1367 break; 1368 } 1369 done: 1370 return rc; 1371 } 1372 1373 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1374 { 1375 long sv = 0, mask; 1376 1377 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1378 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1379 1380 if (ctxt->src.bytes == 2) 1381 sv = (s16)ctxt->src.val & (s16)mask; 1382 else if (ctxt->src.bytes == 4) 1383 sv = (s32)ctxt->src.val & (s32)mask; 1384 else 1385 sv = (s64)ctxt->src.val & (s64)mask; 1386 1387 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1388 ctxt->dst.addr.mem.ea + (sv >> 3)); 1389 } 1390 1391 /* only subword offset */ 1392 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1393 } 1394 1395 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1396 unsigned long addr, void *dest, unsigned size) 1397 { 1398 int rc; 1399 struct read_cache *mc = &ctxt->mem_read; 1400 1401 if (mc->pos < mc->end) 1402 goto read_cached; 1403 1404 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1405 1406 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1407 &ctxt->exception); 1408 if (rc != X86EMUL_CONTINUE) 1409 return rc; 1410 1411 mc->end += size; 1412 1413 read_cached: 1414 memcpy(dest, mc->data + mc->pos, size); 1415 mc->pos += size; 1416 return X86EMUL_CONTINUE; 1417 } 1418 1419 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1420 struct segmented_address addr, 1421 void *data, 1422 unsigned size) 1423 { 1424 int rc; 1425 ulong linear; 1426 1427 rc = linearize(ctxt, addr, size, false, &linear); 1428 if (rc != X86EMUL_CONTINUE) 1429 return rc; 1430 return read_emulated(ctxt, linear, data, size); 1431 } 1432 1433 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1434 struct segmented_address addr, 1435 const void *data, 1436 unsigned size) 1437 { 1438 int rc; 1439 ulong linear; 1440 1441 rc = linearize(ctxt, addr, size, true, &linear); 1442 if (rc != X86EMUL_CONTINUE) 1443 return rc; 1444 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1445 &ctxt->exception); 1446 } 1447 1448 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1449 struct segmented_address addr, 1450 const void *orig_data, const void *data, 1451 unsigned size) 1452 { 1453 int rc; 1454 ulong linear; 1455 1456 rc = linearize(ctxt, addr, size, true, &linear); 1457 if (rc != X86EMUL_CONTINUE) 1458 return rc; 1459 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1460 size, &ctxt->exception); 1461 } 1462 1463 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1464 unsigned int size, unsigned short port, 1465 void *dest) 1466 { 1467 struct read_cache *rc = &ctxt->io_read; 1468 1469 if (rc->pos == rc->end) { /* refill pio read ahead */ 1470 unsigned int in_page, n; 1471 unsigned int count = ctxt->rep_prefix ? 1472 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1473 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1474 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1475 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1476 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1477 if (n == 0) 1478 n = 1; 1479 rc->pos = rc->end = 0; 1480 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1481 return 0; 1482 rc->end = n * size; 1483 } 1484 1485 if (ctxt->rep_prefix && (ctxt->d & String) && 1486 !(ctxt->eflags & X86_EFLAGS_DF)) { 1487 ctxt->dst.data = rc->data + rc->pos; 1488 ctxt->dst.type = OP_MEM_STR; 1489 ctxt->dst.count = (rc->end - rc->pos) / size; 1490 rc->pos = rc->end; 1491 } else { 1492 memcpy(dest, rc->data + rc->pos, size); 1493 rc->pos += size; 1494 } 1495 return 1; 1496 } 1497 1498 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1499 u16 index, struct desc_struct *desc) 1500 { 1501 struct desc_ptr dt; 1502 ulong addr; 1503 1504 ctxt->ops->get_idt(ctxt, &dt); 1505 1506 if (dt.size < index * 8 + 7) 1507 return emulate_gp(ctxt, index << 3 | 0x2); 1508 1509 addr = dt.address + index * 8; 1510 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1511 } 1512 1513 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1514 u16 selector, struct desc_ptr *dt) 1515 { 1516 const struct x86_emulate_ops *ops = ctxt->ops; 1517 u32 base3 = 0; 1518 1519 if (selector & 1 << 2) { 1520 struct desc_struct desc; 1521 u16 sel; 1522 1523 memset(dt, 0, sizeof(*dt)); 1524 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1525 VCPU_SREG_LDTR)) 1526 return; 1527 1528 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1529 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1530 } else 1531 ops->get_gdt(ctxt, dt); 1532 } 1533 1534 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1535 u16 selector, ulong *desc_addr_p) 1536 { 1537 struct desc_ptr dt; 1538 u16 index = selector >> 3; 1539 ulong addr; 1540 1541 get_descriptor_table_ptr(ctxt, selector, &dt); 1542 1543 if (dt.size < index * 8 + 7) 1544 return emulate_gp(ctxt, selector & 0xfffc); 1545 1546 addr = dt.address + index * 8; 1547 1548 #ifdef CONFIG_X86_64 1549 if (addr >> 32 != 0) { 1550 u64 efer = 0; 1551 1552 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1553 if (!(efer & EFER_LMA)) 1554 addr &= (u32)-1; 1555 } 1556 #endif 1557 1558 *desc_addr_p = addr; 1559 return X86EMUL_CONTINUE; 1560 } 1561 1562 /* allowed just for 8 bytes segments */ 1563 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1564 u16 selector, struct desc_struct *desc, 1565 ulong *desc_addr_p) 1566 { 1567 int rc; 1568 1569 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1570 if (rc != X86EMUL_CONTINUE) 1571 return rc; 1572 1573 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1574 } 1575 1576 /* allowed just for 8 bytes segments */ 1577 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1578 u16 selector, struct desc_struct *desc) 1579 { 1580 int rc; 1581 ulong addr; 1582 1583 rc = get_descriptor_ptr(ctxt, selector, &addr); 1584 if (rc != X86EMUL_CONTINUE) 1585 return rc; 1586 1587 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1588 } 1589 1590 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1591 u16 selector, int seg, u8 cpl, 1592 enum x86_transfer_type transfer, 1593 struct desc_struct *desc) 1594 { 1595 struct desc_struct seg_desc, old_desc; 1596 u8 dpl, rpl; 1597 unsigned err_vec = GP_VECTOR; 1598 u32 err_code = 0; 1599 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1600 ulong desc_addr; 1601 int ret; 1602 u16 dummy; 1603 u32 base3 = 0; 1604 1605 memset(&seg_desc, 0, sizeof(seg_desc)); 1606 1607 if (ctxt->mode == X86EMUL_MODE_REAL) { 1608 /* set real mode segment descriptor (keep limit etc. for 1609 * unreal mode) */ 1610 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1611 set_desc_base(&seg_desc, selector << 4); 1612 goto load; 1613 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1614 /* VM86 needs a clean new segment descriptor */ 1615 set_desc_base(&seg_desc, selector << 4); 1616 set_desc_limit(&seg_desc, 0xffff); 1617 seg_desc.type = 3; 1618 seg_desc.p = 1; 1619 seg_desc.s = 1; 1620 seg_desc.dpl = 3; 1621 goto load; 1622 } 1623 1624 rpl = selector & 3; 1625 1626 /* TR should be in GDT only */ 1627 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1628 goto exception; 1629 1630 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1631 if (null_selector) { 1632 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1633 goto exception; 1634 1635 if (seg == VCPU_SREG_SS) { 1636 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1637 goto exception; 1638 1639 /* 1640 * ctxt->ops->set_segment expects the CPL to be in 1641 * SS.DPL, so fake an expand-up 32-bit data segment. 1642 */ 1643 seg_desc.type = 3; 1644 seg_desc.p = 1; 1645 seg_desc.s = 1; 1646 seg_desc.dpl = cpl; 1647 seg_desc.d = 1; 1648 seg_desc.g = 1; 1649 } 1650 1651 /* Skip all following checks */ 1652 goto load; 1653 } 1654 1655 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1656 if (ret != X86EMUL_CONTINUE) 1657 return ret; 1658 1659 err_code = selector & 0xfffc; 1660 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1661 GP_VECTOR; 1662 1663 /* can't load system descriptor into segment selector */ 1664 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1665 if (transfer == X86_TRANSFER_CALL_JMP) 1666 return X86EMUL_UNHANDLEABLE; 1667 goto exception; 1668 } 1669 1670 if (!seg_desc.p) { 1671 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1672 goto exception; 1673 } 1674 1675 dpl = seg_desc.dpl; 1676 1677 switch (seg) { 1678 case VCPU_SREG_SS: 1679 /* 1680 * segment is not a writable data segment or segment 1681 * selector's RPL != CPL or segment selector's RPL != CPL 1682 */ 1683 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1684 goto exception; 1685 break; 1686 case VCPU_SREG_CS: 1687 if (!(seg_desc.type & 8)) 1688 goto exception; 1689 1690 if (seg_desc.type & 4) { 1691 /* conforming */ 1692 if (dpl > cpl) 1693 goto exception; 1694 } else { 1695 /* nonconforming */ 1696 if (rpl > cpl || dpl != cpl) 1697 goto exception; 1698 } 1699 /* in long-mode d/b must be clear if l is set */ 1700 if (seg_desc.d && seg_desc.l) { 1701 u64 efer = 0; 1702 1703 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1704 if (efer & EFER_LMA) 1705 goto exception; 1706 } 1707 1708 /* CS(RPL) <- CPL */ 1709 selector = (selector & 0xfffc) | cpl; 1710 break; 1711 case VCPU_SREG_TR: 1712 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1713 goto exception; 1714 old_desc = seg_desc; 1715 seg_desc.type |= 2; /* busy */ 1716 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1717 sizeof(seg_desc), &ctxt->exception); 1718 if (ret != X86EMUL_CONTINUE) 1719 return ret; 1720 break; 1721 case VCPU_SREG_LDTR: 1722 if (seg_desc.s || seg_desc.type != 2) 1723 goto exception; 1724 break; 1725 default: /* DS, ES, FS, or GS */ 1726 /* 1727 * segment is not a data or readable code segment or 1728 * ((segment is a data or nonconforming code segment) 1729 * and (both RPL and CPL > DPL)) 1730 */ 1731 if ((seg_desc.type & 0xa) == 0x8 || 1732 (((seg_desc.type & 0xc) != 0xc) && 1733 (rpl > dpl && cpl > dpl))) 1734 goto exception; 1735 break; 1736 } 1737 1738 if (seg_desc.s) { 1739 /* mark segment as accessed */ 1740 if (!(seg_desc.type & 1)) { 1741 seg_desc.type |= 1; 1742 ret = write_segment_descriptor(ctxt, selector, 1743 &seg_desc); 1744 if (ret != X86EMUL_CONTINUE) 1745 return ret; 1746 } 1747 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1748 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1749 if (ret != X86EMUL_CONTINUE) 1750 return ret; 1751 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1752 ((u64)base3 << 32), ctxt)) 1753 return emulate_gp(ctxt, 0); 1754 } 1755 load: 1756 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1757 if (desc) 1758 *desc = seg_desc; 1759 return X86EMUL_CONTINUE; 1760 exception: 1761 return emulate_exception(ctxt, err_vec, err_code, true); 1762 } 1763 1764 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1765 u16 selector, int seg) 1766 { 1767 u8 cpl = ctxt->ops->cpl(ctxt); 1768 1769 /* 1770 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1771 * they can load it at CPL<3 (Intel's manual says only LSS can, 1772 * but it's wrong). 1773 * 1774 * However, the Intel manual says that putting IST=1/DPL=3 in 1775 * an interrupt gate will result in SS=3 (the AMD manual instead 1776 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1777 * and only forbid it here. 1778 */ 1779 if (seg == VCPU_SREG_SS && selector == 3 && 1780 ctxt->mode == X86EMUL_MODE_PROT64) 1781 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1782 1783 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1784 X86_TRANSFER_NONE, NULL); 1785 } 1786 1787 static void write_register_operand(struct operand *op) 1788 { 1789 return assign_register(op->addr.reg, op->val, op->bytes); 1790 } 1791 1792 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1793 { 1794 switch (op->type) { 1795 case OP_REG: 1796 write_register_operand(op); 1797 break; 1798 case OP_MEM: 1799 if (ctxt->lock_prefix) 1800 return segmented_cmpxchg(ctxt, 1801 op->addr.mem, 1802 &op->orig_val, 1803 &op->val, 1804 op->bytes); 1805 else 1806 return segmented_write(ctxt, 1807 op->addr.mem, 1808 &op->val, 1809 op->bytes); 1810 break; 1811 case OP_MEM_STR: 1812 return segmented_write(ctxt, 1813 op->addr.mem, 1814 op->data, 1815 op->bytes * op->count); 1816 break; 1817 case OP_XMM: 1818 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); 1819 break; 1820 case OP_MM: 1821 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 1822 break; 1823 case OP_NONE: 1824 /* no writeback */ 1825 break; 1826 default: 1827 break; 1828 } 1829 return X86EMUL_CONTINUE; 1830 } 1831 1832 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1833 { 1834 struct segmented_address addr; 1835 1836 rsp_increment(ctxt, -bytes); 1837 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1838 addr.seg = VCPU_SREG_SS; 1839 1840 return segmented_write(ctxt, addr, data, bytes); 1841 } 1842 1843 static int em_push(struct x86_emulate_ctxt *ctxt) 1844 { 1845 /* Disable writeback. */ 1846 ctxt->dst.type = OP_NONE; 1847 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1848 } 1849 1850 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1851 void *dest, int len) 1852 { 1853 int rc; 1854 struct segmented_address addr; 1855 1856 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1857 addr.seg = VCPU_SREG_SS; 1858 rc = segmented_read(ctxt, addr, dest, len); 1859 if (rc != X86EMUL_CONTINUE) 1860 return rc; 1861 1862 rsp_increment(ctxt, len); 1863 return rc; 1864 } 1865 1866 static int em_pop(struct x86_emulate_ctxt *ctxt) 1867 { 1868 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1869 } 1870 1871 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1872 void *dest, int len) 1873 { 1874 int rc; 1875 unsigned long val, change_mask; 1876 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1877 int cpl = ctxt->ops->cpl(ctxt); 1878 1879 rc = emulate_pop(ctxt, &val, len); 1880 if (rc != X86EMUL_CONTINUE) 1881 return rc; 1882 1883 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1884 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1885 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1886 X86_EFLAGS_AC | X86_EFLAGS_ID; 1887 1888 switch(ctxt->mode) { 1889 case X86EMUL_MODE_PROT64: 1890 case X86EMUL_MODE_PROT32: 1891 case X86EMUL_MODE_PROT16: 1892 if (cpl == 0) 1893 change_mask |= X86_EFLAGS_IOPL; 1894 if (cpl <= iopl) 1895 change_mask |= X86_EFLAGS_IF; 1896 break; 1897 case X86EMUL_MODE_VM86: 1898 if (iopl < 3) 1899 return emulate_gp(ctxt, 0); 1900 change_mask |= X86_EFLAGS_IF; 1901 break; 1902 default: /* real mode */ 1903 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1904 break; 1905 } 1906 1907 *(unsigned long *)dest = 1908 (ctxt->eflags & ~change_mask) | (val & change_mask); 1909 1910 return rc; 1911 } 1912 1913 static int em_popf(struct x86_emulate_ctxt *ctxt) 1914 { 1915 ctxt->dst.type = OP_REG; 1916 ctxt->dst.addr.reg = &ctxt->eflags; 1917 ctxt->dst.bytes = ctxt->op_bytes; 1918 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1919 } 1920 1921 static int em_enter(struct x86_emulate_ctxt *ctxt) 1922 { 1923 int rc; 1924 unsigned frame_size = ctxt->src.val; 1925 unsigned nesting_level = ctxt->src2.val & 31; 1926 ulong rbp; 1927 1928 if (nesting_level) 1929 return X86EMUL_UNHANDLEABLE; 1930 1931 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1932 rc = push(ctxt, &rbp, stack_size(ctxt)); 1933 if (rc != X86EMUL_CONTINUE) 1934 return rc; 1935 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1936 stack_mask(ctxt)); 1937 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1938 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1939 stack_mask(ctxt)); 1940 return X86EMUL_CONTINUE; 1941 } 1942 1943 static int em_leave(struct x86_emulate_ctxt *ctxt) 1944 { 1945 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1946 stack_mask(ctxt)); 1947 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1948 } 1949 1950 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1951 { 1952 int seg = ctxt->src2.val; 1953 1954 ctxt->src.val = get_segment_selector(ctxt, seg); 1955 if (ctxt->op_bytes == 4) { 1956 rsp_increment(ctxt, -2); 1957 ctxt->op_bytes = 2; 1958 } 1959 1960 return em_push(ctxt); 1961 } 1962 1963 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1964 { 1965 int seg = ctxt->src2.val; 1966 unsigned long selector; 1967 int rc; 1968 1969 rc = emulate_pop(ctxt, &selector, 2); 1970 if (rc != X86EMUL_CONTINUE) 1971 return rc; 1972 1973 if (ctxt->modrm_reg == VCPU_SREG_SS) 1974 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1975 if (ctxt->op_bytes > 2) 1976 rsp_increment(ctxt, ctxt->op_bytes - 2); 1977 1978 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1979 return rc; 1980 } 1981 1982 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1983 { 1984 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1985 int rc = X86EMUL_CONTINUE; 1986 int reg = VCPU_REGS_RAX; 1987 1988 while (reg <= VCPU_REGS_RDI) { 1989 (reg == VCPU_REGS_RSP) ? 1990 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1991 1992 rc = em_push(ctxt); 1993 if (rc != X86EMUL_CONTINUE) 1994 return rc; 1995 1996 ++reg; 1997 } 1998 1999 return rc; 2000 } 2001 2002 static int em_pushf(struct x86_emulate_ctxt *ctxt) 2003 { 2004 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 2005 return em_push(ctxt); 2006 } 2007 2008 static int em_popa(struct x86_emulate_ctxt *ctxt) 2009 { 2010 int rc = X86EMUL_CONTINUE; 2011 int reg = VCPU_REGS_RDI; 2012 u32 val; 2013 2014 while (reg >= VCPU_REGS_RAX) { 2015 if (reg == VCPU_REGS_RSP) { 2016 rsp_increment(ctxt, ctxt->op_bytes); 2017 --reg; 2018 } 2019 2020 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2021 if (rc != X86EMUL_CONTINUE) 2022 break; 2023 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2024 --reg; 2025 } 2026 return rc; 2027 } 2028 2029 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2030 { 2031 const struct x86_emulate_ops *ops = ctxt->ops; 2032 int rc; 2033 struct desc_ptr dt; 2034 gva_t cs_addr; 2035 gva_t eip_addr; 2036 u16 cs, eip; 2037 2038 /* TODO: Add limit checks */ 2039 ctxt->src.val = ctxt->eflags; 2040 rc = em_push(ctxt); 2041 if (rc != X86EMUL_CONTINUE) 2042 return rc; 2043 2044 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2045 2046 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2047 rc = em_push(ctxt); 2048 if (rc != X86EMUL_CONTINUE) 2049 return rc; 2050 2051 ctxt->src.val = ctxt->_eip; 2052 rc = em_push(ctxt); 2053 if (rc != X86EMUL_CONTINUE) 2054 return rc; 2055 2056 ops->get_idt(ctxt, &dt); 2057 2058 eip_addr = dt.address + (irq << 2); 2059 cs_addr = dt.address + (irq << 2) + 2; 2060 2061 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2062 if (rc != X86EMUL_CONTINUE) 2063 return rc; 2064 2065 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2066 if (rc != X86EMUL_CONTINUE) 2067 return rc; 2068 2069 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2070 if (rc != X86EMUL_CONTINUE) 2071 return rc; 2072 2073 ctxt->_eip = eip; 2074 2075 return rc; 2076 } 2077 2078 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2079 { 2080 int rc; 2081 2082 invalidate_registers(ctxt); 2083 rc = __emulate_int_real(ctxt, irq); 2084 if (rc == X86EMUL_CONTINUE) 2085 writeback_registers(ctxt); 2086 return rc; 2087 } 2088 2089 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2090 { 2091 switch(ctxt->mode) { 2092 case X86EMUL_MODE_REAL: 2093 return __emulate_int_real(ctxt, irq); 2094 case X86EMUL_MODE_VM86: 2095 case X86EMUL_MODE_PROT16: 2096 case X86EMUL_MODE_PROT32: 2097 case X86EMUL_MODE_PROT64: 2098 default: 2099 /* Protected mode interrupts unimplemented yet */ 2100 return X86EMUL_UNHANDLEABLE; 2101 } 2102 } 2103 2104 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2105 { 2106 int rc = X86EMUL_CONTINUE; 2107 unsigned long temp_eip = 0; 2108 unsigned long temp_eflags = 0; 2109 unsigned long cs = 0; 2110 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2111 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2112 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2113 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2114 X86_EFLAGS_AC | X86_EFLAGS_ID | 2115 X86_EFLAGS_FIXED; 2116 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2117 X86_EFLAGS_VIP; 2118 2119 /* TODO: Add stack limit check */ 2120 2121 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2122 2123 if (rc != X86EMUL_CONTINUE) 2124 return rc; 2125 2126 if (temp_eip & ~0xffff) 2127 return emulate_gp(ctxt, 0); 2128 2129 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2130 2131 if (rc != X86EMUL_CONTINUE) 2132 return rc; 2133 2134 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2135 2136 if (rc != X86EMUL_CONTINUE) 2137 return rc; 2138 2139 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2140 2141 if (rc != X86EMUL_CONTINUE) 2142 return rc; 2143 2144 ctxt->_eip = temp_eip; 2145 2146 if (ctxt->op_bytes == 4) 2147 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2148 else if (ctxt->op_bytes == 2) { 2149 ctxt->eflags &= ~0xffff; 2150 ctxt->eflags |= temp_eflags; 2151 } 2152 2153 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2154 ctxt->eflags |= X86_EFLAGS_FIXED; 2155 ctxt->ops->set_nmi_mask(ctxt, false); 2156 2157 return rc; 2158 } 2159 2160 static int em_iret(struct x86_emulate_ctxt *ctxt) 2161 { 2162 switch(ctxt->mode) { 2163 case X86EMUL_MODE_REAL: 2164 return emulate_iret_real(ctxt); 2165 case X86EMUL_MODE_VM86: 2166 case X86EMUL_MODE_PROT16: 2167 case X86EMUL_MODE_PROT32: 2168 case X86EMUL_MODE_PROT64: 2169 default: 2170 /* iret from protected mode unimplemented yet */ 2171 return X86EMUL_UNHANDLEABLE; 2172 } 2173 } 2174 2175 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2176 { 2177 int rc; 2178 unsigned short sel; 2179 struct desc_struct new_desc; 2180 u8 cpl = ctxt->ops->cpl(ctxt); 2181 2182 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2183 2184 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2185 X86_TRANSFER_CALL_JMP, 2186 &new_desc); 2187 if (rc != X86EMUL_CONTINUE) 2188 return rc; 2189 2190 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 2191 /* Error handling is not implemented. */ 2192 if (rc != X86EMUL_CONTINUE) 2193 return X86EMUL_UNHANDLEABLE; 2194 2195 return rc; 2196 } 2197 2198 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2199 { 2200 return assign_eip_near(ctxt, ctxt->src.val); 2201 } 2202 2203 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2204 { 2205 int rc; 2206 long int old_eip; 2207 2208 old_eip = ctxt->_eip; 2209 rc = assign_eip_near(ctxt, ctxt->src.val); 2210 if (rc != X86EMUL_CONTINUE) 2211 return rc; 2212 ctxt->src.val = old_eip; 2213 rc = em_push(ctxt); 2214 return rc; 2215 } 2216 2217 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2218 { 2219 u64 old = ctxt->dst.orig_val64; 2220 2221 if (ctxt->dst.bytes == 16) 2222 return X86EMUL_UNHANDLEABLE; 2223 2224 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2225 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2226 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2227 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2228 ctxt->eflags &= ~X86_EFLAGS_ZF; 2229 } else { 2230 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2231 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2232 2233 ctxt->eflags |= X86_EFLAGS_ZF; 2234 } 2235 return X86EMUL_CONTINUE; 2236 } 2237 2238 static int em_ret(struct x86_emulate_ctxt *ctxt) 2239 { 2240 int rc; 2241 unsigned long eip; 2242 2243 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2244 if (rc != X86EMUL_CONTINUE) 2245 return rc; 2246 2247 return assign_eip_near(ctxt, eip); 2248 } 2249 2250 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2251 { 2252 int rc; 2253 unsigned long eip, cs; 2254 int cpl = ctxt->ops->cpl(ctxt); 2255 struct desc_struct new_desc; 2256 2257 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2258 if (rc != X86EMUL_CONTINUE) 2259 return rc; 2260 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2261 if (rc != X86EMUL_CONTINUE) 2262 return rc; 2263 /* Outer-privilege level return is not implemented */ 2264 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2265 return X86EMUL_UNHANDLEABLE; 2266 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2267 X86_TRANSFER_RET, 2268 &new_desc); 2269 if (rc != X86EMUL_CONTINUE) 2270 return rc; 2271 rc = assign_eip_far(ctxt, eip, &new_desc); 2272 /* Error handling is not implemented. */ 2273 if (rc != X86EMUL_CONTINUE) 2274 return X86EMUL_UNHANDLEABLE; 2275 2276 return rc; 2277 } 2278 2279 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2280 { 2281 int rc; 2282 2283 rc = em_ret_far(ctxt); 2284 if (rc != X86EMUL_CONTINUE) 2285 return rc; 2286 rsp_increment(ctxt, ctxt->src.val); 2287 return X86EMUL_CONTINUE; 2288 } 2289 2290 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2291 { 2292 /* Save real source value, then compare EAX against destination. */ 2293 ctxt->dst.orig_val = ctxt->dst.val; 2294 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2295 ctxt->src.orig_val = ctxt->src.val; 2296 ctxt->src.val = ctxt->dst.orig_val; 2297 fastop(ctxt, em_cmp); 2298 2299 if (ctxt->eflags & X86_EFLAGS_ZF) { 2300 /* Success: write back to memory; no update of EAX */ 2301 ctxt->src.type = OP_NONE; 2302 ctxt->dst.val = ctxt->src.orig_val; 2303 } else { 2304 /* Failure: write the value we saw to EAX. */ 2305 ctxt->src.type = OP_REG; 2306 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2307 ctxt->src.val = ctxt->dst.orig_val; 2308 /* Create write-cycle to dest by writing the same value */ 2309 ctxt->dst.val = ctxt->dst.orig_val; 2310 } 2311 return X86EMUL_CONTINUE; 2312 } 2313 2314 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2315 { 2316 int seg = ctxt->src2.val; 2317 unsigned short sel; 2318 int rc; 2319 2320 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2321 2322 rc = load_segment_descriptor(ctxt, sel, seg); 2323 if (rc != X86EMUL_CONTINUE) 2324 return rc; 2325 2326 ctxt->dst.val = ctxt->src.val; 2327 return rc; 2328 } 2329 2330 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2331 { 2332 #ifdef CONFIG_X86_64 2333 u32 eax, ebx, ecx, edx; 2334 2335 eax = 0x80000001; 2336 ecx = 0; 2337 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2338 return edx & bit(X86_FEATURE_LM); 2339 #else 2340 return false; 2341 #endif 2342 } 2343 2344 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2345 { 2346 desc->g = (flags >> 23) & 1; 2347 desc->d = (flags >> 22) & 1; 2348 desc->l = (flags >> 21) & 1; 2349 desc->avl = (flags >> 20) & 1; 2350 desc->p = (flags >> 15) & 1; 2351 desc->dpl = (flags >> 13) & 3; 2352 desc->s = (flags >> 12) & 1; 2353 desc->type = (flags >> 8) & 15; 2354 } 2355 2356 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate, 2357 int n) 2358 { 2359 struct desc_struct desc; 2360 int offset; 2361 u16 selector; 2362 2363 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4); 2364 2365 if (n < 3) 2366 offset = 0x7f84 + n * 12; 2367 else 2368 offset = 0x7f2c + (n - 3) * 12; 2369 2370 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2371 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2372 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset)); 2373 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2374 return X86EMUL_CONTINUE; 2375 } 2376 2377 #ifdef CONFIG_X86_64 2378 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate, 2379 int n) 2380 { 2381 struct desc_struct desc; 2382 int offset; 2383 u16 selector; 2384 u32 base3; 2385 2386 offset = 0x7e00 + n * 16; 2387 2388 selector = GET_SMSTATE(u16, smstate, offset); 2389 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8); 2390 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2391 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2392 base3 = GET_SMSTATE(u32, smstate, offset + 12); 2393 2394 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2395 return X86EMUL_CONTINUE; 2396 } 2397 #endif 2398 2399 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2400 u64 cr0, u64 cr3, u64 cr4) 2401 { 2402 int bad; 2403 u64 pcid; 2404 2405 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */ 2406 pcid = 0; 2407 if (cr4 & X86_CR4_PCIDE) { 2408 pcid = cr3 & 0xfff; 2409 cr3 &= ~0xfff; 2410 } 2411 2412 bad = ctxt->ops->set_cr(ctxt, 3, cr3); 2413 if (bad) 2414 return X86EMUL_UNHANDLEABLE; 2415 2416 /* 2417 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2418 * Then enable protected mode. However, PCID cannot be enabled 2419 * if EFER.LMA=0, so set it separately. 2420 */ 2421 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2422 if (bad) 2423 return X86EMUL_UNHANDLEABLE; 2424 2425 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2426 if (bad) 2427 return X86EMUL_UNHANDLEABLE; 2428 2429 if (cr4 & X86_CR4_PCIDE) { 2430 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2431 if (bad) 2432 return X86EMUL_UNHANDLEABLE; 2433 if (pcid) { 2434 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid); 2435 if (bad) 2436 return X86EMUL_UNHANDLEABLE; 2437 } 2438 2439 } 2440 2441 return X86EMUL_CONTINUE; 2442 } 2443 2444 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, 2445 const char *smstate) 2446 { 2447 struct desc_struct desc; 2448 struct desc_ptr dt; 2449 u16 selector; 2450 u32 val, cr0, cr3, cr4; 2451 int i; 2452 2453 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc); 2454 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8); 2455 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED; 2456 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0); 2457 2458 for (i = 0; i < 8; i++) 2459 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4); 2460 2461 val = GET_SMSTATE(u32, smstate, 0x7fcc); 2462 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2463 val = GET_SMSTATE(u32, smstate, 0x7fc8); 2464 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2465 2466 selector = GET_SMSTATE(u32, smstate, 0x7fc4); 2467 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64)); 2468 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60)); 2469 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c)); 2470 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2471 2472 selector = GET_SMSTATE(u32, smstate, 0x7fc0); 2473 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80)); 2474 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c)); 2475 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78)); 2476 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2477 2478 dt.address = GET_SMSTATE(u32, smstate, 0x7f74); 2479 dt.size = GET_SMSTATE(u32, smstate, 0x7f70); 2480 ctxt->ops->set_gdt(ctxt, &dt); 2481 2482 dt.address = GET_SMSTATE(u32, smstate, 0x7f58); 2483 dt.size = GET_SMSTATE(u32, smstate, 0x7f54); 2484 ctxt->ops->set_idt(ctxt, &dt); 2485 2486 for (i = 0; i < 6; i++) { 2487 int r = rsm_load_seg_32(ctxt, smstate, i); 2488 if (r != X86EMUL_CONTINUE) 2489 return r; 2490 } 2491 2492 cr4 = GET_SMSTATE(u32, smstate, 0x7f14); 2493 2494 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8)); 2495 2496 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2497 } 2498 2499 #ifdef CONFIG_X86_64 2500 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, 2501 const char *smstate) 2502 { 2503 struct desc_struct desc; 2504 struct desc_ptr dt; 2505 u64 val, cr0, cr3, cr4; 2506 u32 base3; 2507 u16 selector; 2508 int i, r; 2509 2510 for (i = 0; i < 16; i++) 2511 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8); 2512 2513 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78); 2514 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED; 2515 2516 val = GET_SMSTATE(u32, smstate, 0x7f68); 2517 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2518 val = GET_SMSTATE(u32, smstate, 0x7f60); 2519 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2520 2521 cr0 = GET_SMSTATE(u64, smstate, 0x7f58); 2522 cr3 = GET_SMSTATE(u64, smstate, 0x7f50); 2523 cr4 = GET_SMSTATE(u64, smstate, 0x7f48); 2524 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00)); 2525 val = GET_SMSTATE(u64, smstate, 0x7ed0); 2526 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA); 2527 2528 selector = GET_SMSTATE(u32, smstate, 0x7e90); 2529 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8); 2530 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94)); 2531 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98)); 2532 base3 = GET_SMSTATE(u32, smstate, 0x7e9c); 2533 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2534 2535 dt.size = GET_SMSTATE(u32, smstate, 0x7e84); 2536 dt.address = GET_SMSTATE(u64, smstate, 0x7e88); 2537 ctxt->ops->set_idt(ctxt, &dt); 2538 2539 selector = GET_SMSTATE(u32, smstate, 0x7e70); 2540 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8); 2541 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74)); 2542 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78)); 2543 base3 = GET_SMSTATE(u32, smstate, 0x7e7c); 2544 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2545 2546 dt.size = GET_SMSTATE(u32, smstate, 0x7e64); 2547 dt.address = GET_SMSTATE(u64, smstate, 0x7e68); 2548 ctxt->ops->set_gdt(ctxt, &dt); 2549 2550 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2551 if (r != X86EMUL_CONTINUE) 2552 return r; 2553 2554 for (i = 0; i < 6; i++) { 2555 r = rsm_load_seg_64(ctxt, smstate, i); 2556 if (r != X86EMUL_CONTINUE) 2557 return r; 2558 } 2559 2560 return X86EMUL_CONTINUE; 2561 } 2562 #endif 2563 2564 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2565 { 2566 unsigned long cr0, cr4, efer; 2567 char buf[512]; 2568 u64 smbase; 2569 int ret; 2570 2571 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2572 return emulate_ud(ctxt); 2573 2574 smbase = ctxt->ops->get_smbase(ctxt); 2575 2576 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf)); 2577 if (ret != X86EMUL_CONTINUE) 2578 return X86EMUL_UNHANDLEABLE; 2579 2580 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2581 ctxt->ops->set_nmi_mask(ctxt, false); 2582 2583 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) & 2584 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK)); 2585 2586 /* 2587 * Get back to real mode, to prepare a safe state in which to load 2588 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU 2589 * supports long mode. 2590 */ 2591 if (emulator_has_longmode(ctxt)) { 2592 struct desc_struct cs_desc; 2593 2594 /* Zero CR4.PCIDE before CR0.PG. */ 2595 cr4 = ctxt->ops->get_cr(ctxt, 4); 2596 if (cr4 & X86_CR4_PCIDE) 2597 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2598 2599 /* A 32-bit code segment is required to clear EFER.LMA. */ 2600 memset(&cs_desc, 0, sizeof(cs_desc)); 2601 cs_desc.type = 0xb; 2602 cs_desc.s = cs_desc.g = cs_desc.p = 1; 2603 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS); 2604 } 2605 2606 /* For the 64-bit case, this will clear EFER.LMA. */ 2607 cr0 = ctxt->ops->get_cr(ctxt, 0); 2608 if (cr0 & X86_CR0_PE) 2609 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2610 2611 if (emulator_has_longmode(ctxt)) { 2612 /* Clear CR4.PAE before clearing EFER.LME. */ 2613 cr4 = ctxt->ops->get_cr(ctxt, 4); 2614 if (cr4 & X86_CR4_PAE) 2615 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2616 2617 /* And finally go back to 32-bit mode. */ 2618 efer = 0; 2619 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2620 } 2621 2622 /* 2623 * Give pre_leave_smm() a chance to make ISA-specific changes to the 2624 * vCPU state (e.g. enter guest mode) before loading state from the SMM 2625 * state-save area. 2626 */ 2627 if (ctxt->ops->pre_leave_smm(ctxt, buf)) 2628 return X86EMUL_UNHANDLEABLE; 2629 2630 #ifdef CONFIG_X86_64 2631 if (emulator_has_longmode(ctxt)) 2632 ret = rsm_load_state_64(ctxt, buf); 2633 else 2634 #endif 2635 ret = rsm_load_state_32(ctxt, buf); 2636 2637 if (ret != X86EMUL_CONTINUE) { 2638 /* FIXME: should triple fault */ 2639 return X86EMUL_UNHANDLEABLE; 2640 } 2641 2642 ctxt->ops->post_leave_smm(ctxt); 2643 2644 return X86EMUL_CONTINUE; 2645 } 2646 2647 static void 2648 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2649 struct desc_struct *cs, struct desc_struct *ss) 2650 { 2651 cs->l = 0; /* will be adjusted later */ 2652 set_desc_base(cs, 0); /* flat segment */ 2653 cs->g = 1; /* 4kb granularity */ 2654 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2655 cs->type = 0x0b; /* Read, Execute, Accessed */ 2656 cs->s = 1; 2657 cs->dpl = 0; /* will be adjusted later */ 2658 cs->p = 1; 2659 cs->d = 1; 2660 cs->avl = 0; 2661 2662 set_desc_base(ss, 0); /* flat segment */ 2663 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2664 ss->g = 1; /* 4kb granularity */ 2665 ss->s = 1; 2666 ss->type = 0x03; /* Read/Write, Accessed */ 2667 ss->d = 1; /* 32bit stack segment */ 2668 ss->dpl = 0; 2669 ss->p = 1; 2670 ss->l = 0; 2671 ss->avl = 0; 2672 } 2673 2674 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2675 { 2676 u32 eax, ebx, ecx, edx; 2677 2678 eax = ecx = 0; 2679 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2680 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2681 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2682 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2683 } 2684 2685 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2686 { 2687 const struct x86_emulate_ops *ops = ctxt->ops; 2688 u32 eax, ebx, ecx, edx; 2689 2690 /* 2691 * syscall should always be enabled in longmode - so only become 2692 * vendor specific (cpuid) if other modes are active... 2693 */ 2694 if (ctxt->mode == X86EMUL_MODE_PROT64) 2695 return true; 2696 2697 eax = 0x00000000; 2698 ecx = 0x00000000; 2699 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2700 /* 2701 * Intel ("GenuineIntel") 2702 * remark: Intel CPUs only support "syscall" in 64bit 2703 * longmode. Also an 64bit guest with a 2704 * 32bit compat-app running will #UD !! While this 2705 * behaviour can be fixed (by emulating) into AMD 2706 * response - CPUs of AMD can't behave like Intel. 2707 */ 2708 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2709 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2710 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2711 return false; 2712 2713 /* AMD ("AuthenticAMD") */ 2714 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2715 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2716 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2717 return true; 2718 2719 /* AMD ("AMDisbetter!") */ 2720 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2721 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2722 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2723 return true; 2724 2725 /* Hygon ("HygonGenuine") */ 2726 if (ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx && 2727 ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx && 2728 edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx) 2729 return true; 2730 2731 /* 2732 * default: (not Intel, not AMD, not Hygon), apply Intel's 2733 * stricter rules... 2734 */ 2735 return false; 2736 } 2737 2738 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2739 { 2740 const struct x86_emulate_ops *ops = ctxt->ops; 2741 struct desc_struct cs, ss; 2742 u64 msr_data; 2743 u16 cs_sel, ss_sel; 2744 u64 efer = 0; 2745 2746 /* syscall is not available in real mode */ 2747 if (ctxt->mode == X86EMUL_MODE_REAL || 2748 ctxt->mode == X86EMUL_MODE_VM86) 2749 return emulate_ud(ctxt); 2750 2751 if (!(em_syscall_is_enabled(ctxt))) 2752 return emulate_ud(ctxt); 2753 2754 ops->get_msr(ctxt, MSR_EFER, &efer); 2755 setup_syscalls_segments(ctxt, &cs, &ss); 2756 2757 if (!(efer & EFER_SCE)) 2758 return emulate_ud(ctxt); 2759 2760 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2761 msr_data >>= 32; 2762 cs_sel = (u16)(msr_data & 0xfffc); 2763 ss_sel = (u16)(msr_data + 8); 2764 2765 if (efer & EFER_LMA) { 2766 cs.d = 0; 2767 cs.l = 1; 2768 } 2769 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2770 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2771 2772 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2773 if (efer & EFER_LMA) { 2774 #ifdef CONFIG_X86_64 2775 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2776 2777 ops->get_msr(ctxt, 2778 ctxt->mode == X86EMUL_MODE_PROT64 ? 2779 MSR_LSTAR : MSR_CSTAR, &msr_data); 2780 ctxt->_eip = msr_data; 2781 2782 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2783 ctxt->eflags &= ~msr_data; 2784 ctxt->eflags |= X86_EFLAGS_FIXED; 2785 #endif 2786 } else { 2787 /* legacy mode */ 2788 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2789 ctxt->_eip = (u32)msr_data; 2790 2791 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2792 } 2793 2794 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2795 return X86EMUL_CONTINUE; 2796 } 2797 2798 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2799 { 2800 const struct x86_emulate_ops *ops = ctxt->ops; 2801 struct desc_struct cs, ss; 2802 u64 msr_data; 2803 u16 cs_sel, ss_sel; 2804 u64 efer = 0; 2805 2806 ops->get_msr(ctxt, MSR_EFER, &efer); 2807 /* inject #GP if in real mode */ 2808 if (ctxt->mode == X86EMUL_MODE_REAL) 2809 return emulate_gp(ctxt, 0); 2810 2811 /* 2812 * Not recognized on AMD in compat mode (but is recognized in legacy 2813 * mode). 2814 */ 2815 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2816 && !vendor_intel(ctxt)) 2817 return emulate_ud(ctxt); 2818 2819 /* sysenter/sysexit have not been tested in 64bit mode. */ 2820 if (ctxt->mode == X86EMUL_MODE_PROT64) 2821 return X86EMUL_UNHANDLEABLE; 2822 2823 setup_syscalls_segments(ctxt, &cs, &ss); 2824 2825 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2826 if ((msr_data & 0xfffc) == 0x0) 2827 return emulate_gp(ctxt, 0); 2828 2829 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2830 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2831 ss_sel = cs_sel + 8; 2832 if (efer & EFER_LMA) { 2833 cs.d = 0; 2834 cs.l = 1; 2835 } 2836 2837 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2838 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2839 2840 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2841 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2842 2843 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2844 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2845 (u32)msr_data; 2846 2847 return X86EMUL_CONTINUE; 2848 } 2849 2850 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2851 { 2852 const struct x86_emulate_ops *ops = ctxt->ops; 2853 struct desc_struct cs, ss; 2854 u64 msr_data, rcx, rdx; 2855 int usermode; 2856 u16 cs_sel = 0, ss_sel = 0; 2857 2858 /* inject #GP if in real mode or Virtual 8086 mode */ 2859 if (ctxt->mode == X86EMUL_MODE_REAL || 2860 ctxt->mode == X86EMUL_MODE_VM86) 2861 return emulate_gp(ctxt, 0); 2862 2863 setup_syscalls_segments(ctxt, &cs, &ss); 2864 2865 if ((ctxt->rex_prefix & 0x8) != 0x0) 2866 usermode = X86EMUL_MODE_PROT64; 2867 else 2868 usermode = X86EMUL_MODE_PROT32; 2869 2870 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2871 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2872 2873 cs.dpl = 3; 2874 ss.dpl = 3; 2875 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2876 switch (usermode) { 2877 case X86EMUL_MODE_PROT32: 2878 cs_sel = (u16)(msr_data + 16); 2879 if ((msr_data & 0xfffc) == 0x0) 2880 return emulate_gp(ctxt, 0); 2881 ss_sel = (u16)(msr_data + 24); 2882 rcx = (u32)rcx; 2883 rdx = (u32)rdx; 2884 break; 2885 case X86EMUL_MODE_PROT64: 2886 cs_sel = (u16)(msr_data + 32); 2887 if (msr_data == 0x0) 2888 return emulate_gp(ctxt, 0); 2889 ss_sel = cs_sel + 8; 2890 cs.d = 0; 2891 cs.l = 1; 2892 if (emul_is_noncanonical_address(rcx, ctxt) || 2893 emul_is_noncanonical_address(rdx, ctxt)) 2894 return emulate_gp(ctxt, 0); 2895 break; 2896 } 2897 cs_sel |= SEGMENT_RPL_MASK; 2898 ss_sel |= SEGMENT_RPL_MASK; 2899 2900 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2901 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2902 2903 ctxt->_eip = rdx; 2904 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2905 2906 return X86EMUL_CONTINUE; 2907 } 2908 2909 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2910 { 2911 int iopl; 2912 if (ctxt->mode == X86EMUL_MODE_REAL) 2913 return false; 2914 if (ctxt->mode == X86EMUL_MODE_VM86) 2915 return true; 2916 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2917 return ctxt->ops->cpl(ctxt) > iopl; 2918 } 2919 2920 #define VMWARE_PORT_VMPORT (0x5658) 2921 #define VMWARE_PORT_VMRPC (0x5659) 2922 2923 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2924 u16 port, u16 len) 2925 { 2926 const struct x86_emulate_ops *ops = ctxt->ops; 2927 struct desc_struct tr_seg; 2928 u32 base3; 2929 int r; 2930 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2931 unsigned mask = (1 << len) - 1; 2932 unsigned long base; 2933 2934 /* 2935 * VMware allows access to these ports even if denied 2936 * by TSS I/O permission bitmap. Mimic behavior. 2937 */ 2938 if (enable_vmware_backdoor && 2939 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2940 return true; 2941 2942 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2943 if (!tr_seg.p) 2944 return false; 2945 if (desc_limit_scaled(&tr_seg) < 103) 2946 return false; 2947 base = get_desc_base(&tr_seg); 2948 #ifdef CONFIG_X86_64 2949 base |= ((u64)base3) << 32; 2950 #endif 2951 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2952 if (r != X86EMUL_CONTINUE) 2953 return false; 2954 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2955 return false; 2956 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2957 if (r != X86EMUL_CONTINUE) 2958 return false; 2959 if ((perm >> bit_idx) & mask) 2960 return false; 2961 return true; 2962 } 2963 2964 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2965 u16 port, u16 len) 2966 { 2967 if (ctxt->perm_ok) 2968 return true; 2969 2970 if (emulator_bad_iopl(ctxt)) 2971 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2972 return false; 2973 2974 ctxt->perm_ok = true; 2975 2976 return true; 2977 } 2978 2979 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2980 { 2981 /* 2982 * Intel CPUs mask the counter and pointers in quite strange 2983 * manner when ECX is zero due to REP-string optimizations. 2984 */ 2985 #ifdef CONFIG_X86_64 2986 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2987 return; 2988 2989 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2990 2991 switch (ctxt->b) { 2992 case 0xa4: /* movsb */ 2993 case 0xa5: /* movsd/w */ 2994 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2995 /* fall through */ 2996 case 0xaa: /* stosb */ 2997 case 0xab: /* stosd/w */ 2998 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2999 } 3000 #endif 3001 } 3002 3003 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 3004 struct tss_segment_16 *tss) 3005 { 3006 tss->ip = ctxt->_eip; 3007 tss->flag = ctxt->eflags; 3008 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 3009 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 3010 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 3011 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 3012 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 3013 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 3014 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 3015 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 3016 3017 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3018 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3019 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3020 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3021 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 3022 } 3023 3024 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 3025 struct tss_segment_16 *tss) 3026 { 3027 int ret; 3028 u8 cpl; 3029 3030 ctxt->_eip = tss->ip; 3031 ctxt->eflags = tss->flag | 2; 3032 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 3033 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 3034 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 3035 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 3036 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 3037 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 3038 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 3039 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 3040 3041 /* 3042 * SDM says that segment selectors are loaded before segment 3043 * descriptors 3044 */ 3045 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 3046 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3047 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3048 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3049 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3050 3051 cpl = tss->cs & 3; 3052 3053 /* 3054 * Now load segment descriptors. If fault happens at this stage 3055 * it is handled in a context of new task 3056 */ 3057 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 3058 X86_TRANSFER_TASK_SWITCH, NULL); 3059 if (ret != X86EMUL_CONTINUE) 3060 return ret; 3061 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3062 X86_TRANSFER_TASK_SWITCH, NULL); 3063 if (ret != X86EMUL_CONTINUE) 3064 return ret; 3065 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3066 X86_TRANSFER_TASK_SWITCH, NULL); 3067 if (ret != X86EMUL_CONTINUE) 3068 return ret; 3069 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3070 X86_TRANSFER_TASK_SWITCH, NULL); 3071 if (ret != X86EMUL_CONTINUE) 3072 return ret; 3073 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3074 X86_TRANSFER_TASK_SWITCH, NULL); 3075 if (ret != X86EMUL_CONTINUE) 3076 return ret; 3077 3078 return X86EMUL_CONTINUE; 3079 } 3080 3081 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 3082 u16 tss_selector, u16 old_tss_sel, 3083 ulong old_tss_base, struct desc_struct *new_desc) 3084 { 3085 struct tss_segment_16 tss_seg; 3086 int ret; 3087 u32 new_tss_base = get_desc_base(new_desc); 3088 3089 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3090 if (ret != X86EMUL_CONTINUE) 3091 return ret; 3092 3093 save_state_to_tss16(ctxt, &tss_seg); 3094 3095 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3096 if (ret != X86EMUL_CONTINUE) 3097 return ret; 3098 3099 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3100 if (ret != X86EMUL_CONTINUE) 3101 return ret; 3102 3103 if (old_tss_sel != 0xffff) { 3104 tss_seg.prev_task_link = old_tss_sel; 3105 3106 ret = linear_write_system(ctxt, new_tss_base, 3107 &tss_seg.prev_task_link, 3108 sizeof(tss_seg.prev_task_link)); 3109 if (ret != X86EMUL_CONTINUE) 3110 return ret; 3111 } 3112 3113 return load_state_from_tss16(ctxt, &tss_seg); 3114 } 3115 3116 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 3117 struct tss_segment_32 *tss) 3118 { 3119 /* CR3 and ldt selector are not saved intentionally */ 3120 tss->eip = ctxt->_eip; 3121 tss->eflags = ctxt->eflags; 3122 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 3123 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 3124 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 3125 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 3126 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 3127 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 3128 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 3129 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 3130 3131 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3132 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3133 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3134 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3135 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 3136 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 3137 } 3138 3139 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 3140 struct tss_segment_32 *tss) 3141 { 3142 int ret; 3143 u8 cpl; 3144 3145 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3146 return emulate_gp(ctxt, 0); 3147 ctxt->_eip = tss->eip; 3148 ctxt->eflags = tss->eflags | 2; 3149 3150 /* General purpose registers */ 3151 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3152 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3153 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3154 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3155 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3156 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3157 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3158 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3159 3160 /* 3161 * SDM says that segment selectors are loaded before segment 3162 * descriptors. This is important because CPL checks will 3163 * use CS.RPL. 3164 */ 3165 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3166 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3167 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3168 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3169 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3170 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3171 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3172 3173 /* 3174 * If we're switching between Protected Mode and VM86, we need to make 3175 * sure to update the mode before loading the segment descriptors so 3176 * that the selectors are interpreted correctly. 3177 */ 3178 if (ctxt->eflags & X86_EFLAGS_VM) { 3179 ctxt->mode = X86EMUL_MODE_VM86; 3180 cpl = 3; 3181 } else { 3182 ctxt->mode = X86EMUL_MODE_PROT32; 3183 cpl = tss->cs & 3; 3184 } 3185 3186 /* 3187 * Now load segment descriptors. If fault happenes at this stage 3188 * it is handled in a context of new task 3189 */ 3190 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3191 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3192 if (ret != X86EMUL_CONTINUE) 3193 return ret; 3194 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3195 X86_TRANSFER_TASK_SWITCH, NULL); 3196 if (ret != X86EMUL_CONTINUE) 3197 return ret; 3198 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3199 X86_TRANSFER_TASK_SWITCH, NULL); 3200 if (ret != X86EMUL_CONTINUE) 3201 return ret; 3202 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3203 X86_TRANSFER_TASK_SWITCH, NULL); 3204 if (ret != X86EMUL_CONTINUE) 3205 return ret; 3206 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3207 X86_TRANSFER_TASK_SWITCH, NULL); 3208 if (ret != X86EMUL_CONTINUE) 3209 return ret; 3210 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3211 X86_TRANSFER_TASK_SWITCH, NULL); 3212 if (ret != X86EMUL_CONTINUE) 3213 return ret; 3214 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3215 X86_TRANSFER_TASK_SWITCH, NULL); 3216 3217 return ret; 3218 } 3219 3220 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 3221 u16 tss_selector, u16 old_tss_sel, 3222 ulong old_tss_base, struct desc_struct *new_desc) 3223 { 3224 struct tss_segment_32 tss_seg; 3225 int ret; 3226 u32 new_tss_base = get_desc_base(new_desc); 3227 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3228 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3229 3230 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3231 if (ret != X86EMUL_CONTINUE) 3232 return ret; 3233 3234 save_state_to_tss32(ctxt, &tss_seg); 3235 3236 /* Only GP registers and segment selectors are saved */ 3237 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3238 ldt_sel_offset - eip_offset); 3239 if (ret != X86EMUL_CONTINUE) 3240 return ret; 3241 3242 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3243 if (ret != X86EMUL_CONTINUE) 3244 return ret; 3245 3246 if (old_tss_sel != 0xffff) { 3247 tss_seg.prev_task_link = old_tss_sel; 3248 3249 ret = linear_write_system(ctxt, new_tss_base, 3250 &tss_seg.prev_task_link, 3251 sizeof(tss_seg.prev_task_link)); 3252 if (ret != X86EMUL_CONTINUE) 3253 return ret; 3254 } 3255 3256 return load_state_from_tss32(ctxt, &tss_seg); 3257 } 3258 3259 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3260 u16 tss_selector, int idt_index, int reason, 3261 bool has_error_code, u32 error_code) 3262 { 3263 const struct x86_emulate_ops *ops = ctxt->ops; 3264 struct desc_struct curr_tss_desc, next_tss_desc; 3265 int ret; 3266 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3267 ulong old_tss_base = 3268 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3269 u32 desc_limit; 3270 ulong desc_addr, dr7; 3271 3272 /* FIXME: old_tss_base == ~0 ? */ 3273 3274 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3275 if (ret != X86EMUL_CONTINUE) 3276 return ret; 3277 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3278 if (ret != X86EMUL_CONTINUE) 3279 return ret; 3280 3281 /* FIXME: check that next_tss_desc is tss */ 3282 3283 /* 3284 * Check privileges. The three cases are task switch caused by... 3285 * 3286 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3287 * 2. Exception/IRQ/iret: No check is performed 3288 * 3. jmp/call to TSS/task-gate: No check is performed since the 3289 * hardware checks it before exiting. 3290 */ 3291 if (reason == TASK_SWITCH_GATE) { 3292 if (idt_index != -1) { 3293 /* Software interrupts */ 3294 struct desc_struct task_gate_desc; 3295 int dpl; 3296 3297 ret = read_interrupt_descriptor(ctxt, idt_index, 3298 &task_gate_desc); 3299 if (ret != X86EMUL_CONTINUE) 3300 return ret; 3301 3302 dpl = task_gate_desc.dpl; 3303 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3304 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3305 } 3306 } 3307 3308 desc_limit = desc_limit_scaled(&next_tss_desc); 3309 if (!next_tss_desc.p || 3310 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3311 desc_limit < 0x2b)) { 3312 return emulate_ts(ctxt, tss_selector & 0xfffc); 3313 } 3314 3315 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3316 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3317 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3318 } 3319 3320 if (reason == TASK_SWITCH_IRET) 3321 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3322 3323 /* set back link to prev task only if NT bit is set in eflags 3324 note that old_tss_sel is not used after this point */ 3325 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3326 old_tss_sel = 0xffff; 3327 3328 if (next_tss_desc.type & 8) 3329 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 3330 old_tss_base, &next_tss_desc); 3331 else 3332 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 3333 old_tss_base, &next_tss_desc); 3334 if (ret != X86EMUL_CONTINUE) 3335 return ret; 3336 3337 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3338 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3339 3340 if (reason != TASK_SWITCH_IRET) { 3341 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3342 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3343 } 3344 3345 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3346 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3347 3348 if (has_error_code) { 3349 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3350 ctxt->lock_prefix = 0; 3351 ctxt->src.val = (unsigned long) error_code; 3352 ret = em_push(ctxt); 3353 } 3354 3355 ops->get_dr(ctxt, 7, &dr7); 3356 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3357 3358 return ret; 3359 } 3360 3361 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3362 u16 tss_selector, int idt_index, int reason, 3363 bool has_error_code, u32 error_code) 3364 { 3365 int rc; 3366 3367 invalidate_registers(ctxt); 3368 ctxt->_eip = ctxt->eip; 3369 ctxt->dst.type = OP_NONE; 3370 3371 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3372 has_error_code, error_code); 3373 3374 if (rc == X86EMUL_CONTINUE) { 3375 ctxt->eip = ctxt->_eip; 3376 writeback_registers(ctxt); 3377 } 3378 3379 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3380 } 3381 3382 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3383 struct operand *op) 3384 { 3385 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3386 3387 register_address_increment(ctxt, reg, df * op->bytes); 3388 op->addr.mem.ea = register_address(ctxt, reg); 3389 } 3390 3391 static int em_das(struct x86_emulate_ctxt *ctxt) 3392 { 3393 u8 al, old_al; 3394 bool af, cf, old_cf; 3395 3396 cf = ctxt->eflags & X86_EFLAGS_CF; 3397 al = ctxt->dst.val; 3398 3399 old_al = al; 3400 old_cf = cf; 3401 cf = false; 3402 af = ctxt->eflags & X86_EFLAGS_AF; 3403 if ((al & 0x0f) > 9 || af) { 3404 al -= 6; 3405 cf = old_cf | (al >= 250); 3406 af = true; 3407 } else { 3408 af = false; 3409 } 3410 if (old_al > 0x99 || old_cf) { 3411 al -= 0x60; 3412 cf = true; 3413 } 3414 3415 ctxt->dst.val = al; 3416 /* Set PF, ZF, SF */ 3417 ctxt->src.type = OP_IMM; 3418 ctxt->src.val = 0; 3419 ctxt->src.bytes = 1; 3420 fastop(ctxt, em_or); 3421 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3422 if (cf) 3423 ctxt->eflags |= X86_EFLAGS_CF; 3424 if (af) 3425 ctxt->eflags |= X86_EFLAGS_AF; 3426 return X86EMUL_CONTINUE; 3427 } 3428 3429 static int em_aam(struct x86_emulate_ctxt *ctxt) 3430 { 3431 u8 al, ah; 3432 3433 if (ctxt->src.val == 0) 3434 return emulate_de(ctxt); 3435 3436 al = ctxt->dst.val & 0xff; 3437 ah = al / ctxt->src.val; 3438 al %= ctxt->src.val; 3439 3440 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3441 3442 /* Set PF, ZF, SF */ 3443 ctxt->src.type = OP_IMM; 3444 ctxt->src.val = 0; 3445 ctxt->src.bytes = 1; 3446 fastop(ctxt, em_or); 3447 3448 return X86EMUL_CONTINUE; 3449 } 3450 3451 static int em_aad(struct x86_emulate_ctxt *ctxt) 3452 { 3453 u8 al = ctxt->dst.val & 0xff; 3454 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3455 3456 al = (al + (ah * ctxt->src.val)) & 0xff; 3457 3458 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3459 3460 /* Set PF, ZF, SF */ 3461 ctxt->src.type = OP_IMM; 3462 ctxt->src.val = 0; 3463 ctxt->src.bytes = 1; 3464 fastop(ctxt, em_or); 3465 3466 return X86EMUL_CONTINUE; 3467 } 3468 3469 static int em_call(struct x86_emulate_ctxt *ctxt) 3470 { 3471 int rc; 3472 long rel = ctxt->src.val; 3473 3474 ctxt->src.val = (unsigned long)ctxt->_eip; 3475 rc = jmp_rel(ctxt, rel); 3476 if (rc != X86EMUL_CONTINUE) 3477 return rc; 3478 return em_push(ctxt); 3479 } 3480 3481 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3482 { 3483 u16 sel, old_cs; 3484 ulong old_eip; 3485 int rc; 3486 struct desc_struct old_desc, new_desc; 3487 const struct x86_emulate_ops *ops = ctxt->ops; 3488 int cpl = ctxt->ops->cpl(ctxt); 3489 enum x86emul_mode prev_mode = ctxt->mode; 3490 3491 old_eip = ctxt->_eip; 3492 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3493 3494 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3495 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3496 X86_TRANSFER_CALL_JMP, &new_desc); 3497 if (rc != X86EMUL_CONTINUE) 3498 return rc; 3499 3500 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 3501 if (rc != X86EMUL_CONTINUE) 3502 goto fail; 3503 3504 ctxt->src.val = old_cs; 3505 rc = em_push(ctxt); 3506 if (rc != X86EMUL_CONTINUE) 3507 goto fail; 3508 3509 ctxt->src.val = old_eip; 3510 rc = em_push(ctxt); 3511 /* If we failed, we tainted the memory, but the very least we should 3512 restore cs */ 3513 if (rc != X86EMUL_CONTINUE) { 3514 pr_warn_once("faulting far call emulation tainted memory\n"); 3515 goto fail; 3516 } 3517 return rc; 3518 fail: 3519 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3520 ctxt->mode = prev_mode; 3521 return rc; 3522 3523 } 3524 3525 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3526 { 3527 int rc; 3528 unsigned long eip; 3529 3530 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3531 if (rc != X86EMUL_CONTINUE) 3532 return rc; 3533 rc = assign_eip_near(ctxt, eip); 3534 if (rc != X86EMUL_CONTINUE) 3535 return rc; 3536 rsp_increment(ctxt, ctxt->src.val); 3537 return X86EMUL_CONTINUE; 3538 } 3539 3540 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3541 { 3542 /* Write back the register source. */ 3543 ctxt->src.val = ctxt->dst.val; 3544 write_register_operand(&ctxt->src); 3545 3546 /* Write back the memory destination with implicit LOCK prefix. */ 3547 ctxt->dst.val = ctxt->src.orig_val; 3548 ctxt->lock_prefix = 1; 3549 return X86EMUL_CONTINUE; 3550 } 3551 3552 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3553 { 3554 ctxt->dst.val = ctxt->src2.val; 3555 return fastop(ctxt, em_imul); 3556 } 3557 3558 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3559 { 3560 ctxt->dst.type = OP_REG; 3561 ctxt->dst.bytes = ctxt->src.bytes; 3562 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3563 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3564 3565 return X86EMUL_CONTINUE; 3566 } 3567 3568 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3569 { 3570 u64 tsc_aux = 0; 3571 3572 if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux)) 3573 return emulate_gp(ctxt, 0); 3574 ctxt->dst.val = tsc_aux; 3575 return X86EMUL_CONTINUE; 3576 } 3577 3578 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3579 { 3580 u64 tsc = 0; 3581 3582 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3583 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3584 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3585 return X86EMUL_CONTINUE; 3586 } 3587 3588 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3589 { 3590 u64 pmc; 3591 3592 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3593 return emulate_gp(ctxt, 0); 3594 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3595 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3596 return X86EMUL_CONTINUE; 3597 } 3598 3599 static int em_mov(struct x86_emulate_ctxt *ctxt) 3600 { 3601 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3602 return X86EMUL_CONTINUE; 3603 } 3604 3605 #define FFL(x) bit(X86_FEATURE_##x) 3606 3607 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3608 { 3609 u32 ebx, ecx, edx, eax = 1; 3610 u16 tmp; 3611 3612 /* 3613 * Check MOVBE is set in the guest-visible CPUID leaf. 3614 */ 3615 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3616 if (!(ecx & FFL(MOVBE))) 3617 return emulate_ud(ctxt); 3618 3619 switch (ctxt->op_bytes) { 3620 case 2: 3621 /* 3622 * From MOVBE definition: "...When the operand size is 16 bits, 3623 * the upper word of the destination register remains unchanged 3624 * ..." 3625 * 3626 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3627 * rules so we have to do the operation almost per hand. 3628 */ 3629 tmp = (u16)ctxt->src.val; 3630 ctxt->dst.val &= ~0xffffUL; 3631 ctxt->dst.val |= (unsigned long)swab16(tmp); 3632 break; 3633 case 4: 3634 ctxt->dst.val = swab32((u32)ctxt->src.val); 3635 break; 3636 case 8: 3637 ctxt->dst.val = swab64(ctxt->src.val); 3638 break; 3639 default: 3640 BUG(); 3641 } 3642 return X86EMUL_CONTINUE; 3643 } 3644 3645 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3646 { 3647 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3648 return emulate_gp(ctxt, 0); 3649 3650 /* Disable writeback. */ 3651 ctxt->dst.type = OP_NONE; 3652 return X86EMUL_CONTINUE; 3653 } 3654 3655 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3656 { 3657 unsigned long val; 3658 3659 if (ctxt->mode == X86EMUL_MODE_PROT64) 3660 val = ctxt->src.val & ~0ULL; 3661 else 3662 val = ctxt->src.val & ~0U; 3663 3664 /* #UD condition is already handled. */ 3665 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3666 return emulate_gp(ctxt, 0); 3667 3668 /* Disable writeback. */ 3669 ctxt->dst.type = OP_NONE; 3670 return X86EMUL_CONTINUE; 3671 } 3672 3673 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3674 { 3675 u64 msr_data; 3676 3677 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3678 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3679 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3680 return emulate_gp(ctxt, 0); 3681 3682 return X86EMUL_CONTINUE; 3683 } 3684 3685 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3686 { 3687 u64 msr_data; 3688 3689 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3690 return emulate_gp(ctxt, 0); 3691 3692 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3693 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3694 return X86EMUL_CONTINUE; 3695 } 3696 3697 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3698 { 3699 if (segment > VCPU_SREG_GS && 3700 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3701 ctxt->ops->cpl(ctxt) > 0) 3702 return emulate_gp(ctxt, 0); 3703 3704 ctxt->dst.val = get_segment_selector(ctxt, segment); 3705 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3706 ctxt->dst.bytes = 2; 3707 return X86EMUL_CONTINUE; 3708 } 3709 3710 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3711 { 3712 if (ctxt->modrm_reg > VCPU_SREG_GS) 3713 return emulate_ud(ctxt); 3714 3715 return em_store_sreg(ctxt, ctxt->modrm_reg); 3716 } 3717 3718 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3719 { 3720 u16 sel = ctxt->src.val; 3721 3722 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3723 return emulate_ud(ctxt); 3724 3725 if (ctxt->modrm_reg == VCPU_SREG_SS) 3726 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3727 3728 /* Disable writeback. */ 3729 ctxt->dst.type = OP_NONE; 3730 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3731 } 3732 3733 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3734 { 3735 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3736 } 3737 3738 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3739 { 3740 u16 sel = ctxt->src.val; 3741 3742 /* Disable writeback. */ 3743 ctxt->dst.type = OP_NONE; 3744 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3745 } 3746 3747 static int em_str(struct x86_emulate_ctxt *ctxt) 3748 { 3749 return em_store_sreg(ctxt, VCPU_SREG_TR); 3750 } 3751 3752 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3753 { 3754 u16 sel = ctxt->src.val; 3755 3756 /* Disable writeback. */ 3757 ctxt->dst.type = OP_NONE; 3758 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3759 } 3760 3761 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3762 { 3763 int rc; 3764 ulong linear; 3765 3766 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3767 if (rc == X86EMUL_CONTINUE) 3768 ctxt->ops->invlpg(ctxt, linear); 3769 /* Disable writeback. */ 3770 ctxt->dst.type = OP_NONE; 3771 return X86EMUL_CONTINUE; 3772 } 3773 3774 static int em_clts(struct x86_emulate_ctxt *ctxt) 3775 { 3776 ulong cr0; 3777 3778 cr0 = ctxt->ops->get_cr(ctxt, 0); 3779 cr0 &= ~X86_CR0_TS; 3780 ctxt->ops->set_cr(ctxt, 0, cr0); 3781 return X86EMUL_CONTINUE; 3782 } 3783 3784 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3785 { 3786 int rc = ctxt->ops->fix_hypercall(ctxt); 3787 3788 if (rc != X86EMUL_CONTINUE) 3789 return rc; 3790 3791 /* Let the processor re-execute the fixed hypercall */ 3792 ctxt->_eip = ctxt->eip; 3793 /* Disable writeback. */ 3794 ctxt->dst.type = OP_NONE; 3795 return X86EMUL_CONTINUE; 3796 } 3797 3798 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3799 void (*get)(struct x86_emulate_ctxt *ctxt, 3800 struct desc_ptr *ptr)) 3801 { 3802 struct desc_ptr desc_ptr; 3803 3804 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3805 ctxt->ops->cpl(ctxt) > 0) 3806 return emulate_gp(ctxt, 0); 3807 3808 if (ctxt->mode == X86EMUL_MODE_PROT64) 3809 ctxt->op_bytes = 8; 3810 get(ctxt, &desc_ptr); 3811 if (ctxt->op_bytes == 2) { 3812 ctxt->op_bytes = 4; 3813 desc_ptr.address &= 0x00ffffff; 3814 } 3815 /* Disable writeback. */ 3816 ctxt->dst.type = OP_NONE; 3817 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3818 &desc_ptr, 2 + ctxt->op_bytes); 3819 } 3820 3821 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3822 { 3823 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3824 } 3825 3826 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3827 { 3828 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3829 } 3830 3831 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3832 { 3833 struct desc_ptr desc_ptr; 3834 int rc; 3835 3836 if (ctxt->mode == X86EMUL_MODE_PROT64) 3837 ctxt->op_bytes = 8; 3838 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3839 &desc_ptr.size, &desc_ptr.address, 3840 ctxt->op_bytes); 3841 if (rc != X86EMUL_CONTINUE) 3842 return rc; 3843 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3844 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3845 return emulate_gp(ctxt, 0); 3846 if (lgdt) 3847 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3848 else 3849 ctxt->ops->set_idt(ctxt, &desc_ptr); 3850 /* Disable writeback. */ 3851 ctxt->dst.type = OP_NONE; 3852 return X86EMUL_CONTINUE; 3853 } 3854 3855 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3856 { 3857 return em_lgdt_lidt(ctxt, true); 3858 } 3859 3860 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3861 { 3862 return em_lgdt_lidt(ctxt, false); 3863 } 3864 3865 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3866 { 3867 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3868 ctxt->ops->cpl(ctxt) > 0) 3869 return emulate_gp(ctxt, 0); 3870 3871 if (ctxt->dst.type == OP_MEM) 3872 ctxt->dst.bytes = 2; 3873 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3874 return X86EMUL_CONTINUE; 3875 } 3876 3877 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3878 { 3879 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3880 | (ctxt->src.val & 0x0f)); 3881 ctxt->dst.type = OP_NONE; 3882 return X86EMUL_CONTINUE; 3883 } 3884 3885 static int em_loop(struct x86_emulate_ctxt *ctxt) 3886 { 3887 int rc = X86EMUL_CONTINUE; 3888 3889 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3890 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3891 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3892 rc = jmp_rel(ctxt, ctxt->src.val); 3893 3894 return rc; 3895 } 3896 3897 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3898 { 3899 int rc = X86EMUL_CONTINUE; 3900 3901 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3902 rc = jmp_rel(ctxt, ctxt->src.val); 3903 3904 return rc; 3905 } 3906 3907 static int em_in(struct x86_emulate_ctxt *ctxt) 3908 { 3909 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3910 &ctxt->dst.val)) 3911 return X86EMUL_IO_NEEDED; 3912 3913 return X86EMUL_CONTINUE; 3914 } 3915 3916 static int em_out(struct x86_emulate_ctxt *ctxt) 3917 { 3918 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3919 &ctxt->src.val, 1); 3920 /* Disable writeback. */ 3921 ctxt->dst.type = OP_NONE; 3922 return X86EMUL_CONTINUE; 3923 } 3924 3925 static int em_cli(struct x86_emulate_ctxt *ctxt) 3926 { 3927 if (emulator_bad_iopl(ctxt)) 3928 return emulate_gp(ctxt, 0); 3929 3930 ctxt->eflags &= ~X86_EFLAGS_IF; 3931 return X86EMUL_CONTINUE; 3932 } 3933 3934 static int em_sti(struct x86_emulate_ctxt *ctxt) 3935 { 3936 if (emulator_bad_iopl(ctxt)) 3937 return emulate_gp(ctxt, 0); 3938 3939 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3940 ctxt->eflags |= X86_EFLAGS_IF; 3941 return X86EMUL_CONTINUE; 3942 } 3943 3944 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3945 { 3946 u32 eax, ebx, ecx, edx; 3947 u64 msr = 0; 3948 3949 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3950 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3951 ctxt->ops->cpl(ctxt)) { 3952 return emulate_gp(ctxt, 0); 3953 } 3954 3955 eax = reg_read(ctxt, VCPU_REGS_RAX); 3956 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3957 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 3958 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3959 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3960 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3961 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3962 return X86EMUL_CONTINUE; 3963 } 3964 3965 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3966 { 3967 u32 flags; 3968 3969 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3970 X86_EFLAGS_SF; 3971 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3972 3973 ctxt->eflags &= ~0xffUL; 3974 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3975 return X86EMUL_CONTINUE; 3976 } 3977 3978 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3979 { 3980 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3981 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3982 return X86EMUL_CONTINUE; 3983 } 3984 3985 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3986 { 3987 switch (ctxt->op_bytes) { 3988 #ifdef CONFIG_X86_64 3989 case 8: 3990 asm("bswap %0" : "+r"(ctxt->dst.val)); 3991 break; 3992 #endif 3993 default: 3994 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3995 break; 3996 } 3997 return X86EMUL_CONTINUE; 3998 } 3999 4000 static int em_clflush(struct x86_emulate_ctxt *ctxt) 4001 { 4002 /* emulating clflush regardless of cpuid */ 4003 return X86EMUL_CONTINUE; 4004 } 4005 4006 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 4007 { 4008 ctxt->dst.val = (s32) ctxt->src.val; 4009 return X86EMUL_CONTINUE; 4010 } 4011 4012 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 4013 { 4014 u32 eax = 1, ebx, ecx = 0, edx; 4015 4016 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 4017 if (!(edx & FFL(FXSR))) 4018 return emulate_ud(ctxt); 4019 4020 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 4021 return emulate_nm(ctxt); 4022 4023 /* 4024 * Don't emulate a case that should never be hit, instead of working 4025 * around a lack of fxsave64/fxrstor64 on old compilers. 4026 */ 4027 if (ctxt->mode >= X86EMUL_MODE_PROT64) 4028 return X86EMUL_UNHANDLEABLE; 4029 4030 return X86EMUL_CONTINUE; 4031 } 4032 4033 /* 4034 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 4035 * and restore MXCSR. 4036 */ 4037 static size_t __fxstate_size(int nregs) 4038 { 4039 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 4040 } 4041 4042 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 4043 { 4044 bool cr4_osfxsr; 4045 if (ctxt->mode == X86EMUL_MODE_PROT64) 4046 return __fxstate_size(16); 4047 4048 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 4049 return __fxstate_size(cr4_osfxsr ? 8 : 0); 4050 } 4051 4052 /* 4053 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 4054 * 1) 16 bit mode 4055 * 2) 32 bit mode 4056 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 4057 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 4058 * save and restore 4059 * 3) 64-bit mode with REX.W prefix 4060 * - like (2), but XMM 8-15 are being saved and restored 4061 * 4) 64-bit mode without REX.W prefix 4062 * - like (3), but FIP and FDP are 64 bit 4063 * 4064 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 4065 * desired result. (4) is not emulated. 4066 * 4067 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 4068 * and FPU DS) should match. 4069 */ 4070 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 4071 { 4072 struct fxregs_state fx_state; 4073 int rc; 4074 4075 rc = check_fxsr(ctxt); 4076 if (rc != X86EMUL_CONTINUE) 4077 return rc; 4078 4079 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 4080 4081 if (rc != X86EMUL_CONTINUE) 4082 return rc; 4083 4084 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 4085 fxstate_size(ctxt)); 4086 } 4087 4088 /* 4089 * FXRSTOR might restore XMM registers not provided by the guest. Fill 4090 * in the host registers (via FXSAVE) instead, so they won't be modified. 4091 * (preemption has to stay disabled until FXRSTOR). 4092 * 4093 * Use noinline to keep the stack for other functions called by callers small. 4094 */ 4095 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 4096 const size_t used_size) 4097 { 4098 struct fxregs_state fx_tmp; 4099 int rc; 4100 4101 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 4102 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 4103 __fxstate_size(16) - used_size); 4104 4105 return rc; 4106 } 4107 4108 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 4109 { 4110 struct fxregs_state fx_state; 4111 int rc; 4112 size_t size; 4113 4114 rc = check_fxsr(ctxt); 4115 if (rc != X86EMUL_CONTINUE) 4116 return rc; 4117 4118 size = fxstate_size(ctxt); 4119 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 4120 if (rc != X86EMUL_CONTINUE) 4121 return rc; 4122 4123 if (size < __fxstate_size(16)) { 4124 rc = fxregs_fixup(&fx_state, size); 4125 if (rc != X86EMUL_CONTINUE) 4126 goto out; 4127 } 4128 4129 if (fx_state.mxcsr >> 16) { 4130 rc = emulate_gp(ctxt, 0); 4131 goto out; 4132 } 4133 4134 if (rc == X86EMUL_CONTINUE) 4135 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 4136 4137 out: 4138 return rc; 4139 } 4140 4141 static bool valid_cr(int nr) 4142 { 4143 switch (nr) { 4144 case 0: 4145 case 2 ... 4: 4146 case 8: 4147 return true; 4148 default: 4149 return false; 4150 } 4151 } 4152 4153 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 4154 { 4155 if (!valid_cr(ctxt->modrm_reg)) 4156 return emulate_ud(ctxt); 4157 4158 return X86EMUL_CONTINUE; 4159 } 4160 4161 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 4162 { 4163 u64 new_val = ctxt->src.val64; 4164 int cr = ctxt->modrm_reg; 4165 u64 efer = 0; 4166 4167 static u64 cr_reserved_bits[] = { 4168 0xffffffff00000000ULL, 4169 0, 0, 0, /* CR3 checked later */ 4170 CR4_RESERVED_BITS, 4171 0, 0, 0, 4172 CR8_RESERVED_BITS, 4173 }; 4174 4175 if (!valid_cr(cr)) 4176 return emulate_ud(ctxt); 4177 4178 if (new_val & cr_reserved_bits[cr]) 4179 return emulate_gp(ctxt, 0); 4180 4181 switch (cr) { 4182 case 0: { 4183 u64 cr4; 4184 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 4185 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 4186 return emulate_gp(ctxt, 0); 4187 4188 cr4 = ctxt->ops->get_cr(ctxt, 4); 4189 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4190 4191 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 4192 !(cr4 & X86_CR4_PAE)) 4193 return emulate_gp(ctxt, 0); 4194 4195 break; 4196 } 4197 case 3: { 4198 u64 rsvd = 0; 4199 4200 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4201 if (efer & EFER_LMA) { 4202 u64 maxphyaddr; 4203 u32 eax, ebx, ecx, edx; 4204 4205 eax = 0x80000008; 4206 ecx = 0; 4207 if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, 4208 &edx, false)) 4209 maxphyaddr = eax & 0xff; 4210 else 4211 maxphyaddr = 36; 4212 rsvd = rsvd_bits(maxphyaddr, 63); 4213 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE) 4214 rsvd &= ~X86_CR3_PCID_NOFLUSH; 4215 } 4216 4217 if (new_val & rsvd) 4218 return emulate_gp(ctxt, 0); 4219 4220 break; 4221 } 4222 case 4: { 4223 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4224 4225 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 4226 return emulate_gp(ctxt, 0); 4227 4228 break; 4229 } 4230 } 4231 4232 return X86EMUL_CONTINUE; 4233 } 4234 4235 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 4236 { 4237 unsigned long dr7; 4238 4239 ctxt->ops->get_dr(ctxt, 7, &dr7); 4240 4241 /* Check if DR7.Global_Enable is set */ 4242 return dr7 & (1 << 13); 4243 } 4244 4245 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 4246 { 4247 int dr = ctxt->modrm_reg; 4248 u64 cr4; 4249 4250 if (dr > 7) 4251 return emulate_ud(ctxt); 4252 4253 cr4 = ctxt->ops->get_cr(ctxt, 4); 4254 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 4255 return emulate_ud(ctxt); 4256 4257 if (check_dr7_gd(ctxt)) { 4258 ulong dr6; 4259 4260 ctxt->ops->get_dr(ctxt, 6, &dr6); 4261 dr6 &= ~15; 4262 dr6 |= DR6_BD | DR6_RTM; 4263 ctxt->ops->set_dr(ctxt, 6, dr6); 4264 return emulate_db(ctxt); 4265 } 4266 4267 return X86EMUL_CONTINUE; 4268 } 4269 4270 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 4271 { 4272 u64 new_val = ctxt->src.val64; 4273 int dr = ctxt->modrm_reg; 4274 4275 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 4276 return emulate_gp(ctxt, 0); 4277 4278 return check_dr_read(ctxt); 4279 } 4280 4281 static int check_svme(struct x86_emulate_ctxt *ctxt) 4282 { 4283 u64 efer = 0; 4284 4285 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4286 4287 if (!(efer & EFER_SVME)) 4288 return emulate_ud(ctxt); 4289 4290 return X86EMUL_CONTINUE; 4291 } 4292 4293 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 4294 { 4295 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 4296 4297 /* Valid physical address? */ 4298 if (rax & 0xffff000000000000ULL) 4299 return emulate_gp(ctxt, 0); 4300 4301 return check_svme(ctxt); 4302 } 4303 4304 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 4305 { 4306 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4307 4308 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 4309 return emulate_ud(ctxt); 4310 4311 return X86EMUL_CONTINUE; 4312 } 4313 4314 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 4315 { 4316 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4317 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 4318 4319 /* 4320 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 4321 * in Ring3 when CR4.PCE=0. 4322 */ 4323 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 4324 return X86EMUL_CONTINUE; 4325 4326 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 4327 ctxt->ops->check_pmc(ctxt, rcx)) 4328 return emulate_gp(ctxt, 0); 4329 4330 return X86EMUL_CONTINUE; 4331 } 4332 4333 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4334 { 4335 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4336 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4337 return emulate_gp(ctxt, 0); 4338 4339 return X86EMUL_CONTINUE; 4340 } 4341 4342 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4343 { 4344 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4345 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4346 return emulate_gp(ctxt, 0); 4347 4348 return X86EMUL_CONTINUE; 4349 } 4350 4351 #define D(_y) { .flags = (_y) } 4352 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4353 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4354 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4355 #define N D(NotImpl) 4356 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4357 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4358 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4359 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4360 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4361 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4362 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4363 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4364 #define II(_f, _e, _i) \ 4365 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4366 #define IIP(_f, _e, _i, _p) \ 4367 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4368 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4369 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4370 4371 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4372 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4373 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4374 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4375 #define I2bvIP(_f, _e, _i, _p) \ 4376 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4377 4378 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4379 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4380 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4381 4382 static const struct opcode group7_rm0[] = { 4383 N, 4384 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4385 N, N, N, N, N, N, 4386 }; 4387 4388 static const struct opcode group7_rm1[] = { 4389 DI(SrcNone | Priv, monitor), 4390 DI(SrcNone | Priv, mwait), 4391 N, N, N, N, N, N, 4392 }; 4393 4394 static const struct opcode group7_rm3[] = { 4395 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4396 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4397 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4398 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4399 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4400 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4401 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4402 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4403 }; 4404 4405 static const struct opcode group7_rm7[] = { 4406 N, 4407 DIP(SrcNone, rdtscp, check_rdtsc), 4408 N, N, N, N, N, N, 4409 }; 4410 4411 static const struct opcode group1[] = { 4412 F(Lock, em_add), 4413 F(Lock | PageTable, em_or), 4414 F(Lock, em_adc), 4415 F(Lock, em_sbb), 4416 F(Lock | PageTable, em_and), 4417 F(Lock, em_sub), 4418 F(Lock, em_xor), 4419 F(NoWrite, em_cmp), 4420 }; 4421 4422 static const struct opcode group1A[] = { 4423 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4424 }; 4425 4426 static const struct opcode group2[] = { 4427 F(DstMem | ModRM, em_rol), 4428 F(DstMem | ModRM, em_ror), 4429 F(DstMem | ModRM, em_rcl), 4430 F(DstMem | ModRM, em_rcr), 4431 F(DstMem | ModRM, em_shl), 4432 F(DstMem | ModRM, em_shr), 4433 F(DstMem | ModRM, em_shl), 4434 F(DstMem | ModRM, em_sar), 4435 }; 4436 4437 static const struct opcode group3[] = { 4438 F(DstMem | SrcImm | NoWrite, em_test), 4439 F(DstMem | SrcImm | NoWrite, em_test), 4440 F(DstMem | SrcNone | Lock, em_not), 4441 F(DstMem | SrcNone | Lock, em_neg), 4442 F(DstXacc | Src2Mem, em_mul_ex), 4443 F(DstXacc | Src2Mem, em_imul_ex), 4444 F(DstXacc | Src2Mem, em_div_ex), 4445 F(DstXacc | Src2Mem, em_idiv_ex), 4446 }; 4447 4448 static const struct opcode group4[] = { 4449 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4450 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4451 N, N, N, N, N, N, 4452 }; 4453 4454 static const struct opcode group5[] = { 4455 F(DstMem | SrcNone | Lock, em_inc), 4456 F(DstMem | SrcNone | Lock, em_dec), 4457 I(SrcMem | NearBranch, em_call_near_abs), 4458 I(SrcMemFAddr | ImplicitOps, em_call_far), 4459 I(SrcMem | NearBranch, em_jmp_abs), 4460 I(SrcMemFAddr | ImplicitOps, em_jmp_far), 4461 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4462 }; 4463 4464 static const struct opcode group6[] = { 4465 II(Prot | DstMem, em_sldt, sldt), 4466 II(Prot | DstMem, em_str, str), 4467 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4468 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4469 N, N, N, N, 4470 }; 4471 4472 static const struct group_dual group7 = { { 4473 II(Mov | DstMem, em_sgdt, sgdt), 4474 II(Mov | DstMem, em_sidt, sidt), 4475 II(SrcMem | Priv, em_lgdt, lgdt), 4476 II(SrcMem | Priv, em_lidt, lidt), 4477 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4478 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4479 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4480 }, { 4481 EXT(0, group7_rm0), 4482 EXT(0, group7_rm1), 4483 N, EXT(0, group7_rm3), 4484 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4485 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4486 EXT(0, group7_rm7), 4487 } }; 4488 4489 static const struct opcode group8[] = { 4490 N, N, N, N, 4491 F(DstMem | SrcImmByte | NoWrite, em_bt), 4492 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4493 F(DstMem | SrcImmByte | Lock, em_btr), 4494 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4495 }; 4496 4497 /* 4498 * The "memory" destination is actually always a register, since we come 4499 * from the register case of group9. 4500 */ 4501 static const struct gprefix pfx_0f_c7_7 = { 4502 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp), 4503 }; 4504 4505 4506 static const struct group_dual group9 = { { 4507 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4508 }, { 4509 N, N, N, N, N, N, N, 4510 GP(0, &pfx_0f_c7_7), 4511 } }; 4512 4513 static const struct opcode group11[] = { 4514 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4515 X7(D(Undefined)), 4516 }; 4517 4518 static const struct gprefix pfx_0f_ae_7 = { 4519 I(SrcMem | ByteOp, em_clflush), N, N, N, 4520 }; 4521 4522 static const struct group_dual group15 = { { 4523 I(ModRM | Aligned16, em_fxsave), 4524 I(ModRM | Aligned16, em_fxrstor), 4525 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4526 }, { 4527 N, N, N, N, N, N, N, N, 4528 } }; 4529 4530 static const struct gprefix pfx_0f_6f_0f_7f = { 4531 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4532 }; 4533 4534 static const struct instr_dual instr_dual_0f_2b = { 4535 I(0, em_mov), N 4536 }; 4537 4538 static const struct gprefix pfx_0f_2b = { 4539 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4540 }; 4541 4542 static const struct gprefix pfx_0f_10_0f_11 = { 4543 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4544 }; 4545 4546 static const struct gprefix pfx_0f_28_0f_29 = { 4547 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4548 }; 4549 4550 static const struct gprefix pfx_0f_e7 = { 4551 N, I(Sse, em_mov), N, N, 4552 }; 4553 4554 static const struct escape escape_d9 = { { 4555 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4556 }, { 4557 /* 0xC0 - 0xC7 */ 4558 N, N, N, N, N, N, N, N, 4559 /* 0xC8 - 0xCF */ 4560 N, N, N, N, N, N, N, N, 4561 /* 0xD0 - 0xC7 */ 4562 N, N, N, N, N, N, N, N, 4563 /* 0xD8 - 0xDF */ 4564 N, N, N, N, N, N, N, N, 4565 /* 0xE0 - 0xE7 */ 4566 N, N, N, N, N, N, N, N, 4567 /* 0xE8 - 0xEF */ 4568 N, N, N, N, N, N, N, N, 4569 /* 0xF0 - 0xF7 */ 4570 N, N, N, N, N, N, N, N, 4571 /* 0xF8 - 0xFF */ 4572 N, N, N, N, N, N, N, N, 4573 } }; 4574 4575 static const struct escape escape_db = { { 4576 N, N, N, N, N, N, N, N, 4577 }, { 4578 /* 0xC0 - 0xC7 */ 4579 N, N, N, N, N, N, N, N, 4580 /* 0xC8 - 0xCF */ 4581 N, N, N, N, N, N, N, N, 4582 /* 0xD0 - 0xC7 */ 4583 N, N, N, N, N, N, N, N, 4584 /* 0xD8 - 0xDF */ 4585 N, N, N, N, N, N, N, N, 4586 /* 0xE0 - 0xE7 */ 4587 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4588 /* 0xE8 - 0xEF */ 4589 N, N, N, N, N, N, N, N, 4590 /* 0xF0 - 0xF7 */ 4591 N, N, N, N, N, N, N, N, 4592 /* 0xF8 - 0xFF */ 4593 N, N, N, N, N, N, N, N, 4594 } }; 4595 4596 static const struct escape escape_dd = { { 4597 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4598 }, { 4599 /* 0xC0 - 0xC7 */ 4600 N, N, N, N, N, N, N, N, 4601 /* 0xC8 - 0xCF */ 4602 N, N, N, N, N, N, N, N, 4603 /* 0xD0 - 0xC7 */ 4604 N, N, N, N, N, N, N, N, 4605 /* 0xD8 - 0xDF */ 4606 N, N, N, N, N, N, N, N, 4607 /* 0xE0 - 0xE7 */ 4608 N, N, N, N, N, N, N, N, 4609 /* 0xE8 - 0xEF */ 4610 N, N, N, N, N, N, N, N, 4611 /* 0xF0 - 0xF7 */ 4612 N, N, N, N, N, N, N, N, 4613 /* 0xF8 - 0xFF */ 4614 N, N, N, N, N, N, N, N, 4615 } }; 4616 4617 static const struct instr_dual instr_dual_0f_c3 = { 4618 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4619 }; 4620 4621 static const struct mode_dual mode_dual_63 = { 4622 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4623 }; 4624 4625 static const struct opcode opcode_table[256] = { 4626 /* 0x00 - 0x07 */ 4627 F6ALU(Lock, em_add), 4628 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4629 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4630 /* 0x08 - 0x0F */ 4631 F6ALU(Lock | PageTable, em_or), 4632 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4633 N, 4634 /* 0x10 - 0x17 */ 4635 F6ALU(Lock, em_adc), 4636 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4637 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4638 /* 0x18 - 0x1F */ 4639 F6ALU(Lock, em_sbb), 4640 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4641 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4642 /* 0x20 - 0x27 */ 4643 F6ALU(Lock | PageTable, em_and), N, N, 4644 /* 0x28 - 0x2F */ 4645 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4646 /* 0x30 - 0x37 */ 4647 F6ALU(Lock, em_xor), N, N, 4648 /* 0x38 - 0x3F */ 4649 F6ALU(NoWrite, em_cmp), N, N, 4650 /* 0x40 - 0x4F */ 4651 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4652 /* 0x50 - 0x57 */ 4653 X8(I(SrcReg | Stack, em_push)), 4654 /* 0x58 - 0x5F */ 4655 X8(I(DstReg | Stack, em_pop)), 4656 /* 0x60 - 0x67 */ 4657 I(ImplicitOps | Stack | No64, em_pusha), 4658 I(ImplicitOps | Stack | No64, em_popa), 4659 N, MD(ModRM, &mode_dual_63), 4660 N, N, N, N, 4661 /* 0x68 - 0x6F */ 4662 I(SrcImm | Mov | Stack, em_push), 4663 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4664 I(SrcImmByte | Mov | Stack, em_push), 4665 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4666 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4667 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4668 /* 0x70 - 0x7F */ 4669 X16(D(SrcImmByte | NearBranch)), 4670 /* 0x80 - 0x87 */ 4671 G(ByteOp | DstMem | SrcImm, group1), 4672 G(DstMem | SrcImm, group1), 4673 G(ByteOp | DstMem | SrcImm | No64, group1), 4674 G(DstMem | SrcImmByte, group1), 4675 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4676 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4677 /* 0x88 - 0x8F */ 4678 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4679 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4680 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4681 D(ModRM | SrcMem | NoAccess | DstReg), 4682 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4683 G(0, group1A), 4684 /* 0x90 - 0x97 */ 4685 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4686 /* 0x98 - 0x9F */ 4687 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4688 I(SrcImmFAddr | No64, em_call_far), N, 4689 II(ImplicitOps | Stack, em_pushf, pushf), 4690 II(ImplicitOps | Stack, em_popf, popf), 4691 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4692 /* 0xA0 - 0xA7 */ 4693 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4694 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4695 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4696 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4697 /* 0xA8 - 0xAF */ 4698 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4699 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4700 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4701 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4702 /* 0xB0 - 0xB7 */ 4703 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4704 /* 0xB8 - 0xBF */ 4705 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4706 /* 0xC0 - 0xC7 */ 4707 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4708 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), 4709 I(ImplicitOps | NearBranch, em_ret), 4710 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4711 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4712 G(ByteOp, group11), G(0, group11), 4713 /* 0xC8 - 0xCF */ 4714 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 4715 I(ImplicitOps | SrcImmU16, em_ret_far_imm), 4716 I(ImplicitOps, em_ret_far), 4717 D(ImplicitOps), DI(SrcImmByte, intn), 4718 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 4719 /* 0xD0 - 0xD7 */ 4720 G(Src2One | ByteOp, group2), G(Src2One, group2), 4721 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4722 I(DstAcc | SrcImmUByte | No64, em_aam), 4723 I(DstAcc | SrcImmUByte | No64, em_aad), 4724 F(DstAcc | ByteOp | No64, em_salc), 4725 I(DstAcc | SrcXLat | ByteOp, em_mov), 4726 /* 0xD8 - 0xDF */ 4727 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4728 /* 0xE0 - 0xE7 */ 4729 X3(I(SrcImmByte | NearBranch, em_loop)), 4730 I(SrcImmByte | NearBranch, em_jcxz), 4731 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4732 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4733 /* 0xE8 - 0xEF */ 4734 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), 4735 I(SrcImmFAddr | No64, em_jmp_far), 4736 D(SrcImmByte | ImplicitOps | NearBranch), 4737 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4738 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4739 /* 0xF0 - 0xF7 */ 4740 N, DI(ImplicitOps, icebp), N, N, 4741 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4742 G(ByteOp, group3), G(0, group3), 4743 /* 0xF8 - 0xFF */ 4744 D(ImplicitOps), D(ImplicitOps), 4745 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4746 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4747 }; 4748 4749 static const struct opcode twobyte_table[256] = { 4750 /* 0x00 - 0x0F */ 4751 G(0, group6), GD(0, &group7), N, N, 4752 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4753 II(ImplicitOps | Priv, em_clts, clts), N, 4754 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4755 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4756 /* 0x10 - 0x1F */ 4757 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4758 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4759 N, N, N, N, N, N, 4760 D(ImplicitOps | ModRM | SrcMem | NoAccess), 4761 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), 4762 /* 0x20 - 0x2F */ 4763 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 4764 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4765 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4766 check_cr_write), 4767 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4768 check_dr_write), 4769 N, N, N, N, 4770 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4771 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4772 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4773 N, N, N, N, 4774 /* 0x30 - 0x3F */ 4775 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4776 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4777 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4778 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4779 I(ImplicitOps | EmulateOnUD, em_sysenter), 4780 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 4781 N, N, 4782 N, N, N, N, N, N, N, N, 4783 /* 0x40 - 0x4F */ 4784 X16(D(DstReg | SrcMem | ModRM)), 4785 /* 0x50 - 0x5F */ 4786 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4787 /* 0x60 - 0x6F */ 4788 N, N, N, N, 4789 N, N, N, N, 4790 N, N, N, N, 4791 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4792 /* 0x70 - 0x7F */ 4793 N, N, N, N, 4794 N, N, N, N, 4795 N, N, N, N, 4796 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4797 /* 0x80 - 0x8F */ 4798 X16(D(SrcImm | NearBranch)), 4799 /* 0x90 - 0x9F */ 4800 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4801 /* 0xA0 - 0xA7 */ 4802 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4803 II(ImplicitOps, em_cpuid, cpuid), 4804 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4805 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4806 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4807 /* 0xA8 - 0xAF */ 4808 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4809 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4810 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4811 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4812 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4813 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4814 /* 0xB0 - 0xB7 */ 4815 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4816 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4817 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4818 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4819 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4820 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4821 /* 0xB8 - 0xBF */ 4822 N, N, 4823 G(BitOp, group8), 4824 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4825 I(DstReg | SrcMem | ModRM, em_bsf_c), 4826 I(DstReg | SrcMem | ModRM, em_bsr_c), 4827 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4828 /* 0xC0 - 0xC7 */ 4829 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4830 N, ID(0, &instr_dual_0f_c3), 4831 N, N, N, GD(0, &group9), 4832 /* 0xC8 - 0xCF */ 4833 X8(I(DstReg, em_bswap)), 4834 /* 0xD0 - 0xDF */ 4835 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4836 /* 0xE0 - 0xEF */ 4837 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4838 N, N, N, N, N, N, N, N, 4839 /* 0xF0 - 0xFF */ 4840 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4841 }; 4842 4843 static const struct instr_dual instr_dual_0f_38_f0 = { 4844 I(DstReg | SrcMem | Mov, em_movbe), N 4845 }; 4846 4847 static const struct instr_dual instr_dual_0f_38_f1 = { 4848 I(DstMem | SrcReg | Mov, em_movbe), N 4849 }; 4850 4851 static const struct gprefix three_byte_0f_38_f0 = { 4852 ID(0, &instr_dual_0f_38_f0), N, N, N 4853 }; 4854 4855 static const struct gprefix three_byte_0f_38_f1 = { 4856 ID(0, &instr_dual_0f_38_f1), N, N, N 4857 }; 4858 4859 /* 4860 * Insns below are selected by the prefix which indexed by the third opcode 4861 * byte. 4862 */ 4863 static const struct opcode opcode_map_0f_38[256] = { 4864 /* 0x00 - 0x7f */ 4865 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4866 /* 0x80 - 0xef */ 4867 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4868 /* 0xf0 - 0xf1 */ 4869 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4870 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4871 /* 0xf2 - 0xff */ 4872 N, N, X4(N), X8(N) 4873 }; 4874 4875 #undef D 4876 #undef N 4877 #undef G 4878 #undef GD 4879 #undef I 4880 #undef GP 4881 #undef EXT 4882 #undef MD 4883 #undef ID 4884 4885 #undef D2bv 4886 #undef D2bvIP 4887 #undef I2bv 4888 #undef I2bvIP 4889 #undef I6ALU 4890 4891 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4892 { 4893 unsigned size; 4894 4895 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4896 if (size == 8) 4897 size = 4; 4898 return size; 4899 } 4900 4901 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4902 unsigned size, bool sign_extension) 4903 { 4904 int rc = X86EMUL_CONTINUE; 4905 4906 op->type = OP_IMM; 4907 op->bytes = size; 4908 op->addr.mem.ea = ctxt->_eip; 4909 /* NB. Immediates are sign-extended as necessary. */ 4910 switch (op->bytes) { 4911 case 1: 4912 op->val = insn_fetch(s8, ctxt); 4913 break; 4914 case 2: 4915 op->val = insn_fetch(s16, ctxt); 4916 break; 4917 case 4: 4918 op->val = insn_fetch(s32, ctxt); 4919 break; 4920 case 8: 4921 op->val = insn_fetch(s64, ctxt); 4922 break; 4923 } 4924 if (!sign_extension) { 4925 switch (op->bytes) { 4926 case 1: 4927 op->val &= 0xff; 4928 break; 4929 case 2: 4930 op->val &= 0xffff; 4931 break; 4932 case 4: 4933 op->val &= 0xffffffff; 4934 break; 4935 } 4936 } 4937 done: 4938 return rc; 4939 } 4940 4941 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4942 unsigned d) 4943 { 4944 int rc = X86EMUL_CONTINUE; 4945 4946 switch (d) { 4947 case OpReg: 4948 decode_register_operand(ctxt, op); 4949 break; 4950 case OpImmUByte: 4951 rc = decode_imm(ctxt, op, 1, false); 4952 break; 4953 case OpMem: 4954 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4955 mem_common: 4956 *op = ctxt->memop; 4957 ctxt->memopp = op; 4958 if (ctxt->d & BitOp) 4959 fetch_bit_operand(ctxt); 4960 op->orig_val = op->val; 4961 break; 4962 case OpMem64: 4963 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4964 goto mem_common; 4965 case OpAcc: 4966 op->type = OP_REG; 4967 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4968 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4969 fetch_register_operand(op); 4970 op->orig_val = op->val; 4971 break; 4972 case OpAccLo: 4973 op->type = OP_REG; 4974 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4975 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4976 fetch_register_operand(op); 4977 op->orig_val = op->val; 4978 break; 4979 case OpAccHi: 4980 if (ctxt->d & ByteOp) { 4981 op->type = OP_NONE; 4982 break; 4983 } 4984 op->type = OP_REG; 4985 op->bytes = ctxt->op_bytes; 4986 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4987 fetch_register_operand(op); 4988 op->orig_val = op->val; 4989 break; 4990 case OpDI: 4991 op->type = OP_MEM; 4992 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4993 op->addr.mem.ea = 4994 register_address(ctxt, VCPU_REGS_RDI); 4995 op->addr.mem.seg = VCPU_SREG_ES; 4996 op->val = 0; 4997 op->count = 1; 4998 break; 4999 case OpDX: 5000 op->type = OP_REG; 5001 op->bytes = 2; 5002 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 5003 fetch_register_operand(op); 5004 break; 5005 case OpCL: 5006 op->type = OP_IMM; 5007 op->bytes = 1; 5008 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 5009 break; 5010 case OpImmByte: 5011 rc = decode_imm(ctxt, op, 1, true); 5012 break; 5013 case OpOne: 5014 op->type = OP_IMM; 5015 op->bytes = 1; 5016 op->val = 1; 5017 break; 5018 case OpImm: 5019 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 5020 break; 5021 case OpImm64: 5022 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 5023 break; 5024 case OpMem8: 5025 ctxt->memop.bytes = 1; 5026 if (ctxt->memop.type == OP_REG) { 5027 ctxt->memop.addr.reg = decode_register(ctxt, 5028 ctxt->modrm_rm, true); 5029 fetch_register_operand(&ctxt->memop); 5030 } 5031 goto mem_common; 5032 case OpMem16: 5033 ctxt->memop.bytes = 2; 5034 goto mem_common; 5035 case OpMem32: 5036 ctxt->memop.bytes = 4; 5037 goto mem_common; 5038 case OpImmU16: 5039 rc = decode_imm(ctxt, op, 2, false); 5040 break; 5041 case OpImmU: 5042 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 5043 break; 5044 case OpSI: 5045 op->type = OP_MEM; 5046 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5047 op->addr.mem.ea = 5048 register_address(ctxt, VCPU_REGS_RSI); 5049 op->addr.mem.seg = ctxt->seg_override; 5050 op->val = 0; 5051 op->count = 1; 5052 break; 5053 case OpXLat: 5054 op->type = OP_MEM; 5055 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5056 op->addr.mem.ea = 5057 address_mask(ctxt, 5058 reg_read(ctxt, VCPU_REGS_RBX) + 5059 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 5060 op->addr.mem.seg = ctxt->seg_override; 5061 op->val = 0; 5062 break; 5063 case OpImmFAddr: 5064 op->type = OP_IMM; 5065 op->addr.mem.ea = ctxt->_eip; 5066 op->bytes = ctxt->op_bytes + 2; 5067 insn_fetch_arr(op->valptr, op->bytes, ctxt); 5068 break; 5069 case OpMemFAddr: 5070 ctxt->memop.bytes = ctxt->op_bytes + 2; 5071 goto mem_common; 5072 case OpES: 5073 op->type = OP_IMM; 5074 op->val = VCPU_SREG_ES; 5075 break; 5076 case OpCS: 5077 op->type = OP_IMM; 5078 op->val = VCPU_SREG_CS; 5079 break; 5080 case OpSS: 5081 op->type = OP_IMM; 5082 op->val = VCPU_SREG_SS; 5083 break; 5084 case OpDS: 5085 op->type = OP_IMM; 5086 op->val = VCPU_SREG_DS; 5087 break; 5088 case OpFS: 5089 op->type = OP_IMM; 5090 op->val = VCPU_SREG_FS; 5091 break; 5092 case OpGS: 5093 op->type = OP_IMM; 5094 op->val = VCPU_SREG_GS; 5095 break; 5096 case OpImplicit: 5097 /* Special instructions do their own operand decoding. */ 5098 default: 5099 op->type = OP_NONE; /* Disable writeback. */ 5100 break; 5101 } 5102 5103 done: 5104 return rc; 5105 } 5106 5107 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 5108 { 5109 int rc = X86EMUL_CONTINUE; 5110 int mode = ctxt->mode; 5111 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 5112 bool op_prefix = false; 5113 bool has_seg_override = false; 5114 struct opcode opcode; 5115 u16 dummy; 5116 struct desc_struct desc; 5117 5118 ctxt->memop.type = OP_NONE; 5119 ctxt->memopp = NULL; 5120 ctxt->_eip = ctxt->eip; 5121 ctxt->fetch.ptr = ctxt->fetch.data; 5122 ctxt->fetch.end = ctxt->fetch.data + insn_len; 5123 ctxt->opcode_len = 1; 5124 if (insn_len > 0) 5125 memcpy(ctxt->fetch.data, insn, insn_len); 5126 else { 5127 rc = __do_insn_fetch_bytes(ctxt, 1); 5128 if (rc != X86EMUL_CONTINUE) 5129 return rc; 5130 } 5131 5132 switch (mode) { 5133 case X86EMUL_MODE_REAL: 5134 case X86EMUL_MODE_VM86: 5135 def_op_bytes = def_ad_bytes = 2; 5136 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 5137 if (desc.d) 5138 def_op_bytes = def_ad_bytes = 4; 5139 break; 5140 case X86EMUL_MODE_PROT16: 5141 def_op_bytes = def_ad_bytes = 2; 5142 break; 5143 case X86EMUL_MODE_PROT32: 5144 def_op_bytes = def_ad_bytes = 4; 5145 break; 5146 #ifdef CONFIG_X86_64 5147 case X86EMUL_MODE_PROT64: 5148 def_op_bytes = 4; 5149 def_ad_bytes = 8; 5150 break; 5151 #endif 5152 default: 5153 return EMULATION_FAILED; 5154 } 5155 5156 ctxt->op_bytes = def_op_bytes; 5157 ctxt->ad_bytes = def_ad_bytes; 5158 5159 /* Legacy prefixes. */ 5160 for (;;) { 5161 switch (ctxt->b = insn_fetch(u8, ctxt)) { 5162 case 0x66: /* operand-size override */ 5163 op_prefix = true; 5164 /* switch between 2/4 bytes */ 5165 ctxt->op_bytes = def_op_bytes ^ 6; 5166 break; 5167 case 0x67: /* address-size override */ 5168 if (mode == X86EMUL_MODE_PROT64) 5169 /* switch between 4/8 bytes */ 5170 ctxt->ad_bytes = def_ad_bytes ^ 12; 5171 else 5172 /* switch between 2/4 bytes */ 5173 ctxt->ad_bytes = def_ad_bytes ^ 6; 5174 break; 5175 case 0x26: /* ES override */ 5176 case 0x2e: /* CS override */ 5177 case 0x36: /* SS override */ 5178 case 0x3e: /* DS override */ 5179 has_seg_override = true; 5180 ctxt->seg_override = (ctxt->b >> 3) & 3; 5181 break; 5182 case 0x64: /* FS override */ 5183 case 0x65: /* GS override */ 5184 has_seg_override = true; 5185 ctxt->seg_override = ctxt->b & 7; 5186 break; 5187 case 0x40 ... 0x4f: /* REX */ 5188 if (mode != X86EMUL_MODE_PROT64) 5189 goto done_prefixes; 5190 ctxt->rex_prefix = ctxt->b; 5191 continue; 5192 case 0xf0: /* LOCK */ 5193 ctxt->lock_prefix = 1; 5194 break; 5195 case 0xf2: /* REPNE/REPNZ */ 5196 case 0xf3: /* REP/REPE/REPZ */ 5197 ctxt->rep_prefix = ctxt->b; 5198 break; 5199 default: 5200 goto done_prefixes; 5201 } 5202 5203 /* Any legacy prefix after a REX prefix nullifies its effect. */ 5204 5205 ctxt->rex_prefix = 0; 5206 } 5207 5208 done_prefixes: 5209 5210 /* REX prefix. */ 5211 if (ctxt->rex_prefix & 8) 5212 ctxt->op_bytes = 8; /* REX.W */ 5213 5214 /* Opcode byte(s). */ 5215 opcode = opcode_table[ctxt->b]; 5216 /* Two-byte opcode? */ 5217 if (ctxt->b == 0x0f) { 5218 ctxt->opcode_len = 2; 5219 ctxt->b = insn_fetch(u8, ctxt); 5220 opcode = twobyte_table[ctxt->b]; 5221 5222 /* 0F_38 opcode map */ 5223 if (ctxt->b == 0x38) { 5224 ctxt->opcode_len = 3; 5225 ctxt->b = insn_fetch(u8, ctxt); 5226 opcode = opcode_map_0f_38[ctxt->b]; 5227 } 5228 } 5229 ctxt->d = opcode.flags; 5230 5231 if (ctxt->d & ModRM) 5232 ctxt->modrm = insn_fetch(u8, ctxt); 5233 5234 /* vex-prefix instructions are not implemented */ 5235 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 5236 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 5237 ctxt->d = NotImpl; 5238 } 5239 5240 while (ctxt->d & GroupMask) { 5241 switch (ctxt->d & GroupMask) { 5242 case Group: 5243 goffset = (ctxt->modrm >> 3) & 7; 5244 opcode = opcode.u.group[goffset]; 5245 break; 5246 case GroupDual: 5247 goffset = (ctxt->modrm >> 3) & 7; 5248 if ((ctxt->modrm >> 6) == 3) 5249 opcode = opcode.u.gdual->mod3[goffset]; 5250 else 5251 opcode = opcode.u.gdual->mod012[goffset]; 5252 break; 5253 case RMExt: 5254 goffset = ctxt->modrm & 7; 5255 opcode = opcode.u.group[goffset]; 5256 break; 5257 case Prefix: 5258 if (ctxt->rep_prefix && op_prefix) 5259 return EMULATION_FAILED; 5260 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 5261 switch (simd_prefix) { 5262 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5263 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5264 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5265 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5266 } 5267 break; 5268 case Escape: 5269 if (ctxt->modrm > 0xbf) 5270 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 5271 else 5272 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5273 break; 5274 case InstrDual: 5275 if ((ctxt->modrm >> 6) == 3) 5276 opcode = opcode.u.idual->mod3; 5277 else 5278 opcode = opcode.u.idual->mod012; 5279 break; 5280 case ModeDual: 5281 if (ctxt->mode == X86EMUL_MODE_PROT64) 5282 opcode = opcode.u.mdual->mode64; 5283 else 5284 opcode = opcode.u.mdual->mode32; 5285 break; 5286 default: 5287 return EMULATION_FAILED; 5288 } 5289 5290 ctxt->d &= ~(u64)GroupMask; 5291 ctxt->d |= opcode.flags; 5292 } 5293 5294 /* Unrecognised? */ 5295 if (ctxt->d == 0) 5296 return EMULATION_FAILED; 5297 5298 ctxt->execute = opcode.u.execute; 5299 5300 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 5301 return EMULATION_FAILED; 5302 5303 if (unlikely(ctxt->d & 5304 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5305 No16))) { 5306 /* 5307 * These are copied unconditionally here, and checked unconditionally 5308 * in x86_emulate_insn. 5309 */ 5310 ctxt->check_perm = opcode.check_perm; 5311 ctxt->intercept = opcode.intercept; 5312 5313 if (ctxt->d & NotImpl) 5314 return EMULATION_FAILED; 5315 5316 if (mode == X86EMUL_MODE_PROT64) { 5317 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5318 ctxt->op_bytes = 8; 5319 else if (ctxt->d & NearBranch) 5320 ctxt->op_bytes = 8; 5321 } 5322 5323 if (ctxt->d & Op3264) { 5324 if (mode == X86EMUL_MODE_PROT64) 5325 ctxt->op_bytes = 8; 5326 else 5327 ctxt->op_bytes = 4; 5328 } 5329 5330 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5331 ctxt->op_bytes = 4; 5332 5333 if (ctxt->d & Sse) 5334 ctxt->op_bytes = 16; 5335 else if (ctxt->d & Mmx) 5336 ctxt->op_bytes = 8; 5337 } 5338 5339 /* ModRM and SIB bytes. */ 5340 if (ctxt->d & ModRM) { 5341 rc = decode_modrm(ctxt, &ctxt->memop); 5342 if (!has_seg_override) { 5343 has_seg_override = true; 5344 ctxt->seg_override = ctxt->modrm_seg; 5345 } 5346 } else if (ctxt->d & MemAbs) 5347 rc = decode_abs(ctxt, &ctxt->memop); 5348 if (rc != X86EMUL_CONTINUE) 5349 goto done; 5350 5351 if (!has_seg_override) 5352 ctxt->seg_override = VCPU_SREG_DS; 5353 5354 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5355 5356 /* 5357 * Decode and fetch the source operand: register, memory 5358 * or immediate. 5359 */ 5360 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5361 if (rc != X86EMUL_CONTINUE) 5362 goto done; 5363 5364 /* 5365 * Decode and fetch the second source operand: register, memory 5366 * or immediate. 5367 */ 5368 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5369 if (rc != X86EMUL_CONTINUE) 5370 goto done; 5371 5372 /* Decode and fetch the destination operand: register or memory. */ 5373 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5374 5375 if (ctxt->rip_relative && likely(ctxt->memopp)) 5376 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5377 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5378 5379 done: 5380 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5381 } 5382 5383 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5384 { 5385 return ctxt->d & PageTable; 5386 } 5387 5388 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5389 { 5390 /* The second termination condition only applies for REPE 5391 * and REPNE. Test if the repeat string operation prefix is 5392 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5393 * corresponding termination condition according to: 5394 * - if REPE/REPZ and ZF = 0 then done 5395 * - if REPNE/REPNZ and ZF = 1 then done 5396 */ 5397 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5398 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5399 && (((ctxt->rep_prefix == REPE_PREFIX) && 5400 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5401 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5402 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5403 return true; 5404 5405 return false; 5406 } 5407 5408 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5409 { 5410 int rc; 5411 5412 rc = asm_safe("fwait"); 5413 5414 if (unlikely(rc != X86EMUL_CONTINUE)) 5415 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5416 5417 return X86EMUL_CONTINUE; 5418 } 5419 5420 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 5421 struct operand *op) 5422 { 5423 if (op->type == OP_MM) 5424 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 5425 } 5426 5427 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 5428 { 5429 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5430 5431 if (!(ctxt->d & ByteOp)) 5432 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5433 5434 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5435 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5436 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5437 : "c"(ctxt->src2.val)); 5438 5439 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5440 if (!fop) /* exception is returned in fop variable */ 5441 return emulate_de(ctxt); 5442 return X86EMUL_CONTINUE; 5443 } 5444 5445 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5446 { 5447 memset(&ctxt->rip_relative, 0, 5448 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 5449 5450 ctxt->io_read.pos = 0; 5451 ctxt->io_read.end = 0; 5452 ctxt->mem_read.end = 0; 5453 } 5454 5455 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5456 { 5457 const struct x86_emulate_ops *ops = ctxt->ops; 5458 int rc = X86EMUL_CONTINUE; 5459 int saved_dst_type = ctxt->dst.type; 5460 unsigned emul_flags; 5461 5462 ctxt->mem_read.pos = 0; 5463 5464 /* LOCK prefix is allowed only with some instructions */ 5465 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5466 rc = emulate_ud(ctxt); 5467 goto done; 5468 } 5469 5470 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5471 rc = emulate_ud(ctxt); 5472 goto done; 5473 } 5474 5475 emul_flags = ctxt->ops->get_hflags(ctxt); 5476 if (unlikely(ctxt->d & 5477 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5478 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5479 (ctxt->d & Undefined)) { 5480 rc = emulate_ud(ctxt); 5481 goto done; 5482 } 5483 5484 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5485 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5486 rc = emulate_ud(ctxt); 5487 goto done; 5488 } 5489 5490 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5491 rc = emulate_nm(ctxt); 5492 goto done; 5493 } 5494 5495 if (ctxt->d & Mmx) { 5496 rc = flush_pending_x87_faults(ctxt); 5497 if (rc != X86EMUL_CONTINUE) 5498 goto done; 5499 /* 5500 * Now that we know the fpu is exception safe, we can fetch 5501 * operands from it. 5502 */ 5503 fetch_possible_mmx_operand(ctxt, &ctxt->src); 5504 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 5505 if (!(ctxt->d & Mov)) 5506 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 5507 } 5508 5509 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5510 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5511 X86_ICPT_PRE_EXCEPT); 5512 if (rc != X86EMUL_CONTINUE) 5513 goto done; 5514 } 5515 5516 /* Instruction can only be executed in protected mode */ 5517 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5518 rc = emulate_ud(ctxt); 5519 goto done; 5520 } 5521 5522 /* Privileged instruction can be executed only in CPL=0 */ 5523 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5524 if (ctxt->d & PrivUD) 5525 rc = emulate_ud(ctxt); 5526 else 5527 rc = emulate_gp(ctxt, 0); 5528 goto done; 5529 } 5530 5531 /* Do instruction specific permission checks */ 5532 if (ctxt->d & CheckPerm) { 5533 rc = ctxt->check_perm(ctxt); 5534 if (rc != X86EMUL_CONTINUE) 5535 goto done; 5536 } 5537 5538 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5539 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5540 X86_ICPT_POST_EXCEPT); 5541 if (rc != X86EMUL_CONTINUE) 5542 goto done; 5543 } 5544 5545 if (ctxt->rep_prefix && (ctxt->d & String)) { 5546 /* All REP prefixes have the same first termination condition */ 5547 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5548 string_registers_quirk(ctxt); 5549 ctxt->eip = ctxt->_eip; 5550 ctxt->eflags &= ~X86_EFLAGS_RF; 5551 goto done; 5552 } 5553 } 5554 } 5555 5556 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5557 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5558 ctxt->src.valptr, ctxt->src.bytes); 5559 if (rc != X86EMUL_CONTINUE) 5560 goto done; 5561 ctxt->src.orig_val64 = ctxt->src.val64; 5562 } 5563 5564 if (ctxt->src2.type == OP_MEM) { 5565 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5566 &ctxt->src2.val, ctxt->src2.bytes); 5567 if (rc != X86EMUL_CONTINUE) 5568 goto done; 5569 } 5570 5571 if ((ctxt->d & DstMask) == ImplicitOps) 5572 goto special_insn; 5573 5574 5575 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5576 /* optimisation - avoid slow emulated read if Mov */ 5577 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5578 &ctxt->dst.val, ctxt->dst.bytes); 5579 if (rc != X86EMUL_CONTINUE) { 5580 if (!(ctxt->d & NoWrite) && 5581 rc == X86EMUL_PROPAGATE_FAULT && 5582 ctxt->exception.vector == PF_VECTOR) 5583 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5584 goto done; 5585 } 5586 } 5587 /* Copy full 64-bit value for CMPXCHG8B. */ 5588 ctxt->dst.orig_val64 = ctxt->dst.val64; 5589 5590 special_insn: 5591 5592 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5593 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5594 X86_ICPT_POST_MEMACCESS); 5595 if (rc != X86EMUL_CONTINUE) 5596 goto done; 5597 } 5598 5599 if (ctxt->rep_prefix && (ctxt->d & String)) 5600 ctxt->eflags |= X86_EFLAGS_RF; 5601 else 5602 ctxt->eflags &= ~X86_EFLAGS_RF; 5603 5604 if (ctxt->execute) { 5605 if (ctxt->d & Fastop) { 5606 void (*fop)(struct fastop *) = (void *)ctxt->execute; 5607 rc = fastop(ctxt, fop); 5608 if (rc != X86EMUL_CONTINUE) 5609 goto done; 5610 goto writeback; 5611 } 5612 rc = ctxt->execute(ctxt); 5613 if (rc != X86EMUL_CONTINUE) 5614 goto done; 5615 goto writeback; 5616 } 5617 5618 if (ctxt->opcode_len == 2) 5619 goto twobyte_insn; 5620 else if (ctxt->opcode_len == 3) 5621 goto threebyte_insn; 5622 5623 switch (ctxt->b) { 5624 case 0x70 ... 0x7f: /* jcc (short) */ 5625 if (test_cc(ctxt->b, ctxt->eflags)) 5626 rc = jmp_rel(ctxt, ctxt->src.val); 5627 break; 5628 case 0x8d: /* lea r16/r32, m */ 5629 ctxt->dst.val = ctxt->src.addr.mem.ea; 5630 break; 5631 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5632 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5633 ctxt->dst.type = OP_NONE; 5634 else 5635 rc = em_xchg(ctxt); 5636 break; 5637 case 0x98: /* cbw/cwde/cdqe */ 5638 switch (ctxt->op_bytes) { 5639 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5640 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5641 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5642 } 5643 break; 5644 case 0xcc: /* int3 */ 5645 rc = emulate_int(ctxt, 3); 5646 break; 5647 case 0xcd: /* int n */ 5648 rc = emulate_int(ctxt, ctxt->src.val); 5649 break; 5650 case 0xce: /* into */ 5651 if (ctxt->eflags & X86_EFLAGS_OF) 5652 rc = emulate_int(ctxt, 4); 5653 break; 5654 case 0xe9: /* jmp rel */ 5655 case 0xeb: /* jmp rel short */ 5656 rc = jmp_rel(ctxt, ctxt->src.val); 5657 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5658 break; 5659 case 0xf4: /* hlt */ 5660 ctxt->ops->halt(ctxt); 5661 break; 5662 case 0xf5: /* cmc */ 5663 /* complement carry flag from eflags reg */ 5664 ctxt->eflags ^= X86_EFLAGS_CF; 5665 break; 5666 case 0xf8: /* clc */ 5667 ctxt->eflags &= ~X86_EFLAGS_CF; 5668 break; 5669 case 0xf9: /* stc */ 5670 ctxt->eflags |= X86_EFLAGS_CF; 5671 break; 5672 case 0xfc: /* cld */ 5673 ctxt->eflags &= ~X86_EFLAGS_DF; 5674 break; 5675 case 0xfd: /* std */ 5676 ctxt->eflags |= X86_EFLAGS_DF; 5677 break; 5678 default: 5679 goto cannot_emulate; 5680 } 5681 5682 if (rc != X86EMUL_CONTINUE) 5683 goto done; 5684 5685 writeback: 5686 if (ctxt->d & SrcWrite) { 5687 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5688 rc = writeback(ctxt, &ctxt->src); 5689 if (rc != X86EMUL_CONTINUE) 5690 goto done; 5691 } 5692 if (!(ctxt->d & NoWrite)) { 5693 rc = writeback(ctxt, &ctxt->dst); 5694 if (rc != X86EMUL_CONTINUE) 5695 goto done; 5696 } 5697 5698 /* 5699 * restore dst type in case the decoding will be reused 5700 * (happens for string instruction ) 5701 */ 5702 ctxt->dst.type = saved_dst_type; 5703 5704 if ((ctxt->d & SrcMask) == SrcSI) 5705 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5706 5707 if ((ctxt->d & DstMask) == DstDI) 5708 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5709 5710 if (ctxt->rep_prefix && (ctxt->d & String)) { 5711 unsigned int count; 5712 struct read_cache *r = &ctxt->io_read; 5713 if ((ctxt->d & SrcMask) == SrcSI) 5714 count = ctxt->src.count; 5715 else 5716 count = ctxt->dst.count; 5717 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5718 5719 if (!string_insn_completed(ctxt)) { 5720 /* 5721 * Re-enter guest when pio read ahead buffer is empty 5722 * or, if it is not used, after each 1024 iteration. 5723 */ 5724 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5725 (r->end == 0 || r->end != r->pos)) { 5726 /* 5727 * Reset read cache. Usually happens before 5728 * decode, but since instruction is restarted 5729 * we have to do it here. 5730 */ 5731 ctxt->mem_read.end = 0; 5732 writeback_registers(ctxt); 5733 return EMULATION_RESTART; 5734 } 5735 goto done; /* skip rip writeback */ 5736 } 5737 ctxt->eflags &= ~X86_EFLAGS_RF; 5738 } 5739 5740 ctxt->eip = ctxt->_eip; 5741 5742 done: 5743 if (rc == X86EMUL_PROPAGATE_FAULT) { 5744 WARN_ON(ctxt->exception.vector > 0x1f); 5745 ctxt->have_exception = true; 5746 } 5747 if (rc == X86EMUL_INTERCEPTED) 5748 return EMULATION_INTERCEPTED; 5749 5750 if (rc == X86EMUL_CONTINUE) 5751 writeback_registers(ctxt); 5752 5753 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5754 5755 twobyte_insn: 5756 switch (ctxt->b) { 5757 case 0x09: /* wbinvd */ 5758 (ctxt->ops->wbinvd)(ctxt); 5759 break; 5760 case 0x08: /* invd */ 5761 case 0x0d: /* GrpP (prefetch) */ 5762 case 0x18: /* Grp16 (prefetch/nop) */ 5763 case 0x1f: /* nop */ 5764 break; 5765 case 0x20: /* mov cr, reg */ 5766 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5767 break; 5768 case 0x21: /* mov from dr to reg */ 5769 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5770 break; 5771 case 0x40 ... 0x4f: /* cmov */ 5772 if (test_cc(ctxt->b, ctxt->eflags)) 5773 ctxt->dst.val = ctxt->src.val; 5774 else if (ctxt->op_bytes != 4) 5775 ctxt->dst.type = OP_NONE; /* no writeback */ 5776 break; 5777 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5778 if (test_cc(ctxt->b, ctxt->eflags)) 5779 rc = jmp_rel(ctxt, ctxt->src.val); 5780 break; 5781 case 0x90 ... 0x9f: /* setcc r/m8 */ 5782 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5783 break; 5784 case 0xb6 ... 0xb7: /* movzx */ 5785 ctxt->dst.bytes = ctxt->op_bytes; 5786 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5787 : (u16) ctxt->src.val; 5788 break; 5789 case 0xbe ... 0xbf: /* movsx */ 5790 ctxt->dst.bytes = ctxt->op_bytes; 5791 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5792 (s16) ctxt->src.val; 5793 break; 5794 default: 5795 goto cannot_emulate; 5796 } 5797 5798 threebyte_insn: 5799 5800 if (rc != X86EMUL_CONTINUE) 5801 goto done; 5802 5803 goto writeback; 5804 5805 cannot_emulate: 5806 return EMULATION_FAILED; 5807 } 5808 5809 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5810 { 5811 invalidate_registers(ctxt); 5812 } 5813 5814 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5815 { 5816 writeback_registers(ctxt); 5817 } 5818 5819 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5820 { 5821 if (ctxt->rep_prefix && (ctxt->d & String)) 5822 return false; 5823 5824 if (ctxt->d & TwoMemOp) 5825 return false; 5826 5827 return true; 5828 } 5829