1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/kvm_host.h> 23 #include "kvm_cache_regs.h" 24 #include "kvm_emulate.h" 25 #include <linux/stringify.h> 26 #include <asm/debugreg.h> 27 #include <asm/nospec-branch.h> 28 #include <asm/ibt.h> 29 30 #include "x86.h" 31 #include "tss.h" 32 #include "mmu.h" 33 #include "pmu.h" 34 35 /* 36 * Operand types 37 */ 38 #define OpNone 0ull 39 #define OpImplicit 1ull /* No generic decode */ 40 #define OpReg 2ull /* Register */ 41 #define OpMem 3ull /* Memory */ 42 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 43 #define OpDI 5ull /* ES:DI/EDI/RDI */ 44 #define OpMem64 6ull /* Memory, 64-bit */ 45 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 46 #define OpDX 8ull /* DX register */ 47 #define OpCL 9ull /* CL register (for shifts) */ 48 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 49 #define OpOne 11ull /* Implied 1 */ 50 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 51 #define OpMem16 13ull /* Memory operand (16-bit). */ 52 #define OpMem32 14ull /* Memory operand (32-bit). */ 53 #define OpImmU 15ull /* Immediate operand, zero extended */ 54 #define OpSI 16ull /* SI/ESI/RSI */ 55 #define OpImmFAddr 17ull /* Immediate far address */ 56 #define OpMemFAddr 18ull /* Far address in memory */ 57 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 58 #define OpES 20ull /* ES */ 59 #define OpCS 21ull /* CS */ 60 #define OpSS 22ull /* SS */ 61 #define OpDS 23ull /* DS */ 62 #define OpFS 24ull /* FS */ 63 #define OpGS 25ull /* GS */ 64 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 65 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 66 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 67 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 68 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 69 70 #define OpBits 5 /* Width of operand field */ 71 #define OpMask ((1ull << OpBits) - 1) 72 73 /* 74 * Opcode effective-address decode tables. 75 * Note that we only emulate instructions that have at least one memory 76 * operand (excluding implicit stack references). We assume that stack 77 * references and instruction fetches will never occur in special memory 78 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 79 * not be handled. 80 */ 81 82 /* Operand sizes: 8-bit operands or specified/overridden size. */ 83 #define ByteOp (1<<0) /* 8-bit operands. */ 84 /* Destination operand type. */ 85 #define DstShift 1 86 #define ImplicitOps (OpImplicit << DstShift) 87 #define DstReg (OpReg << DstShift) 88 #define DstMem (OpMem << DstShift) 89 #define DstAcc (OpAcc << DstShift) 90 #define DstDI (OpDI << DstShift) 91 #define DstMem64 (OpMem64 << DstShift) 92 #define DstMem16 (OpMem16 << DstShift) 93 #define DstImmUByte (OpImmUByte << DstShift) 94 #define DstDX (OpDX << DstShift) 95 #define DstAccLo (OpAccLo << DstShift) 96 #define DstMask (OpMask << DstShift) 97 /* Source operand type. */ 98 #define SrcShift 6 99 #define SrcNone (OpNone << SrcShift) 100 #define SrcReg (OpReg << SrcShift) 101 #define SrcMem (OpMem << SrcShift) 102 #define SrcMem16 (OpMem16 << SrcShift) 103 #define SrcMem32 (OpMem32 << SrcShift) 104 #define SrcImm (OpImm << SrcShift) 105 #define SrcImmByte (OpImmByte << SrcShift) 106 #define SrcOne (OpOne << SrcShift) 107 #define SrcImmUByte (OpImmUByte << SrcShift) 108 #define SrcImmU (OpImmU << SrcShift) 109 #define SrcSI (OpSI << SrcShift) 110 #define SrcXLat (OpXLat << SrcShift) 111 #define SrcImmFAddr (OpImmFAddr << SrcShift) 112 #define SrcMemFAddr (OpMemFAddr << SrcShift) 113 #define SrcAcc (OpAcc << SrcShift) 114 #define SrcImmU16 (OpImmU16 << SrcShift) 115 #define SrcImm64 (OpImm64 << SrcShift) 116 #define SrcDX (OpDX << SrcShift) 117 #define SrcMem8 (OpMem8 << SrcShift) 118 #define SrcAccHi (OpAccHi << SrcShift) 119 #define SrcMask (OpMask << SrcShift) 120 #define BitOp (1<<11) 121 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 122 #define String (1<<13) /* String instruction (rep capable) */ 123 #define Stack (1<<14) /* Stack instruction (push/pop) */ 124 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 125 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 126 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 127 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 128 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 129 #define Escape (5<<15) /* Escape to coprocessor instruction */ 130 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 131 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 132 #define Sse (1<<18) /* SSE Vector instruction */ 133 /* Generic ModRM decode. */ 134 #define ModRM (1<<19) 135 /* Destination is only written; never read. */ 136 #define Mov (1<<20) 137 /* Misc flags */ 138 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 139 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 140 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 141 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 142 #define Undefined (1<<25) /* No Such Instruction */ 143 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 144 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 145 #define No64 (1<<28) 146 #define PageTable (1 << 29) /* instruction used to write page table */ 147 #define NotImpl (1 << 30) /* instruction is not implemented */ 148 /* Source 2 operand type */ 149 #define Src2Shift (31) 150 #define Src2None (OpNone << Src2Shift) 151 #define Src2Mem (OpMem << Src2Shift) 152 #define Src2CL (OpCL << Src2Shift) 153 #define Src2ImmByte (OpImmByte << Src2Shift) 154 #define Src2One (OpOne << Src2Shift) 155 #define Src2Imm (OpImm << Src2Shift) 156 #define Src2ES (OpES << Src2Shift) 157 #define Src2CS (OpCS << Src2Shift) 158 #define Src2SS (OpSS << Src2Shift) 159 #define Src2DS (OpDS << Src2Shift) 160 #define Src2FS (OpFS << Src2Shift) 161 #define Src2GS (OpGS << Src2Shift) 162 #define Src2Mask (OpMask << Src2Shift) 163 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 164 #define AlignMask ((u64)7 << 41) 165 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 166 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 167 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 168 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 169 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 170 #define NoWrite ((u64)1 << 45) /* No writeback */ 171 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 172 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 173 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 174 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 175 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 176 #define NearBranch ((u64)1 << 52) /* Near branches */ 177 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 178 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 179 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 180 #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ 181 182 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 183 184 #define X2(x...) x, x 185 #define X3(x...) X2(x), x 186 #define X4(x...) X2(x), X2(x) 187 #define X5(x...) X4(x), x 188 #define X6(x...) X4(x), X2(x) 189 #define X7(x...) X4(x), X3(x) 190 #define X8(x...) X4(x), X4(x) 191 #define X16(x...) X8(x), X8(x) 192 193 struct opcode { 194 u64 flags; 195 u8 intercept; 196 u8 pad[7]; 197 union { 198 int (*execute)(struct x86_emulate_ctxt *ctxt); 199 const struct opcode *group; 200 const struct group_dual *gdual; 201 const struct gprefix *gprefix; 202 const struct escape *esc; 203 const struct instr_dual *idual; 204 const struct mode_dual *mdual; 205 void (*fastop)(struct fastop *fake); 206 } u; 207 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 208 }; 209 210 struct group_dual { 211 struct opcode mod012[8]; 212 struct opcode mod3[8]; 213 }; 214 215 struct gprefix { 216 struct opcode pfx_no; 217 struct opcode pfx_66; 218 struct opcode pfx_f2; 219 struct opcode pfx_f3; 220 }; 221 222 struct escape { 223 struct opcode op[8]; 224 struct opcode high[64]; 225 }; 226 227 struct instr_dual { 228 struct opcode mod012; 229 struct opcode mod3; 230 }; 231 232 struct mode_dual { 233 struct opcode mode32; 234 struct opcode mode64; 235 }; 236 237 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 238 239 enum x86_transfer_type { 240 X86_TRANSFER_NONE, 241 X86_TRANSFER_CALL_JMP, 242 X86_TRANSFER_RET, 243 X86_TRANSFER_TASK_SWITCH, 244 }; 245 246 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 247 { 248 unsigned long dirty = ctxt->regs_dirty; 249 unsigned reg; 250 251 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS) 252 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 253 } 254 255 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 256 { 257 ctxt->regs_dirty = 0; 258 ctxt->regs_valid = 0; 259 } 260 261 /* 262 * These EFLAGS bits are restored from saved value during emulation, and 263 * any changes are written back to the saved value after emulation. 264 */ 265 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 266 X86_EFLAGS_PF|X86_EFLAGS_CF) 267 268 #ifdef CONFIG_X86_64 269 #define ON64(x) x 270 #else 271 #define ON64(x) 272 #endif 273 274 /* 275 * fastop functions have a special calling convention: 276 * 277 * dst: rax (in/out) 278 * src: rdx (in/out) 279 * src2: rcx (in) 280 * flags: rflags (in/out) 281 * ex: rsi (in:fastop pointer, out:zero if exception) 282 * 283 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 284 * different operand sizes can be reached by calculation, rather than a jump 285 * table (which would be bigger than the code). 286 * 287 * The 16 byte alignment, considering 5 bytes for the RET thunk, 3 for ENDBR 288 * and 1 for the straight line speculation INT3, leaves 7 bytes for the 289 * body of the function. Currently none is larger than 4. 290 */ 291 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); 292 293 #define FASTOP_SIZE 16 294 295 #define __FOP_FUNC(name) \ 296 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 297 ".type " name ", @function \n\t" \ 298 name ":\n\t" \ 299 ASM_ENDBR \ 300 IBT_NOSEAL(name) 301 302 #define FOP_FUNC(name) \ 303 __FOP_FUNC(#name) 304 305 #define __FOP_RET(name) \ 306 "11: " ASM_RET \ 307 ".size " name ", .-" name "\n\t" 308 309 #define FOP_RET(name) \ 310 __FOP_RET(#name) 311 312 #define __FOP_START(op, align) \ 313 extern void em_##op(struct fastop *fake); \ 314 asm(".pushsection .text, \"ax\" \n\t" \ 315 ".global em_" #op " \n\t" \ 316 ".align " __stringify(align) " \n\t" \ 317 "em_" #op ":\n\t" 318 319 #define FOP_START(op) __FOP_START(op, FASTOP_SIZE) 320 321 #define FOP_END \ 322 ".popsection") 323 324 #define __FOPNOP(name) \ 325 __FOP_FUNC(name) \ 326 __FOP_RET(name) 327 328 #define FOPNOP() \ 329 __FOPNOP(__stringify(__UNIQUE_ID(nop))) 330 331 #define FOP1E(op, dst) \ 332 __FOP_FUNC(#op "_" #dst) \ 333 "10: " #op " %" #dst " \n\t" \ 334 __FOP_RET(#op "_" #dst) 335 336 #define FOP1EEX(op, dst) \ 337 FOP1E(op, dst) _ASM_EXTABLE_TYPE_REG(10b, 11b, EX_TYPE_ZERO_REG, %%esi) 338 339 #define FASTOP1(op) \ 340 FOP_START(op) \ 341 FOP1E(op##b, al) \ 342 FOP1E(op##w, ax) \ 343 FOP1E(op##l, eax) \ 344 ON64(FOP1E(op##q, rax)) \ 345 FOP_END 346 347 /* 1-operand, using src2 (for MUL/DIV r/m) */ 348 #define FASTOP1SRC2(op, name) \ 349 FOP_START(name) \ 350 FOP1E(op, cl) \ 351 FOP1E(op, cx) \ 352 FOP1E(op, ecx) \ 353 ON64(FOP1E(op, rcx)) \ 354 FOP_END 355 356 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 357 #define FASTOP1SRC2EX(op, name) \ 358 FOP_START(name) \ 359 FOP1EEX(op, cl) \ 360 FOP1EEX(op, cx) \ 361 FOP1EEX(op, ecx) \ 362 ON64(FOP1EEX(op, rcx)) \ 363 FOP_END 364 365 #define FOP2E(op, dst, src) \ 366 __FOP_FUNC(#op "_" #dst "_" #src) \ 367 #op " %" #src ", %" #dst " \n\t" \ 368 __FOP_RET(#op "_" #dst "_" #src) 369 370 #define FASTOP2(op) \ 371 FOP_START(op) \ 372 FOP2E(op##b, al, dl) \ 373 FOP2E(op##w, ax, dx) \ 374 FOP2E(op##l, eax, edx) \ 375 ON64(FOP2E(op##q, rax, rdx)) \ 376 FOP_END 377 378 /* 2 operand, word only */ 379 #define FASTOP2W(op) \ 380 FOP_START(op) \ 381 FOPNOP() \ 382 FOP2E(op##w, ax, dx) \ 383 FOP2E(op##l, eax, edx) \ 384 ON64(FOP2E(op##q, rax, rdx)) \ 385 FOP_END 386 387 /* 2 operand, src is CL */ 388 #define FASTOP2CL(op) \ 389 FOP_START(op) \ 390 FOP2E(op##b, al, cl) \ 391 FOP2E(op##w, ax, cl) \ 392 FOP2E(op##l, eax, cl) \ 393 ON64(FOP2E(op##q, rax, cl)) \ 394 FOP_END 395 396 /* 2 operand, src and dest are reversed */ 397 #define FASTOP2R(op, name) \ 398 FOP_START(name) \ 399 FOP2E(op##b, dl, al) \ 400 FOP2E(op##w, dx, ax) \ 401 FOP2E(op##l, edx, eax) \ 402 ON64(FOP2E(op##q, rdx, rax)) \ 403 FOP_END 404 405 #define FOP3E(op, dst, src, src2) \ 406 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 407 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\ 408 __FOP_RET(#op "_" #dst "_" #src "_" #src2) 409 410 /* 3-operand, word-only, src2=cl */ 411 #define FASTOP3WCL(op) \ 412 FOP_START(op) \ 413 FOPNOP() \ 414 FOP3E(op##w, ax, dx, cl) \ 415 FOP3E(op##l, eax, edx, cl) \ 416 ON64(FOP3E(op##q, rax, rdx, cl)) \ 417 FOP_END 418 419 /* Special case for SETcc - 1 instruction per cc */ 420 #define FOP_SETCC(op) \ 421 FOP_FUNC(op) \ 422 #op " %al \n\t" \ 423 FOP_RET(op) 424 425 FOP_START(setcc) 426 FOP_SETCC(seto) 427 FOP_SETCC(setno) 428 FOP_SETCC(setc) 429 FOP_SETCC(setnc) 430 FOP_SETCC(setz) 431 FOP_SETCC(setnz) 432 FOP_SETCC(setbe) 433 FOP_SETCC(setnbe) 434 FOP_SETCC(sets) 435 FOP_SETCC(setns) 436 FOP_SETCC(setp) 437 FOP_SETCC(setnp) 438 FOP_SETCC(setl) 439 FOP_SETCC(setnl) 440 FOP_SETCC(setle) 441 FOP_SETCC(setnle) 442 FOP_END; 443 444 FOP_START(salc) 445 FOP_FUNC(salc) 446 "pushf; sbb %al, %al; popf \n\t" 447 FOP_RET(salc) 448 FOP_END; 449 450 /* 451 * XXX: inoutclob user must know where the argument is being expanded. 452 * Using asm goto would allow us to remove _fault. 453 */ 454 #define asm_safe(insn, inoutclob...) \ 455 ({ \ 456 int _fault = 0; \ 457 \ 458 asm volatile("1:" insn "\n" \ 459 "2:\n" \ 460 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \ 461 : [_fault] "+r"(_fault) inoutclob ); \ 462 \ 463 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 464 }) 465 466 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 467 enum x86_intercept intercept, 468 enum x86_intercept_stage stage) 469 { 470 struct x86_instruction_info info = { 471 .intercept = intercept, 472 .rep_prefix = ctxt->rep_prefix, 473 .modrm_mod = ctxt->modrm_mod, 474 .modrm_reg = ctxt->modrm_reg, 475 .modrm_rm = ctxt->modrm_rm, 476 .src_val = ctxt->src.val64, 477 .dst_val = ctxt->dst.val64, 478 .src_bytes = ctxt->src.bytes, 479 .dst_bytes = ctxt->dst.bytes, 480 .ad_bytes = ctxt->ad_bytes, 481 .next_rip = ctxt->eip, 482 }; 483 484 return ctxt->ops->intercept(ctxt, &info, stage); 485 } 486 487 static void assign_masked(ulong *dest, ulong src, ulong mask) 488 { 489 *dest = (*dest & ~mask) | (src & mask); 490 } 491 492 static void assign_register(unsigned long *reg, u64 val, int bytes) 493 { 494 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 495 switch (bytes) { 496 case 1: 497 *(u8 *)reg = (u8)val; 498 break; 499 case 2: 500 *(u16 *)reg = (u16)val; 501 break; 502 case 4: 503 *reg = (u32)val; 504 break; /* 64b: zero-extend */ 505 case 8: 506 *reg = val; 507 break; 508 } 509 } 510 511 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 512 { 513 return (1UL << (ctxt->ad_bytes << 3)) - 1; 514 } 515 516 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 517 { 518 u16 sel; 519 struct desc_struct ss; 520 521 if (ctxt->mode == X86EMUL_MODE_PROT64) 522 return ~0UL; 523 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 524 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 525 } 526 527 static int stack_size(struct x86_emulate_ctxt *ctxt) 528 { 529 return (__fls(stack_mask(ctxt)) + 1) >> 3; 530 } 531 532 /* Access/update address held in a register, based on addressing mode. */ 533 static inline unsigned long 534 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 535 { 536 if (ctxt->ad_bytes == sizeof(unsigned long)) 537 return reg; 538 else 539 return reg & ad_mask(ctxt); 540 } 541 542 static inline unsigned long 543 register_address(struct x86_emulate_ctxt *ctxt, int reg) 544 { 545 return address_mask(ctxt, reg_read(ctxt, reg)); 546 } 547 548 static void masked_increment(ulong *reg, ulong mask, int inc) 549 { 550 assign_masked(reg, *reg + inc, mask); 551 } 552 553 static inline void 554 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 555 { 556 ulong *preg = reg_rmw(ctxt, reg); 557 558 assign_register(preg, *preg + inc, ctxt->ad_bytes); 559 } 560 561 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 562 { 563 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 564 } 565 566 static u32 desc_limit_scaled(struct desc_struct *desc) 567 { 568 u32 limit = get_desc_limit(desc); 569 570 return desc->g ? (limit << 12) | 0xfff : limit; 571 } 572 573 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 574 { 575 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 576 return 0; 577 578 return ctxt->ops->get_cached_segment_base(ctxt, seg); 579 } 580 581 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 582 u32 error, bool valid) 583 { 584 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt)) 585 return X86EMUL_UNHANDLEABLE; 586 587 ctxt->exception.vector = vec; 588 ctxt->exception.error_code = error; 589 ctxt->exception.error_code_valid = valid; 590 return X86EMUL_PROPAGATE_FAULT; 591 } 592 593 static int emulate_db(struct x86_emulate_ctxt *ctxt) 594 { 595 return emulate_exception(ctxt, DB_VECTOR, 0, false); 596 } 597 598 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 599 { 600 return emulate_exception(ctxt, GP_VECTOR, err, true); 601 } 602 603 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 604 { 605 return emulate_exception(ctxt, SS_VECTOR, err, true); 606 } 607 608 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 609 { 610 return emulate_exception(ctxt, UD_VECTOR, 0, false); 611 } 612 613 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 614 { 615 return emulate_exception(ctxt, TS_VECTOR, err, true); 616 } 617 618 static int emulate_de(struct x86_emulate_ctxt *ctxt) 619 { 620 return emulate_exception(ctxt, DE_VECTOR, 0, false); 621 } 622 623 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 624 { 625 return emulate_exception(ctxt, NM_VECTOR, 0, false); 626 } 627 628 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 629 { 630 u16 selector; 631 struct desc_struct desc; 632 633 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 634 return selector; 635 } 636 637 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 638 unsigned seg) 639 { 640 u16 dummy; 641 u32 base3; 642 struct desc_struct desc; 643 644 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 645 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 646 } 647 648 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 649 { 650 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 651 } 652 653 static inline bool emul_is_noncanonical_address(u64 la, 654 struct x86_emulate_ctxt *ctxt) 655 { 656 return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt)); 657 } 658 659 /* 660 * x86 defines three classes of vector instructions: explicitly 661 * aligned, explicitly unaligned, and the rest, which change behaviour 662 * depending on whether they're AVX encoded or not. 663 * 664 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 665 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 666 * 512 bytes of data must be aligned to a 16 byte boundary. 667 */ 668 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 669 { 670 u64 alignment = ctxt->d & AlignMask; 671 672 if (likely(size < 16)) 673 return 1; 674 675 switch (alignment) { 676 case Unaligned: 677 case Avx: 678 return 1; 679 case Aligned16: 680 return 16; 681 case Aligned: 682 default: 683 return size; 684 } 685 } 686 687 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 688 struct segmented_address addr, 689 unsigned *max_size, unsigned size, 690 bool write, bool fetch, 691 enum x86emul_mode mode, ulong *linear) 692 { 693 struct desc_struct desc; 694 bool usable; 695 ulong la; 696 u32 lim; 697 u16 sel; 698 u8 va_bits; 699 700 la = seg_base(ctxt, addr.seg) + addr.ea; 701 *max_size = 0; 702 switch (mode) { 703 case X86EMUL_MODE_PROT64: 704 *linear = la; 705 va_bits = ctxt_virt_addr_bits(ctxt); 706 if (!__is_canonical_address(la, va_bits)) 707 goto bad; 708 709 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 710 if (size > *max_size) 711 goto bad; 712 break; 713 default: 714 *linear = la = (u32)la; 715 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 716 addr.seg); 717 if (!usable) 718 goto bad; 719 /* code segment in protected mode or read-only data segment */ 720 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 721 || !(desc.type & 2)) && write) 722 goto bad; 723 /* unreadable code segment */ 724 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 725 goto bad; 726 lim = desc_limit_scaled(&desc); 727 if (!(desc.type & 8) && (desc.type & 4)) { 728 /* expand-down segment */ 729 if (addr.ea <= lim) 730 goto bad; 731 lim = desc.d ? 0xffffffff : 0xffff; 732 } 733 if (addr.ea > lim) 734 goto bad; 735 if (lim == 0xffffffff) 736 *max_size = ~0u; 737 else { 738 *max_size = (u64)lim + 1 - addr.ea; 739 if (size > *max_size) 740 goto bad; 741 } 742 break; 743 } 744 if (la & (insn_alignment(ctxt, size) - 1)) 745 return emulate_gp(ctxt, 0); 746 return X86EMUL_CONTINUE; 747 bad: 748 if (addr.seg == VCPU_SREG_SS) 749 return emulate_ss(ctxt, 0); 750 else 751 return emulate_gp(ctxt, 0); 752 } 753 754 static int linearize(struct x86_emulate_ctxt *ctxt, 755 struct segmented_address addr, 756 unsigned size, bool write, 757 ulong *linear) 758 { 759 unsigned max_size; 760 return __linearize(ctxt, addr, &max_size, size, write, false, 761 ctxt->mode, linear); 762 } 763 764 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst) 765 { 766 ulong linear; 767 int rc; 768 unsigned max_size; 769 struct segmented_address addr = { .seg = VCPU_SREG_CS, 770 .ea = dst }; 771 772 if (ctxt->op_bytes != sizeof(unsigned long)) 773 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 774 rc = __linearize(ctxt, addr, &max_size, 1, false, true, ctxt->mode, &linear); 775 if (rc == X86EMUL_CONTINUE) 776 ctxt->_eip = addr.ea; 777 return rc; 778 } 779 780 static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt) 781 { 782 u64 efer; 783 struct desc_struct cs; 784 u16 selector; 785 u32 base3; 786 787 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 788 789 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) { 790 /* Real mode. cpu must not have long mode active */ 791 if (efer & EFER_LMA) 792 return X86EMUL_UNHANDLEABLE; 793 ctxt->mode = X86EMUL_MODE_REAL; 794 return X86EMUL_CONTINUE; 795 } 796 797 if (ctxt->eflags & X86_EFLAGS_VM) { 798 /* Protected/VM86 mode. cpu must not have long mode active */ 799 if (efer & EFER_LMA) 800 return X86EMUL_UNHANDLEABLE; 801 ctxt->mode = X86EMUL_MODE_VM86; 802 return X86EMUL_CONTINUE; 803 } 804 805 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS)) 806 return X86EMUL_UNHANDLEABLE; 807 808 if (efer & EFER_LMA) { 809 if (cs.l) { 810 /* Proper long mode */ 811 ctxt->mode = X86EMUL_MODE_PROT64; 812 } else if (cs.d) { 813 /* 32 bit compatibility mode*/ 814 ctxt->mode = X86EMUL_MODE_PROT32; 815 } else { 816 ctxt->mode = X86EMUL_MODE_PROT16; 817 } 818 } else { 819 /* Legacy 32 bit / 16 bit mode */ 820 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 821 } 822 823 return X86EMUL_CONTINUE; 824 } 825 826 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 827 { 828 return assign_eip(ctxt, dst); 829 } 830 831 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst) 832 { 833 int rc = emulator_recalc_and_set_mode(ctxt); 834 835 if (rc != X86EMUL_CONTINUE) 836 return rc; 837 838 return assign_eip(ctxt, dst); 839 } 840 841 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 842 { 843 return assign_eip_near(ctxt, ctxt->_eip + rel); 844 } 845 846 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 847 void *data, unsigned size) 848 { 849 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 850 } 851 852 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 853 ulong linear, void *data, 854 unsigned int size) 855 { 856 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 857 } 858 859 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 860 struct segmented_address addr, 861 void *data, 862 unsigned size) 863 { 864 int rc; 865 ulong linear; 866 867 rc = linearize(ctxt, addr, size, false, &linear); 868 if (rc != X86EMUL_CONTINUE) 869 return rc; 870 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 871 } 872 873 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 874 struct segmented_address addr, 875 void *data, 876 unsigned int size) 877 { 878 int rc; 879 ulong linear; 880 881 rc = linearize(ctxt, addr, size, true, &linear); 882 if (rc != X86EMUL_CONTINUE) 883 return rc; 884 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 885 } 886 887 /* 888 * Prefetch the remaining bytes of the instruction without crossing page 889 * boundary if they are not in fetch_cache yet. 890 */ 891 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 892 { 893 int rc; 894 unsigned size, max_size; 895 unsigned long linear; 896 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 897 struct segmented_address addr = { .seg = VCPU_SREG_CS, 898 .ea = ctxt->eip + cur_size }; 899 900 /* 901 * We do not know exactly how many bytes will be needed, and 902 * __linearize is expensive, so fetch as much as possible. We 903 * just have to avoid going beyond the 15 byte limit, the end 904 * of the segment, or the end of the page. 905 * 906 * __linearize is called with size 0 so that it does not do any 907 * boundary check itself. Instead, we use max_size to check 908 * against op_size. 909 */ 910 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 911 &linear); 912 if (unlikely(rc != X86EMUL_CONTINUE)) 913 return rc; 914 915 size = min_t(unsigned, 15UL ^ cur_size, max_size); 916 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 917 918 /* 919 * One instruction can only straddle two pages, 920 * and one has been loaded at the beginning of 921 * x86_decode_insn. So, if not enough bytes 922 * still, we must have hit the 15-byte boundary. 923 */ 924 if (unlikely(size < op_size)) 925 return emulate_gp(ctxt, 0); 926 927 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 928 size, &ctxt->exception); 929 if (unlikely(rc != X86EMUL_CONTINUE)) 930 return rc; 931 ctxt->fetch.end += size; 932 return X86EMUL_CONTINUE; 933 } 934 935 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 936 unsigned size) 937 { 938 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 939 940 if (unlikely(done_size < size)) 941 return __do_insn_fetch_bytes(ctxt, size - done_size); 942 else 943 return X86EMUL_CONTINUE; 944 } 945 946 /* Fetch next part of the instruction being emulated. */ 947 #define insn_fetch(_type, _ctxt) \ 948 ({ _type _x; \ 949 \ 950 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 951 if (rc != X86EMUL_CONTINUE) \ 952 goto done; \ 953 ctxt->_eip += sizeof(_type); \ 954 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 955 ctxt->fetch.ptr += sizeof(_type); \ 956 _x; \ 957 }) 958 959 #define insn_fetch_arr(_arr, _size, _ctxt) \ 960 ({ \ 961 rc = do_insn_fetch_bytes(_ctxt, _size); \ 962 if (rc != X86EMUL_CONTINUE) \ 963 goto done; \ 964 ctxt->_eip += (_size); \ 965 memcpy(_arr, ctxt->fetch.ptr, _size); \ 966 ctxt->fetch.ptr += (_size); \ 967 }) 968 969 /* 970 * Given the 'reg' portion of a ModRM byte, and a register block, return a 971 * pointer into the block that addresses the relevant register. 972 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 973 */ 974 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 975 int byteop) 976 { 977 void *p; 978 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 979 980 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 981 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 982 else 983 p = reg_rmw(ctxt, modrm_reg); 984 return p; 985 } 986 987 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 988 struct segmented_address addr, 989 u16 *size, unsigned long *address, int op_bytes) 990 { 991 int rc; 992 993 if (op_bytes == 2) 994 op_bytes = 3; 995 *address = 0; 996 rc = segmented_read_std(ctxt, addr, size, 2); 997 if (rc != X86EMUL_CONTINUE) 998 return rc; 999 addr.ea += 2; 1000 rc = segmented_read_std(ctxt, addr, address, op_bytes); 1001 return rc; 1002 } 1003 1004 FASTOP2(add); 1005 FASTOP2(or); 1006 FASTOP2(adc); 1007 FASTOP2(sbb); 1008 FASTOP2(and); 1009 FASTOP2(sub); 1010 FASTOP2(xor); 1011 FASTOP2(cmp); 1012 FASTOP2(test); 1013 1014 FASTOP1SRC2(mul, mul_ex); 1015 FASTOP1SRC2(imul, imul_ex); 1016 FASTOP1SRC2EX(div, div_ex); 1017 FASTOP1SRC2EX(idiv, idiv_ex); 1018 1019 FASTOP3WCL(shld); 1020 FASTOP3WCL(shrd); 1021 1022 FASTOP2W(imul); 1023 1024 FASTOP1(not); 1025 FASTOP1(neg); 1026 FASTOP1(inc); 1027 FASTOP1(dec); 1028 1029 FASTOP2CL(rol); 1030 FASTOP2CL(ror); 1031 FASTOP2CL(rcl); 1032 FASTOP2CL(rcr); 1033 FASTOP2CL(shl); 1034 FASTOP2CL(shr); 1035 FASTOP2CL(sar); 1036 1037 FASTOP2W(bsf); 1038 FASTOP2W(bsr); 1039 FASTOP2W(bt); 1040 FASTOP2W(bts); 1041 FASTOP2W(btr); 1042 FASTOP2W(btc); 1043 1044 FASTOP2(xadd); 1045 1046 FASTOP2R(cmp, cmp_r); 1047 1048 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1049 { 1050 /* If src is zero, do not writeback, but update flags */ 1051 if (ctxt->src.val == 0) 1052 ctxt->dst.type = OP_NONE; 1053 return fastop(ctxt, em_bsf); 1054 } 1055 1056 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1057 { 1058 /* If src is zero, do not writeback, but update flags */ 1059 if (ctxt->src.val == 0) 1060 ctxt->dst.type = OP_NONE; 1061 return fastop(ctxt, em_bsr); 1062 } 1063 1064 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1065 { 1066 u8 rc; 1067 void (*fop)(void) = (void *)em_setcc + FASTOP_SIZE * (condition & 0xf); 1068 1069 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1070 asm("push %[flags]; popf; " CALL_NOSPEC 1071 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1072 return rc; 1073 } 1074 1075 static void fetch_register_operand(struct operand *op) 1076 { 1077 switch (op->bytes) { 1078 case 1: 1079 op->val = *(u8 *)op->addr.reg; 1080 break; 1081 case 2: 1082 op->val = *(u16 *)op->addr.reg; 1083 break; 1084 case 4: 1085 op->val = *(u32 *)op->addr.reg; 1086 break; 1087 case 8: 1088 op->val = *(u64 *)op->addr.reg; 1089 break; 1090 } 1091 } 1092 1093 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1094 { 1095 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1096 return emulate_nm(ctxt); 1097 1098 kvm_fpu_get(); 1099 asm volatile("fninit"); 1100 kvm_fpu_put(); 1101 return X86EMUL_CONTINUE; 1102 } 1103 1104 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1105 { 1106 u16 fcw; 1107 1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1109 return emulate_nm(ctxt); 1110 1111 kvm_fpu_get(); 1112 asm volatile("fnstcw %0": "+m"(fcw)); 1113 kvm_fpu_put(); 1114 1115 ctxt->dst.val = fcw; 1116 1117 return X86EMUL_CONTINUE; 1118 } 1119 1120 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1121 { 1122 u16 fsw; 1123 1124 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1125 return emulate_nm(ctxt); 1126 1127 kvm_fpu_get(); 1128 asm volatile("fnstsw %0": "+m"(fsw)); 1129 kvm_fpu_put(); 1130 1131 ctxt->dst.val = fsw; 1132 1133 return X86EMUL_CONTINUE; 1134 } 1135 1136 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1137 struct operand *op) 1138 { 1139 unsigned int reg; 1140 1141 if (ctxt->d & ModRM) 1142 reg = ctxt->modrm_reg; 1143 else 1144 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1145 1146 if (ctxt->d & Sse) { 1147 op->type = OP_XMM; 1148 op->bytes = 16; 1149 op->addr.xmm = reg; 1150 kvm_read_sse_reg(reg, &op->vec_val); 1151 return; 1152 } 1153 if (ctxt->d & Mmx) { 1154 reg &= 7; 1155 op->type = OP_MM; 1156 op->bytes = 8; 1157 op->addr.mm = reg; 1158 return; 1159 } 1160 1161 op->type = OP_REG; 1162 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1163 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1164 1165 fetch_register_operand(op); 1166 op->orig_val = op->val; 1167 } 1168 1169 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1170 { 1171 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1172 ctxt->modrm_seg = VCPU_SREG_SS; 1173 } 1174 1175 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1176 struct operand *op) 1177 { 1178 u8 sib; 1179 int index_reg, base_reg, scale; 1180 int rc = X86EMUL_CONTINUE; 1181 ulong modrm_ea = 0; 1182 1183 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1184 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1185 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1186 1187 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1188 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1189 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1190 ctxt->modrm_seg = VCPU_SREG_DS; 1191 1192 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1193 op->type = OP_REG; 1194 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1195 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1196 ctxt->d & ByteOp); 1197 if (ctxt->d & Sse) { 1198 op->type = OP_XMM; 1199 op->bytes = 16; 1200 op->addr.xmm = ctxt->modrm_rm; 1201 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val); 1202 return rc; 1203 } 1204 if (ctxt->d & Mmx) { 1205 op->type = OP_MM; 1206 op->bytes = 8; 1207 op->addr.mm = ctxt->modrm_rm & 7; 1208 return rc; 1209 } 1210 fetch_register_operand(op); 1211 return rc; 1212 } 1213 1214 op->type = OP_MEM; 1215 1216 if (ctxt->ad_bytes == 2) { 1217 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1218 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1219 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1220 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1221 1222 /* 16-bit ModR/M decode. */ 1223 switch (ctxt->modrm_mod) { 1224 case 0: 1225 if (ctxt->modrm_rm == 6) 1226 modrm_ea += insn_fetch(u16, ctxt); 1227 break; 1228 case 1: 1229 modrm_ea += insn_fetch(s8, ctxt); 1230 break; 1231 case 2: 1232 modrm_ea += insn_fetch(u16, ctxt); 1233 break; 1234 } 1235 switch (ctxt->modrm_rm) { 1236 case 0: 1237 modrm_ea += bx + si; 1238 break; 1239 case 1: 1240 modrm_ea += bx + di; 1241 break; 1242 case 2: 1243 modrm_ea += bp + si; 1244 break; 1245 case 3: 1246 modrm_ea += bp + di; 1247 break; 1248 case 4: 1249 modrm_ea += si; 1250 break; 1251 case 5: 1252 modrm_ea += di; 1253 break; 1254 case 6: 1255 if (ctxt->modrm_mod != 0) 1256 modrm_ea += bp; 1257 break; 1258 case 7: 1259 modrm_ea += bx; 1260 break; 1261 } 1262 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1263 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1264 ctxt->modrm_seg = VCPU_SREG_SS; 1265 modrm_ea = (u16)modrm_ea; 1266 } else { 1267 /* 32/64-bit ModR/M decode. */ 1268 if ((ctxt->modrm_rm & 7) == 4) { 1269 sib = insn_fetch(u8, ctxt); 1270 index_reg |= (sib >> 3) & 7; 1271 base_reg |= sib & 7; 1272 scale = sib >> 6; 1273 1274 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1275 modrm_ea += insn_fetch(s32, ctxt); 1276 else { 1277 modrm_ea += reg_read(ctxt, base_reg); 1278 adjust_modrm_seg(ctxt, base_reg); 1279 /* Increment ESP on POP [ESP] */ 1280 if ((ctxt->d & IncSP) && 1281 base_reg == VCPU_REGS_RSP) 1282 modrm_ea += ctxt->op_bytes; 1283 } 1284 if (index_reg != 4) 1285 modrm_ea += reg_read(ctxt, index_reg) << scale; 1286 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1287 modrm_ea += insn_fetch(s32, ctxt); 1288 if (ctxt->mode == X86EMUL_MODE_PROT64) 1289 ctxt->rip_relative = 1; 1290 } else { 1291 base_reg = ctxt->modrm_rm; 1292 modrm_ea += reg_read(ctxt, base_reg); 1293 adjust_modrm_seg(ctxt, base_reg); 1294 } 1295 switch (ctxt->modrm_mod) { 1296 case 1: 1297 modrm_ea += insn_fetch(s8, ctxt); 1298 break; 1299 case 2: 1300 modrm_ea += insn_fetch(s32, ctxt); 1301 break; 1302 } 1303 } 1304 op->addr.mem.ea = modrm_ea; 1305 if (ctxt->ad_bytes != 8) 1306 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1307 1308 done: 1309 return rc; 1310 } 1311 1312 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1313 struct operand *op) 1314 { 1315 int rc = X86EMUL_CONTINUE; 1316 1317 op->type = OP_MEM; 1318 switch (ctxt->ad_bytes) { 1319 case 2: 1320 op->addr.mem.ea = insn_fetch(u16, ctxt); 1321 break; 1322 case 4: 1323 op->addr.mem.ea = insn_fetch(u32, ctxt); 1324 break; 1325 case 8: 1326 op->addr.mem.ea = insn_fetch(u64, ctxt); 1327 break; 1328 } 1329 done: 1330 return rc; 1331 } 1332 1333 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1334 { 1335 long sv = 0, mask; 1336 1337 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1338 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1339 1340 if (ctxt->src.bytes == 2) 1341 sv = (s16)ctxt->src.val & (s16)mask; 1342 else if (ctxt->src.bytes == 4) 1343 sv = (s32)ctxt->src.val & (s32)mask; 1344 else 1345 sv = (s64)ctxt->src.val & (s64)mask; 1346 1347 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1348 ctxt->dst.addr.mem.ea + (sv >> 3)); 1349 } 1350 1351 /* only subword offset */ 1352 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1353 } 1354 1355 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1356 unsigned long addr, void *dest, unsigned size) 1357 { 1358 int rc; 1359 struct read_cache *mc = &ctxt->mem_read; 1360 1361 if (mc->pos < mc->end) 1362 goto read_cached; 1363 1364 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt)) 1365 return X86EMUL_UNHANDLEABLE; 1366 1367 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1368 &ctxt->exception); 1369 if (rc != X86EMUL_CONTINUE) 1370 return rc; 1371 1372 mc->end += size; 1373 1374 read_cached: 1375 memcpy(dest, mc->data + mc->pos, size); 1376 mc->pos += size; 1377 return X86EMUL_CONTINUE; 1378 } 1379 1380 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1381 struct segmented_address addr, 1382 void *data, 1383 unsigned size) 1384 { 1385 int rc; 1386 ulong linear; 1387 1388 rc = linearize(ctxt, addr, size, false, &linear); 1389 if (rc != X86EMUL_CONTINUE) 1390 return rc; 1391 return read_emulated(ctxt, linear, data, size); 1392 } 1393 1394 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1395 struct segmented_address addr, 1396 const void *data, 1397 unsigned size) 1398 { 1399 int rc; 1400 ulong linear; 1401 1402 rc = linearize(ctxt, addr, size, true, &linear); 1403 if (rc != X86EMUL_CONTINUE) 1404 return rc; 1405 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1406 &ctxt->exception); 1407 } 1408 1409 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1410 struct segmented_address addr, 1411 const void *orig_data, const void *data, 1412 unsigned size) 1413 { 1414 int rc; 1415 ulong linear; 1416 1417 rc = linearize(ctxt, addr, size, true, &linear); 1418 if (rc != X86EMUL_CONTINUE) 1419 return rc; 1420 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1421 size, &ctxt->exception); 1422 } 1423 1424 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1425 unsigned int size, unsigned short port, 1426 void *dest) 1427 { 1428 struct read_cache *rc = &ctxt->io_read; 1429 1430 if (rc->pos == rc->end) { /* refill pio read ahead */ 1431 unsigned int in_page, n; 1432 unsigned int count = ctxt->rep_prefix ? 1433 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1434 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1435 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1436 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1437 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1438 if (n == 0) 1439 n = 1; 1440 rc->pos = rc->end = 0; 1441 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1442 return 0; 1443 rc->end = n * size; 1444 } 1445 1446 if (ctxt->rep_prefix && (ctxt->d & String) && 1447 !(ctxt->eflags & X86_EFLAGS_DF)) { 1448 ctxt->dst.data = rc->data + rc->pos; 1449 ctxt->dst.type = OP_MEM_STR; 1450 ctxt->dst.count = (rc->end - rc->pos) / size; 1451 rc->pos = rc->end; 1452 } else { 1453 memcpy(dest, rc->data + rc->pos, size); 1454 rc->pos += size; 1455 } 1456 return 1; 1457 } 1458 1459 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1460 u16 index, struct desc_struct *desc) 1461 { 1462 struct desc_ptr dt; 1463 ulong addr; 1464 1465 ctxt->ops->get_idt(ctxt, &dt); 1466 1467 if (dt.size < index * 8 + 7) 1468 return emulate_gp(ctxt, index << 3 | 0x2); 1469 1470 addr = dt.address + index * 8; 1471 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1472 } 1473 1474 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1475 u16 selector, struct desc_ptr *dt) 1476 { 1477 const struct x86_emulate_ops *ops = ctxt->ops; 1478 u32 base3 = 0; 1479 1480 if (selector & 1 << 2) { 1481 struct desc_struct desc; 1482 u16 sel; 1483 1484 memset(dt, 0, sizeof(*dt)); 1485 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1486 VCPU_SREG_LDTR)) 1487 return; 1488 1489 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1490 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1491 } else 1492 ops->get_gdt(ctxt, dt); 1493 } 1494 1495 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1496 u16 selector, ulong *desc_addr_p) 1497 { 1498 struct desc_ptr dt; 1499 u16 index = selector >> 3; 1500 ulong addr; 1501 1502 get_descriptor_table_ptr(ctxt, selector, &dt); 1503 1504 if (dt.size < index * 8 + 7) 1505 return emulate_gp(ctxt, selector & 0xfffc); 1506 1507 addr = dt.address + index * 8; 1508 1509 #ifdef CONFIG_X86_64 1510 if (addr >> 32 != 0) { 1511 u64 efer = 0; 1512 1513 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1514 if (!(efer & EFER_LMA)) 1515 addr &= (u32)-1; 1516 } 1517 #endif 1518 1519 *desc_addr_p = addr; 1520 return X86EMUL_CONTINUE; 1521 } 1522 1523 /* allowed just for 8 bytes segments */ 1524 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1525 u16 selector, struct desc_struct *desc, 1526 ulong *desc_addr_p) 1527 { 1528 int rc; 1529 1530 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1531 if (rc != X86EMUL_CONTINUE) 1532 return rc; 1533 1534 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1535 } 1536 1537 /* allowed just for 8 bytes segments */ 1538 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1539 u16 selector, struct desc_struct *desc) 1540 { 1541 int rc; 1542 ulong addr; 1543 1544 rc = get_descriptor_ptr(ctxt, selector, &addr); 1545 if (rc != X86EMUL_CONTINUE) 1546 return rc; 1547 1548 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1549 } 1550 1551 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1552 u16 selector, int seg, u8 cpl, 1553 enum x86_transfer_type transfer, 1554 struct desc_struct *desc) 1555 { 1556 struct desc_struct seg_desc, old_desc; 1557 u8 dpl, rpl; 1558 unsigned err_vec = GP_VECTOR; 1559 u32 err_code = 0; 1560 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1561 ulong desc_addr; 1562 int ret; 1563 u16 dummy; 1564 u32 base3 = 0; 1565 1566 memset(&seg_desc, 0, sizeof(seg_desc)); 1567 1568 if (ctxt->mode == X86EMUL_MODE_REAL) { 1569 /* set real mode segment descriptor (keep limit etc. for 1570 * unreal mode) */ 1571 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1572 set_desc_base(&seg_desc, selector << 4); 1573 goto load; 1574 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1575 /* VM86 needs a clean new segment descriptor */ 1576 set_desc_base(&seg_desc, selector << 4); 1577 set_desc_limit(&seg_desc, 0xffff); 1578 seg_desc.type = 3; 1579 seg_desc.p = 1; 1580 seg_desc.s = 1; 1581 seg_desc.dpl = 3; 1582 goto load; 1583 } 1584 1585 rpl = selector & 3; 1586 1587 /* TR should be in GDT only */ 1588 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1589 goto exception; 1590 1591 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1592 if (null_selector) { 1593 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1594 goto exception; 1595 1596 if (seg == VCPU_SREG_SS) { 1597 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1598 goto exception; 1599 1600 /* 1601 * ctxt->ops->set_segment expects the CPL to be in 1602 * SS.DPL, so fake an expand-up 32-bit data segment. 1603 */ 1604 seg_desc.type = 3; 1605 seg_desc.p = 1; 1606 seg_desc.s = 1; 1607 seg_desc.dpl = cpl; 1608 seg_desc.d = 1; 1609 seg_desc.g = 1; 1610 } 1611 1612 /* Skip all following checks */ 1613 goto load; 1614 } 1615 1616 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1617 if (ret != X86EMUL_CONTINUE) 1618 return ret; 1619 1620 err_code = selector & 0xfffc; 1621 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1622 GP_VECTOR; 1623 1624 /* can't load system descriptor into segment selector */ 1625 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1626 if (transfer == X86_TRANSFER_CALL_JMP) 1627 return X86EMUL_UNHANDLEABLE; 1628 goto exception; 1629 } 1630 1631 dpl = seg_desc.dpl; 1632 1633 switch (seg) { 1634 case VCPU_SREG_SS: 1635 /* 1636 * segment is not a writable data segment or segment 1637 * selector's RPL != CPL or DPL != CPL 1638 */ 1639 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1640 goto exception; 1641 break; 1642 case VCPU_SREG_CS: 1643 if (!(seg_desc.type & 8)) 1644 goto exception; 1645 1646 if (transfer == X86_TRANSFER_RET) { 1647 /* RET can never return to an inner privilege level. */ 1648 if (rpl < cpl) 1649 goto exception; 1650 /* Outer-privilege level return is not implemented */ 1651 if (rpl > cpl) 1652 return X86EMUL_UNHANDLEABLE; 1653 } 1654 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) { 1655 if (seg_desc.type & 4) { 1656 /* conforming */ 1657 if (dpl > rpl) 1658 goto exception; 1659 } else { 1660 /* nonconforming */ 1661 if (dpl != rpl) 1662 goto exception; 1663 } 1664 } else { /* X86_TRANSFER_CALL_JMP */ 1665 if (seg_desc.type & 4) { 1666 /* conforming */ 1667 if (dpl > cpl) 1668 goto exception; 1669 } else { 1670 /* nonconforming */ 1671 if (rpl > cpl || dpl != cpl) 1672 goto exception; 1673 } 1674 } 1675 /* in long-mode d/b must be clear if l is set */ 1676 if (seg_desc.d && seg_desc.l) { 1677 u64 efer = 0; 1678 1679 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1680 if (efer & EFER_LMA) 1681 goto exception; 1682 } 1683 1684 /* CS(RPL) <- CPL */ 1685 selector = (selector & 0xfffc) | cpl; 1686 break; 1687 case VCPU_SREG_TR: 1688 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1689 goto exception; 1690 break; 1691 case VCPU_SREG_LDTR: 1692 if (seg_desc.s || seg_desc.type != 2) 1693 goto exception; 1694 break; 1695 default: /* DS, ES, FS, or GS */ 1696 /* 1697 * segment is not a data or readable code segment or 1698 * ((segment is a data or nonconforming code segment) 1699 * and ((RPL > DPL) or (CPL > DPL))) 1700 */ 1701 if ((seg_desc.type & 0xa) == 0x8 || 1702 (((seg_desc.type & 0xc) != 0xc) && 1703 (rpl > dpl || cpl > dpl))) 1704 goto exception; 1705 break; 1706 } 1707 1708 if (!seg_desc.p) { 1709 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1710 goto exception; 1711 } 1712 1713 if (seg_desc.s) { 1714 /* mark segment as accessed */ 1715 if (!(seg_desc.type & 1)) { 1716 seg_desc.type |= 1; 1717 ret = write_segment_descriptor(ctxt, selector, 1718 &seg_desc); 1719 if (ret != X86EMUL_CONTINUE) 1720 return ret; 1721 } 1722 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1723 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1724 if (ret != X86EMUL_CONTINUE) 1725 return ret; 1726 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1727 ((u64)base3 << 32), ctxt)) 1728 return emulate_gp(ctxt, err_code); 1729 } 1730 1731 if (seg == VCPU_SREG_TR) { 1732 old_desc = seg_desc; 1733 seg_desc.type |= 2; /* busy */ 1734 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1735 sizeof(seg_desc), &ctxt->exception); 1736 if (ret != X86EMUL_CONTINUE) 1737 return ret; 1738 } 1739 load: 1740 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1741 if (desc) 1742 *desc = seg_desc; 1743 return X86EMUL_CONTINUE; 1744 exception: 1745 return emulate_exception(ctxt, err_vec, err_code, true); 1746 } 1747 1748 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1749 u16 selector, int seg) 1750 { 1751 u8 cpl = ctxt->ops->cpl(ctxt); 1752 1753 /* 1754 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1755 * they can load it at CPL<3 (Intel's manual says only LSS can, 1756 * but it's wrong). 1757 * 1758 * However, the Intel manual says that putting IST=1/DPL=3 in 1759 * an interrupt gate will result in SS=3 (the AMD manual instead 1760 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1761 * and only forbid it here. 1762 */ 1763 if (seg == VCPU_SREG_SS && selector == 3 && 1764 ctxt->mode == X86EMUL_MODE_PROT64) 1765 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1766 1767 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1768 X86_TRANSFER_NONE, NULL); 1769 } 1770 1771 static void write_register_operand(struct operand *op) 1772 { 1773 return assign_register(op->addr.reg, op->val, op->bytes); 1774 } 1775 1776 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1777 { 1778 switch (op->type) { 1779 case OP_REG: 1780 write_register_operand(op); 1781 break; 1782 case OP_MEM: 1783 if (ctxt->lock_prefix) 1784 return segmented_cmpxchg(ctxt, 1785 op->addr.mem, 1786 &op->orig_val, 1787 &op->val, 1788 op->bytes); 1789 else 1790 return segmented_write(ctxt, 1791 op->addr.mem, 1792 &op->val, 1793 op->bytes); 1794 break; 1795 case OP_MEM_STR: 1796 return segmented_write(ctxt, 1797 op->addr.mem, 1798 op->data, 1799 op->bytes * op->count); 1800 break; 1801 case OP_XMM: 1802 kvm_write_sse_reg(op->addr.xmm, &op->vec_val); 1803 break; 1804 case OP_MM: 1805 kvm_write_mmx_reg(op->addr.mm, &op->mm_val); 1806 break; 1807 case OP_NONE: 1808 /* no writeback */ 1809 break; 1810 default: 1811 break; 1812 } 1813 return X86EMUL_CONTINUE; 1814 } 1815 1816 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1817 { 1818 struct segmented_address addr; 1819 1820 rsp_increment(ctxt, -bytes); 1821 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1822 addr.seg = VCPU_SREG_SS; 1823 1824 return segmented_write(ctxt, addr, data, bytes); 1825 } 1826 1827 static int em_push(struct x86_emulate_ctxt *ctxt) 1828 { 1829 /* Disable writeback. */ 1830 ctxt->dst.type = OP_NONE; 1831 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1832 } 1833 1834 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1835 void *dest, int len) 1836 { 1837 int rc; 1838 struct segmented_address addr; 1839 1840 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1841 addr.seg = VCPU_SREG_SS; 1842 rc = segmented_read(ctxt, addr, dest, len); 1843 if (rc != X86EMUL_CONTINUE) 1844 return rc; 1845 1846 rsp_increment(ctxt, len); 1847 return rc; 1848 } 1849 1850 static int em_pop(struct x86_emulate_ctxt *ctxt) 1851 { 1852 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1853 } 1854 1855 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1856 void *dest, int len) 1857 { 1858 int rc; 1859 unsigned long val, change_mask; 1860 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1861 int cpl = ctxt->ops->cpl(ctxt); 1862 1863 rc = emulate_pop(ctxt, &val, len); 1864 if (rc != X86EMUL_CONTINUE) 1865 return rc; 1866 1867 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1868 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1869 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1870 X86_EFLAGS_AC | X86_EFLAGS_ID; 1871 1872 switch(ctxt->mode) { 1873 case X86EMUL_MODE_PROT64: 1874 case X86EMUL_MODE_PROT32: 1875 case X86EMUL_MODE_PROT16: 1876 if (cpl == 0) 1877 change_mask |= X86_EFLAGS_IOPL; 1878 if (cpl <= iopl) 1879 change_mask |= X86_EFLAGS_IF; 1880 break; 1881 case X86EMUL_MODE_VM86: 1882 if (iopl < 3) 1883 return emulate_gp(ctxt, 0); 1884 change_mask |= X86_EFLAGS_IF; 1885 break; 1886 default: /* real mode */ 1887 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1888 break; 1889 } 1890 1891 *(unsigned long *)dest = 1892 (ctxt->eflags & ~change_mask) | (val & change_mask); 1893 1894 return rc; 1895 } 1896 1897 static int em_popf(struct x86_emulate_ctxt *ctxt) 1898 { 1899 ctxt->dst.type = OP_REG; 1900 ctxt->dst.addr.reg = &ctxt->eflags; 1901 ctxt->dst.bytes = ctxt->op_bytes; 1902 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1903 } 1904 1905 static int em_enter(struct x86_emulate_ctxt *ctxt) 1906 { 1907 int rc; 1908 unsigned frame_size = ctxt->src.val; 1909 unsigned nesting_level = ctxt->src2.val & 31; 1910 ulong rbp; 1911 1912 if (nesting_level) 1913 return X86EMUL_UNHANDLEABLE; 1914 1915 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1916 rc = push(ctxt, &rbp, stack_size(ctxt)); 1917 if (rc != X86EMUL_CONTINUE) 1918 return rc; 1919 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1920 stack_mask(ctxt)); 1921 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1922 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1923 stack_mask(ctxt)); 1924 return X86EMUL_CONTINUE; 1925 } 1926 1927 static int em_leave(struct x86_emulate_ctxt *ctxt) 1928 { 1929 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1930 stack_mask(ctxt)); 1931 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1932 } 1933 1934 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1935 { 1936 int seg = ctxt->src2.val; 1937 1938 ctxt->src.val = get_segment_selector(ctxt, seg); 1939 if (ctxt->op_bytes == 4) { 1940 rsp_increment(ctxt, -2); 1941 ctxt->op_bytes = 2; 1942 } 1943 1944 return em_push(ctxt); 1945 } 1946 1947 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1948 { 1949 int seg = ctxt->src2.val; 1950 unsigned long selector; 1951 int rc; 1952 1953 rc = emulate_pop(ctxt, &selector, 2); 1954 if (rc != X86EMUL_CONTINUE) 1955 return rc; 1956 1957 if (seg == VCPU_SREG_SS) 1958 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1959 if (ctxt->op_bytes > 2) 1960 rsp_increment(ctxt, ctxt->op_bytes - 2); 1961 1962 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1963 return rc; 1964 } 1965 1966 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1967 { 1968 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1969 int rc = X86EMUL_CONTINUE; 1970 int reg = VCPU_REGS_RAX; 1971 1972 while (reg <= VCPU_REGS_RDI) { 1973 (reg == VCPU_REGS_RSP) ? 1974 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1975 1976 rc = em_push(ctxt); 1977 if (rc != X86EMUL_CONTINUE) 1978 return rc; 1979 1980 ++reg; 1981 } 1982 1983 return rc; 1984 } 1985 1986 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1987 { 1988 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1989 return em_push(ctxt); 1990 } 1991 1992 static int em_popa(struct x86_emulate_ctxt *ctxt) 1993 { 1994 int rc = X86EMUL_CONTINUE; 1995 int reg = VCPU_REGS_RDI; 1996 u32 val; 1997 1998 while (reg >= VCPU_REGS_RAX) { 1999 if (reg == VCPU_REGS_RSP) { 2000 rsp_increment(ctxt, ctxt->op_bytes); 2001 --reg; 2002 } 2003 2004 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2005 if (rc != X86EMUL_CONTINUE) 2006 break; 2007 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2008 --reg; 2009 } 2010 return rc; 2011 } 2012 2013 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2014 { 2015 const struct x86_emulate_ops *ops = ctxt->ops; 2016 int rc; 2017 struct desc_ptr dt; 2018 gva_t cs_addr; 2019 gva_t eip_addr; 2020 u16 cs, eip; 2021 2022 /* TODO: Add limit checks */ 2023 ctxt->src.val = ctxt->eflags; 2024 rc = em_push(ctxt); 2025 if (rc != X86EMUL_CONTINUE) 2026 return rc; 2027 2028 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2029 2030 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2031 rc = em_push(ctxt); 2032 if (rc != X86EMUL_CONTINUE) 2033 return rc; 2034 2035 ctxt->src.val = ctxt->_eip; 2036 rc = em_push(ctxt); 2037 if (rc != X86EMUL_CONTINUE) 2038 return rc; 2039 2040 ops->get_idt(ctxt, &dt); 2041 2042 eip_addr = dt.address + (irq << 2); 2043 cs_addr = dt.address + (irq << 2) + 2; 2044 2045 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2046 if (rc != X86EMUL_CONTINUE) 2047 return rc; 2048 2049 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2050 if (rc != X86EMUL_CONTINUE) 2051 return rc; 2052 2053 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2054 if (rc != X86EMUL_CONTINUE) 2055 return rc; 2056 2057 ctxt->_eip = eip; 2058 2059 return rc; 2060 } 2061 2062 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2063 { 2064 int rc; 2065 2066 invalidate_registers(ctxt); 2067 rc = __emulate_int_real(ctxt, irq); 2068 if (rc == X86EMUL_CONTINUE) 2069 writeback_registers(ctxt); 2070 return rc; 2071 } 2072 2073 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2074 { 2075 switch(ctxt->mode) { 2076 case X86EMUL_MODE_REAL: 2077 return __emulate_int_real(ctxt, irq); 2078 case X86EMUL_MODE_VM86: 2079 case X86EMUL_MODE_PROT16: 2080 case X86EMUL_MODE_PROT32: 2081 case X86EMUL_MODE_PROT64: 2082 default: 2083 /* Protected mode interrupts unimplemented yet */ 2084 return X86EMUL_UNHANDLEABLE; 2085 } 2086 } 2087 2088 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2089 { 2090 int rc = X86EMUL_CONTINUE; 2091 unsigned long temp_eip = 0; 2092 unsigned long temp_eflags = 0; 2093 unsigned long cs = 0; 2094 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2095 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2096 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2097 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2098 X86_EFLAGS_AC | X86_EFLAGS_ID | 2099 X86_EFLAGS_FIXED; 2100 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2101 X86_EFLAGS_VIP; 2102 2103 /* TODO: Add stack limit check */ 2104 2105 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2106 2107 if (rc != X86EMUL_CONTINUE) 2108 return rc; 2109 2110 if (temp_eip & ~0xffff) 2111 return emulate_gp(ctxt, 0); 2112 2113 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2114 2115 if (rc != X86EMUL_CONTINUE) 2116 return rc; 2117 2118 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2119 2120 if (rc != X86EMUL_CONTINUE) 2121 return rc; 2122 2123 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2124 2125 if (rc != X86EMUL_CONTINUE) 2126 return rc; 2127 2128 ctxt->_eip = temp_eip; 2129 2130 if (ctxt->op_bytes == 4) 2131 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2132 else if (ctxt->op_bytes == 2) { 2133 ctxt->eflags &= ~0xffff; 2134 ctxt->eflags |= temp_eflags; 2135 } 2136 2137 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2138 ctxt->eflags |= X86_EFLAGS_FIXED; 2139 ctxt->ops->set_nmi_mask(ctxt, false); 2140 2141 return rc; 2142 } 2143 2144 static int em_iret(struct x86_emulate_ctxt *ctxt) 2145 { 2146 switch(ctxt->mode) { 2147 case X86EMUL_MODE_REAL: 2148 return emulate_iret_real(ctxt); 2149 case X86EMUL_MODE_VM86: 2150 case X86EMUL_MODE_PROT16: 2151 case X86EMUL_MODE_PROT32: 2152 case X86EMUL_MODE_PROT64: 2153 default: 2154 /* iret from protected mode unimplemented yet */ 2155 return X86EMUL_UNHANDLEABLE; 2156 } 2157 } 2158 2159 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2160 { 2161 int rc; 2162 unsigned short sel; 2163 struct desc_struct new_desc; 2164 u8 cpl = ctxt->ops->cpl(ctxt); 2165 2166 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2167 2168 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2169 X86_TRANSFER_CALL_JMP, 2170 &new_desc); 2171 if (rc != X86EMUL_CONTINUE) 2172 return rc; 2173 2174 rc = assign_eip_far(ctxt, ctxt->src.val); 2175 /* Error handling is not implemented. */ 2176 if (rc != X86EMUL_CONTINUE) 2177 return X86EMUL_UNHANDLEABLE; 2178 2179 return rc; 2180 } 2181 2182 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2183 { 2184 return assign_eip_near(ctxt, ctxt->src.val); 2185 } 2186 2187 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2188 { 2189 int rc; 2190 long int old_eip; 2191 2192 old_eip = ctxt->_eip; 2193 rc = assign_eip_near(ctxt, ctxt->src.val); 2194 if (rc != X86EMUL_CONTINUE) 2195 return rc; 2196 ctxt->src.val = old_eip; 2197 rc = em_push(ctxt); 2198 return rc; 2199 } 2200 2201 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2202 { 2203 u64 old = ctxt->dst.orig_val64; 2204 2205 if (ctxt->dst.bytes == 16) 2206 return X86EMUL_UNHANDLEABLE; 2207 2208 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2209 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2210 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2211 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2212 ctxt->eflags &= ~X86_EFLAGS_ZF; 2213 } else { 2214 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2215 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2216 2217 ctxt->eflags |= X86_EFLAGS_ZF; 2218 } 2219 return X86EMUL_CONTINUE; 2220 } 2221 2222 static int em_ret(struct x86_emulate_ctxt *ctxt) 2223 { 2224 int rc; 2225 unsigned long eip; 2226 2227 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2228 if (rc != X86EMUL_CONTINUE) 2229 return rc; 2230 2231 return assign_eip_near(ctxt, eip); 2232 } 2233 2234 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2235 { 2236 int rc; 2237 unsigned long eip, cs; 2238 int cpl = ctxt->ops->cpl(ctxt); 2239 struct desc_struct new_desc; 2240 2241 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2242 if (rc != X86EMUL_CONTINUE) 2243 return rc; 2244 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2245 if (rc != X86EMUL_CONTINUE) 2246 return rc; 2247 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2248 X86_TRANSFER_RET, 2249 &new_desc); 2250 if (rc != X86EMUL_CONTINUE) 2251 return rc; 2252 rc = assign_eip_far(ctxt, eip); 2253 /* Error handling is not implemented. */ 2254 if (rc != X86EMUL_CONTINUE) 2255 return X86EMUL_UNHANDLEABLE; 2256 2257 return rc; 2258 } 2259 2260 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2261 { 2262 int rc; 2263 2264 rc = em_ret_far(ctxt); 2265 if (rc != X86EMUL_CONTINUE) 2266 return rc; 2267 rsp_increment(ctxt, ctxt->src.val); 2268 return X86EMUL_CONTINUE; 2269 } 2270 2271 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2272 { 2273 /* Save real source value, then compare EAX against destination. */ 2274 ctxt->dst.orig_val = ctxt->dst.val; 2275 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2276 ctxt->src.orig_val = ctxt->src.val; 2277 ctxt->src.val = ctxt->dst.orig_val; 2278 fastop(ctxt, em_cmp); 2279 2280 if (ctxt->eflags & X86_EFLAGS_ZF) { 2281 /* Success: write back to memory; no update of EAX */ 2282 ctxt->src.type = OP_NONE; 2283 ctxt->dst.val = ctxt->src.orig_val; 2284 } else { 2285 /* Failure: write the value we saw to EAX. */ 2286 ctxt->src.type = OP_REG; 2287 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2288 ctxt->src.val = ctxt->dst.orig_val; 2289 /* Create write-cycle to dest by writing the same value */ 2290 ctxt->dst.val = ctxt->dst.orig_val; 2291 } 2292 return X86EMUL_CONTINUE; 2293 } 2294 2295 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2296 { 2297 int seg = ctxt->src2.val; 2298 unsigned short sel; 2299 int rc; 2300 2301 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2302 2303 rc = load_segment_descriptor(ctxt, sel, seg); 2304 if (rc != X86EMUL_CONTINUE) 2305 return rc; 2306 2307 ctxt->dst.val = ctxt->src.val; 2308 return rc; 2309 } 2310 2311 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2312 { 2313 if (!ctxt->ops->is_smm(ctxt)) 2314 return emulate_ud(ctxt); 2315 2316 if (ctxt->ops->leave_smm(ctxt)) 2317 ctxt->ops->triple_fault(ctxt); 2318 2319 return emulator_recalc_and_set_mode(ctxt); 2320 } 2321 2322 static void 2323 setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss) 2324 { 2325 cs->l = 0; /* will be adjusted later */ 2326 set_desc_base(cs, 0); /* flat segment */ 2327 cs->g = 1; /* 4kb granularity */ 2328 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2329 cs->type = 0x0b; /* Read, Execute, Accessed */ 2330 cs->s = 1; 2331 cs->dpl = 0; /* will be adjusted later */ 2332 cs->p = 1; 2333 cs->d = 1; 2334 cs->avl = 0; 2335 2336 set_desc_base(ss, 0); /* flat segment */ 2337 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2338 ss->g = 1; /* 4kb granularity */ 2339 ss->s = 1; 2340 ss->type = 0x03; /* Read/Write, Accessed */ 2341 ss->d = 1; /* 32bit stack segment */ 2342 ss->dpl = 0; 2343 ss->p = 1; 2344 ss->l = 0; 2345 ss->avl = 0; 2346 } 2347 2348 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2349 { 2350 u32 eax, ebx, ecx, edx; 2351 2352 eax = ecx = 0; 2353 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2354 return is_guest_vendor_intel(ebx, ecx, edx); 2355 } 2356 2357 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2358 { 2359 const struct x86_emulate_ops *ops = ctxt->ops; 2360 u32 eax, ebx, ecx, edx; 2361 2362 /* 2363 * syscall should always be enabled in longmode - so only become 2364 * vendor specific (cpuid) if other modes are active... 2365 */ 2366 if (ctxt->mode == X86EMUL_MODE_PROT64) 2367 return true; 2368 2369 eax = 0x00000000; 2370 ecx = 0x00000000; 2371 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2372 /* 2373 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a 2374 * 64bit guest with a 32bit compat-app running will #UD !! While this 2375 * behaviour can be fixed (by emulating) into AMD response - CPUs of 2376 * AMD can't behave like Intel. 2377 */ 2378 if (is_guest_vendor_intel(ebx, ecx, edx)) 2379 return false; 2380 2381 if (is_guest_vendor_amd(ebx, ecx, edx) || 2382 is_guest_vendor_hygon(ebx, ecx, edx)) 2383 return true; 2384 2385 /* 2386 * default: (not Intel, not AMD, not Hygon), apply Intel's 2387 * stricter rules... 2388 */ 2389 return false; 2390 } 2391 2392 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2393 { 2394 const struct x86_emulate_ops *ops = ctxt->ops; 2395 struct desc_struct cs, ss; 2396 u64 msr_data; 2397 u16 cs_sel, ss_sel; 2398 u64 efer = 0; 2399 2400 /* syscall is not available in real mode */ 2401 if (ctxt->mode == X86EMUL_MODE_REAL || 2402 ctxt->mode == X86EMUL_MODE_VM86) 2403 return emulate_ud(ctxt); 2404 2405 if (!(em_syscall_is_enabled(ctxt))) 2406 return emulate_ud(ctxt); 2407 2408 ops->get_msr(ctxt, MSR_EFER, &efer); 2409 if (!(efer & EFER_SCE)) 2410 return emulate_ud(ctxt); 2411 2412 setup_syscalls_segments(&cs, &ss); 2413 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2414 msr_data >>= 32; 2415 cs_sel = (u16)(msr_data & 0xfffc); 2416 ss_sel = (u16)(msr_data + 8); 2417 2418 if (efer & EFER_LMA) { 2419 cs.d = 0; 2420 cs.l = 1; 2421 } 2422 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2423 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2424 2425 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2426 if (efer & EFER_LMA) { 2427 #ifdef CONFIG_X86_64 2428 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2429 2430 ops->get_msr(ctxt, 2431 ctxt->mode == X86EMUL_MODE_PROT64 ? 2432 MSR_LSTAR : MSR_CSTAR, &msr_data); 2433 ctxt->_eip = msr_data; 2434 2435 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2436 ctxt->eflags &= ~msr_data; 2437 ctxt->eflags |= X86_EFLAGS_FIXED; 2438 #endif 2439 } else { 2440 /* legacy mode */ 2441 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2442 ctxt->_eip = (u32)msr_data; 2443 2444 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2445 } 2446 2447 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2448 return X86EMUL_CONTINUE; 2449 } 2450 2451 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2452 { 2453 const struct x86_emulate_ops *ops = ctxt->ops; 2454 struct desc_struct cs, ss; 2455 u64 msr_data; 2456 u16 cs_sel, ss_sel; 2457 u64 efer = 0; 2458 2459 ops->get_msr(ctxt, MSR_EFER, &efer); 2460 /* inject #GP if in real mode */ 2461 if (ctxt->mode == X86EMUL_MODE_REAL) 2462 return emulate_gp(ctxt, 0); 2463 2464 /* 2465 * Not recognized on AMD in compat mode (but is recognized in legacy 2466 * mode). 2467 */ 2468 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2469 && !vendor_intel(ctxt)) 2470 return emulate_ud(ctxt); 2471 2472 /* sysenter/sysexit have not been tested in 64bit mode. */ 2473 if (ctxt->mode == X86EMUL_MODE_PROT64) 2474 return X86EMUL_UNHANDLEABLE; 2475 2476 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2477 if ((msr_data & 0xfffc) == 0x0) 2478 return emulate_gp(ctxt, 0); 2479 2480 setup_syscalls_segments(&cs, &ss); 2481 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2482 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2483 ss_sel = cs_sel + 8; 2484 if (efer & EFER_LMA) { 2485 cs.d = 0; 2486 cs.l = 1; 2487 } 2488 2489 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2490 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2491 2492 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2493 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2494 2495 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2496 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2497 (u32)msr_data; 2498 if (efer & EFER_LMA) 2499 ctxt->mode = X86EMUL_MODE_PROT64; 2500 2501 return X86EMUL_CONTINUE; 2502 } 2503 2504 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2505 { 2506 const struct x86_emulate_ops *ops = ctxt->ops; 2507 struct desc_struct cs, ss; 2508 u64 msr_data, rcx, rdx; 2509 int usermode; 2510 u16 cs_sel = 0, ss_sel = 0; 2511 2512 /* inject #GP if in real mode or Virtual 8086 mode */ 2513 if (ctxt->mode == X86EMUL_MODE_REAL || 2514 ctxt->mode == X86EMUL_MODE_VM86) 2515 return emulate_gp(ctxt, 0); 2516 2517 setup_syscalls_segments(&cs, &ss); 2518 2519 if ((ctxt->rex_prefix & 0x8) != 0x0) 2520 usermode = X86EMUL_MODE_PROT64; 2521 else 2522 usermode = X86EMUL_MODE_PROT32; 2523 2524 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2525 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2526 2527 cs.dpl = 3; 2528 ss.dpl = 3; 2529 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2530 switch (usermode) { 2531 case X86EMUL_MODE_PROT32: 2532 cs_sel = (u16)(msr_data + 16); 2533 if ((msr_data & 0xfffc) == 0x0) 2534 return emulate_gp(ctxt, 0); 2535 ss_sel = (u16)(msr_data + 24); 2536 rcx = (u32)rcx; 2537 rdx = (u32)rdx; 2538 break; 2539 case X86EMUL_MODE_PROT64: 2540 cs_sel = (u16)(msr_data + 32); 2541 if (msr_data == 0x0) 2542 return emulate_gp(ctxt, 0); 2543 ss_sel = cs_sel + 8; 2544 cs.d = 0; 2545 cs.l = 1; 2546 if (emul_is_noncanonical_address(rcx, ctxt) || 2547 emul_is_noncanonical_address(rdx, ctxt)) 2548 return emulate_gp(ctxt, 0); 2549 break; 2550 } 2551 cs_sel |= SEGMENT_RPL_MASK; 2552 ss_sel |= SEGMENT_RPL_MASK; 2553 2554 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2555 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2556 2557 ctxt->_eip = rdx; 2558 ctxt->mode = usermode; 2559 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2560 2561 return X86EMUL_CONTINUE; 2562 } 2563 2564 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2565 { 2566 int iopl; 2567 if (ctxt->mode == X86EMUL_MODE_REAL) 2568 return false; 2569 if (ctxt->mode == X86EMUL_MODE_VM86) 2570 return true; 2571 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2572 return ctxt->ops->cpl(ctxt) > iopl; 2573 } 2574 2575 #define VMWARE_PORT_VMPORT (0x5658) 2576 #define VMWARE_PORT_VMRPC (0x5659) 2577 2578 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2579 u16 port, u16 len) 2580 { 2581 const struct x86_emulate_ops *ops = ctxt->ops; 2582 struct desc_struct tr_seg; 2583 u32 base3; 2584 int r; 2585 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2586 unsigned mask = (1 << len) - 1; 2587 unsigned long base; 2588 2589 /* 2590 * VMware allows access to these ports even if denied 2591 * by TSS I/O permission bitmap. Mimic behavior. 2592 */ 2593 if (enable_vmware_backdoor && 2594 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2595 return true; 2596 2597 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2598 if (!tr_seg.p) 2599 return false; 2600 if (desc_limit_scaled(&tr_seg) < 103) 2601 return false; 2602 base = get_desc_base(&tr_seg); 2603 #ifdef CONFIG_X86_64 2604 base |= ((u64)base3) << 32; 2605 #endif 2606 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2607 if (r != X86EMUL_CONTINUE) 2608 return false; 2609 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2610 return false; 2611 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2612 if (r != X86EMUL_CONTINUE) 2613 return false; 2614 if ((perm >> bit_idx) & mask) 2615 return false; 2616 return true; 2617 } 2618 2619 static bool emulator_io_permitted(struct x86_emulate_ctxt *ctxt, 2620 u16 port, u16 len) 2621 { 2622 if (ctxt->perm_ok) 2623 return true; 2624 2625 if (emulator_bad_iopl(ctxt)) 2626 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2627 return false; 2628 2629 ctxt->perm_ok = true; 2630 2631 return true; 2632 } 2633 2634 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2635 { 2636 /* 2637 * Intel CPUs mask the counter and pointers in quite strange 2638 * manner when ECX is zero due to REP-string optimizations. 2639 */ 2640 #ifdef CONFIG_X86_64 2641 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2642 return; 2643 2644 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2645 2646 switch (ctxt->b) { 2647 case 0xa4: /* movsb */ 2648 case 0xa5: /* movsd/w */ 2649 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2650 fallthrough; 2651 case 0xaa: /* stosb */ 2652 case 0xab: /* stosd/w */ 2653 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2654 } 2655 #endif 2656 } 2657 2658 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2659 struct tss_segment_16 *tss) 2660 { 2661 tss->ip = ctxt->_eip; 2662 tss->flag = ctxt->eflags; 2663 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2664 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2665 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2666 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2667 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2668 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2669 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2670 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2671 2672 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2673 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2674 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2675 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2676 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2677 } 2678 2679 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2680 struct tss_segment_16 *tss) 2681 { 2682 int ret; 2683 u8 cpl; 2684 2685 ctxt->_eip = tss->ip; 2686 ctxt->eflags = tss->flag | 2; 2687 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2688 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2689 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2690 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2691 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2692 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2693 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2694 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2695 2696 /* 2697 * SDM says that segment selectors are loaded before segment 2698 * descriptors 2699 */ 2700 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2701 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2702 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2703 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2704 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2705 2706 cpl = tss->cs & 3; 2707 2708 /* 2709 * Now load segment descriptors. If fault happens at this stage 2710 * it is handled in a context of new task 2711 */ 2712 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 2713 X86_TRANSFER_TASK_SWITCH, NULL); 2714 if (ret != X86EMUL_CONTINUE) 2715 return ret; 2716 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2717 X86_TRANSFER_TASK_SWITCH, NULL); 2718 if (ret != X86EMUL_CONTINUE) 2719 return ret; 2720 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2721 X86_TRANSFER_TASK_SWITCH, NULL); 2722 if (ret != X86EMUL_CONTINUE) 2723 return ret; 2724 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2725 X86_TRANSFER_TASK_SWITCH, NULL); 2726 if (ret != X86EMUL_CONTINUE) 2727 return ret; 2728 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2729 X86_TRANSFER_TASK_SWITCH, NULL); 2730 if (ret != X86EMUL_CONTINUE) 2731 return ret; 2732 2733 return X86EMUL_CONTINUE; 2734 } 2735 2736 static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2737 ulong old_tss_base, struct desc_struct *new_desc) 2738 { 2739 struct tss_segment_16 tss_seg; 2740 int ret; 2741 u32 new_tss_base = get_desc_base(new_desc); 2742 2743 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2744 if (ret != X86EMUL_CONTINUE) 2745 return ret; 2746 2747 save_state_to_tss16(ctxt, &tss_seg); 2748 2749 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2750 if (ret != X86EMUL_CONTINUE) 2751 return ret; 2752 2753 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2754 if (ret != X86EMUL_CONTINUE) 2755 return ret; 2756 2757 if (old_tss_sel != 0xffff) { 2758 tss_seg.prev_task_link = old_tss_sel; 2759 2760 ret = linear_write_system(ctxt, new_tss_base, 2761 &tss_seg.prev_task_link, 2762 sizeof(tss_seg.prev_task_link)); 2763 if (ret != X86EMUL_CONTINUE) 2764 return ret; 2765 } 2766 2767 return load_state_from_tss16(ctxt, &tss_seg); 2768 } 2769 2770 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2771 struct tss_segment_32 *tss) 2772 { 2773 /* CR3 and ldt selector are not saved intentionally */ 2774 tss->eip = ctxt->_eip; 2775 tss->eflags = ctxt->eflags; 2776 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2777 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2778 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2779 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2780 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2781 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2782 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2783 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2784 2785 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2786 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2787 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2788 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2789 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2790 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2791 } 2792 2793 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2794 struct tss_segment_32 *tss) 2795 { 2796 int ret; 2797 u8 cpl; 2798 2799 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2800 return emulate_gp(ctxt, 0); 2801 ctxt->_eip = tss->eip; 2802 ctxt->eflags = tss->eflags | 2; 2803 2804 /* General purpose registers */ 2805 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2806 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2807 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2808 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2809 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2810 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2811 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2812 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2813 2814 /* 2815 * SDM says that segment selectors are loaded before segment 2816 * descriptors. This is important because CPL checks will 2817 * use CS.RPL. 2818 */ 2819 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2820 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2821 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2822 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2823 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2824 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2825 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2826 2827 /* 2828 * If we're switching between Protected Mode and VM86, we need to make 2829 * sure to update the mode before loading the segment descriptors so 2830 * that the selectors are interpreted correctly. 2831 */ 2832 if (ctxt->eflags & X86_EFLAGS_VM) { 2833 ctxt->mode = X86EMUL_MODE_VM86; 2834 cpl = 3; 2835 } else { 2836 ctxt->mode = X86EMUL_MODE_PROT32; 2837 cpl = tss->cs & 3; 2838 } 2839 2840 /* 2841 * Now load segment descriptors. If fault happens at this stage 2842 * it is handled in a context of new task 2843 */ 2844 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 2845 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 2846 if (ret != X86EMUL_CONTINUE) 2847 return ret; 2848 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2849 X86_TRANSFER_TASK_SWITCH, NULL); 2850 if (ret != X86EMUL_CONTINUE) 2851 return ret; 2852 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2853 X86_TRANSFER_TASK_SWITCH, NULL); 2854 if (ret != X86EMUL_CONTINUE) 2855 return ret; 2856 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2857 X86_TRANSFER_TASK_SWITCH, NULL); 2858 if (ret != X86EMUL_CONTINUE) 2859 return ret; 2860 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2861 X86_TRANSFER_TASK_SWITCH, NULL); 2862 if (ret != X86EMUL_CONTINUE) 2863 return ret; 2864 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 2865 X86_TRANSFER_TASK_SWITCH, NULL); 2866 if (ret != X86EMUL_CONTINUE) 2867 return ret; 2868 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 2869 X86_TRANSFER_TASK_SWITCH, NULL); 2870 2871 return ret; 2872 } 2873 2874 static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2875 ulong old_tss_base, struct desc_struct *new_desc) 2876 { 2877 struct tss_segment_32 tss_seg; 2878 int ret; 2879 u32 new_tss_base = get_desc_base(new_desc); 2880 u32 eip_offset = offsetof(struct tss_segment_32, eip); 2881 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 2882 2883 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2884 if (ret != X86EMUL_CONTINUE) 2885 return ret; 2886 2887 save_state_to_tss32(ctxt, &tss_seg); 2888 2889 /* Only GP registers and segment selectors are saved */ 2890 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 2891 ldt_sel_offset - eip_offset); 2892 if (ret != X86EMUL_CONTINUE) 2893 return ret; 2894 2895 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2896 if (ret != X86EMUL_CONTINUE) 2897 return ret; 2898 2899 if (old_tss_sel != 0xffff) { 2900 tss_seg.prev_task_link = old_tss_sel; 2901 2902 ret = linear_write_system(ctxt, new_tss_base, 2903 &tss_seg.prev_task_link, 2904 sizeof(tss_seg.prev_task_link)); 2905 if (ret != X86EMUL_CONTINUE) 2906 return ret; 2907 } 2908 2909 return load_state_from_tss32(ctxt, &tss_seg); 2910 } 2911 2912 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2913 u16 tss_selector, int idt_index, int reason, 2914 bool has_error_code, u32 error_code) 2915 { 2916 const struct x86_emulate_ops *ops = ctxt->ops; 2917 struct desc_struct curr_tss_desc, next_tss_desc; 2918 int ret; 2919 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2920 ulong old_tss_base = 2921 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2922 u32 desc_limit; 2923 ulong desc_addr, dr7; 2924 2925 /* FIXME: old_tss_base == ~0 ? */ 2926 2927 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2928 if (ret != X86EMUL_CONTINUE) 2929 return ret; 2930 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2931 if (ret != X86EMUL_CONTINUE) 2932 return ret; 2933 2934 /* FIXME: check that next_tss_desc is tss */ 2935 2936 /* 2937 * Check privileges. The three cases are task switch caused by... 2938 * 2939 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2940 * 2. Exception/IRQ/iret: No check is performed 2941 * 3. jmp/call to TSS/task-gate: No check is performed since the 2942 * hardware checks it before exiting. 2943 */ 2944 if (reason == TASK_SWITCH_GATE) { 2945 if (idt_index != -1) { 2946 /* Software interrupts */ 2947 struct desc_struct task_gate_desc; 2948 int dpl; 2949 2950 ret = read_interrupt_descriptor(ctxt, idt_index, 2951 &task_gate_desc); 2952 if (ret != X86EMUL_CONTINUE) 2953 return ret; 2954 2955 dpl = task_gate_desc.dpl; 2956 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2957 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2958 } 2959 } 2960 2961 desc_limit = desc_limit_scaled(&next_tss_desc); 2962 if (!next_tss_desc.p || 2963 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2964 desc_limit < 0x2b)) { 2965 return emulate_ts(ctxt, tss_selector & 0xfffc); 2966 } 2967 2968 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2969 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2970 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2971 } 2972 2973 if (reason == TASK_SWITCH_IRET) 2974 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2975 2976 /* set back link to prev task only if NT bit is set in eflags 2977 note that old_tss_sel is not used after this point */ 2978 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2979 old_tss_sel = 0xffff; 2980 2981 if (next_tss_desc.type & 8) 2982 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc); 2983 else 2984 ret = task_switch_16(ctxt, old_tss_sel, 2985 old_tss_base, &next_tss_desc); 2986 if (ret != X86EMUL_CONTINUE) 2987 return ret; 2988 2989 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2990 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2991 2992 if (reason != TASK_SWITCH_IRET) { 2993 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2994 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2995 } 2996 2997 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2998 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2999 3000 if (has_error_code) { 3001 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3002 ctxt->lock_prefix = 0; 3003 ctxt->src.val = (unsigned long) error_code; 3004 ret = em_push(ctxt); 3005 } 3006 3007 ops->get_dr(ctxt, 7, &dr7); 3008 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3009 3010 return ret; 3011 } 3012 3013 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3014 u16 tss_selector, int idt_index, int reason, 3015 bool has_error_code, u32 error_code) 3016 { 3017 int rc; 3018 3019 invalidate_registers(ctxt); 3020 ctxt->_eip = ctxt->eip; 3021 ctxt->dst.type = OP_NONE; 3022 3023 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3024 has_error_code, error_code); 3025 3026 if (rc == X86EMUL_CONTINUE) { 3027 ctxt->eip = ctxt->_eip; 3028 writeback_registers(ctxt); 3029 } 3030 3031 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3032 } 3033 3034 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3035 struct operand *op) 3036 { 3037 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3038 3039 register_address_increment(ctxt, reg, df * op->bytes); 3040 op->addr.mem.ea = register_address(ctxt, reg); 3041 } 3042 3043 static int em_das(struct x86_emulate_ctxt *ctxt) 3044 { 3045 u8 al, old_al; 3046 bool af, cf, old_cf; 3047 3048 cf = ctxt->eflags & X86_EFLAGS_CF; 3049 al = ctxt->dst.val; 3050 3051 old_al = al; 3052 old_cf = cf; 3053 cf = false; 3054 af = ctxt->eflags & X86_EFLAGS_AF; 3055 if ((al & 0x0f) > 9 || af) { 3056 al -= 6; 3057 cf = old_cf | (al >= 250); 3058 af = true; 3059 } else { 3060 af = false; 3061 } 3062 if (old_al > 0x99 || old_cf) { 3063 al -= 0x60; 3064 cf = true; 3065 } 3066 3067 ctxt->dst.val = al; 3068 /* Set PF, ZF, SF */ 3069 ctxt->src.type = OP_IMM; 3070 ctxt->src.val = 0; 3071 ctxt->src.bytes = 1; 3072 fastop(ctxt, em_or); 3073 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3074 if (cf) 3075 ctxt->eflags |= X86_EFLAGS_CF; 3076 if (af) 3077 ctxt->eflags |= X86_EFLAGS_AF; 3078 return X86EMUL_CONTINUE; 3079 } 3080 3081 static int em_aam(struct x86_emulate_ctxt *ctxt) 3082 { 3083 u8 al, ah; 3084 3085 if (ctxt->src.val == 0) 3086 return emulate_de(ctxt); 3087 3088 al = ctxt->dst.val & 0xff; 3089 ah = al / ctxt->src.val; 3090 al %= ctxt->src.val; 3091 3092 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3093 3094 /* Set PF, ZF, SF */ 3095 ctxt->src.type = OP_IMM; 3096 ctxt->src.val = 0; 3097 ctxt->src.bytes = 1; 3098 fastop(ctxt, em_or); 3099 3100 return X86EMUL_CONTINUE; 3101 } 3102 3103 static int em_aad(struct x86_emulate_ctxt *ctxt) 3104 { 3105 u8 al = ctxt->dst.val & 0xff; 3106 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3107 3108 al = (al + (ah * ctxt->src.val)) & 0xff; 3109 3110 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3111 3112 /* Set PF, ZF, SF */ 3113 ctxt->src.type = OP_IMM; 3114 ctxt->src.val = 0; 3115 ctxt->src.bytes = 1; 3116 fastop(ctxt, em_or); 3117 3118 return X86EMUL_CONTINUE; 3119 } 3120 3121 static int em_call(struct x86_emulate_ctxt *ctxt) 3122 { 3123 int rc; 3124 long rel = ctxt->src.val; 3125 3126 ctxt->src.val = (unsigned long)ctxt->_eip; 3127 rc = jmp_rel(ctxt, rel); 3128 if (rc != X86EMUL_CONTINUE) 3129 return rc; 3130 return em_push(ctxt); 3131 } 3132 3133 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3134 { 3135 u16 sel, old_cs; 3136 ulong old_eip; 3137 int rc; 3138 struct desc_struct old_desc, new_desc; 3139 const struct x86_emulate_ops *ops = ctxt->ops; 3140 int cpl = ctxt->ops->cpl(ctxt); 3141 enum x86emul_mode prev_mode = ctxt->mode; 3142 3143 old_eip = ctxt->_eip; 3144 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3145 3146 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3147 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3148 X86_TRANSFER_CALL_JMP, &new_desc); 3149 if (rc != X86EMUL_CONTINUE) 3150 return rc; 3151 3152 rc = assign_eip_far(ctxt, ctxt->src.val); 3153 if (rc != X86EMUL_CONTINUE) 3154 goto fail; 3155 3156 ctxt->src.val = old_cs; 3157 rc = em_push(ctxt); 3158 if (rc != X86EMUL_CONTINUE) 3159 goto fail; 3160 3161 ctxt->src.val = old_eip; 3162 rc = em_push(ctxt); 3163 /* If we failed, we tainted the memory, but the very least we should 3164 restore cs */ 3165 if (rc != X86EMUL_CONTINUE) { 3166 pr_warn_once("faulting far call emulation tainted memory\n"); 3167 goto fail; 3168 } 3169 return rc; 3170 fail: 3171 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3172 ctxt->mode = prev_mode; 3173 return rc; 3174 3175 } 3176 3177 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3178 { 3179 int rc; 3180 unsigned long eip; 3181 3182 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3183 if (rc != X86EMUL_CONTINUE) 3184 return rc; 3185 rc = assign_eip_near(ctxt, eip); 3186 if (rc != X86EMUL_CONTINUE) 3187 return rc; 3188 rsp_increment(ctxt, ctxt->src.val); 3189 return X86EMUL_CONTINUE; 3190 } 3191 3192 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3193 { 3194 /* Write back the register source. */ 3195 ctxt->src.val = ctxt->dst.val; 3196 write_register_operand(&ctxt->src); 3197 3198 /* Write back the memory destination with implicit LOCK prefix. */ 3199 ctxt->dst.val = ctxt->src.orig_val; 3200 ctxt->lock_prefix = 1; 3201 return X86EMUL_CONTINUE; 3202 } 3203 3204 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3205 { 3206 ctxt->dst.val = ctxt->src2.val; 3207 return fastop(ctxt, em_imul); 3208 } 3209 3210 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3211 { 3212 ctxt->dst.type = OP_REG; 3213 ctxt->dst.bytes = ctxt->src.bytes; 3214 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3215 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3216 3217 return X86EMUL_CONTINUE; 3218 } 3219 3220 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3221 { 3222 u64 tsc_aux = 0; 3223 3224 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3225 return emulate_ud(ctxt); 3226 3227 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3228 ctxt->dst.val = tsc_aux; 3229 return X86EMUL_CONTINUE; 3230 } 3231 3232 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3233 { 3234 u64 tsc = 0; 3235 3236 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3237 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3238 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3239 return X86EMUL_CONTINUE; 3240 } 3241 3242 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3243 { 3244 u64 pmc; 3245 3246 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3247 return emulate_gp(ctxt, 0); 3248 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3249 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3250 return X86EMUL_CONTINUE; 3251 } 3252 3253 static int em_mov(struct x86_emulate_ctxt *ctxt) 3254 { 3255 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3256 return X86EMUL_CONTINUE; 3257 } 3258 3259 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3260 { 3261 u16 tmp; 3262 3263 if (!ctxt->ops->guest_has_movbe(ctxt)) 3264 return emulate_ud(ctxt); 3265 3266 switch (ctxt->op_bytes) { 3267 case 2: 3268 /* 3269 * From MOVBE definition: "...When the operand size is 16 bits, 3270 * the upper word of the destination register remains unchanged 3271 * ..." 3272 * 3273 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3274 * rules so we have to do the operation almost per hand. 3275 */ 3276 tmp = (u16)ctxt->src.val; 3277 ctxt->dst.val &= ~0xffffUL; 3278 ctxt->dst.val |= (unsigned long)swab16(tmp); 3279 break; 3280 case 4: 3281 ctxt->dst.val = swab32((u32)ctxt->src.val); 3282 break; 3283 case 8: 3284 ctxt->dst.val = swab64(ctxt->src.val); 3285 break; 3286 default: 3287 BUG(); 3288 } 3289 return X86EMUL_CONTINUE; 3290 } 3291 3292 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3293 { 3294 int cr_num = ctxt->modrm_reg; 3295 int r; 3296 3297 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) 3298 return emulate_gp(ctxt, 0); 3299 3300 /* Disable writeback. */ 3301 ctxt->dst.type = OP_NONE; 3302 3303 if (cr_num == 0) { 3304 /* 3305 * CR0 write might have updated CR0.PE and/or CR0.PG 3306 * which can affect the cpu's execution mode. 3307 */ 3308 r = emulator_recalc_and_set_mode(ctxt); 3309 if (r != X86EMUL_CONTINUE) 3310 return r; 3311 } 3312 3313 return X86EMUL_CONTINUE; 3314 } 3315 3316 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3317 { 3318 unsigned long val; 3319 3320 if (ctxt->mode == X86EMUL_MODE_PROT64) 3321 val = ctxt->src.val & ~0ULL; 3322 else 3323 val = ctxt->src.val & ~0U; 3324 3325 /* #UD condition is already handled. */ 3326 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3327 return emulate_gp(ctxt, 0); 3328 3329 /* Disable writeback. */ 3330 ctxt->dst.type = OP_NONE; 3331 return X86EMUL_CONTINUE; 3332 } 3333 3334 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3335 { 3336 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3337 u64 msr_data; 3338 int r; 3339 3340 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3341 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3342 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data); 3343 3344 if (r == X86EMUL_PROPAGATE_FAULT) 3345 return emulate_gp(ctxt, 0); 3346 3347 return r; 3348 } 3349 3350 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3351 { 3352 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3353 u64 msr_data; 3354 int r; 3355 3356 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data); 3357 3358 if (r == X86EMUL_PROPAGATE_FAULT) 3359 return emulate_gp(ctxt, 0); 3360 3361 if (r == X86EMUL_CONTINUE) { 3362 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3363 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3364 } 3365 return r; 3366 } 3367 3368 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3369 { 3370 if (segment > VCPU_SREG_GS && 3371 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3372 ctxt->ops->cpl(ctxt) > 0) 3373 return emulate_gp(ctxt, 0); 3374 3375 ctxt->dst.val = get_segment_selector(ctxt, segment); 3376 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3377 ctxt->dst.bytes = 2; 3378 return X86EMUL_CONTINUE; 3379 } 3380 3381 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3382 { 3383 if (ctxt->modrm_reg > VCPU_SREG_GS) 3384 return emulate_ud(ctxt); 3385 3386 return em_store_sreg(ctxt, ctxt->modrm_reg); 3387 } 3388 3389 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3390 { 3391 u16 sel = ctxt->src.val; 3392 3393 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3394 return emulate_ud(ctxt); 3395 3396 if (ctxt->modrm_reg == VCPU_SREG_SS) 3397 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3398 3399 /* Disable writeback. */ 3400 ctxt->dst.type = OP_NONE; 3401 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3402 } 3403 3404 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3405 { 3406 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3407 } 3408 3409 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3410 { 3411 u16 sel = ctxt->src.val; 3412 3413 /* Disable writeback. */ 3414 ctxt->dst.type = OP_NONE; 3415 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3416 } 3417 3418 static int em_str(struct x86_emulate_ctxt *ctxt) 3419 { 3420 return em_store_sreg(ctxt, VCPU_SREG_TR); 3421 } 3422 3423 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3424 { 3425 u16 sel = ctxt->src.val; 3426 3427 /* Disable writeback. */ 3428 ctxt->dst.type = OP_NONE; 3429 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3430 } 3431 3432 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3433 { 3434 int rc; 3435 ulong linear; 3436 3437 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3438 if (rc == X86EMUL_CONTINUE) 3439 ctxt->ops->invlpg(ctxt, linear); 3440 /* Disable writeback. */ 3441 ctxt->dst.type = OP_NONE; 3442 return X86EMUL_CONTINUE; 3443 } 3444 3445 static int em_clts(struct x86_emulate_ctxt *ctxt) 3446 { 3447 ulong cr0; 3448 3449 cr0 = ctxt->ops->get_cr(ctxt, 0); 3450 cr0 &= ~X86_CR0_TS; 3451 ctxt->ops->set_cr(ctxt, 0, cr0); 3452 return X86EMUL_CONTINUE; 3453 } 3454 3455 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3456 { 3457 int rc = ctxt->ops->fix_hypercall(ctxt); 3458 3459 if (rc != X86EMUL_CONTINUE) 3460 return rc; 3461 3462 /* Let the processor re-execute the fixed hypercall */ 3463 ctxt->_eip = ctxt->eip; 3464 /* Disable writeback. */ 3465 ctxt->dst.type = OP_NONE; 3466 return X86EMUL_CONTINUE; 3467 } 3468 3469 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3470 void (*get)(struct x86_emulate_ctxt *ctxt, 3471 struct desc_ptr *ptr)) 3472 { 3473 struct desc_ptr desc_ptr; 3474 3475 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3476 ctxt->ops->cpl(ctxt) > 0) 3477 return emulate_gp(ctxt, 0); 3478 3479 if (ctxt->mode == X86EMUL_MODE_PROT64) 3480 ctxt->op_bytes = 8; 3481 get(ctxt, &desc_ptr); 3482 if (ctxt->op_bytes == 2) { 3483 ctxt->op_bytes = 4; 3484 desc_ptr.address &= 0x00ffffff; 3485 } 3486 /* Disable writeback. */ 3487 ctxt->dst.type = OP_NONE; 3488 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3489 &desc_ptr, 2 + ctxt->op_bytes); 3490 } 3491 3492 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3493 { 3494 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3495 } 3496 3497 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3498 { 3499 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3500 } 3501 3502 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3503 { 3504 struct desc_ptr desc_ptr; 3505 int rc; 3506 3507 if (ctxt->mode == X86EMUL_MODE_PROT64) 3508 ctxt->op_bytes = 8; 3509 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3510 &desc_ptr.size, &desc_ptr.address, 3511 ctxt->op_bytes); 3512 if (rc != X86EMUL_CONTINUE) 3513 return rc; 3514 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3515 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3516 return emulate_gp(ctxt, 0); 3517 if (lgdt) 3518 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3519 else 3520 ctxt->ops->set_idt(ctxt, &desc_ptr); 3521 /* Disable writeback. */ 3522 ctxt->dst.type = OP_NONE; 3523 return X86EMUL_CONTINUE; 3524 } 3525 3526 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3527 { 3528 return em_lgdt_lidt(ctxt, true); 3529 } 3530 3531 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3532 { 3533 return em_lgdt_lidt(ctxt, false); 3534 } 3535 3536 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3537 { 3538 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3539 ctxt->ops->cpl(ctxt) > 0) 3540 return emulate_gp(ctxt, 0); 3541 3542 if (ctxt->dst.type == OP_MEM) 3543 ctxt->dst.bytes = 2; 3544 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3545 return X86EMUL_CONTINUE; 3546 } 3547 3548 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3549 { 3550 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3551 | (ctxt->src.val & 0x0f)); 3552 ctxt->dst.type = OP_NONE; 3553 return X86EMUL_CONTINUE; 3554 } 3555 3556 static int em_loop(struct x86_emulate_ctxt *ctxt) 3557 { 3558 int rc = X86EMUL_CONTINUE; 3559 3560 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3561 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3562 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3563 rc = jmp_rel(ctxt, ctxt->src.val); 3564 3565 return rc; 3566 } 3567 3568 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3569 { 3570 int rc = X86EMUL_CONTINUE; 3571 3572 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3573 rc = jmp_rel(ctxt, ctxt->src.val); 3574 3575 return rc; 3576 } 3577 3578 static int em_in(struct x86_emulate_ctxt *ctxt) 3579 { 3580 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3581 &ctxt->dst.val)) 3582 return X86EMUL_IO_NEEDED; 3583 3584 return X86EMUL_CONTINUE; 3585 } 3586 3587 static int em_out(struct x86_emulate_ctxt *ctxt) 3588 { 3589 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3590 &ctxt->src.val, 1); 3591 /* Disable writeback. */ 3592 ctxt->dst.type = OP_NONE; 3593 return X86EMUL_CONTINUE; 3594 } 3595 3596 static int em_cli(struct x86_emulate_ctxt *ctxt) 3597 { 3598 if (emulator_bad_iopl(ctxt)) 3599 return emulate_gp(ctxt, 0); 3600 3601 ctxt->eflags &= ~X86_EFLAGS_IF; 3602 return X86EMUL_CONTINUE; 3603 } 3604 3605 static int em_sti(struct x86_emulate_ctxt *ctxt) 3606 { 3607 if (emulator_bad_iopl(ctxt)) 3608 return emulate_gp(ctxt, 0); 3609 3610 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3611 ctxt->eflags |= X86_EFLAGS_IF; 3612 return X86EMUL_CONTINUE; 3613 } 3614 3615 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3616 { 3617 u32 eax, ebx, ecx, edx; 3618 u64 msr = 0; 3619 3620 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3621 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3622 ctxt->ops->cpl(ctxt)) { 3623 return emulate_gp(ctxt, 0); 3624 } 3625 3626 eax = reg_read(ctxt, VCPU_REGS_RAX); 3627 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3628 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3629 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3630 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3631 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3632 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3633 return X86EMUL_CONTINUE; 3634 } 3635 3636 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3637 { 3638 u32 flags; 3639 3640 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3641 X86_EFLAGS_SF; 3642 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3643 3644 ctxt->eflags &= ~0xffUL; 3645 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3646 return X86EMUL_CONTINUE; 3647 } 3648 3649 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3650 { 3651 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3652 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3653 return X86EMUL_CONTINUE; 3654 } 3655 3656 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3657 { 3658 switch (ctxt->op_bytes) { 3659 #ifdef CONFIG_X86_64 3660 case 8: 3661 asm("bswap %0" : "+r"(ctxt->dst.val)); 3662 break; 3663 #endif 3664 default: 3665 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3666 break; 3667 } 3668 return X86EMUL_CONTINUE; 3669 } 3670 3671 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3672 { 3673 /* emulating clflush regardless of cpuid */ 3674 return X86EMUL_CONTINUE; 3675 } 3676 3677 static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 3678 { 3679 /* emulating clflushopt regardless of cpuid */ 3680 return X86EMUL_CONTINUE; 3681 } 3682 3683 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3684 { 3685 ctxt->dst.val = (s32) ctxt->src.val; 3686 return X86EMUL_CONTINUE; 3687 } 3688 3689 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 3690 { 3691 if (!ctxt->ops->guest_has_fxsr(ctxt)) 3692 return emulate_ud(ctxt); 3693 3694 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 3695 return emulate_nm(ctxt); 3696 3697 /* 3698 * Don't emulate a case that should never be hit, instead of working 3699 * around a lack of fxsave64/fxrstor64 on old compilers. 3700 */ 3701 if (ctxt->mode >= X86EMUL_MODE_PROT64) 3702 return X86EMUL_UNHANDLEABLE; 3703 3704 return X86EMUL_CONTINUE; 3705 } 3706 3707 /* 3708 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 3709 * and restore MXCSR. 3710 */ 3711 static size_t __fxstate_size(int nregs) 3712 { 3713 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 3714 } 3715 3716 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 3717 { 3718 bool cr4_osfxsr; 3719 if (ctxt->mode == X86EMUL_MODE_PROT64) 3720 return __fxstate_size(16); 3721 3722 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 3723 return __fxstate_size(cr4_osfxsr ? 8 : 0); 3724 } 3725 3726 /* 3727 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 3728 * 1) 16 bit mode 3729 * 2) 32 bit mode 3730 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 3731 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 3732 * save and restore 3733 * 3) 64-bit mode with REX.W prefix 3734 * - like (2), but XMM 8-15 are being saved and restored 3735 * 4) 64-bit mode without REX.W prefix 3736 * - like (3), but FIP and FDP are 64 bit 3737 * 3738 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 3739 * desired result. (4) is not emulated. 3740 * 3741 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 3742 * and FPU DS) should match. 3743 */ 3744 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 3745 { 3746 struct fxregs_state fx_state; 3747 int rc; 3748 3749 rc = check_fxsr(ctxt); 3750 if (rc != X86EMUL_CONTINUE) 3751 return rc; 3752 3753 kvm_fpu_get(); 3754 3755 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 3756 3757 kvm_fpu_put(); 3758 3759 if (rc != X86EMUL_CONTINUE) 3760 return rc; 3761 3762 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 3763 fxstate_size(ctxt)); 3764 } 3765 3766 /* 3767 * FXRSTOR might restore XMM registers not provided by the guest. Fill 3768 * in the host registers (via FXSAVE) instead, so they won't be modified. 3769 * (preemption has to stay disabled until FXRSTOR). 3770 * 3771 * Use noinline to keep the stack for other functions called by callers small. 3772 */ 3773 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 3774 const size_t used_size) 3775 { 3776 struct fxregs_state fx_tmp; 3777 int rc; 3778 3779 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 3780 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 3781 __fxstate_size(16) - used_size); 3782 3783 return rc; 3784 } 3785 3786 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 3787 { 3788 struct fxregs_state fx_state; 3789 int rc; 3790 size_t size; 3791 3792 rc = check_fxsr(ctxt); 3793 if (rc != X86EMUL_CONTINUE) 3794 return rc; 3795 3796 size = fxstate_size(ctxt); 3797 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 3798 if (rc != X86EMUL_CONTINUE) 3799 return rc; 3800 3801 kvm_fpu_get(); 3802 3803 if (size < __fxstate_size(16)) { 3804 rc = fxregs_fixup(&fx_state, size); 3805 if (rc != X86EMUL_CONTINUE) 3806 goto out; 3807 } 3808 3809 if (fx_state.mxcsr >> 16) { 3810 rc = emulate_gp(ctxt, 0); 3811 goto out; 3812 } 3813 3814 if (rc == X86EMUL_CONTINUE) 3815 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 3816 3817 out: 3818 kvm_fpu_put(); 3819 3820 return rc; 3821 } 3822 3823 static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 3824 { 3825 u32 eax, ecx, edx; 3826 3827 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE)) 3828 return emulate_ud(ctxt); 3829 3830 eax = reg_read(ctxt, VCPU_REGS_RAX); 3831 edx = reg_read(ctxt, VCPU_REGS_RDX); 3832 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3833 3834 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 3835 return emulate_gp(ctxt, 0); 3836 3837 return X86EMUL_CONTINUE; 3838 } 3839 3840 static bool valid_cr(int nr) 3841 { 3842 switch (nr) { 3843 case 0: 3844 case 2 ... 4: 3845 case 8: 3846 return true; 3847 default: 3848 return false; 3849 } 3850 } 3851 3852 static int check_cr_access(struct x86_emulate_ctxt *ctxt) 3853 { 3854 if (!valid_cr(ctxt->modrm_reg)) 3855 return emulate_ud(ctxt); 3856 3857 return X86EMUL_CONTINUE; 3858 } 3859 3860 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3861 { 3862 unsigned long dr7; 3863 3864 ctxt->ops->get_dr(ctxt, 7, &dr7); 3865 3866 return dr7 & DR7_GD; 3867 } 3868 3869 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3870 { 3871 int dr = ctxt->modrm_reg; 3872 u64 cr4; 3873 3874 if (dr > 7) 3875 return emulate_ud(ctxt); 3876 3877 cr4 = ctxt->ops->get_cr(ctxt, 4); 3878 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3879 return emulate_ud(ctxt); 3880 3881 if (check_dr7_gd(ctxt)) { 3882 ulong dr6; 3883 3884 ctxt->ops->get_dr(ctxt, 6, &dr6); 3885 dr6 &= ~DR_TRAP_BITS; 3886 dr6 |= DR6_BD | DR6_ACTIVE_LOW; 3887 ctxt->ops->set_dr(ctxt, 6, dr6); 3888 return emulate_db(ctxt); 3889 } 3890 3891 return X86EMUL_CONTINUE; 3892 } 3893 3894 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3895 { 3896 u64 new_val = ctxt->src.val64; 3897 int dr = ctxt->modrm_reg; 3898 3899 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3900 return emulate_gp(ctxt, 0); 3901 3902 return check_dr_read(ctxt); 3903 } 3904 3905 static int check_svme(struct x86_emulate_ctxt *ctxt) 3906 { 3907 u64 efer = 0; 3908 3909 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3910 3911 if (!(efer & EFER_SVME)) 3912 return emulate_ud(ctxt); 3913 3914 return X86EMUL_CONTINUE; 3915 } 3916 3917 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3918 { 3919 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3920 3921 /* Valid physical address? */ 3922 if (rax & 0xffff000000000000ULL) 3923 return emulate_gp(ctxt, 0); 3924 3925 return check_svme(ctxt); 3926 } 3927 3928 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3929 { 3930 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3931 3932 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3933 return emulate_gp(ctxt, 0); 3934 3935 return X86EMUL_CONTINUE; 3936 } 3937 3938 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3939 { 3940 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3941 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3942 3943 /* 3944 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 3945 * in Ring3 when CR4.PCE=0. 3946 */ 3947 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 3948 return X86EMUL_CONTINUE; 3949 3950 /* 3951 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE 3952 * check however is unnecessary because CPL is always 0 outside 3953 * protected mode. 3954 */ 3955 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3956 ctxt->ops->check_pmc(ctxt, rcx)) 3957 return emulate_gp(ctxt, 0); 3958 3959 return X86EMUL_CONTINUE; 3960 } 3961 3962 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3963 { 3964 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3965 if (!emulator_io_permitted(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3966 return emulate_gp(ctxt, 0); 3967 3968 return X86EMUL_CONTINUE; 3969 } 3970 3971 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3972 { 3973 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3974 if (!emulator_io_permitted(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3975 return emulate_gp(ctxt, 0); 3976 3977 return X86EMUL_CONTINUE; 3978 } 3979 3980 #define D(_y) { .flags = (_y) } 3981 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 3982 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 3983 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3984 #define N D(NotImpl) 3985 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3986 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3987 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3988 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 3989 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 3990 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3991 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3992 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 3993 #define II(_f, _e, _i) \ 3994 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 3995 #define IIP(_f, _e, _i, _p) \ 3996 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 3997 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3998 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3999 4000 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4001 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4002 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4003 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4004 #define I2bvIP(_f, _e, _i, _p) \ 4005 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4006 4007 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4008 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4009 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4010 4011 static const struct opcode group7_rm0[] = { 4012 N, 4013 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4014 N, N, N, N, N, N, 4015 }; 4016 4017 static const struct opcode group7_rm1[] = { 4018 DI(SrcNone | Priv, monitor), 4019 DI(SrcNone | Priv, mwait), 4020 N, N, N, N, N, N, 4021 }; 4022 4023 static const struct opcode group7_rm2[] = { 4024 N, 4025 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 4026 N, N, N, N, N, N, 4027 }; 4028 4029 static const struct opcode group7_rm3[] = { 4030 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4031 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4032 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4033 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4034 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4035 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4036 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4037 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4038 }; 4039 4040 static const struct opcode group7_rm7[] = { 4041 N, 4042 DIP(SrcNone, rdtscp, check_rdtsc), 4043 N, N, N, N, N, N, 4044 }; 4045 4046 static const struct opcode group1[] = { 4047 F(Lock, em_add), 4048 F(Lock | PageTable, em_or), 4049 F(Lock, em_adc), 4050 F(Lock, em_sbb), 4051 F(Lock | PageTable, em_and), 4052 F(Lock, em_sub), 4053 F(Lock, em_xor), 4054 F(NoWrite, em_cmp), 4055 }; 4056 4057 static const struct opcode group1A[] = { 4058 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4059 }; 4060 4061 static const struct opcode group2[] = { 4062 F(DstMem | ModRM, em_rol), 4063 F(DstMem | ModRM, em_ror), 4064 F(DstMem | ModRM, em_rcl), 4065 F(DstMem | ModRM, em_rcr), 4066 F(DstMem | ModRM, em_shl), 4067 F(DstMem | ModRM, em_shr), 4068 F(DstMem | ModRM, em_shl), 4069 F(DstMem | ModRM, em_sar), 4070 }; 4071 4072 static const struct opcode group3[] = { 4073 F(DstMem | SrcImm | NoWrite, em_test), 4074 F(DstMem | SrcImm | NoWrite, em_test), 4075 F(DstMem | SrcNone | Lock, em_not), 4076 F(DstMem | SrcNone | Lock, em_neg), 4077 F(DstXacc | Src2Mem, em_mul_ex), 4078 F(DstXacc | Src2Mem, em_imul_ex), 4079 F(DstXacc | Src2Mem, em_div_ex), 4080 F(DstXacc | Src2Mem, em_idiv_ex), 4081 }; 4082 4083 static const struct opcode group4[] = { 4084 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4085 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4086 N, N, N, N, N, N, 4087 }; 4088 4089 static const struct opcode group5[] = { 4090 F(DstMem | SrcNone | Lock, em_inc), 4091 F(DstMem | SrcNone | Lock, em_dec), 4092 I(SrcMem | NearBranch | IsBranch, em_call_near_abs), 4093 I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far), 4094 I(SrcMem | NearBranch | IsBranch, em_jmp_abs), 4095 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), 4096 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4097 }; 4098 4099 static const struct opcode group6[] = { 4100 II(Prot | DstMem, em_sldt, sldt), 4101 II(Prot | DstMem, em_str, str), 4102 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4103 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4104 N, N, N, N, 4105 }; 4106 4107 static const struct group_dual group7 = { { 4108 II(Mov | DstMem, em_sgdt, sgdt), 4109 II(Mov | DstMem, em_sidt, sidt), 4110 II(SrcMem | Priv, em_lgdt, lgdt), 4111 II(SrcMem | Priv, em_lidt, lidt), 4112 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4113 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4114 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4115 }, { 4116 EXT(0, group7_rm0), 4117 EXT(0, group7_rm1), 4118 EXT(0, group7_rm2), 4119 EXT(0, group7_rm3), 4120 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4121 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4122 EXT(0, group7_rm7), 4123 } }; 4124 4125 static const struct opcode group8[] = { 4126 N, N, N, N, 4127 F(DstMem | SrcImmByte | NoWrite, em_bt), 4128 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4129 F(DstMem | SrcImmByte | Lock, em_btr), 4130 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4131 }; 4132 4133 /* 4134 * The "memory" destination is actually always a register, since we come 4135 * from the register case of group9. 4136 */ 4137 static const struct gprefix pfx_0f_c7_7 = { 4138 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4139 }; 4140 4141 4142 static const struct group_dual group9 = { { 4143 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4144 }, { 4145 N, N, N, N, N, N, N, 4146 GP(0, &pfx_0f_c7_7), 4147 } }; 4148 4149 static const struct opcode group11[] = { 4150 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4151 X7(D(Undefined)), 4152 }; 4153 4154 static const struct gprefix pfx_0f_ae_7 = { 4155 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4156 }; 4157 4158 static const struct group_dual group15 = { { 4159 I(ModRM | Aligned16, em_fxsave), 4160 I(ModRM | Aligned16, em_fxrstor), 4161 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4162 }, { 4163 N, N, N, N, N, N, N, N, 4164 } }; 4165 4166 static const struct gprefix pfx_0f_6f_0f_7f = { 4167 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4168 }; 4169 4170 static const struct instr_dual instr_dual_0f_2b = { 4171 I(0, em_mov), N 4172 }; 4173 4174 static const struct gprefix pfx_0f_2b = { 4175 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4176 }; 4177 4178 static const struct gprefix pfx_0f_10_0f_11 = { 4179 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4180 }; 4181 4182 static const struct gprefix pfx_0f_28_0f_29 = { 4183 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4184 }; 4185 4186 static const struct gprefix pfx_0f_e7 = { 4187 N, I(Sse, em_mov), N, N, 4188 }; 4189 4190 static const struct escape escape_d9 = { { 4191 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4192 }, { 4193 /* 0xC0 - 0xC7 */ 4194 N, N, N, N, N, N, N, N, 4195 /* 0xC8 - 0xCF */ 4196 N, N, N, N, N, N, N, N, 4197 /* 0xD0 - 0xC7 */ 4198 N, N, N, N, N, N, N, N, 4199 /* 0xD8 - 0xDF */ 4200 N, N, N, N, N, N, N, N, 4201 /* 0xE0 - 0xE7 */ 4202 N, N, N, N, N, N, N, N, 4203 /* 0xE8 - 0xEF */ 4204 N, N, N, N, N, N, N, N, 4205 /* 0xF0 - 0xF7 */ 4206 N, N, N, N, N, N, N, N, 4207 /* 0xF8 - 0xFF */ 4208 N, N, N, N, N, N, N, N, 4209 } }; 4210 4211 static const struct escape escape_db = { { 4212 N, N, N, N, N, N, N, N, 4213 }, { 4214 /* 0xC0 - 0xC7 */ 4215 N, N, N, N, N, N, N, N, 4216 /* 0xC8 - 0xCF */ 4217 N, N, N, N, N, N, N, N, 4218 /* 0xD0 - 0xC7 */ 4219 N, N, N, N, N, N, N, N, 4220 /* 0xD8 - 0xDF */ 4221 N, N, N, N, N, N, N, N, 4222 /* 0xE0 - 0xE7 */ 4223 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4224 /* 0xE8 - 0xEF */ 4225 N, N, N, N, N, N, N, N, 4226 /* 0xF0 - 0xF7 */ 4227 N, N, N, N, N, N, N, N, 4228 /* 0xF8 - 0xFF */ 4229 N, N, N, N, N, N, N, N, 4230 } }; 4231 4232 static const struct escape escape_dd = { { 4233 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4234 }, { 4235 /* 0xC0 - 0xC7 */ 4236 N, N, N, N, N, N, N, N, 4237 /* 0xC8 - 0xCF */ 4238 N, N, N, N, N, N, N, N, 4239 /* 0xD0 - 0xC7 */ 4240 N, N, N, N, N, N, N, N, 4241 /* 0xD8 - 0xDF */ 4242 N, N, N, N, N, N, N, N, 4243 /* 0xE0 - 0xE7 */ 4244 N, N, N, N, N, N, N, N, 4245 /* 0xE8 - 0xEF */ 4246 N, N, N, N, N, N, N, N, 4247 /* 0xF0 - 0xF7 */ 4248 N, N, N, N, N, N, N, N, 4249 /* 0xF8 - 0xFF */ 4250 N, N, N, N, N, N, N, N, 4251 } }; 4252 4253 static const struct instr_dual instr_dual_0f_c3 = { 4254 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4255 }; 4256 4257 static const struct mode_dual mode_dual_63 = { 4258 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4259 }; 4260 4261 static const struct instr_dual instr_dual_8d = { 4262 D(DstReg | SrcMem | ModRM | NoAccess), N 4263 }; 4264 4265 static const struct opcode opcode_table[256] = { 4266 /* 0x00 - 0x07 */ 4267 F6ALU(Lock, em_add), 4268 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4269 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4270 /* 0x08 - 0x0F */ 4271 F6ALU(Lock | PageTable, em_or), 4272 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4273 N, 4274 /* 0x10 - 0x17 */ 4275 F6ALU(Lock, em_adc), 4276 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4277 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4278 /* 0x18 - 0x1F */ 4279 F6ALU(Lock, em_sbb), 4280 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4281 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4282 /* 0x20 - 0x27 */ 4283 F6ALU(Lock | PageTable, em_and), N, N, 4284 /* 0x28 - 0x2F */ 4285 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4286 /* 0x30 - 0x37 */ 4287 F6ALU(Lock, em_xor), N, N, 4288 /* 0x38 - 0x3F */ 4289 F6ALU(NoWrite, em_cmp), N, N, 4290 /* 0x40 - 0x4F */ 4291 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4292 /* 0x50 - 0x57 */ 4293 X8(I(SrcReg | Stack, em_push)), 4294 /* 0x58 - 0x5F */ 4295 X8(I(DstReg | Stack, em_pop)), 4296 /* 0x60 - 0x67 */ 4297 I(ImplicitOps | Stack | No64, em_pusha), 4298 I(ImplicitOps | Stack | No64, em_popa), 4299 N, MD(ModRM, &mode_dual_63), 4300 N, N, N, N, 4301 /* 0x68 - 0x6F */ 4302 I(SrcImm | Mov | Stack, em_push), 4303 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4304 I(SrcImmByte | Mov | Stack, em_push), 4305 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4306 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4307 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4308 /* 0x70 - 0x7F */ 4309 X16(D(SrcImmByte | NearBranch | IsBranch)), 4310 /* 0x80 - 0x87 */ 4311 G(ByteOp | DstMem | SrcImm, group1), 4312 G(DstMem | SrcImm, group1), 4313 G(ByteOp | DstMem | SrcImm | No64, group1), 4314 G(DstMem | SrcImmByte, group1), 4315 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4316 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4317 /* 0x88 - 0x8F */ 4318 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4319 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4320 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4321 ID(0, &instr_dual_8d), 4322 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4323 G(0, group1A), 4324 /* 0x90 - 0x97 */ 4325 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4326 /* 0x98 - 0x9F */ 4327 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4328 I(SrcImmFAddr | No64 | IsBranch, em_call_far), N, 4329 II(ImplicitOps | Stack, em_pushf, pushf), 4330 II(ImplicitOps | Stack, em_popf, popf), 4331 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4332 /* 0xA0 - 0xA7 */ 4333 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4334 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4335 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4336 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4337 /* 0xA8 - 0xAF */ 4338 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4339 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4340 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4341 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4342 /* 0xB0 - 0xB7 */ 4343 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4344 /* 0xB8 - 0xBF */ 4345 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4346 /* 0xC0 - 0xC7 */ 4347 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4348 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch, em_ret_near_imm), 4349 I(ImplicitOps | NearBranch | IsBranch, em_ret), 4350 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4351 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4352 G(ByteOp, group11), G(0, group11), 4353 /* 0xC8 - 0xCF */ 4354 I(Stack | SrcImmU16 | Src2ImmByte | IsBranch, em_enter), 4355 I(Stack | IsBranch, em_leave), 4356 I(ImplicitOps | SrcImmU16 | IsBranch, em_ret_far_imm), 4357 I(ImplicitOps | IsBranch, em_ret_far), 4358 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch, intn), 4359 D(ImplicitOps | No64 | IsBranch), 4360 II(ImplicitOps | IsBranch, em_iret, iret), 4361 /* 0xD0 - 0xD7 */ 4362 G(Src2One | ByteOp, group2), G(Src2One, group2), 4363 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4364 I(DstAcc | SrcImmUByte | No64, em_aam), 4365 I(DstAcc | SrcImmUByte | No64, em_aad), 4366 F(DstAcc | ByteOp | No64, em_salc), 4367 I(DstAcc | SrcXLat | ByteOp, em_mov), 4368 /* 0xD8 - 0xDF */ 4369 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4370 /* 0xE0 - 0xE7 */ 4371 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), 4372 I(SrcImmByte | NearBranch | IsBranch, em_jcxz), 4373 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4374 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4375 /* 0xE8 - 0xEF */ 4376 I(SrcImm | NearBranch | IsBranch, em_call), 4377 D(SrcImm | ImplicitOps | NearBranch | IsBranch), 4378 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), 4379 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), 4380 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4381 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4382 /* 0xF0 - 0xF7 */ 4383 N, DI(ImplicitOps, icebp), N, N, 4384 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4385 G(ByteOp, group3), G(0, group3), 4386 /* 0xF8 - 0xFF */ 4387 D(ImplicitOps), D(ImplicitOps), 4388 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4389 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4390 }; 4391 4392 static const struct opcode twobyte_table[256] = { 4393 /* 0x00 - 0x0F */ 4394 G(0, group6), GD(0, &group7), N, N, 4395 N, I(ImplicitOps | EmulateOnUD | IsBranch, em_syscall), 4396 II(ImplicitOps | Priv, em_clts, clts), N, 4397 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4398 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4399 /* 0x10 - 0x1F */ 4400 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4401 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4402 N, N, N, N, N, N, 4403 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4404 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4405 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4406 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4407 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4408 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4409 /* 0x20 - 0x2F */ 4410 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4411 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4412 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4413 check_cr_access), 4414 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4415 check_dr_write), 4416 N, N, N, N, 4417 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4418 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4419 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4420 N, N, N, N, 4421 /* 0x30 - 0x3F */ 4422 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4423 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4424 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4425 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4426 I(ImplicitOps | EmulateOnUD | IsBranch, em_sysenter), 4427 I(ImplicitOps | Priv | EmulateOnUD | IsBranch, em_sysexit), 4428 N, N, 4429 N, N, N, N, N, N, N, N, 4430 /* 0x40 - 0x4F */ 4431 X16(D(DstReg | SrcMem | ModRM)), 4432 /* 0x50 - 0x5F */ 4433 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4434 /* 0x60 - 0x6F */ 4435 N, N, N, N, 4436 N, N, N, N, 4437 N, N, N, N, 4438 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4439 /* 0x70 - 0x7F */ 4440 N, N, N, N, 4441 N, N, N, N, 4442 N, N, N, N, 4443 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4444 /* 0x80 - 0x8F */ 4445 X16(D(SrcImm | NearBranch | IsBranch)), 4446 /* 0x90 - 0x9F */ 4447 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4448 /* 0xA0 - 0xA7 */ 4449 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4450 II(ImplicitOps, em_cpuid, cpuid), 4451 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4452 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4453 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4454 /* 0xA8 - 0xAF */ 4455 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4456 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4457 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4458 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4459 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4460 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4461 /* 0xB0 - 0xB7 */ 4462 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4463 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4464 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4465 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4466 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4467 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4468 /* 0xB8 - 0xBF */ 4469 N, N, 4470 G(BitOp, group8), 4471 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4472 I(DstReg | SrcMem | ModRM, em_bsf_c), 4473 I(DstReg | SrcMem | ModRM, em_bsr_c), 4474 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4475 /* 0xC0 - 0xC7 */ 4476 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4477 N, ID(0, &instr_dual_0f_c3), 4478 N, N, N, GD(0, &group9), 4479 /* 0xC8 - 0xCF */ 4480 X8(I(DstReg, em_bswap)), 4481 /* 0xD0 - 0xDF */ 4482 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4483 /* 0xE0 - 0xEF */ 4484 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4485 N, N, N, N, N, N, N, N, 4486 /* 0xF0 - 0xFF */ 4487 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4488 }; 4489 4490 static const struct instr_dual instr_dual_0f_38_f0 = { 4491 I(DstReg | SrcMem | Mov, em_movbe), N 4492 }; 4493 4494 static const struct instr_dual instr_dual_0f_38_f1 = { 4495 I(DstMem | SrcReg | Mov, em_movbe), N 4496 }; 4497 4498 static const struct gprefix three_byte_0f_38_f0 = { 4499 ID(0, &instr_dual_0f_38_f0), N, N, N 4500 }; 4501 4502 static const struct gprefix three_byte_0f_38_f1 = { 4503 ID(0, &instr_dual_0f_38_f1), N, N, N 4504 }; 4505 4506 /* 4507 * Insns below are selected by the prefix which indexed by the third opcode 4508 * byte. 4509 */ 4510 static const struct opcode opcode_map_0f_38[256] = { 4511 /* 0x00 - 0x7f */ 4512 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4513 /* 0x80 - 0xef */ 4514 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4515 /* 0xf0 - 0xf1 */ 4516 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4517 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4518 /* 0xf2 - 0xff */ 4519 N, N, X4(N), X8(N) 4520 }; 4521 4522 #undef D 4523 #undef N 4524 #undef G 4525 #undef GD 4526 #undef I 4527 #undef GP 4528 #undef EXT 4529 #undef MD 4530 #undef ID 4531 4532 #undef D2bv 4533 #undef D2bvIP 4534 #undef I2bv 4535 #undef I2bvIP 4536 #undef I6ALU 4537 4538 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4539 { 4540 unsigned size; 4541 4542 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4543 if (size == 8) 4544 size = 4; 4545 return size; 4546 } 4547 4548 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4549 unsigned size, bool sign_extension) 4550 { 4551 int rc = X86EMUL_CONTINUE; 4552 4553 op->type = OP_IMM; 4554 op->bytes = size; 4555 op->addr.mem.ea = ctxt->_eip; 4556 /* NB. Immediates are sign-extended as necessary. */ 4557 switch (op->bytes) { 4558 case 1: 4559 op->val = insn_fetch(s8, ctxt); 4560 break; 4561 case 2: 4562 op->val = insn_fetch(s16, ctxt); 4563 break; 4564 case 4: 4565 op->val = insn_fetch(s32, ctxt); 4566 break; 4567 case 8: 4568 op->val = insn_fetch(s64, ctxt); 4569 break; 4570 } 4571 if (!sign_extension) { 4572 switch (op->bytes) { 4573 case 1: 4574 op->val &= 0xff; 4575 break; 4576 case 2: 4577 op->val &= 0xffff; 4578 break; 4579 case 4: 4580 op->val &= 0xffffffff; 4581 break; 4582 } 4583 } 4584 done: 4585 return rc; 4586 } 4587 4588 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4589 unsigned d) 4590 { 4591 int rc = X86EMUL_CONTINUE; 4592 4593 switch (d) { 4594 case OpReg: 4595 decode_register_operand(ctxt, op); 4596 break; 4597 case OpImmUByte: 4598 rc = decode_imm(ctxt, op, 1, false); 4599 break; 4600 case OpMem: 4601 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4602 mem_common: 4603 *op = ctxt->memop; 4604 ctxt->memopp = op; 4605 if (ctxt->d & BitOp) 4606 fetch_bit_operand(ctxt); 4607 op->orig_val = op->val; 4608 break; 4609 case OpMem64: 4610 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4611 goto mem_common; 4612 case OpAcc: 4613 op->type = OP_REG; 4614 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4615 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4616 fetch_register_operand(op); 4617 op->orig_val = op->val; 4618 break; 4619 case OpAccLo: 4620 op->type = OP_REG; 4621 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4622 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4623 fetch_register_operand(op); 4624 op->orig_val = op->val; 4625 break; 4626 case OpAccHi: 4627 if (ctxt->d & ByteOp) { 4628 op->type = OP_NONE; 4629 break; 4630 } 4631 op->type = OP_REG; 4632 op->bytes = ctxt->op_bytes; 4633 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4634 fetch_register_operand(op); 4635 op->orig_val = op->val; 4636 break; 4637 case OpDI: 4638 op->type = OP_MEM; 4639 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4640 op->addr.mem.ea = 4641 register_address(ctxt, VCPU_REGS_RDI); 4642 op->addr.mem.seg = VCPU_SREG_ES; 4643 op->val = 0; 4644 op->count = 1; 4645 break; 4646 case OpDX: 4647 op->type = OP_REG; 4648 op->bytes = 2; 4649 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4650 fetch_register_operand(op); 4651 break; 4652 case OpCL: 4653 op->type = OP_IMM; 4654 op->bytes = 1; 4655 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4656 break; 4657 case OpImmByte: 4658 rc = decode_imm(ctxt, op, 1, true); 4659 break; 4660 case OpOne: 4661 op->type = OP_IMM; 4662 op->bytes = 1; 4663 op->val = 1; 4664 break; 4665 case OpImm: 4666 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4667 break; 4668 case OpImm64: 4669 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4670 break; 4671 case OpMem8: 4672 ctxt->memop.bytes = 1; 4673 if (ctxt->memop.type == OP_REG) { 4674 ctxt->memop.addr.reg = decode_register(ctxt, 4675 ctxt->modrm_rm, true); 4676 fetch_register_operand(&ctxt->memop); 4677 } 4678 goto mem_common; 4679 case OpMem16: 4680 ctxt->memop.bytes = 2; 4681 goto mem_common; 4682 case OpMem32: 4683 ctxt->memop.bytes = 4; 4684 goto mem_common; 4685 case OpImmU16: 4686 rc = decode_imm(ctxt, op, 2, false); 4687 break; 4688 case OpImmU: 4689 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4690 break; 4691 case OpSI: 4692 op->type = OP_MEM; 4693 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4694 op->addr.mem.ea = 4695 register_address(ctxt, VCPU_REGS_RSI); 4696 op->addr.mem.seg = ctxt->seg_override; 4697 op->val = 0; 4698 op->count = 1; 4699 break; 4700 case OpXLat: 4701 op->type = OP_MEM; 4702 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4703 op->addr.mem.ea = 4704 address_mask(ctxt, 4705 reg_read(ctxt, VCPU_REGS_RBX) + 4706 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4707 op->addr.mem.seg = ctxt->seg_override; 4708 op->val = 0; 4709 break; 4710 case OpImmFAddr: 4711 op->type = OP_IMM; 4712 op->addr.mem.ea = ctxt->_eip; 4713 op->bytes = ctxt->op_bytes + 2; 4714 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4715 break; 4716 case OpMemFAddr: 4717 ctxt->memop.bytes = ctxt->op_bytes + 2; 4718 goto mem_common; 4719 case OpES: 4720 op->type = OP_IMM; 4721 op->val = VCPU_SREG_ES; 4722 break; 4723 case OpCS: 4724 op->type = OP_IMM; 4725 op->val = VCPU_SREG_CS; 4726 break; 4727 case OpSS: 4728 op->type = OP_IMM; 4729 op->val = VCPU_SREG_SS; 4730 break; 4731 case OpDS: 4732 op->type = OP_IMM; 4733 op->val = VCPU_SREG_DS; 4734 break; 4735 case OpFS: 4736 op->type = OP_IMM; 4737 op->val = VCPU_SREG_FS; 4738 break; 4739 case OpGS: 4740 op->type = OP_IMM; 4741 op->val = VCPU_SREG_GS; 4742 break; 4743 case OpImplicit: 4744 /* Special instructions do their own operand decoding. */ 4745 default: 4746 op->type = OP_NONE; /* Disable writeback. */ 4747 break; 4748 } 4749 4750 done: 4751 return rc; 4752 } 4753 4754 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) 4755 { 4756 int rc = X86EMUL_CONTINUE; 4757 int mode = ctxt->mode; 4758 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4759 bool op_prefix = false; 4760 bool has_seg_override = false; 4761 struct opcode opcode; 4762 u16 dummy; 4763 struct desc_struct desc; 4764 4765 ctxt->memop.type = OP_NONE; 4766 ctxt->memopp = NULL; 4767 ctxt->_eip = ctxt->eip; 4768 ctxt->fetch.ptr = ctxt->fetch.data; 4769 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4770 ctxt->opcode_len = 1; 4771 ctxt->intercept = x86_intercept_none; 4772 if (insn_len > 0) 4773 memcpy(ctxt->fetch.data, insn, insn_len); 4774 else { 4775 rc = __do_insn_fetch_bytes(ctxt, 1); 4776 if (rc != X86EMUL_CONTINUE) 4777 goto done; 4778 } 4779 4780 switch (mode) { 4781 case X86EMUL_MODE_REAL: 4782 case X86EMUL_MODE_VM86: 4783 def_op_bytes = def_ad_bytes = 2; 4784 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 4785 if (desc.d) 4786 def_op_bytes = def_ad_bytes = 4; 4787 break; 4788 case X86EMUL_MODE_PROT16: 4789 def_op_bytes = def_ad_bytes = 2; 4790 break; 4791 case X86EMUL_MODE_PROT32: 4792 def_op_bytes = def_ad_bytes = 4; 4793 break; 4794 #ifdef CONFIG_X86_64 4795 case X86EMUL_MODE_PROT64: 4796 def_op_bytes = 4; 4797 def_ad_bytes = 8; 4798 break; 4799 #endif 4800 default: 4801 return EMULATION_FAILED; 4802 } 4803 4804 ctxt->op_bytes = def_op_bytes; 4805 ctxt->ad_bytes = def_ad_bytes; 4806 4807 /* Legacy prefixes. */ 4808 for (;;) { 4809 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4810 case 0x66: /* operand-size override */ 4811 op_prefix = true; 4812 /* switch between 2/4 bytes */ 4813 ctxt->op_bytes = def_op_bytes ^ 6; 4814 break; 4815 case 0x67: /* address-size override */ 4816 if (mode == X86EMUL_MODE_PROT64) 4817 /* switch between 4/8 bytes */ 4818 ctxt->ad_bytes = def_ad_bytes ^ 12; 4819 else 4820 /* switch between 2/4 bytes */ 4821 ctxt->ad_bytes = def_ad_bytes ^ 6; 4822 break; 4823 case 0x26: /* ES override */ 4824 has_seg_override = true; 4825 ctxt->seg_override = VCPU_SREG_ES; 4826 break; 4827 case 0x2e: /* CS override */ 4828 has_seg_override = true; 4829 ctxt->seg_override = VCPU_SREG_CS; 4830 break; 4831 case 0x36: /* SS override */ 4832 has_seg_override = true; 4833 ctxt->seg_override = VCPU_SREG_SS; 4834 break; 4835 case 0x3e: /* DS override */ 4836 has_seg_override = true; 4837 ctxt->seg_override = VCPU_SREG_DS; 4838 break; 4839 case 0x64: /* FS override */ 4840 has_seg_override = true; 4841 ctxt->seg_override = VCPU_SREG_FS; 4842 break; 4843 case 0x65: /* GS override */ 4844 has_seg_override = true; 4845 ctxt->seg_override = VCPU_SREG_GS; 4846 break; 4847 case 0x40 ... 0x4f: /* REX */ 4848 if (mode != X86EMUL_MODE_PROT64) 4849 goto done_prefixes; 4850 ctxt->rex_prefix = ctxt->b; 4851 continue; 4852 case 0xf0: /* LOCK */ 4853 ctxt->lock_prefix = 1; 4854 break; 4855 case 0xf2: /* REPNE/REPNZ */ 4856 case 0xf3: /* REP/REPE/REPZ */ 4857 ctxt->rep_prefix = ctxt->b; 4858 break; 4859 default: 4860 goto done_prefixes; 4861 } 4862 4863 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4864 4865 ctxt->rex_prefix = 0; 4866 } 4867 4868 done_prefixes: 4869 4870 /* REX prefix. */ 4871 if (ctxt->rex_prefix & 8) 4872 ctxt->op_bytes = 8; /* REX.W */ 4873 4874 /* Opcode byte(s). */ 4875 opcode = opcode_table[ctxt->b]; 4876 /* Two-byte opcode? */ 4877 if (ctxt->b == 0x0f) { 4878 ctxt->opcode_len = 2; 4879 ctxt->b = insn_fetch(u8, ctxt); 4880 opcode = twobyte_table[ctxt->b]; 4881 4882 /* 0F_38 opcode map */ 4883 if (ctxt->b == 0x38) { 4884 ctxt->opcode_len = 3; 4885 ctxt->b = insn_fetch(u8, ctxt); 4886 opcode = opcode_map_0f_38[ctxt->b]; 4887 } 4888 } 4889 ctxt->d = opcode.flags; 4890 4891 if (ctxt->d & ModRM) 4892 ctxt->modrm = insn_fetch(u8, ctxt); 4893 4894 /* vex-prefix instructions are not implemented */ 4895 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 4896 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 4897 ctxt->d = NotImpl; 4898 } 4899 4900 while (ctxt->d & GroupMask) { 4901 switch (ctxt->d & GroupMask) { 4902 case Group: 4903 goffset = (ctxt->modrm >> 3) & 7; 4904 opcode = opcode.u.group[goffset]; 4905 break; 4906 case GroupDual: 4907 goffset = (ctxt->modrm >> 3) & 7; 4908 if ((ctxt->modrm >> 6) == 3) 4909 opcode = opcode.u.gdual->mod3[goffset]; 4910 else 4911 opcode = opcode.u.gdual->mod012[goffset]; 4912 break; 4913 case RMExt: 4914 goffset = ctxt->modrm & 7; 4915 opcode = opcode.u.group[goffset]; 4916 break; 4917 case Prefix: 4918 if (ctxt->rep_prefix && op_prefix) 4919 return EMULATION_FAILED; 4920 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4921 switch (simd_prefix) { 4922 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4923 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4924 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4925 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4926 } 4927 break; 4928 case Escape: 4929 if (ctxt->modrm > 0xbf) { 4930 size_t size = ARRAY_SIZE(opcode.u.esc->high); 4931 u32 index = array_index_nospec( 4932 ctxt->modrm - 0xc0, size); 4933 4934 opcode = opcode.u.esc->high[index]; 4935 } else { 4936 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4937 } 4938 break; 4939 case InstrDual: 4940 if ((ctxt->modrm >> 6) == 3) 4941 opcode = opcode.u.idual->mod3; 4942 else 4943 opcode = opcode.u.idual->mod012; 4944 break; 4945 case ModeDual: 4946 if (ctxt->mode == X86EMUL_MODE_PROT64) 4947 opcode = opcode.u.mdual->mode64; 4948 else 4949 opcode = opcode.u.mdual->mode32; 4950 break; 4951 default: 4952 return EMULATION_FAILED; 4953 } 4954 4955 ctxt->d &= ~(u64)GroupMask; 4956 ctxt->d |= opcode.flags; 4957 } 4958 4959 ctxt->is_branch = opcode.flags & IsBranch; 4960 4961 /* Unrecognised? */ 4962 if (ctxt->d == 0) 4963 return EMULATION_FAILED; 4964 4965 ctxt->execute = opcode.u.execute; 4966 4967 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) && 4968 likely(!(ctxt->d & EmulateOnUD))) 4969 return EMULATION_FAILED; 4970 4971 if (unlikely(ctxt->d & 4972 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 4973 No16))) { 4974 /* 4975 * These are copied unconditionally here, and checked unconditionally 4976 * in x86_emulate_insn. 4977 */ 4978 ctxt->check_perm = opcode.check_perm; 4979 ctxt->intercept = opcode.intercept; 4980 4981 if (ctxt->d & NotImpl) 4982 return EMULATION_FAILED; 4983 4984 if (mode == X86EMUL_MODE_PROT64) { 4985 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 4986 ctxt->op_bytes = 8; 4987 else if (ctxt->d & NearBranch) 4988 ctxt->op_bytes = 8; 4989 } 4990 4991 if (ctxt->d & Op3264) { 4992 if (mode == X86EMUL_MODE_PROT64) 4993 ctxt->op_bytes = 8; 4994 else 4995 ctxt->op_bytes = 4; 4996 } 4997 4998 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 4999 ctxt->op_bytes = 4; 5000 5001 if (ctxt->d & Sse) 5002 ctxt->op_bytes = 16; 5003 else if (ctxt->d & Mmx) 5004 ctxt->op_bytes = 8; 5005 } 5006 5007 /* ModRM and SIB bytes. */ 5008 if (ctxt->d & ModRM) { 5009 rc = decode_modrm(ctxt, &ctxt->memop); 5010 if (!has_seg_override) { 5011 has_seg_override = true; 5012 ctxt->seg_override = ctxt->modrm_seg; 5013 } 5014 } else if (ctxt->d & MemAbs) 5015 rc = decode_abs(ctxt, &ctxt->memop); 5016 if (rc != X86EMUL_CONTINUE) 5017 goto done; 5018 5019 if (!has_seg_override) 5020 ctxt->seg_override = VCPU_SREG_DS; 5021 5022 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5023 5024 /* 5025 * Decode and fetch the source operand: register, memory 5026 * or immediate. 5027 */ 5028 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5029 if (rc != X86EMUL_CONTINUE) 5030 goto done; 5031 5032 /* 5033 * Decode and fetch the second source operand: register, memory 5034 * or immediate. 5035 */ 5036 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5037 if (rc != X86EMUL_CONTINUE) 5038 goto done; 5039 5040 /* Decode and fetch the destination operand: register or memory. */ 5041 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5042 5043 if (ctxt->rip_relative && likely(ctxt->memopp)) 5044 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5045 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5046 5047 done: 5048 if (rc == X86EMUL_PROPAGATE_FAULT) 5049 ctxt->have_exception = true; 5050 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5051 } 5052 5053 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5054 { 5055 return ctxt->d & PageTable; 5056 } 5057 5058 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5059 { 5060 /* The second termination condition only applies for REPE 5061 * and REPNE. Test if the repeat string operation prefix is 5062 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5063 * corresponding termination condition according to: 5064 * - if REPE/REPZ and ZF = 0 then done 5065 * - if REPNE/REPNZ and ZF = 1 then done 5066 */ 5067 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5068 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5069 && (((ctxt->rep_prefix == REPE_PREFIX) && 5070 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5071 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5072 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5073 return true; 5074 5075 return false; 5076 } 5077 5078 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5079 { 5080 int rc; 5081 5082 kvm_fpu_get(); 5083 rc = asm_safe("fwait"); 5084 kvm_fpu_put(); 5085 5086 if (unlikely(rc != X86EMUL_CONTINUE)) 5087 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5088 5089 return X86EMUL_CONTINUE; 5090 } 5091 5092 static void fetch_possible_mmx_operand(struct operand *op) 5093 { 5094 if (op->type == OP_MM) 5095 kvm_read_mmx_reg(op->addr.mm, &op->mm_val); 5096 } 5097 5098 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop) 5099 { 5100 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5101 5102 if (!(ctxt->d & ByteOp)) 5103 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5104 5105 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5106 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5107 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5108 : "c"(ctxt->src2.val)); 5109 5110 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5111 if (!fop) /* exception is returned in fop variable */ 5112 return emulate_de(ctxt); 5113 return X86EMUL_CONTINUE; 5114 } 5115 5116 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5117 { 5118 /* Clear fields that are set conditionally but read without a guard. */ 5119 ctxt->rip_relative = false; 5120 ctxt->rex_prefix = 0; 5121 ctxt->lock_prefix = 0; 5122 ctxt->rep_prefix = 0; 5123 ctxt->regs_valid = 0; 5124 ctxt->regs_dirty = 0; 5125 5126 ctxt->io_read.pos = 0; 5127 ctxt->io_read.end = 0; 5128 ctxt->mem_read.end = 0; 5129 } 5130 5131 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5132 { 5133 const struct x86_emulate_ops *ops = ctxt->ops; 5134 int rc = X86EMUL_CONTINUE; 5135 int saved_dst_type = ctxt->dst.type; 5136 bool is_guest_mode = ctxt->ops->is_guest_mode(ctxt); 5137 5138 ctxt->mem_read.pos = 0; 5139 5140 /* LOCK prefix is allowed only with some instructions */ 5141 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5142 rc = emulate_ud(ctxt); 5143 goto done; 5144 } 5145 5146 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5147 rc = emulate_ud(ctxt); 5148 goto done; 5149 } 5150 5151 if (unlikely(ctxt->d & 5152 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5153 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5154 (ctxt->d & Undefined)) { 5155 rc = emulate_ud(ctxt); 5156 goto done; 5157 } 5158 5159 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5160 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5161 rc = emulate_ud(ctxt); 5162 goto done; 5163 } 5164 5165 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5166 rc = emulate_nm(ctxt); 5167 goto done; 5168 } 5169 5170 if (ctxt->d & Mmx) { 5171 rc = flush_pending_x87_faults(ctxt); 5172 if (rc != X86EMUL_CONTINUE) 5173 goto done; 5174 /* 5175 * Now that we know the fpu is exception safe, we can fetch 5176 * operands from it. 5177 */ 5178 fetch_possible_mmx_operand(&ctxt->src); 5179 fetch_possible_mmx_operand(&ctxt->src2); 5180 if (!(ctxt->d & Mov)) 5181 fetch_possible_mmx_operand(&ctxt->dst); 5182 } 5183 5184 if (unlikely(is_guest_mode) && ctxt->intercept) { 5185 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5186 X86_ICPT_PRE_EXCEPT); 5187 if (rc != X86EMUL_CONTINUE) 5188 goto done; 5189 } 5190 5191 /* Instruction can only be executed in protected mode */ 5192 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5193 rc = emulate_ud(ctxt); 5194 goto done; 5195 } 5196 5197 /* Privileged instruction can be executed only in CPL=0 */ 5198 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5199 if (ctxt->d & PrivUD) 5200 rc = emulate_ud(ctxt); 5201 else 5202 rc = emulate_gp(ctxt, 0); 5203 goto done; 5204 } 5205 5206 /* Do instruction specific permission checks */ 5207 if (ctxt->d & CheckPerm) { 5208 rc = ctxt->check_perm(ctxt); 5209 if (rc != X86EMUL_CONTINUE) 5210 goto done; 5211 } 5212 5213 if (unlikely(is_guest_mode) && (ctxt->d & Intercept)) { 5214 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5215 X86_ICPT_POST_EXCEPT); 5216 if (rc != X86EMUL_CONTINUE) 5217 goto done; 5218 } 5219 5220 if (ctxt->rep_prefix && (ctxt->d & String)) { 5221 /* All REP prefixes have the same first termination condition */ 5222 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5223 string_registers_quirk(ctxt); 5224 ctxt->eip = ctxt->_eip; 5225 ctxt->eflags &= ~X86_EFLAGS_RF; 5226 goto done; 5227 } 5228 } 5229 } 5230 5231 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5232 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5233 ctxt->src.valptr, ctxt->src.bytes); 5234 if (rc != X86EMUL_CONTINUE) 5235 goto done; 5236 ctxt->src.orig_val64 = ctxt->src.val64; 5237 } 5238 5239 if (ctxt->src2.type == OP_MEM) { 5240 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5241 &ctxt->src2.val, ctxt->src2.bytes); 5242 if (rc != X86EMUL_CONTINUE) 5243 goto done; 5244 } 5245 5246 if ((ctxt->d & DstMask) == ImplicitOps) 5247 goto special_insn; 5248 5249 5250 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5251 /* optimisation - avoid slow emulated read if Mov */ 5252 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5253 &ctxt->dst.val, ctxt->dst.bytes); 5254 if (rc != X86EMUL_CONTINUE) { 5255 if (!(ctxt->d & NoWrite) && 5256 rc == X86EMUL_PROPAGATE_FAULT && 5257 ctxt->exception.vector == PF_VECTOR) 5258 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5259 goto done; 5260 } 5261 } 5262 /* Copy full 64-bit value for CMPXCHG8B. */ 5263 ctxt->dst.orig_val64 = ctxt->dst.val64; 5264 5265 special_insn: 5266 5267 if (unlikely(is_guest_mode) && (ctxt->d & Intercept)) { 5268 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5269 X86_ICPT_POST_MEMACCESS); 5270 if (rc != X86EMUL_CONTINUE) 5271 goto done; 5272 } 5273 5274 if (ctxt->rep_prefix && (ctxt->d & String)) 5275 ctxt->eflags |= X86_EFLAGS_RF; 5276 else 5277 ctxt->eflags &= ~X86_EFLAGS_RF; 5278 5279 if (ctxt->execute) { 5280 if (ctxt->d & Fastop) 5281 rc = fastop(ctxt, ctxt->fop); 5282 else 5283 rc = ctxt->execute(ctxt); 5284 if (rc != X86EMUL_CONTINUE) 5285 goto done; 5286 goto writeback; 5287 } 5288 5289 if (ctxt->opcode_len == 2) 5290 goto twobyte_insn; 5291 else if (ctxt->opcode_len == 3) 5292 goto threebyte_insn; 5293 5294 switch (ctxt->b) { 5295 case 0x70 ... 0x7f: /* jcc (short) */ 5296 if (test_cc(ctxt->b, ctxt->eflags)) 5297 rc = jmp_rel(ctxt, ctxt->src.val); 5298 break; 5299 case 0x8d: /* lea r16/r32, m */ 5300 ctxt->dst.val = ctxt->src.addr.mem.ea; 5301 break; 5302 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5303 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5304 ctxt->dst.type = OP_NONE; 5305 else 5306 rc = em_xchg(ctxt); 5307 break; 5308 case 0x98: /* cbw/cwde/cdqe */ 5309 switch (ctxt->op_bytes) { 5310 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5311 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5312 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5313 } 5314 break; 5315 case 0xcc: /* int3 */ 5316 rc = emulate_int(ctxt, 3); 5317 break; 5318 case 0xcd: /* int n */ 5319 rc = emulate_int(ctxt, ctxt->src.val); 5320 break; 5321 case 0xce: /* into */ 5322 if (ctxt->eflags & X86_EFLAGS_OF) 5323 rc = emulate_int(ctxt, 4); 5324 break; 5325 case 0xe9: /* jmp rel */ 5326 case 0xeb: /* jmp rel short */ 5327 rc = jmp_rel(ctxt, ctxt->src.val); 5328 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5329 break; 5330 case 0xf4: /* hlt */ 5331 ctxt->ops->halt(ctxt); 5332 break; 5333 case 0xf5: /* cmc */ 5334 /* complement carry flag from eflags reg */ 5335 ctxt->eflags ^= X86_EFLAGS_CF; 5336 break; 5337 case 0xf8: /* clc */ 5338 ctxt->eflags &= ~X86_EFLAGS_CF; 5339 break; 5340 case 0xf9: /* stc */ 5341 ctxt->eflags |= X86_EFLAGS_CF; 5342 break; 5343 case 0xfc: /* cld */ 5344 ctxt->eflags &= ~X86_EFLAGS_DF; 5345 break; 5346 case 0xfd: /* std */ 5347 ctxt->eflags |= X86_EFLAGS_DF; 5348 break; 5349 default: 5350 goto cannot_emulate; 5351 } 5352 5353 if (rc != X86EMUL_CONTINUE) 5354 goto done; 5355 5356 writeback: 5357 if (ctxt->d & SrcWrite) { 5358 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5359 rc = writeback(ctxt, &ctxt->src); 5360 if (rc != X86EMUL_CONTINUE) 5361 goto done; 5362 } 5363 if (!(ctxt->d & NoWrite)) { 5364 rc = writeback(ctxt, &ctxt->dst); 5365 if (rc != X86EMUL_CONTINUE) 5366 goto done; 5367 } 5368 5369 /* 5370 * restore dst type in case the decoding will be reused 5371 * (happens for string instruction ) 5372 */ 5373 ctxt->dst.type = saved_dst_type; 5374 5375 if ((ctxt->d & SrcMask) == SrcSI) 5376 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5377 5378 if ((ctxt->d & DstMask) == DstDI) 5379 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5380 5381 if (ctxt->rep_prefix && (ctxt->d & String)) { 5382 unsigned int count; 5383 struct read_cache *r = &ctxt->io_read; 5384 if ((ctxt->d & SrcMask) == SrcSI) 5385 count = ctxt->src.count; 5386 else 5387 count = ctxt->dst.count; 5388 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5389 5390 if (!string_insn_completed(ctxt)) { 5391 /* 5392 * Re-enter guest when pio read ahead buffer is empty 5393 * or, if it is not used, after each 1024 iteration. 5394 */ 5395 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5396 (r->end == 0 || r->end != r->pos)) { 5397 /* 5398 * Reset read cache. Usually happens before 5399 * decode, but since instruction is restarted 5400 * we have to do it here. 5401 */ 5402 ctxt->mem_read.end = 0; 5403 writeback_registers(ctxt); 5404 return EMULATION_RESTART; 5405 } 5406 goto done; /* skip rip writeback */ 5407 } 5408 ctxt->eflags &= ~X86_EFLAGS_RF; 5409 } 5410 5411 ctxt->eip = ctxt->_eip; 5412 if (ctxt->mode != X86EMUL_MODE_PROT64) 5413 ctxt->eip = (u32)ctxt->_eip; 5414 5415 done: 5416 if (rc == X86EMUL_PROPAGATE_FAULT) { 5417 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt)) 5418 return EMULATION_FAILED; 5419 ctxt->have_exception = true; 5420 } 5421 if (rc == X86EMUL_INTERCEPTED) 5422 return EMULATION_INTERCEPTED; 5423 5424 if (rc == X86EMUL_CONTINUE) 5425 writeback_registers(ctxt); 5426 5427 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5428 5429 twobyte_insn: 5430 switch (ctxt->b) { 5431 case 0x09: /* wbinvd */ 5432 (ctxt->ops->wbinvd)(ctxt); 5433 break; 5434 case 0x08: /* invd */ 5435 case 0x0d: /* GrpP (prefetch) */ 5436 case 0x18: /* Grp16 (prefetch/nop) */ 5437 case 0x1f: /* nop */ 5438 break; 5439 case 0x20: /* mov cr, reg */ 5440 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5441 break; 5442 case 0x21: /* mov from dr to reg */ 5443 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5444 break; 5445 case 0x40 ... 0x4f: /* cmov */ 5446 if (test_cc(ctxt->b, ctxt->eflags)) 5447 ctxt->dst.val = ctxt->src.val; 5448 else if (ctxt->op_bytes != 4) 5449 ctxt->dst.type = OP_NONE; /* no writeback */ 5450 break; 5451 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5452 if (test_cc(ctxt->b, ctxt->eflags)) 5453 rc = jmp_rel(ctxt, ctxt->src.val); 5454 break; 5455 case 0x90 ... 0x9f: /* setcc r/m8 */ 5456 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5457 break; 5458 case 0xb6 ... 0xb7: /* movzx */ 5459 ctxt->dst.bytes = ctxt->op_bytes; 5460 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5461 : (u16) ctxt->src.val; 5462 break; 5463 case 0xbe ... 0xbf: /* movsx */ 5464 ctxt->dst.bytes = ctxt->op_bytes; 5465 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5466 (s16) ctxt->src.val; 5467 break; 5468 default: 5469 goto cannot_emulate; 5470 } 5471 5472 threebyte_insn: 5473 5474 if (rc != X86EMUL_CONTINUE) 5475 goto done; 5476 5477 goto writeback; 5478 5479 cannot_emulate: 5480 return EMULATION_FAILED; 5481 } 5482 5483 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5484 { 5485 invalidate_registers(ctxt); 5486 } 5487 5488 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5489 { 5490 writeback_registers(ctxt); 5491 } 5492 5493 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5494 { 5495 if (ctxt->rep_prefix && (ctxt->d & String)) 5496 return false; 5497 5498 if (ctxt->d & TwoMemOp) 5499 return false; 5500 5501 return true; 5502 } 5503