1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <linux/module.h> 26 #include <asm/kvm_emulate.h> 27 #include <linux/stringify.h> 28 29 #include "x86.h" 30 #include "tss.h" 31 32 /* 33 * Operand types 34 */ 35 #define OpNone 0ull 36 #define OpImplicit 1ull /* No generic decode */ 37 #define OpReg 2ull /* Register */ 38 #define OpMem 3ull /* Memory */ 39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 40 #define OpDI 5ull /* ES:DI/EDI/RDI */ 41 #define OpMem64 6ull /* Memory, 64-bit */ 42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 43 #define OpDX 8ull /* DX register */ 44 #define OpCL 9ull /* CL register (for shifts) */ 45 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 46 #define OpOne 11ull /* Implied 1 */ 47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 48 #define OpMem16 13ull /* Memory operand (16-bit). */ 49 #define OpMem32 14ull /* Memory operand (32-bit). */ 50 #define OpImmU 15ull /* Immediate operand, zero extended */ 51 #define OpSI 16ull /* SI/ESI/RSI */ 52 #define OpImmFAddr 17ull /* Immediate far address */ 53 #define OpMemFAddr 18ull /* Far address in memory */ 54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 55 #define OpES 20ull /* ES */ 56 #define OpCS 21ull /* CS */ 57 #define OpSS 22ull /* SS */ 58 #define OpDS 23ull /* DS */ 59 #define OpFS 24ull /* FS */ 60 #define OpGS 25ull /* GS */ 61 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 64 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 65 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 66 67 #define OpBits 5 /* Width of operand field */ 68 #define OpMask ((1ull << OpBits) - 1) 69 70 /* 71 * Opcode effective-address decode tables. 72 * Note that we only emulate instructions that have at least one memory 73 * operand (excluding implicit stack references). We assume that stack 74 * references and instruction fetches will never occur in special memory 75 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 76 * not be handled. 77 */ 78 79 /* Operand sizes: 8-bit operands or specified/overridden size. */ 80 #define ByteOp (1<<0) /* 8-bit operands. */ 81 /* Destination operand type. */ 82 #define DstShift 1 83 #define ImplicitOps (OpImplicit << DstShift) 84 #define DstReg (OpReg << DstShift) 85 #define DstMem (OpMem << DstShift) 86 #define DstAcc (OpAcc << DstShift) 87 #define DstDI (OpDI << DstShift) 88 #define DstMem64 (OpMem64 << DstShift) 89 #define DstImmUByte (OpImmUByte << DstShift) 90 #define DstDX (OpDX << DstShift) 91 #define DstAccLo (OpAccLo << DstShift) 92 #define DstMask (OpMask << DstShift) 93 /* Source operand type. */ 94 #define SrcShift 6 95 #define SrcNone (OpNone << SrcShift) 96 #define SrcReg (OpReg << SrcShift) 97 #define SrcMem (OpMem << SrcShift) 98 #define SrcMem16 (OpMem16 << SrcShift) 99 #define SrcMem32 (OpMem32 << SrcShift) 100 #define SrcImm (OpImm << SrcShift) 101 #define SrcImmByte (OpImmByte << SrcShift) 102 #define SrcOne (OpOne << SrcShift) 103 #define SrcImmUByte (OpImmUByte << SrcShift) 104 #define SrcImmU (OpImmU << SrcShift) 105 #define SrcSI (OpSI << SrcShift) 106 #define SrcXLat (OpXLat << SrcShift) 107 #define SrcImmFAddr (OpImmFAddr << SrcShift) 108 #define SrcMemFAddr (OpMemFAddr << SrcShift) 109 #define SrcAcc (OpAcc << SrcShift) 110 #define SrcImmU16 (OpImmU16 << SrcShift) 111 #define SrcImm64 (OpImm64 << SrcShift) 112 #define SrcDX (OpDX << SrcShift) 113 #define SrcMem8 (OpMem8 << SrcShift) 114 #define SrcAccHi (OpAccHi << SrcShift) 115 #define SrcMask (OpMask << SrcShift) 116 #define BitOp (1<<11) 117 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 118 #define String (1<<13) /* String instruction (rep capable) */ 119 #define Stack (1<<14) /* Stack instruction (push/pop) */ 120 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 121 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 122 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 123 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 124 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 125 #define Escape (5<<15) /* Escape to coprocessor instruction */ 126 #define Sse (1<<18) /* SSE Vector instruction */ 127 /* Generic ModRM decode. */ 128 #define ModRM (1<<19) 129 /* Destination is only written; never read. */ 130 #define Mov (1<<20) 131 /* Misc flags */ 132 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 133 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 134 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 135 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 136 #define Undefined (1<<25) /* No Such Instruction */ 137 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 138 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 139 #define No64 (1<<28) 140 #define PageTable (1 << 29) /* instruction used to write page table */ 141 #define NotImpl (1 << 30) /* instruction is not implemented */ 142 /* Source 2 operand type */ 143 #define Src2Shift (31) 144 #define Src2None (OpNone << Src2Shift) 145 #define Src2Mem (OpMem << Src2Shift) 146 #define Src2CL (OpCL << Src2Shift) 147 #define Src2ImmByte (OpImmByte << Src2Shift) 148 #define Src2One (OpOne << Src2Shift) 149 #define Src2Imm (OpImm << Src2Shift) 150 #define Src2ES (OpES << Src2Shift) 151 #define Src2CS (OpCS << Src2Shift) 152 #define Src2SS (OpSS << Src2Shift) 153 #define Src2DS (OpDS << Src2Shift) 154 #define Src2FS (OpFS << Src2Shift) 155 #define Src2GS (OpGS << Src2Shift) 156 #define Src2Mask (OpMask << Src2Shift) 157 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 158 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 159 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ 160 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ 161 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 162 #define NoWrite ((u64)1 << 45) /* No writeback */ 163 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 164 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 165 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 166 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 167 #define NoBigReal ((u64)1 << 50) /* No big real mode */ 168 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 169 170 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 171 172 #define X2(x...) x, x 173 #define X3(x...) X2(x), x 174 #define X4(x...) X2(x), X2(x) 175 #define X5(x...) X4(x), x 176 #define X6(x...) X4(x), X2(x) 177 #define X7(x...) X4(x), X3(x) 178 #define X8(x...) X4(x), X4(x) 179 #define X16(x...) X8(x), X8(x) 180 181 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 182 #define FASTOP_SIZE 8 183 184 /* 185 * fastop functions have a special calling convention: 186 * 187 * dst: rax (in/out) 188 * src: rdx (in/out) 189 * src2: rcx (in) 190 * flags: rflags (in/out) 191 * ex: rsi (in:fastop pointer, out:zero if exception) 192 * 193 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 194 * different operand sizes can be reached by calculation, rather than a jump 195 * table (which would be bigger than the code). 196 * 197 * fastop functions are declared as taking a never-defined fastop parameter, 198 * so they can't be called from C directly. 199 */ 200 201 struct fastop; 202 203 struct opcode { 204 u64 flags : 56; 205 u64 intercept : 8; 206 union { 207 int (*execute)(struct x86_emulate_ctxt *ctxt); 208 const struct opcode *group; 209 const struct group_dual *gdual; 210 const struct gprefix *gprefix; 211 const struct escape *esc; 212 void (*fastop)(struct fastop *fake); 213 } u; 214 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 215 }; 216 217 struct group_dual { 218 struct opcode mod012[8]; 219 struct opcode mod3[8]; 220 }; 221 222 struct gprefix { 223 struct opcode pfx_no; 224 struct opcode pfx_66; 225 struct opcode pfx_f2; 226 struct opcode pfx_f3; 227 }; 228 229 struct escape { 230 struct opcode op[8]; 231 struct opcode high[64]; 232 }; 233 234 /* EFLAGS bit definitions. */ 235 #define EFLG_ID (1<<21) 236 #define EFLG_VIP (1<<20) 237 #define EFLG_VIF (1<<19) 238 #define EFLG_AC (1<<18) 239 #define EFLG_VM (1<<17) 240 #define EFLG_RF (1<<16) 241 #define EFLG_IOPL (3<<12) 242 #define EFLG_NT (1<<14) 243 #define EFLG_OF (1<<11) 244 #define EFLG_DF (1<<10) 245 #define EFLG_IF (1<<9) 246 #define EFLG_TF (1<<8) 247 #define EFLG_SF (1<<7) 248 #define EFLG_ZF (1<<6) 249 #define EFLG_AF (1<<4) 250 #define EFLG_PF (1<<2) 251 #define EFLG_CF (1<<0) 252 253 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 254 #define EFLG_RESERVED_ONE_MASK 2 255 256 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 257 { 258 if (!(ctxt->regs_valid & (1 << nr))) { 259 ctxt->regs_valid |= 1 << nr; 260 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 261 } 262 return ctxt->_regs[nr]; 263 } 264 265 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 266 { 267 ctxt->regs_valid |= 1 << nr; 268 ctxt->regs_dirty |= 1 << nr; 269 return &ctxt->_regs[nr]; 270 } 271 272 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 273 { 274 reg_read(ctxt, nr); 275 return reg_write(ctxt, nr); 276 } 277 278 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 279 { 280 unsigned reg; 281 282 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 283 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 284 } 285 286 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 287 { 288 ctxt->regs_dirty = 0; 289 ctxt->regs_valid = 0; 290 } 291 292 /* 293 * These EFLAGS bits are restored from saved value during emulation, and 294 * any changes are written back to the saved value after emulation. 295 */ 296 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) 297 298 #ifdef CONFIG_X86_64 299 #define ON64(x) x 300 #else 301 #define ON64(x) 302 #endif 303 304 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 305 306 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" 307 #define FOP_RET "ret \n\t" 308 309 #define FOP_START(op) \ 310 extern void em_##op(struct fastop *fake); \ 311 asm(".pushsection .text, \"ax\" \n\t" \ 312 ".global em_" #op " \n\t" \ 313 FOP_ALIGN \ 314 "em_" #op ": \n\t" 315 316 #define FOP_END \ 317 ".popsection") 318 319 #define FOPNOP() FOP_ALIGN FOP_RET 320 321 #define FOP1E(op, dst) \ 322 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET 323 324 #define FOP1EEX(op, dst) \ 325 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 326 327 #define FASTOP1(op) \ 328 FOP_START(op) \ 329 FOP1E(op##b, al) \ 330 FOP1E(op##w, ax) \ 331 FOP1E(op##l, eax) \ 332 ON64(FOP1E(op##q, rax)) \ 333 FOP_END 334 335 /* 1-operand, using src2 (for MUL/DIV r/m) */ 336 #define FASTOP1SRC2(op, name) \ 337 FOP_START(name) \ 338 FOP1E(op, cl) \ 339 FOP1E(op, cx) \ 340 FOP1E(op, ecx) \ 341 ON64(FOP1E(op, rcx)) \ 342 FOP_END 343 344 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 345 #define FASTOP1SRC2EX(op, name) \ 346 FOP_START(name) \ 347 FOP1EEX(op, cl) \ 348 FOP1EEX(op, cx) \ 349 FOP1EEX(op, ecx) \ 350 ON64(FOP1EEX(op, rcx)) \ 351 FOP_END 352 353 #define FOP2E(op, dst, src) \ 354 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET 355 356 #define FASTOP2(op) \ 357 FOP_START(op) \ 358 FOP2E(op##b, al, dl) \ 359 FOP2E(op##w, ax, dx) \ 360 FOP2E(op##l, eax, edx) \ 361 ON64(FOP2E(op##q, rax, rdx)) \ 362 FOP_END 363 364 /* 2 operand, word only */ 365 #define FASTOP2W(op) \ 366 FOP_START(op) \ 367 FOPNOP() \ 368 FOP2E(op##w, ax, dx) \ 369 FOP2E(op##l, eax, edx) \ 370 ON64(FOP2E(op##q, rax, rdx)) \ 371 FOP_END 372 373 /* 2 operand, src is CL */ 374 #define FASTOP2CL(op) \ 375 FOP_START(op) \ 376 FOP2E(op##b, al, cl) \ 377 FOP2E(op##w, ax, cl) \ 378 FOP2E(op##l, eax, cl) \ 379 ON64(FOP2E(op##q, rax, cl)) \ 380 FOP_END 381 382 #define FOP3E(op, dst, src, src2) \ 383 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 384 385 /* 3-operand, word-only, src2=cl */ 386 #define FASTOP3WCL(op) \ 387 FOP_START(op) \ 388 FOPNOP() \ 389 FOP3E(op##w, ax, dx, cl) \ 390 FOP3E(op##l, eax, edx, cl) \ 391 ON64(FOP3E(op##q, rax, rdx, cl)) \ 392 FOP_END 393 394 /* Special case for SETcc - 1 instruction per cc */ 395 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" 396 397 asm(".global kvm_fastop_exception \n" 398 "kvm_fastop_exception: xor %esi, %esi; ret"); 399 400 FOP_START(setcc) 401 FOP_SETCC(seto) 402 FOP_SETCC(setno) 403 FOP_SETCC(setc) 404 FOP_SETCC(setnc) 405 FOP_SETCC(setz) 406 FOP_SETCC(setnz) 407 FOP_SETCC(setbe) 408 FOP_SETCC(setnbe) 409 FOP_SETCC(sets) 410 FOP_SETCC(setns) 411 FOP_SETCC(setp) 412 FOP_SETCC(setnp) 413 FOP_SETCC(setl) 414 FOP_SETCC(setnl) 415 FOP_SETCC(setle) 416 FOP_SETCC(setnle) 417 FOP_END; 418 419 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 420 FOP_END; 421 422 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 423 enum x86_intercept intercept, 424 enum x86_intercept_stage stage) 425 { 426 struct x86_instruction_info info = { 427 .intercept = intercept, 428 .rep_prefix = ctxt->rep_prefix, 429 .modrm_mod = ctxt->modrm_mod, 430 .modrm_reg = ctxt->modrm_reg, 431 .modrm_rm = ctxt->modrm_rm, 432 .src_val = ctxt->src.val64, 433 .dst_val = ctxt->dst.val64, 434 .src_bytes = ctxt->src.bytes, 435 .dst_bytes = ctxt->dst.bytes, 436 .ad_bytes = ctxt->ad_bytes, 437 .next_rip = ctxt->eip, 438 }; 439 440 return ctxt->ops->intercept(ctxt, &info, stage); 441 } 442 443 static void assign_masked(ulong *dest, ulong src, ulong mask) 444 { 445 *dest = (*dest & ~mask) | (src & mask); 446 } 447 448 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 449 { 450 return (1UL << (ctxt->ad_bytes << 3)) - 1; 451 } 452 453 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 454 { 455 u16 sel; 456 struct desc_struct ss; 457 458 if (ctxt->mode == X86EMUL_MODE_PROT64) 459 return ~0UL; 460 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 461 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 462 } 463 464 static int stack_size(struct x86_emulate_ctxt *ctxt) 465 { 466 return (__fls(stack_mask(ctxt)) + 1) >> 3; 467 } 468 469 /* Access/update address held in a register, based on addressing mode. */ 470 static inline unsigned long 471 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 472 { 473 if (ctxt->ad_bytes == sizeof(unsigned long)) 474 return reg; 475 else 476 return reg & ad_mask(ctxt); 477 } 478 479 static inline unsigned long 480 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) 481 { 482 return address_mask(ctxt, reg); 483 } 484 485 static void masked_increment(ulong *reg, ulong mask, int inc) 486 { 487 assign_masked(reg, *reg + inc, mask); 488 } 489 490 static inline void 491 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) 492 { 493 ulong mask; 494 495 if (ctxt->ad_bytes == sizeof(unsigned long)) 496 mask = ~0UL; 497 else 498 mask = ad_mask(ctxt); 499 masked_increment(reg, mask, inc); 500 } 501 502 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 503 { 504 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 505 } 506 507 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 508 { 509 register_address_increment(ctxt, &ctxt->_eip, rel); 510 } 511 512 static u32 desc_limit_scaled(struct desc_struct *desc) 513 { 514 u32 limit = get_desc_limit(desc); 515 516 return desc->g ? (limit << 12) | 0xfff : limit; 517 } 518 519 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 520 { 521 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 522 return 0; 523 524 return ctxt->ops->get_cached_segment_base(ctxt, seg); 525 } 526 527 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 528 u32 error, bool valid) 529 { 530 WARN_ON(vec > 0x1f); 531 ctxt->exception.vector = vec; 532 ctxt->exception.error_code = error; 533 ctxt->exception.error_code_valid = valid; 534 return X86EMUL_PROPAGATE_FAULT; 535 } 536 537 static int emulate_db(struct x86_emulate_ctxt *ctxt) 538 { 539 return emulate_exception(ctxt, DB_VECTOR, 0, false); 540 } 541 542 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 543 { 544 return emulate_exception(ctxt, GP_VECTOR, err, true); 545 } 546 547 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 548 { 549 return emulate_exception(ctxt, SS_VECTOR, err, true); 550 } 551 552 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 553 { 554 return emulate_exception(ctxt, UD_VECTOR, 0, false); 555 } 556 557 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 558 { 559 return emulate_exception(ctxt, TS_VECTOR, err, true); 560 } 561 562 static int emulate_de(struct x86_emulate_ctxt *ctxt) 563 { 564 return emulate_exception(ctxt, DE_VECTOR, 0, false); 565 } 566 567 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 568 { 569 return emulate_exception(ctxt, NM_VECTOR, 0, false); 570 } 571 572 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 573 { 574 u16 selector; 575 struct desc_struct desc; 576 577 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 578 return selector; 579 } 580 581 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 582 unsigned seg) 583 { 584 u16 dummy; 585 u32 base3; 586 struct desc_struct desc; 587 588 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 589 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 590 } 591 592 /* 593 * x86 defines three classes of vector instructions: explicitly 594 * aligned, explicitly unaligned, and the rest, which change behaviour 595 * depending on whether they're AVX encoded or not. 596 * 597 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 598 * subject to the same check. 599 */ 600 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) 601 { 602 if (likely(size < 16)) 603 return false; 604 605 if (ctxt->d & Aligned) 606 return true; 607 else if (ctxt->d & Unaligned) 608 return false; 609 else if (ctxt->d & Avx) 610 return false; 611 else 612 return true; 613 } 614 615 static int __linearize(struct x86_emulate_ctxt *ctxt, 616 struct segmented_address addr, 617 unsigned size, bool write, bool fetch, 618 ulong *linear) 619 { 620 struct desc_struct desc; 621 bool usable; 622 ulong la; 623 u32 lim; 624 u16 sel; 625 unsigned cpl; 626 627 la = seg_base(ctxt, addr.seg) + addr.ea; 628 switch (ctxt->mode) { 629 case X86EMUL_MODE_PROT64: 630 if (((signed long)la << 16) >> 16 != la) 631 return emulate_gp(ctxt, 0); 632 break; 633 default: 634 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 635 addr.seg); 636 if (!usable) 637 goto bad; 638 /* code segment in protected mode or read-only data segment */ 639 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 640 || !(desc.type & 2)) && write) 641 goto bad; 642 /* unreadable code segment */ 643 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 644 goto bad; 645 lim = desc_limit_scaled(&desc); 646 if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch && 647 (ctxt->d & NoBigReal)) { 648 /* la is between zero and 0xffff */ 649 if (la > 0xffff || (u32)(la + size - 1) > 0xffff) 650 goto bad; 651 } else if ((desc.type & 8) || !(desc.type & 4)) { 652 /* expand-up segment */ 653 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 654 goto bad; 655 } else { 656 /* expand-down segment */ 657 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) 658 goto bad; 659 lim = desc.d ? 0xffffffff : 0xffff; 660 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 661 goto bad; 662 } 663 cpl = ctxt->ops->cpl(ctxt); 664 if (!(desc.type & 8)) { 665 /* data segment */ 666 if (cpl > desc.dpl) 667 goto bad; 668 } else if ((desc.type & 8) && !(desc.type & 4)) { 669 /* nonconforming code segment */ 670 if (cpl != desc.dpl) 671 goto bad; 672 } else if ((desc.type & 8) && (desc.type & 4)) { 673 /* conforming code segment */ 674 if (cpl < desc.dpl) 675 goto bad; 676 } 677 break; 678 } 679 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) 680 la &= (u32)-1; 681 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) 682 return emulate_gp(ctxt, 0); 683 *linear = la; 684 return X86EMUL_CONTINUE; 685 bad: 686 if (addr.seg == VCPU_SREG_SS) 687 return emulate_ss(ctxt, sel); 688 else 689 return emulate_gp(ctxt, sel); 690 } 691 692 static int linearize(struct x86_emulate_ctxt *ctxt, 693 struct segmented_address addr, 694 unsigned size, bool write, 695 ulong *linear) 696 { 697 return __linearize(ctxt, addr, size, write, false, linear); 698 } 699 700 701 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 702 struct segmented_address addr, 703 void *data, 704 unsigned size) 705 { 706 int rc; 707 ulong linear; 708 709 rc = linearize(ctxt, addr, size, false, &linear); 710 if (rc != X86EMUL_CONTINUE) 711 return rc; 712 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 713 } 714 715 /* 716 * Prefetch the remaining bytes of the instruction without crossing page 717 * boundary if they are not in fetch_cache yet. 718 */ 719 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 720 { 721 int rc; 722 unsigned size; 723 unsigned long linear; 724 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 725 struct segmented_address addr = { .seg = VCPU_SREG_CS, 726 .ea = ctxt->eip + cur_size }; 727 728 size = 15UL ^ cur_size; 729 rc = __linearize(ctxt, addr, size, false, true, &linear); 730 if (unlikely(rc != X86EMUL_CONTINUE)) 731 return rc; 732 733 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 734 735 /* 736 * One instruction can only straddle two pages, 737 * and one has been loaded at the beginning of 738 * x86_decode_insn. So, if not enough bytes 739 * still, we must have hit the 15-byte boundary. 740 */ 741 if (unlikely(size < op_size)) 742 return X86EMUL_UNHANDLEABLE; 743 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 744 size, &ctxt->exception); 745 if (unlikely(rc != X86EMUL_CONTINUE)) 746 return rc; 747 ctxt->fetch.end += size; 748 return X86EMUL_CONTINUE; 749 } 750 751 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 752 unsigned size) 753 { 754 if (unlikely(ctxt->fetch.end - ctxt->fetch.ptr < size)) 755 return __do_insn_fetch_bytes(ctxt, size); 756 else 757 return X86EMUL_CONTINUE; 758 } 759 760 /* Fetch next part of the instruction being emulated. */ 761 #define insn_fetch(_type, _ctxt) \ 762 ({ _type _x; \ 763 \ 764 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 765 if (rc != X86EMUL_CONTINUE) \ 766 goto done; \ 767 ctxt->_eip += sizeof(_type); \ 768 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \ 769 ctxt->fetch.ptr += sizeof(_type); \ 770 _x; \ 771 }) 772 773 #define insn_fetch_arr(_arr, _size, _ctxt) \ 774 ({ \ 775 rc = do_insn_fetch_bytes(_ctxt, _size); \ 776 if (rc != X86EMUL_CONTINUE) \ 777 goto done; \ 778 ctxt->_eip += (_size); \ 779 memcpy(_arr, ctxt->fetch.ptr, _size); \ 780 ctxt->fetch.ptr += (_size); \ 781 }) 782 783 /* 784 * Given the 'reg' portion of a ModRM byte, and a register block, return a 785 * pointer into the block that addresses the relevant register. 786 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 787 */ 788 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 789 int byteop) 790 { 791 void *p; 792 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 793 794 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 795 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 796 else 797 p = reg_rmw(ctxt, modrm_reg); 798 return p; 799 } 800 801 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 802 struct segmented_address addr, 803 u16 *size, unsigned long *address, int op_bytes) 804 { 805 int rc; 806 807 if (op_bytes == 2) 808 op_bytes = 3; 809 *address = 0; 810 rc = segmented_read_std(ctxt, addr, size, 2); 811 if (rc != X86EMUL_CONTINUE) 812 return rc; 813 addr.ea += 2; 814 rc = segmented_read_std(ctxt, addr, address, op_bytes); 815 return rc; 816 } 817 818 FASTOP2(add); 819 FASTOP2(or); 820 FASTOP2(adc); 821 FASTOP2(sbb); 822 FASTOP2(and); 823 FASTOP2(sub); 824 FASTOP2(xor); 825 FASTOP2(cmp); 826 FASTOP2(test); 827 828 FASTOP1SRC2(mul, mul_ex); 829 FASTOP1SRC2(imul, imul_ex); 830 FASTOP1SRC2EX(div, div_ex); 831 FASTOP1SRC2EX(idiv, idiv_ex); 832 833 FASTOP3WCL(shld); 834 FASTOP3WCL(shrd); 835 836 FASTOP2W(imul); 837 838 FASTOP1(not); 839 FASTOP1(neg); 840 FASTOP1(inc); 841 FASTOP1(dec); 842 843 FASTOP2CL(rol); 844 FASTOP2CL(ror); 845 FASTOP2CL(rcl); 846 FASTOP2CL(rcr); 847 FASTOP2CL(shl); 848 FASTOP2CL(shr); 849 FASTOP2CL(sar); 850 851 FASTOP2W(bsf); 852 FASTOP2W(bsr); 853 FASTOP2W(bt); 854 FASTOP2W(bts); 855 FASTOP2W(btr); 856 FASTOP2W(btc); 857 858 FASTOP2(xadd); 859 860 static u8 test_cc(unsigned int condition, unsigned long flags) 861 { 862 u8 rc; 863 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 864 865 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 866 asm("push %[flags]; popf; call *%[fastop]" 867 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); 868 return rc; 869 } 870 871 static void fetch_register_operand(struct operand *op) 872 { 873 switch (op->bytes) { 874 case 1: 875 op->val = *(u8 *)op->addr.reg; 876 break; 877 case 2: 878 op->val = *(u16 *)op->addr.reg; 879 break; 880 case 4: 881 op->val = *(u32 *)op->addr.reg; 882 break; 883 case 8: 884 op->val = *(u64 *)op->addr.reg; 885 break; 886 } 887 } 888 889 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 890 { 891 ctxt->ops->get_fpu(ctxt); 892 switch (reg) { 893 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 894 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 895 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 896 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 897 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 898 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 899 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 900 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 901 #ifdef CONFIG_X86_64 902 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 903 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 904 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 905 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 906 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 907 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 908 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 909 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 910 #endif 911 default: BUG(); 912 } 913 ctxt->ops->put_fpu(ctxt); 914 } 915 916 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 917 int reg) 918 { 919 ctxt->ops->get_fpu(ctxt); 920 switch (reg) { 921 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 922 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 923 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 924 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 925 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 926 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 927 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 928 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 929 #ifdef CONFIG_X86_64 930 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 931 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 932 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 933 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 934 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 935 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 936 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 937 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 938 #endif 939 default: BUG(); 940 } 941 ctxt->ops->put_fpu(ctxt); 942 } 943 944 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 945 { 946 ctxt->ops->get_fpu(ctxt); 947 switch (reg) { 948 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 949 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 950 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 951 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 952 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 953 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 954 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 955 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 956 default: BUG(); 957 } 958 ctxt->ops->put_fpu(ctxt); 959 } 960 961 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 962 { 963 ctxt->ops->get_fpu(ctxt); 964 switch (reg) { 965 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 966 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 967 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 968 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 969 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 970 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 971 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 972 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 973 default: BUG(); 974 } 975 ctxt->ops->put_fpu(ctxt); 976 } 977 978 static int em_fninit(struct x86_emulate_ctxt *ctxt) 979 { 980 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 981 return emulate_nm(ctxt); 982 983 ctxt->ops->get_fpu(ctxt); 984 asm volatile("fninit"); 985 ctxt->ops->put_fpu(ctxt); 986 return X86EMUL_CONTINUE; 987 } 988 989 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 990 { 991 u16 fcw; 992 993 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 994 return emulate_nm(ctxt); 995 996 ctxt->ops->get_fpu(ctxt); 997 asm volatile("fnstcw %0": "+m"(fcw)); 998 ctxt->ops->put_fpu(ctxt); 999 1000 /* force 2 byte destination */ 1001 ctxt->dst.bytes = 2; 1002 ctxt->dst.val = fcw; 1003 1004 return X86EMUL_CONTINUE; 1005 } 1006 1007 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1008 { 1009 u16 fsw; 1010 1011 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1012 return emulate_nm(ctxt); 1013 1014 ctxt->ops->get_fpu(ctxt); 1015 asm volatile("fnstsw %0": "+m"(fsw)); 1016 ctxt->ops->put_fpu(ctxt); 1017 1018 /* force 2 byte destination */ 1019 ctxt->dst.bytes = 2; 1020 ctxt->dst.val = fsw; 1021 1022 return X86EMUL_CONTINUE; 1023 } 1024 1025 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1026 struct operand *op) 1027 { 1028 unsigned reg = ctxt->modrm_reg; 1029 1030 if (!(ctxt->d & ModRM)) 1031 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1032 1033 if (ctxt->d & Sse) { 1034 op->type = OP_XMM; 1035 op->bytes = 16; 1036 op->addr.xmm = reg; 1037 read_sse_reg(ctxt, &op->vec_val, reg); 1038 return; 1039 } 1040 if (ctxt->d & Mmx) { 1041 reg &= 7; 1042 op->type = OP_MM; 1043 op->bytes = 8; 1044 op->addr.mm = reg; 1045 return; 1046 } 1047 1048 op->type = OP_REG; 1049 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1050 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1051 1052 fetch_register_operand(op); 1053 op->orig_val = op->val; 1054 } 1055 1056 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1057 { 1058 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1059 ctxt->modrm_seg = VCPU_SREG_SS; 1060 } 1061 1062 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1063 struct operand *op) 1064 { 1065 u8 sib; 1066 int index_reg, base_reg, scale; 1067 int rc = X86EMUL_CONTINUE; 1068 ulong modrm_ea = 0; 1069 1070 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1071 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1072 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1073 1074 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1075 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1076 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1077 ctxt->modrm_seg = VCPU_SREG_DS; 1078 1079 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1080 op->type = OP_REG; 1081 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1082 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1083 ctxt->d & ByteOp); 1084 if (ctxt->d & Sse) { 1085 op->type = OP_XMM; 1086 op->bytes = 16; 1087 op->addr.xmm = ctxt->modrm_rm; 1088 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1089 return rc; 1090 } 1091 if (ctxt->d & Mmx) { 1092 op->type = OP_MM; 1093 op->bytes = 8; 1094 op->addr.mm = ctxt->modrm_rm & 7; 1095 return rc; 1096 } 1097 fetch_register_operand(op); 1098 return rc; 1099 } 1100 1101 op->type = OP_MEM; 1102 1103 if (ctxt->ad_bytes == 2) { 1104 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1105 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1106 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1107 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1108 1109 /* 16-bit ModR/M decode. */ 1110 switch (ctxt->modrm_mod) { 1111 case 0: 1112 if (ctxt->modrm_rm == 6) 1113 modrm_ea += insn_fetch(u16, ctxt); 1114 break; 1115 case 1: 1116 modrm_ea += insn_fetch(s8, ctxt); 1117 break; 1118 case 2: 1119 modrm_ea += insn_fetch(u16, ctxt); 1120 break; 1121 } 1122 switch (ctxt->modrm_rm) { 1123 case 0: 1124 modrm_ea += bx + si; 1125 break; 1126 case 1: 1127 modrm_ea += bx + di; 1128 break; 1129 case 2: 1130 modrm_ea += bp + si; 1131 break; 1132 case 3: 1133 modrm_ea += bp + di; 1134 break; 1135 case 4: 1136 modrm_ea += si; 1137 break; 1138 case 5: 1139 modrm_ea += di; 1140 break; 1141 case 6: 1142 if (ctxt->modrm_mod != 0) 1143 modrm_ea += bp; 1144 break; 1145 case 7: 1146 modrm_ea += bx; 1147 break; 1148 } 1149 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1150 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1151 ctxt->modrm_seg = VCPU_SREG_SS; 1152 modrm_ea = (u16)modrm_ea; 1153 } else { 1154 /* 32/64-bit ModR/M decode. */ 1155 if ((ctxt->modrm_rm & 7) == 4) { 1156 sib = insn_fetch(u8, ctxt); 1157 index_reg |= (sib >> 3) & 7; 1158 base_reg |= sib & 7; 1159 scale = sib >> 6; 1160 1161 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1162 modrm_ea += insn_fetch(s32, ctxt); 1163 else { 1164 modrm_ea += reg_read(ctxt, base_reg); 1165 adjust_modrm_seg(ctxt, base_reg); 1166 } 1167 if (index_reg != 4) 1168 modrm_ea += reg_read(ctxt, index_reg) << scale; 1169 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1170 if (ctxt->mode == X86EMUL_MODE_PROT64) 1171 ctxt->rip_relative = 1; 1172 } else { 1173 base_reg = ctxt->modrm_rm; 1174 modrm_ea += reg_read(ctxt, base_reg); 1175 adjust_modrm_seg(ctxt, base_reg); 1176 } 1177 switch (ctxt->modrm_mod) { 1178 case 0: 1179 if (ctxt->modrm_rm == 5) 1180 modrm_ea += insn_fetch(s32, ctxt); 1181 break; 1182 case 1: 1183 modrm_ea += insn_fetch(s8, ctxt); 1184 break; 1185 case 2: 1186 modrm_ea += insn_fetch(s32, ctxt); 1187 break; 1188 } 1189 } 1190 op->addr.mem.ea = modrm_ea; 1191 if (ctxt->ad_bytes != 8) 1192 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1193 1194 done: 1195 return rc; 1196 } 1197 1198 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1199 struct operand *op) 1200 { 1201 int rc = X86EMUL_CONTINUE; 1202 1203 op->type = OP_MEM; 1204 switch (ctxt->ad_bytes) { 1205 case 2: 1206 op->addr.mem.ea = insn_fetch(u16, ctxt); 1207 break; 1208 case 4: 1209 op->addr.mem.ea = insn_fetch(u32, ctxt); 1210 break; 1211 case 8: 1212 op->addr.mem.ea = insn_fetch(u64, ctxt); 1213 break; 1214 } 1215 done: 1216 return rc; 1217 } 1218 1219 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1220 { 1221 long sv = 0, mask; 1222 1223 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1224 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1225 1226 if (ctxt->src.bytes == 2) 1227 sv = (s16)ctxt->src.val & (s16)mask; 1228 else if (ctxt->src.bytes == 4) 1229 sv = (s32)ctxt->src.val & (s32)mask; 1230 else 1231 sv = (s64)ctxt->src.val & (s64)mask; 1232 1233 ctxt->dst.addr.mem.ea += (sv >> 3); 1234 } 1235 1236 /* only subword offset */ 1237 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1238 } 1239 1240 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1241 unsigned long addr, void *dest, unsigned size) 1242 { 1243 int rc; 1244 struct read_cache *mc = &ctxt->mem_read; 1245 1246 if (mc->pos < mc->end) 1247 goto read_cached; 1248 1249 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1250 1251 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1252 &ctxt->exception); 1253 if (rc != X86EMUL_CONTINUE) 1254 return rc; 1255 1256 mc->end += size; 1257 1258 read_cached: 1259 memcpy(dest, mc->data + mc->pos, size); 1260 mc->pos += size; 1261 return X86EMUL_CONTINUE; 1262 } 1263 1264 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1265 struct segmented_address addr, 1266 void *data, 1267 unsigned size) 1268 { 1269 int rc; 1270 ulong linear; 1271 1272 rc = linearize(ctxt, addr, size, false, &linear); 1273 if (rc != X86EMUL_CONTINUE) 1274 return rc; 1275 return read_emulated(ctxt, linear, data, size); 1276 } 1277 1278 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1279 struct segmented_address addr, 1280 const void *data, 1281 unsigned size) 1282 { 1283 int rc; 1284 ulong linear; 1285 1286 rc = linearize(ctxt, addr, size, true, &linear); 1287 if (rc != X86EMUL_CONTINUE) 1288 return rc; 1289 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1290 &ctxt->exception); 1291 } 1292 1293 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1294 struct segmented_address addr, 1295 const void *orig_data, const void *data, 1296 unsigned size) 1297 { 1298 int rc; 1299 ulong linear; 1300 1301 rc = linearize(ctxt, addr, size, true, &linear); 1302 if (rc != X86EMUL_CONTINUE) 1303 return rc; 1304 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1305 size, &ctxt->exception); 1306 } 1307 1308 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1309 unsigned int size, unsigned short port, 1310 void *dest) 1311 { 1312 struct read_cache *rc = &ctxt->io_read; 1313 1314 if (rc->pos == rc->end) { /* refill pio read ahead */ 1315 unsigned int in_page, n; 1316 unsigned int count = ctxt->rep_prefix ? 1317 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1318 in_page = (ctxt->eflags & EFLG_DF) ? 1319 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1320 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1321 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1322 if (n == 0) 1323 n = 1; 1324 rc->pos = rc->end = 0; 1325 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1326 return 0; 1327 rc->end = n * size; 1328 } 1329 1330 if (ctxt->rep_prefix && (ctxt->d & String) && 1331 !(ctxt->eflags & EFLG_DF)) { 1332 ctxt->dst.data = rc->data + rc->pos; 1333 ctxt->dst.type = OP_MEM_STR; 1334 ctxt->dst.count = (rc->end - rc->pos) / size; 1335 rc->pos = rc->end; 1336 } else { 1337 memcpy(dest, rc->data + rc->pos, size); 1338 rc->pos += size; 1339 } 1340 return 1; 1341 } 1342 1343 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1344 u16 index, struct desc_struct *desc) 1345 { 1346 struct desc_ptr dt; 1347 ulong addr; 1348 1349 ctxt->ops->get_idt(ctxt, &dt); 1350 1351 if (dt.size < index * 8 + 7) 1352 return emulate_gp(ctxt, index << 3 | 0x2); 1353 1354 addr = dt.address + index * 8; 1355 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1356 &ctxt->exception); 1357 } 1358 1359 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1360 u16 selector, struct desc_ptr *dt) 1361 { 1362 const struct x86_emulate_ops *ops = ctxt->ops; 1363 u32 base3 = 0; 1364 1365 if (selector & 1 << 2) { 1366 struct desc_struct desc; 1367 u16 sel; 1368 1369 memset (dt, 0, sizeof *dt); 1370 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1371 VCPU_SREG_LDTR)) 1372 return; 1373 1374 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1375 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1376 } else 1377 ops->get_gdt(ctxt, dt); 1378 } 1379 1380 /* allowed just for 8 bytes segments */ 1381 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1382 u16 selector, struct desc_struct *desc, 1383 ulong *desc_addr_p) 1384 { 1385 struct desc_ptr dt; 1386 u16 index = selector >> 3; 1387 ulong addr; 1388 1389 get_descriptor_table_ptr(ctxt, selector, &dt); 1390 1391 if (dt.size < index * 8 + 7) 1392 return emulate_gp(ctxt, selector & 0xfffc); 1393 1394 *desc_addr_p = addr = dt.address + index * 8; 1395 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1396 &ctxt->exception); 1397 } 1398 1399 /* allowed just for 8 bytes segments */ 1400 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1401 u16 selector, struct desc_struct *desc) 1402 { 1403 struct desc_ptr dt; 1404 u16 index = selector >> 3; 1405 ulong addr; 1406 1407 get_descriptor_table_ptr(ctxt, selector, &dt); 1408 1409 if (dt.size < index * 8 + 7) 1410 return emulate_gp(ctxt, selector & 0xfffc); 1411 1412 addr = dt.address + index * 8; 1413 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1414 &ctxt->exception); 1415 } 1416 1417 /* Does not support long mode */ 1418 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1419 u16 selector, int seg, u8 cpl, bool in_task_switch) 1420 { 1421 struct desc_struct seg_desc, old_desc; 1422 u8 dpl, rpl; 1423 unsigned err_vec = GP_VECTOR; 1424 u32 err_code = 0; 1425 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1426 ulong desc_addr; 1427 int ret; 1428 u16 dummy; 1429 u32 base3 = 0; 1430 1431 memset(&seg_desc, 0, sizeof seg_desc); 1432 1433 if (ctxt->mode == X86EMUL_MODE_REAL) { 1434 /* set real mode segment descriptor (keep limit etc. for 1435 * unreal mode) */ 1436 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1437 set_desc_base(&seg_desc, selector << 4); 1438 goto load; 1439 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1440 /* VM86 needs a clean new segment descriptor */ 1441 set_desc_base(&seg_desc, selector << 4); 1442 set_desc_limit(&seg_desc, 0xffff); 1443 seg_desc.type = 3; 1444 seg_desc.p = 1; 1445 seg_desc.s = 1; 1446 seg_desc.dpl = 3; 1447 goto load; 1448 } 1449 1450 rpl = selector & 3; 1451 1452 /* NULL selector is not valid for TR, CS and SS (except for long mode) */ 1453 if ((seg == VCPU_SREG_CS 1454 || (seg == VCPU_SREG_SS 1455 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) 1456 || seg == VCPU_SREG_TR) 1457 && null_selector) 1458 goto exception; 1459 1460 /* TR should be in GDT only */ 1461 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1462 goto exception; 1463 1464 if (null_selector) /* for NULL selector skip all following checks */ 1465 goto load; 1466 1467 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1468 if (ret != X86EMUL_CONTINUE) 1469 return ret; 1470 1471 err_code = selector & 0xfffc; 1472 err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR; 1473 1474 /* can't load system descriptor into segment selector */ 1475 if (seg <= VCPU_SREG_GS && !seg_desc.s) 1476 goto exception; 1477 1478 if (!seg_desc.p) { 1479 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1480 goto exception; 1481 } 1482 1483 dpl = seg_desc.dpl; 1484 1485 switch (seg) { 1486 case VCPU_SREG_SS: 1487 /* 1488 * segment is not a writable data segment or segment 1489 * selector's RPL != CPL or segment selector's RPL != CPL 1490 */ 1491 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1492 goto exception; 1493 break; 1494 case VCPU_SREG_CS: 1495 if (!(seg_desc.type & 8)) 1496 goto exception; 1497 1498 if (seg_desc.type & 4) { 1499 /* conforming */ 1500 if (dpl > cpl) 1501 goto exception; 1502 } else { 1503 /* nonconforming */ 1504 if (rpl > cpl || dpl != cpl) 1505 goto exception; 1506 } 1507 /* in long-mode d/b must be clear if l is set */ 1508 if (seg_desc.d && seg_desc.l) { 1509 u64 efer = 0; 1510 1511 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1512 if (efer & EFER_LMA) 1513 goto exception; 1514 } 1515 1516 /* CS(RPL) <- CPL */ 1517 selector = (selector & 0xfffc) | cpl; 1518 break; 1519 case VCPU_SREG_TR: 1520 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1521 goto exception; 1522 old_desc = seg_desc; 1523 seg_desc.type |= 2; /* busy */ 1524 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1525 sizeof(seg_desc), &ctxt->exception); 1526 if (ret != X86EMUL_CONTINUE) 1527 return ret; 1528 break; 1529 case VCPU_SREG_LDTR: 1530 if (seg_desc.s || seg_desc.type != 2) 1531 goto exception; 1532 break; 1533 default: /* DS, ES, FS, or GS */ 1534 /* 1535 * segment is not a data or readable code segment or 1536 * ((segment is a data or nonconforming code segment) 1537 * and (both RPL and CPL > DPL)) 1538 */ 1539 if ((seg_desc.type & 0xa) == 0x8 || 1540 (((seg_desc.type & 0xc) != 0xc) && 1541 (rpl > dpl && cpl > dpl))) 1542 goto exception; 1543 break; 1544 } 1545 1546 if (seg_desc.s) { 1547 /* mark segment as accessed */ 1548 seg_desc.type |= 1; 1549 ret = write_segment_descriptor(ctxt, selector, &seg_desc); 1550 if (ret != X86EMUL_CONTINUE) 1551 return ret; 1552 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1553 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3, 1554 sizeof(base3), &ctxt->exception); 1555 if (ret != X86EMUL_CONTINUE) 1556 return ret; 1557 } 1558 load: 1559 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1560 return X86EMUL_CONTINUE; 1561 exception: 1562 return emulate_exception(ctxt, err_vec, err_code, true); 1563 } 1564 1565 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1566 u16 selector, int seg) 1567 { 1568 u8 cpl = ctxt->ops->cpl(ctxt); 1569 return __load_segment_descriptor(ctxt, selector, seg, cpl, false); 1570 } 1571 1572 static void write_register_operand(struct operand *op) 1573 { 1574 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 1575 switch (op->bytes) { 1576 case 1: 1577 *(u8 *)op->addr.reg = (u8)op->val; 1578 break; 1579 case 2: 1580 *(u16 *)op->addr.reg = (u16)op->val; 1581 break; 1582 case 4: 1583 *op->addr.reg = (u32)op->val; 1584 break; /* 64b: zero-extend */ 1585 case 8: 1586 *op->addr.reg = op->val; 1587 break; 1588 } 1589 } 1590 1591 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1592 { 1593 switch (op->type) { 1594 case OP_REG: 1595 write_register_operand(op); 1596 break; 1597 case OP_MEM: 1598 if (ctxt->lock_prefix) 1599 return segmented_cmpxchg(ctxt, 1600 op->addr.mem, 1601 &op->orig_val, 1602 &op->val, 1603 op->bytes); 1604 else 1605 return segmented_write(ctxt, 1606 op->addr.mem, 1607 &op->val, 1608 op->bytes); 1609 break; 1610 case OP_MEM_STR: 1611 return segmented_write(ctxt, 1612 op->addr.mem, 1613 op->data, 1614 op->bytes * op->count); 1615 break; 1616 case OP_XMM: 1617 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); 1618 break; 1619 case OP_MM: 1620 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 1621 break; 1622 case OP_NONE: 1623 /* no writeback */ 1624 break; 1625 default: 1626 break; 1627 } 1628 return X86EMUL_CONTINUE; 1629 } 1630 1631 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1632 { 1633 struct segmented_address addr; 1634 1635 rsp_increment(ctxt, -bytes); 1636 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1637 addr.seg = VCPU_SREG_SS; 1638 1639 return segmented_write(ctxt, addr, data, bytes); 1640 } 1641 1642 static int em_push(struct x86_emulate_ctxt *ctxt) 1643 { 1644 /* Disable writeback. */ 1645 ctxt->dst.type = OP_NONE; 1646 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1647 } 1648 1649 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1650 void *dest, int len) 1651 { 1652 int rc; 1653 struct segmented_address addr; 1654 1655 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1656 addr.seg = VCPU_SREG_SS; 1657 rc = segmented_read(ctxt, addr, dest, len); 1658 if (rc != X86EMUL_CONTINUE) 1659 return rc; 1660 1661 rsp_increment(ctxt, len); 1662 return rc; 1663 } 1664 1665 static int em_pop(struct x86_emulate_ctxt *ctxt) 1666 { 1667 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1668 } 1669 1670 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1671 void *dest, int len) 1672 { 1673 int rc; 1674 unsigned long val, change_mask; 1675 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 1676 int cpl = ctxt->ops->cpl(ctxt); 1677 1678 rc = emulate_pop(ctxt, &val, len); 1679 if (rc != X86EMUL_CONTINUE) 1680 return rc; 1681 1682 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF 1683 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID; 1684 1685 switch(ctxt->mode) { 1686 case X86EMUL_MODE_PROT64: 1687 case X86EMUL_MODE_PROT32: 1688 case X86EMUL_MODE_PROT16: 1689 if (cpl == 0) 1690 change_mask |= EFLG_IOPL; 1691 if (cpl <= iopl) 1692 change_mask |= EFLG_IF; 1693 break; 1694 case X86EMUL_MODE_VM86: 1695 if (iopl < 3) 1696 return emulate_gp(ctxt, 0); 1697 change_mask |= EFLG_IF; 1698 break; 1699 default: /* real mode */ 1700 change_mask |= (EFLG_IOPL | EFLG_IF); 1701 break; 1702 } 1703 1704 *(unsigned long *)dest = 1705 (ctxt->eflags & ~change_mask) | (val & change_mask); 1706 1707 return rc; 1708 } 1709 1710 static int em_popf(struct x86_emulate_ctxt *ctxt) 1711 { 1712 ctxt->dst.type = OP_REG; 1713 ctxt->dst.addr.reg = &ctxt->eflags; 1714 ctxt->dst.bytes = ctxt->op_bytes; 1715 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1716 } 1717 1718 static int em_enter(struct x86_emulate_ctxt *ctxt) 1719 { 1720 int rc; 1721 unsigned frame_size = ctxt->src.val; 1722 unsigned nesting_level = ctxt->src2.val & 31; 1723 ulong rbp; 1724 1725 if (nesting_level) 1726 return X86EMUL_UNHANDLEABLE; 1727 1728 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1729 rc = push(ctxt, &rbp, stack_size(ctxt)); 1730 if (rc != X86EMUL_CONTINUE) 1731 return rc; 1732 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1733 stack_mask(ctxt)); 1734 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1735 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1736 stack_mask(ctxt)); 1737 return X86EMUL_CONTINUE; 1738 } 1739 1740 static int em_leave(struct x86_emulate_ctxt *ctxt) 1741 { 1742 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1743 stack_mask(ctxt)); 1744 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1745 } 1746 1747 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1748 { 1749 int seg = ctxt->src2.val; 1750 1751 ctxt->src.val = get_segment_selector(ctxt, seg); 1752 1753 return em_push(ctxt); 1754 } 1755 1756 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1757 { 1758 int seg = ctxt->src2.val; 1759 unsigned long selector; 1760 int rc; 1761 1762 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); 1763 if (rc != X86EMUL_CONTINUE) 1764 return rc; 1765 1766 if (ctxt->modrm_reg == VCPU_SREG_SS) 1767 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1768 1769 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1770 return rc; 1771 } 1772 1773 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1774 { 1775 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1776 int rc = X86EMUL_CONTINUE; 1777 int reg = VCPU_REGS_RAX; 1778 1779 while (reg <= VCPU_REGS_RDI) { 1780 (reg == VCPU_REGS_RSP) ? 1781 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1782 1783 rc = em_push(ctxt); 1784 if (rc != X86EMUL_CONTINUE) 1785 return rc; 1786 1787 ++reg; 1788 } 1789 1790 return rc; 1791 } 1792 1793 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1794 { 1795 ctxt->src.val = (unsigned long)ctxt->eflags; 1796 return em_push(ctxt); 1797 } 1798 1799 static int em_popa(struct x86_emulate_ctxt *ctxt) 1800 { 1801 int rc = X86EMUL_CONTINUE; 1802 int reg = VCPU_REGS_RDI; 1803 1804 while (reg >= VCPU_REGS_RAX) { 1805 if (reg == VCPU_REGS_RSP) { 1806 rsp_increment(ctxt, ctxt->op_bytes); 1807 --reg; 1808 } 1809 1810 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); 1811 if (rc != X86EMUL_CONTINUE) 1812 break; 1813 --reg; 1814 } 1815 return rc; 1816 } 1817 1818 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1819 { 1820 const struct x86_emulate_ops *ops = ctxt->ops; 1821 int rc; 1822 struct desc_ptr dt; 1823 gva_t cs_addr; 1824 gva_t eip_addr; 1825 u16 cs, eip; 1826 1827 /* TODO: Add limit checks */ 1828 ctxt->src.val = ctxt->eflags; 1829 rc = em_push(ctxt); 1830 if (rc != X86EMUL_CONTINUE) 1831 return rc; 1832 1833 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); 1834 1835 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 1836 rc = em_push(ctxt); 1837 if (rc != X86EMUL_CONTINUE) 1838 return rc; 1839 1840 ctxt->src.val = ctxt->_eip; 1841 rc = em_push(ctxt); 1842 if (rc != X86EMUL_CONTINUE) 1843 return rc; 1844 1845 ops->get_idt(ctxt, &dt); 1846 1847 eip_addr = dt.address + (irq << 2); 1848 cs_addr = dt.address + (irq << 2) + 2; 1849 1850 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 1851 if (rc != X86EMUL_CONTINUE) 1852 return rc; 1853 1854 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 1855 if (rc != X86EMUL_CONTINUE) 1856 return rc; 1857 1858 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 1859 if (rc != X86EMUL_CONTINUE) 1860 return rc; 1861 1862 ctxt->_eip = eip; 1863 1864 return rc; 1865 } 1866 1867 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1868 { 1869 int rc; 1870 1871 invalidate_registers(ctxt); 1872 rc = __emulate_int_real(ctxt, irq); 1873 if (rc == X86EMUL_CONTINUE) 1874 writeback_registers(ctxt); 1875 return rc; 1876 } 1877 1878 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 1879 { 1880 switch(ctxt->mode) { 1881 case X86EMUL_MODE_REAL: 1882 return __emulate_int_real(ctxt, irq); 1883 case X86EMUL_MODE_VM86: 1884 case X86EMUL_MODE_PROT16: 1885 case X86EMUL_MODE_PROT32: 1886 case X86EMUL_MODE_PROT64: 1887 default: 1888 /* Protected mode interrupts unimplemented yet */ 1889 return X86EMUL_UNHANDLEABLE; 1890 } 1891 } 1892 1893 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 1894 { 1895 int rc = X86EMUL_CONTINUE; 1896 unsigned long temp_eip = 0; 1897 unsigned long temp_eflags = 0; 1898 unsigned long cs = 0; 1899 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | 1900 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | 1901 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ 1902 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; 1903 1904 /* TODO: Add stack limit check */ 1905 1906 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 1907 1908 if (rc != X86EMUL_CONTINUE) 1909 return rc; 1910 1911 if (temp_eip & ~0xffff) 1912 return emulate_gp(ctxt, 0); 1913 1914 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 1915 1916 if (rc != X86EMUL_CONTINUE) 1917 return rc; 1918 1919 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 1920 1921 if (rc != X86EMUL_CONTINUE) 1922 return rc; 1923 1924 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 1925 1926 if (rc != X86EMUL_CONTINUE) 1927 return rc; 1928 1929 ctxt->_eip = temp_eip; 1930 1931 1932 if (ctxt->op_bytes == 4) 1933 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 1934 else if (ctxt->op_bytes == 2) { 1935 ctxt->eflags &= ~0xffff; 1936 ctxt->eflags |= temp_eflags; 1937 } 1938 1939 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 1940 ctxt->eflags |= EFLG_RESERVED_ONE_MASK; 1941 1942 return rc; 1943 } 1944 1945 static int em_iret(struct x86_emulate_ctxt *ctxt) 1946 { 1947 switch(ctxt->mode) { 1948 case X86EMUL_MODE_REAL: 1949 return emulate_iret_real(ctxt); 1950 case X86EMUL_MODE_VM86: 1951 case X86EMUL_MODE_PROT16: 1952 case X86EMUL_MODE_PROT32: 1953 case X86EMUL_MODE_PROT64: 1954 default: 1955 /* iret from protected mode unimplemented yet */ 1956 return X86EMUL_UNHANDLEABLE; 1957 } 1958 } 1959 1960 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 1961 { 1962 int rc; 1963 unsigned short sel; 1964 1965 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 1966 1967 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); 1968 if (rc != X86EMUL_CONTINUE) 1969 return rc; 1970 1971 ctxt->_eip = 0; 1972 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 1973 return X86EMUL_CONTINUE; 1974 } 1975 1976 static int em_grp45(struct x86_emulate_ctxt *ctxt) 1977 { 1978 int rc = X86EMUL_CONTINUE; 1979 1980 switch (ctxt->modrm_reg) { 1981 case 2: /* call near abs */ { 1982 long int old_eip; 1983 old_eip = ctxt->_eip; 1984 ctxt->_eip = ctxt->src.val; 1985 ctxt->src.val = old_eip; 1986 rc = em_push(ctxt); 1987 break; 1988 } 1989 case 4: /* jmp abs */ 1990 ctxt->_eip = ctxt->src.val; 1991 break; 1992 case 5: /* jmp far */ 1993 rc = em_jmp_far(ctxt); 1994 break; 1995 case 6: /* push */ 1996 rc = em_push(ctxt); 1997 break; 1998 } 1999 return rc; 2000 } 2001 2002 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2003 { 2004 u64 old = ctxt->dst.orig_val64; 2005 2006 if (ctxt->dst.bytes == 16) 2007 return X86EMUL_UNHANDLEABLE; 2008 2009 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2010 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2011 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2012 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2013 ctxt->eflags &= ~EFLG_ZF; 2014 } else { 2015 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2016 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2017 2018 ctxt->eflags |= EFLG_ZF; 2019 } 2020 return X86EMUL_CONTINUE; 2021 } 2022 2023 static int em_ret(struct x86_emulate_ctxt *ctxt) 2024 { 2025 ctxt->dst.type = OP_REG; 2026 ctxt->dst.addr.reg = &ctxt->_eip; 2027 ctxt->dst.bytes = ctxt->op_bytes; 2028 return em_pop(ctxt); 2029 } 2030 2031 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2032 { 2033 int rc; 2034 unsigned long cs; 2035 int cpl = ctxt->ops->cpl(ctxt); 2036 2037 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); 2038 if (rc != X86EMUL_CONTINUE) 2039 return rc; 2040 if (ctxt->op_bytes == 4) 2041 ctxt->_eip = (u32)ctxt->_eip; 2042 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2043 if (rc != X86EMUL_CONTINUE) 2044 return rc; 2045 /* Outer-privilege level return is not implemented */ 2046 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2047 return X86EMUL_UNHANDLEABLE; 2048 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2049 return rc; 2050 } 2051 2052 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2053 { 2054 int rc; 2055 2056 rc = em_ret_far(ctxt); 2057 if (rc != X86EMUL_CONTINUE) 2058 return rc; 2059 rsp_increment(ctxt, ctxt->src.val); 2060 return X86EMUL_CONTINUE; 2061 } 2062 2063 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2064 { 2065 /* Save real source value, then compare EAX against destination. */ 2066 ctxt->dst.orig_val = ctxt->dst.val; 2067 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2068 ctxt->src.orig_val = ctxt->src.val; 2069 ctxt->src.val = ctxt->dst.orig_val; 2070 fastop(ctxt, em_cmp); 2071 2072 if (ctxt->eflags & EFLG_ZF) { 2073 /* Success: write back to memory. */ 2074 ctxt->dst.val = ctxt->src.orig_val; 2075 } else { 2076 /* Failure: write the value we saw to EAX. */ 2077 ctxt->dst.type = OP_REG; 2078 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2079 ctxt->dst.val = ctxt->dst.orig_val; 2080 } 2081 return X86EMUL_CONTINUE; 2082 } 2083 2084 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2085 { 2086 int seg = ctxt->src2.val; 2087 unsigned short sel; 2088 int rc; 2089 2090 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2091 2092 rc = load_segment_descriptor(ctxt, sel, seg); 2093 if (rc != X86EMUL_CONTINUE) 2094 return rc; 2095 2096 ctxt->dst.val = ctxt->src.val; 2097 return rc; 2098 } 2099 2100 static void 2101 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2102 struct desc_struct *cs, struct desc_struct *ss) 2103 { 2104 cs->l = 0; /* will be adjusted later */ 2105 set_desc_base(cs, 0); /* flat segment */ 2106 cs->g = 1; /* 4kb granularity */ 2107 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2108 cs->type = 0x0b; /* Read, Execute, Accessed */ 2109 cs->s = 1; 2110 cs->dpl = 0; /* will be adjusted later */ 2111 cs->p = 1; 2112 cs->d = 1; 2113 cs->avl = 0; 2114 2115 set_desc_base(ss, 0); /* flat segment */ 2116 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2117 ss->g = 1; /* 4kb granularity */ 2118 ss->s = 1; 2119 ss->type = 0x03; /* Read/Write, Accessed */ 2120 ss->d = 1; /* 32bit stack segment */ 2121 ss->dpl = 0; 2122 ss->p = 1; 2123 ss->l = 0; 2124 ss->avl = 0; 2125 } 2126 2127 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2128 { 2129 u32 eax, ebx, ecx, edx; 2130 2131 eax = ecx = 0; 2132 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2133 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2134 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2135 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2136 } 2137 2138 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2139 { 2140 const struct x86_emulate_ops *ops = ctxt->ops; 2141 u32 eax, ebx, ecx, edx; 2142 2143 /* 2144 * syscall should always be enabled in longmode - so only become 2145 * vendor specific (cpuid) if other modes are active... 2146 */ 2147 if (ctxt->mode == X86EMUL_MODE_PROT64) 2148 return true; 2149 2150 eax = 0x00000000; 2151 ecx = 0x00000000; 2152 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2153 /* 2154 * Intel ("GenuineIntel") 2155 * remark: Intel CPUs only support "syscall" in 64bit 2156 * longmode. Also an 64bit guest with a 2157 * 32bit compat-app running will #UD !! While this 2158 * behaviour can be fixed (by emulating) into AMD 2159 * response - CPUs of AMD can't behave like Intel. 2160 */ 2161 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2162 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2163 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2164 return false; 2165 2166 /* AMD ("AuthenticAMD") */ 2167 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2168 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2169 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2170 return true; 2171 2172 /* AMD ("AMDisbetter!") */ 2173 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2174 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2175 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2176 return true; 2177 2178 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 2179 return false; 2180 } 2181 2182 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2183 { 2184 const struct x86_emulate_ops *ops = ctxt->ops; 2185 struct desc_struct cs, ss; 2186 u64 msr_data; 2187 u16 cs_sel, ss_sel; 2188 u64 efer = 0; 2189 2190 /* syscall is not available in real mode */ 2191 if (ctxt->mode == X86EMUL_MODE_REAL || 2192 ctxt->mode == X86EMUL_MODE_VM86) 2193 return emulate_ud(ctxt); 2194 2195 if (!(em_syscall_is_enabled(ctxt))) 2196 return emulate_ud(ctxt); 2197 2198 ops->get_msr(ctxt, MSR_EFER, &efer); 2199 setup_syscalls_segments(ctxt, &cs, &ss); 2200 2201 if (!(efer & EFER_SCE)) 2202 return emulate_ud(ctxt); 2203 2204 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2205 msr_data >>= 32; 2206 cs_sel = (u16)(msr_data & 0xfffc); 2207 ss_sel = (u16)(msr_data + 8); 2208 2209 if (efer & EFER_LMA) { 2210 cs.d = 0; 2211 cs.l = 1; 2212 } 2213 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2214 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2215 2216 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2217 if (efer & EFER_LMA) { 2218 #ifdef CONFIG_X86_64 2219 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2220 2221 ops->get_msr(ctxt, 2222 ctxt->mode == X86EMUL_MODE_PROT64 ? 2223 MSR_LSTAR : MSR_CSTAR, &msr_data); 2224 ctxt->_eip = msr_data; 2225 2226 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2227 ctxt->eflags &= ~msr_data; 2228 #endif 2229 } else { 2230 /* legacy mode */ 2231 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2232 ctxt->_eip = (u32)msr_data; 2233 2234 ctxt->eflags &= ~(EFLG_VM | EFLG_IF); 2235 } 2236 2237 return X86EMUL_CONTINUE; 2238 } 2239 2240 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2241 { 2242 const struct x86_emulate_ops *ops = ctxt->ops; 2243 struct desc_struct cs, ss; 2244 u64 msr_data; 2245 u16 cs_sel, ss_sel; 2246 u64 efer = 0; 2247 2248 ops->get_msr(ctxt, MSR_EFER, &efer); 2249 /* inject #GP if in real mode */ 2250 if (ctxt->mode == X86EMUL_MODE_REAL) 2251 return emulate_gp(ctxt, 0); 2252 2253 /* 2254 * Not recognized on AMD in compat mode (but is recognized in legacy 2255 * mode). 2256 */ 2257 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) 2258 && !vendor_intel(ctxt)) 2259 return emulate_ud(ctxt); 2260 2261 /* XXX sysenter/sysexit have not been tested in 64bit mode. 2262 * Therefore, we inject an #UD. 2263 */ 2264 if (ctxt->mode == X86EMUL_MODE_PROT64) 2265 return emulate_ud(ctxt); 2266 2267 setup_syscalls_segments(ctxt, &cs, &ss); 2268 2269 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2270 switch (ctxt->mode) { 2271 case X86EMUL_MODE_PROT32: 2272 if ((msr_data & 0xfffc) == 0x0) 2273 return emulate_gp(ctxt, 0); 2274 break; 2275 case X86EMUL_MODE_PROT64: 2276 if (msr_data == 0x0) 2277 return emulate_gp(ctxt, 0); 2278 break; 2279 default: 2280 break; 2281 } 2282 2283 ctxt->eflags &= ~(EFLG_VM | EFLG_IF); 2284 cs_sel = (u16)msr_data; 2285 cs_sel &= ~SELECTOR_RPL_MASK; 2286 ss_sel = cs_sel + 8; 2287 ss_sel &= ~SELECTOR_RPL_MASK; 2288 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { 2289 cs.d = 0; 2290 cs.l = 1; 2291 } 2292 2293 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2294 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2295 2296 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2297 ctxt->_eip = msr_data; 2298 2299 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2300 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; 2301 2302 return X86EMUL_CONTINUE; 2303 } 2304 2305 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2306 { 2307 const struct x86_emulate_ops *ops = ctxt->ops; 2308 struct desc_struct cs, ss; 2309 u64 msr_data; 2310 int usermode; 2311 u16 cs_sel = 0, ss_sel = 0; 2312 2313 /* inject #GP if in real mode or Virtual 8086 mode */ 2314 if (ctxt->mode == X86EMUL_MODE_REAL || 2315 ctxt->mode == X86EMUL_MODE_VM86) 2316 return emulate_gp(ctxt, 0); 2317 2318 setup_syscalls_segments(ctxt, &cs, &ss); 2319 2320 if ((ctxt->rex_prefix & 0x8) != 0x0) 2321 usermode = X86EMUL_MODE_PROT64; 2322 else 2323 usermode = X86EMUL_MODE_PROT32; 2324 2325 cs.dpl = 3; 2326 ss.dpl = 3; 2327 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2328 switch (usermode) { 2329 case X86EMUL_MODE_PROT32: 2330 cs_sel = (u16)(msr_data + 16); 2331 if ((msr_data & 0xfffc) == 0x0) 2332 return emulate_gp(ctxt, 0); 2333 ss_sel = (u16)(msr_data + 24); 2334 break; 2335 case X86EMUL_MODE_PROT64: 2336 cs_sel = (u16)(msr_data + 32); 2337 if (msr_data == 0x0) 2338 return emulate_gp(ctxt, 0); 2339 ss_sel = cs_sel + 8; 2340 cs.d = 0; 2341 cs.l = 1; 2342 break; 2343 } 2344 cs_sel |= SELECTOR_RPL_MASK; 2345 ss_sel |= SELECTOR_RPL_MASK; 2346 2347 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2348 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2349 2350 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); 2351 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); 2352 2353 return X86EMUL_CONTINUE; 2354 } 2355 2356 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2357 { 2358 int iopl; 2359 if (ctxt->mode == X86EMUL_MODE_REAL) 2360 return false; 2361 if (ctxt->mode == X86EMUL_MODE_VM86) 2362 return true; 2363 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 2364 return ctxt->ops->cpl(ctxt) > iopl; 2365 } 2366 2367 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2368 u16 port, u16 len) 2369 { 2370 const struct x86_emulate_ops *ops = ctxt->ops; 2371 struct desc_struct tr_seg; 2372 u32 base3; 2373 int r; 2374 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2375 unsigned mask = (1 << len) - 1; 2376 unsigned long base; 2377 2378 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2379 if (!tr_seg.p) 2380 return false; 2381 if (desc_limit_scaled(&tr_seg) < 103) 2382 return false; 2383 base = get_desc_base(&tr_seg); 2384 #ifdef CONFIG_X86_64 2385 base |= ((u64)base3) << 32; 2386 #endif 2387 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2388 if (r != X86EMUL_CONTINUE) 2389 return false; 2390 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2391 return false; 2392 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2393 if (r != X86EMUL_CONTINUE) 2394 return false; 2395 if ((perm >> bit_idx) & mask) 2396 return false; 2397 return true; 2398 } 2399 2400 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2401 u16 port, u16 len) 2402 { 2403 if (ctxt->perm_ok) 2404 return true; 2405 2406 if (emulator_bad_iopl(ctxt)) 2407 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2408 return false; 2409 2410 ctxt->perm_ok = true; 2411 2412 return true; 2413 } 2414 2415 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2416 struct tss_segment_16 *tss) 2417 { 2418 tss->ip = ctxt->_eip; 2419 tss->flag = ctxt->eflags; 2420 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2421 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2422 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2423 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2424 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2425 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2426 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2427 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2428 2429 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2430 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2431 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2432 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2433 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2434 } 2435 2436 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2437 struct tss_segment_16 *tss) 2438 { 2439 int ret; 2440 u8 cpl; 2441 2442 ctxt->_eip = tss->ip; 2443 ctxt->eflags = tss->flag | 2; 2444 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2445 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2446 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2447 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2448 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2449 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2450 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2451 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2452 2453 /* 2454 * SDM says that segment selectors are loaded before segment 2455 * descriptors 2456 */ 2457 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2458 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2459 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2460 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2461 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2462 2463 cpl = tss->cs & 3; 2464 2465 /* 2466 * Now load segment descriptors. If fault happens at this stage 2467 * it is handled in a context of new task 2468 */ 2469 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true); 2470 if (ret != X86EMUL_CONTINUE) 2471 return ret; 2472 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true); 2473 if (ret != X86EMUL_CONTINUE) 2474 return ret; 2475 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true); 2476 if (ret != X86EMUL_CONTINUE) 2477 return ret; 2478 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true); 2479 if (ret != X86EMUL_CONTINUE) 2480 return ret; 2481 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true); 2482 if (ret != X86EMUL_CONTINUE) 2483 return ret; 2484 2485 return X86EMUL_CONTINUE; 2486 } 2487 2488 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2489 u16 tss_selector, u16 old_tss_sel, 2490 ulong old_tss_base, struct desc_struct *new_desc) 2491 { 2492 const struct x86_emulate_ops *ops = ctxt->ops; 2493 struct tss_segment_16 tss_seg; 2494 int ret; 2495 u32 new_tss_base = get_desc_base(new_desc); 2496 2497 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2498 &ctxt->exception); 2499 if (ret != X86EMUL_CONTINUE) 2500 /* FIXME: need to provide precise fault address */ 2501 return ret; 2502 2503 save_state_to_tss16(ctxt, &tss_seg); 2504 2505 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2506 &ctxt->exception); 2507 if (ret != X86EMUL_CONTINUE) 2508 /* FIXME: need to provide precise fault address */ 2509 return ret; 2510 2511 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2512 &ctxt->exception); 2513 if (ret != X86EMUL_CONTINUE) 2514 /* FIXME: need to provide precise fault address */ 2515 return ret; 2516 2517 if (old_tss_sel != 0xffff) { 2518 tss_seg.prev_task_link = old_tss_sel; 2519 2520 ret = ops->write_std(ctxt, new_tss_base, 2521 &tss_seg.prev_task_link, 2522 sizeof tss_seg.prev_task_link, 2523 &ctxt->exception); 2524 if (ret != X86EMUL_CONTINUE) 2525 /* FIXME: need to provide precise fault address */ 2526 return ret; 2527 } 2528 2529 return load_state_from_tss16(ctxt, &tss_seg); 2530 } 2531 2532 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2533 struct tss_segment_32 *tss) 2534 { 2535 /* CR3 and ldt selector are not saved intentionally */ 2536 tss->eip = ctxt->_eip; 2537 tss->eflags = ctxt->eflags; 2538 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2539 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2540 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2541 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2542 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2543 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2544 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2545 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2546 2547 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2548 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2549 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2550 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2551 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2552 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2553 } 2554 2555 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2556 struct tss_segment_32 *tss) 2557 { 2558 int ret; 2559 u8 cpl; 2560 2561 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2562 return emulate_gp(ctxt, 0); 2563 ctxt->_eip = tss->eip; 2564 ctxt->eflags = tss->eflags | 2; 2565 2566 /* General purpose registers */ 2567 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2568 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2569 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2570 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2571 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2572 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2573 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2574 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2575 2576 /* 2577 * SDM says that segment selectors are loaded before segment 2578 * descriptors. This is important because CPL checks will 2579 * use CS.RPL. 2580 */ 2581 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2582 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2583 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2584 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2585 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2586 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2587 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2588 2589 /* 2590 * If we're switching between Protected Mode and VM86, we need to make 2591 * sure to update the mode before loading the segment descriptors so 2592 * that the selectors are interpreted correctly. 2593 */ 2594 if (ctxt->eflags & X86_EFLAGS_VM) { 2595 ctxt->mode = X86EMUL_MODE_VM86; 2596 cpl = 3; 2597 } else { 2598 ctxt->mode = X86EMUL_MODE_PROT32; 2599 cpl = tss->cs & 3; 2600 } 2601 2602 /* 2603 * Now load segment descriptors. If fault happenes at this stage 2604 * it is handled in a context of new task 2605 */ 2606 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true); 2607 if (ret != X86EMUL_CONTINUE) 2608 return ret; 2609 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true); 2610 if (ret != X86EMUL_CONTINUE) 2611 return ret; 2612 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true); 2613 if (ret != X86EMUL_CONTINUE) 2614 return ret; 2615 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true); 2616 if (ret != X86EMUL_CONTINUE) 2617 return ret; 2618 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true); 2619 if (ret != X86EMUL_CONTINUE) 2620 return ret; 2621 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true); 2622 if (ret != X86EMUL_CONTINUE) 2623 return ret; 2624 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true); 2625 if (ret != X86EMUL_CONTINUE) 2626 return ret; 2627 2628 return X86EMUL_CONTINUE; 2629 } 2630 2631 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 2632 u16 tss_selector, u16 old_tss_sel, 2633 ulong old_tss_base, struct desc_struct *new_desc) 2634 { 2635 const struct x86_emulate_ops *ops = ctxt->ops; 2636 struct tss_segment_32 tss_seg; 2637 int ret; 2638 u32 new_tss_base = get_desc_base(new_desc); 2639 u32 eip_offset = offsetof(struct tss_segment_32, eip); 2640 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 2641 2642 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2643 &ctxt->exception); 2644 if (ret != X86EMUL_CONTINUE) 2645 /* FIXME: need to provide precise fault address */ 2646 return ret; 2647 2648 save_state_to_tss32(ctxt, &tss_seg); 2649 2650 /* Only GP registers and segment selectors are saved */ 2651 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 2652 ldt_sel_offset - eip_offset, &ctxt->exception); 2653 if (ret != X86EMUL_CONTINUE) 2654 /* FIXME: need to provide precise fault address */ 2655 return ret; 2656 2657 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2658 &ctxt->exception); 2659 if (ret != X86EMUL_CONTINUE) 2660 /* FIXME: need to provide precise fault address */ 2661 return ret; 2662 2663 if (old_tss_sel != 0xffff) { 2664 tss_seg.prev_task_link = old_tss_sel; 2665 2666 ret = ops->write_std(ctxt, new_tss_base, 2667 &tss_seg.prev_task_link, 2668 sizeof tss_seg.prev_task_link, 2669 &ctxt->exception); 2670 if (ret != X86EMUL_CONTINUE) 2671 /* FIXME: need to provide precise fault address */ 2672 return ret; 2673 } 2674 2675 return load_state_from_tss32(ctxt, &tss_seg); 2676 } 2677 2678 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2679 u16 tss_selector, int idt_index, int reason, 2680 bool has_error_code, u32 error_code) 2681 { 2682 const struct x86_emulate_ops *ops = ctxt->ops; 2683 struct desc_struct curr_tss_desc, next_tss_desc; 2684 int ret; 2685 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2686 ulong old_tss_base = 2687 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2688 u32 desc_limit; 2689 ulong desc_addr; 2690 2691 /* FIXME: old_tss_base == ~0 ? */ 2692 2693 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2694 if (ret != X86EMUL_CONTINUE) 2695 return ret; 2696 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2697 if (ret != X86EMUL_CONTINUE) 2698 return ret; 2699 2700 /* FIXME: check that next_tss_desc is tss */ 2701 2702 /* 2703 * Check privileges. The three cases are task switch caused by... 2704 * 2705 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2706 * 2. Exception/IRQ/iret: No check is performed 2707 * 3. jmp/call to TSS: Check against DPL of the TSS 2708 */ 2709 if (reason == TASK_SWITCH_GATE) { 2710 if (idt_index != -1) { 2711 /* Software interrupts */ 2712 struct desc_struct task_gate_desc; 2713 int dpl; 2714 2715 ret = read_interrupt_descriptor(ctxt, idt_index, 2716 &task_gate_desc); 2717 if (ret != X86EMUL_CONTINUE) 2718 return ret; 2719 2720 dpl = task_gate_desc.dpl; 2721 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2722 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2723 } 2724 } else if (reason != TASK_SWITCH_IRET) { 2725 int dpl = next_tss_desc.dpl; 2726 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2727 return emulate_gp(ctxt, tss_selector); 2728 } 2729 2730 2731 desc_limit = desc_limit_scaled(&next_tss_desc); 2732 if (!next_tss_desc.p || 2733 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2734 desc_limit < 0x2b)) { 2735 return emulate_ts(ctxt, tss_selector & 0xfffc); 2736 } 2737 2738 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2739 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2740 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2741 } 2742 2743 if (reason == TASK_SWITCH_IRET) 2744 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2745 2746 /* set back link to prev task only if NT bit is set in eflags 2747 note that old_tss_sel is not used after this point */ 2748 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2749 old_tss_sel = 0xffff; 2750 2751 if (next_tss_desc.type & 8) 2752 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 2753 old_tss_base, &next_tss_desc); 2754 else 2755 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 2756 old_tss_base, &next_tss_desc); 2757 if (ret != X86EMUL_CONTINUE) 2758 return ret; 2759 2760 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2761 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2762 2763 if (reason != TASK_SWITCH_IRET) { 2764 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2765 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2766 } 2767 2768 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2769 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2770 2771 if (has_error_code) { 2772 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2773 ctxt->lock_prefix = 0; 2774 ctxt->src.val = (unsigned long) error_code; 2775 ret = em_push(ctxt); 2776 } 2777 2778 return ret; 2779 } 2780 2781 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2782 u16 tss_selector, int idt_index, int reason, 2783 bool has_error_code, u32 error_code) 2784 { 2785 int rc; 2786 2787 invalidate_registers(ctxt); 2788 ctxt->_eip = ctxt->eip; 2789 ctxt->dst.type = OP_NONE; 2790 2791 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2792 has_error_code, error_code); 2793 2794 if (rc == X86EMUL_CONTINUE) { 2795 ctxt->eip = ctxt->_eip; 2796 writeback_registers(ctxt); 2797 } 2798 2799 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2800 } 2801 2802 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 2803 struct operand *op) 2804 { 2805 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; 2806 2807 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes); 2808 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg)); 2809 } 2810 2811 static int em_das(struct x86_emulate_ctxt *ctxt) 2812 { 2813 u8 al, old_al; 2814 bool af, cf, old_cf; 2815 2816 cf = ctxt->eflags & X86_EFLAGS_CF; 2817 al = ctxt->dst.val; 2818 2819 old_al = al; 2820 old_cf = cf; 2821 cf = false; 2822 af = ctxt->eflags & X86_EFLAGS_AF; 2823 if ((al & 0x0f) > 9 || af) { 2824 al -= 6; 2825 cf = old_cf | (al >= 250); 2826 af = true; 2827 } else { 2828 af = false; 2829 } 2830 if (old_al > 0x99 || old_cf) { 2831 al -= 0x60; 2832 cf = true; 2833 } 2834 2835 ctxt->dst.val = al; 2836 /* Set PF, ZF, SF */ 2837 ctxt->src.type = OP_IMM; 2838 ctxt->src.val = 0; 2839 ctxt->src.bytes = 1; 2840 fastop(ctxt, em_or); 2841 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 2842 if (cf) 2843 ctxt->eflags |= X86_EFLAGS_CF; 2844 if (af) 2845 ctxt->eflags |= X86_EFLAGS_AF; 2846 return X86EMUL_CONTINUE; 2847 } 2848 2849 static int em_aam(struct x86_emulate_ctxt *ctxt) 2850 { 2851 u8 al, ah; 2852 2853 if (ctxt->src.val == 0) 2854 return emulate_de(ctxt); 2855 2856 al = ctxt->dst.val & 0xff; 2857 ah = al / ctxt->src.val; 2858 al %= ctxt->src.val; 2859 2860 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 2861 2862 /* Set PF, ZF, SF */ 2863 ctxt->src.type = OP_IMM; 2864 ctxt->src.val = 0; 2865 ctxt->src.bytes = 1; 2866 fastop(ctxt, em_or); 2867 2868 return X86EMUL_CONTINUE; 2869 } 2870 2871 static int em_aad(struct x86_emulate_ctxt *ctxt) 2872 { 2873 u8 al = ctxt->dst.val & 0xff; 2874 u8 ah = (ctxt->dst.val >> 8) & 0xff; 2875 2876 al = (al + (ah * ctxt->src.val)) & 0xff; 2877 2878 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 2879 2880 /* Set PF, ZF, SF */ 2881 ctxt->src.type = OP_IMM; 2882 ctxt->src.val = 0; 2883 ctxt->src.bytes = 1; 2884 fastop(ctxt, em_or); 2885 2886 return X86EMUL_CONTINUE; 2887 } 2888 2889 static int em_call(struct x86_emulate_ctxt *ctxt) 2890 { 2891 long rel = ctxt->src.val; 2892 2893 ctxt->src.val = (unsigned long)ctxt->_eip; 2894 jmp_rel(ctxt, rel); 2895 return em_push(ctxt); 2896 } 2897 2898 static int em_call_far(struct x86_emulate_ctxt *ctxt) 2899 { 2900 u16 sel, old_cs; 2901 ulong old_eip; 2902 int rc; 2903 2904 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2905 old_eip = ctxt->_eip; 2906 2907 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2908 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) 2909 return X86EMUL_CONTINUE; 2910 2911 ctxt->_eip = 0; 2912 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 2913 2914 ctxt->src.val = old_cs; 2915 rc = em_push(ctxt); 2916 if (rc != X86EMUL_CONTINUE) 2917 return rc; 2918 2919 ctxt->src.val = old_eip; 2920 return em_push(ctxt); 2921 } 2922 2923 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 2924 { 2925 int rc; 2926 2927 ctxt->dst.type = OP_REG; 2928 ctxt->dst.addr.reg = &ctxt->_eip; 2929 ctxt->dst.bytes = ctxt->op_bytes; 2930 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 2931 if (rc != X86EMUL_CONTINUE) 2932 return rc; 2933 rsp_increment(ctxt, ctxt->src.val); 2934 return X86EMUL_CONTINUE; 2935 } 2936 2937 static int em_xchg(struct x86_emulate_ctxt *ctxt) 2938 { 2939 /* Write back the register source. */ 2940 ctxt->src.val = ctxt->dst.val; 2941 write_register_operand(&ctxt->src); 2942 2943 /* Write back the memory destination with implicit LOCK prefix. */ 2944 ctxt->dst.val = ctxt->src.orig_val; 2945 ctxt->lock_prefix = 1; 2946 return X86EMUL_CONTINUE; 2947 } 2948 2949 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 2950 { 2951 ctxt->dst.val = ctxt->src2.val; 2952 return fastop(ctxt, em_imul); 2953 } 2954 2955 static int em_cwd(struct x86_emulate_ctxt *ctxt) 2956 { 2957 ctxt->dst.type = OP_REG; 2958 ctxt->dst.bytes = ctxt->src.bytes; 2959 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 2960 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 2961 2962 return X86EMUL_CONTINUE; 2963 } 2964 2965 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 2966 { 2967 u64 tsc = 0; 2968 2969 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 2970 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 2971 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 2972 return X86EMUL_CONTINUE; 2973 } 2974 2975 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 2976 { 2977 u64 pmc; 2978 2979 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 2980 return emulate_gp(ctxt, 0); 2981 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 2982 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 2983 return X86EMUL_CONTINUE; 2984 } 2985 2986 static int em_mov(struct x86_emulate_ctxt *ctxt) 2987 { 2988 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 2989 return X86EMUL_CONTINUE; 2990 } 2991 2992 #define FFL(x) bit(X86_FEATURE_##x) 2993 2994 static int em_movbe(struct x86_emulate_ctxt *ctxt) 2995 { 2996 u32 ebx, ecx, edx, eax = 1; 2997 u16 tmp; 2998 2999 /* 3000 * Check MOVBE is set in the guest-visible CPUID leaf. 3001 */ 3002 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 3003 if (!(ecx & FFL(MOVBE))) 3004 return emulate_ud(ctxt); 3005 3006 switch (ctxt->op_bytes) { 3007 case 2: 3008 /* 3009 * From MOVBE definition: "...When the operand size is 16 bits, 3010 * the upper word of the destination register remains unchanged 3011 * ..." 3012 * 3013 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3014 * rules so we have to do the operation almost per hand. 3015 */ 3016 tmp = (u16)ctxt->src.val; 3017 ctxt->dst.val &= ~0xffffUL; 3018 ctxt->dst.val |= (unsigned long)swab16(tmp); 3019 break; 3020 case 4: 3021 ctxt->dst.val = swab32((u32)ctxt->src.val); 3022 break; 3023 case 8: 3024 ctxt->dst.val = swab64(ctxt->src.val); 3025 break; 3026 default: 3027 BUG(); 3028 } 3029 return X86EMUL_CONTINUE; 3030 } 3031 3032 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3033 { 3034 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3035 return emulate_gp(ctxt, 0); 3036 3037 /* Disable writeback. */ 3038 ctxt->dst.type = OP_NONE; 3039 return X86EMUL_CONTINUE; 3040 } 3041 3042 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3043 { 3044 unsigned long val; 3045 3046 if (ctxt->mode == X86EMUL_MODE_PROT64) 3047 val = ctxt->src.val & ~0ULL; 3048 else 3049 val = ctxt->src.val & ~0U; 3050 3051 /* #UD condition is already handled. */ 3052 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3053 return emulate_gp(ctxt, 0); 3054 3055 /* Disable writeback. */ 3056 ctxt->dst.type = OP_NONE; 3057 return X86EMUL_CONTINUE; 3058 } 3059 3060 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3061 { 3062 u64 msr_data; 3063 3064 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3065 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3066 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3067 return emulate_gp(ctxt, 0); 3068 3069 return X86EMUL_CONTINUE; 3070 } 3071 3072 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3073 { 3074 u64 msr_data; 3075 3076 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3077 return emulate_gp(ctxt, 0); 3078 3079 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3080 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3081 return X86EMUL_CONTINUE; 3082 } 3083 3084 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3085 { 3086 if (ctxt->modrm_reg > VCPU_SREG_GS) 3087 return emulate_ud(ctxt); 3088 3089 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 3090 return X86EMUL_CONTINUE; 3091 } 3092 3093 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3094 { 3095 u16 sel = ctxt->src.val; 3096 3097 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3098 return emulate_ud(ctxt); 3099 3100 if (ctxt->modrm_reg == VCPU_SREG_SS) 3101 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3102 3103 /* Disable writeback. */ 3104 ctxt->dst.type = OP_NONE; 3105 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3106 } 3107 3108 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3109 { 3110 u16 sel = ctxt->src.val; 3111 3112 /* Disable writeback. */ 3113 ctxt->dst.type = OP_NONE; 3114 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3115 } 3116 3117 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3118 { 3119 u16 sel = ctxt->src.val; 3120 3121 /* Disable writeback. */ 3122 ctxt->dst.type = OP_NONE; 3123 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3124 } 3125 3126 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3127 { 3128 int rc; 3129 ulong linear; 3130 3131 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3132 if (rc == X86EMUL_CONTINUE) 3133 ctxt->ops->invlpg(ctxt, linear); 3134 /* Disable writeback. */ 3135 ctxt->dst.type = OP_NONE; 3136 return X86EMUL_CONTINUE; 3137 } 3138 3139 static int em_clts(struct x86_emulate_ctxt *ctxt) 3140 { 3141 ulong cr0; 3142 3143 cr0 = ctxt->ops->get_cr(ctxt, 0); 3144 cr0 &= ~X86_CR0_TS; 3145 ctxt->ops->set_cr(ctxt, 0, cr0); 3146 return X86EMUL_CONTINUE; 3147 } 3148 3149 static int em_vmcall(struct x86_emulate_ctxt *ctxt) 3150 { 3151 int rc = ctxt->ops->fix_hypercall(ctxt); 3152 3153 if (rc != X86EMUL_CONTINUE) 3154 return rc; 3155 3156 /* Let the processor re-execute the fixed hypercall */ 3157 ctxt->_eip = ctxt->eip; 3158 /* Disable writeback. */ 3159 ctxt->dst.type = OP_NONE; 3160 return X86EMUL_CONTINUE; 3161 } 3162 3163 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3164 void (*get)(struct x86_emulate_ctxt *ctxt, 3165 struct desc_ptr *ptr)) 3166 { 3167 struct desc_ptr desc_ptr; 3168 3169 if (ctxt->mode == X86EMUL_MODE_PROT64) 3170 ctxt->op_bytes = 8; 3171 get(ctxt, &desc_ptr); 3172 if (ctxt->op_bytes == 2) { 3173 ctxt->op_bytes = 4; 3174 desc_ptr.address &= 0x00ffffff; 3175 } 3176 /* Disable writeback. */ 3177 ctxt->dst.type = OP_NONE; 3178 return segmented_write(ctxt, ctxt->dst.addr.mem, 3179 &desc_ptr, 2 + ctxt->op_bytes); 3180 } 3181 3182 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3183 { 3184 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3185 } 3186 3187 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3188 { 3189 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3190 } 3191 3192 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3193 { 3194 struct desc_ptr desc_ptr; 3195 int rc; 3196 3197 if (ctxt->mode == X86EMUL_MODE_PROT64) 3198 ctxt->op_bytes = 8; 3199 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3200 &desc_ptr.size, &desc_ptr.address, 3201 ctxt->op_bytes); 3202 if (rc != X86EMUL_CONTINUE) 3203 return rc; 3204 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3205 /* Disable writeback. */ 3206 ctxt->dst.type = OP_NONE; 3207 return X86EMUL_CONTINUE; 3208 } 3209 3210 static int em_vmmcall(struct x86_emulate_ctxt *ctxt) 3211 { 3212 int rc; 3213 3214 rc = ctxt->ops->fix_hypercall(ctxt); 3215 3216 /* Disable writeback. */ 3217 ctxt->dst.type = OP_NONE; 3218 return rc; 3219 } 3220 3221 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3222 { 3223 struct desc_ptr desc_ptr; 3224 int rc; 3225 3226 if (ctxt->mode == X86EMUL_MODE_PROT64) 3227 ctxt->op_bytes = 8; 3228 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3229 &desc_ptr.size, &desc_ptr.address, 3230 ctxt->op_bytes); 3231 if (rc != X86EMUL_CONTINUE) 3232 return rc; 3233 ctxt->ops->set_idt(ctxt, &desc_ptr); 3234 /* Disable writeback. */ 3235 ctxt->dst.type = OP_NONE; 3236 return X86EMUL_CONTINUE; 3237 } 3238 3239 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3240 { 3241 if (ctxt->dst.type == OP_MEM) 3242 ctxt->dst.bytes = 2; 3243 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3244 return X86EMUL_CONTINUE; 3245 } 3246 3247 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3248 { 3249 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3250 | (ctxt->src.val & 0x0f)); 3251 ctxt->dst.type = OP_NONE; 3252 return X86EMUL_CONTINUE; 3253 } 3254 3255 static int em_loop(struct x86_emulate_ctxt *ctxt) 3256 { 3257 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); 3258 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3259 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3260 jmp_rel(ctxt, ctxt->src.val); 3261 3262 return X86EMUL_CONTINUE; 3263 } 3264 3265 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3266 { 3267 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3268 jmp_rel(ctxt, ctxt->src.val); 3269 3270 return X86EMUL_CONTINUE; 3271 } 3272 3273 static int em_in(struct x86_emulate_ctxt *ctxt) 3274 { 3275 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3276 &ctxt->dst.val)) 3277 return X86EMUL_IO_NEEDED; 3278 3279 return X86EMUL_CONTINUE; 3280 } 3281 3282 static int em_out(struct x86_emulate_ctxt *ctxt) 3283 { 3284 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3285 &ctxt->src.val, 1); 3286 /* Disable writeback. */ 3287 ctxt->dst.type = OP_NONE; 3288 return X86EMUL_CONTINUE; 3289 } 3290 3291 static int em_cli(struct x86_emulate_ctxt *ctxt) 3292 { 3293 if (emulator_bad_iopl(ctxt)) 3294 return emulate_gp(ctxt, 0); 3295 3296 ctxt->eflags &= ~X86_EFLAGS_IF; 3297 return X86EMUL_CONTINUE; 3298 } 3299 3300 static int em_sti(struct x86_emulate_ctxt *ctxt) 3301 { 3302 if (emulator_bad_iopl(ctxt)) 3303 return emulate_gp(ctxt, 0); 3304 3305 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3306 ctxt->eflags |= X86_EFLAGS_IF; 3307 return X86EMUL_CONTINUE; 3308 } 3309 3310 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3311 { 3312 u32 eax, ebx, ecx, edx; 3313 3314 eax = reg_read(ctxt, VCPU_REGS_RAX); 3315 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3316 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 3317 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3318 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3319 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3320 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3321 return X86EMUL_CONTINUE; 3322 } 3323 3324 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3325 { 3326 u32 flags; 3327 3328 flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF; 3329 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3330 3331 ctxt->eflags &= ~0xffUL; 3332 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3333 return X86EMUL_CONTINUE; 3334 } 3335 3336 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3337 { 3338 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3339 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3340 return X86EMUL_CONTINUE; 3341 } 3342 3343 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3344 { 3345 switch (ctxt->op_bytes) { 3346 #ifdef CONFIG_X86_64 3347 case 8: 3348 asm("bswap %0" : "+r"(ctxt->dst.val)); 3349 break; 3350 #endif 3351 default: 3352 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3353 break; 3354 } 3355 return X86EMUL_CONTINUE; 3356 } 3357 3358 static bool valid_cr(int nr) 3359 { 3360 switch (nr) { 3361 case 0: 3362 case 2 ... 4: 3363 case 8: 3364 return true; 3365 default: 3366 return false; 3367 } 3368 } 3369 3370 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 3371 { 3372 if (!valid_cr(ctxt->modrm_reg)) 3373 return emulate_ud(ctxt); 3374 3375 return X86EMUL_CONTINUE; 3376 } 3377 3378 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 3379 { 3380 u64 new_val = ctxt->src.val64; 3381 int cr = ctxt->modrm_reg; 3382 u64 efer = 0; 3383 3384 static u64 cr_reserved_bits[] = { 3385 0xffffffff00000000ULL, 3386 0, 0, 0, /* CR3 checked later */ 3387 CR4_RESERVED_BITS, 3388 0, 0, 0, 3389 CR8_RESERVED_BITS, 3390 }; 3391 3392 if (!valid_cr(cr)) 3393 return emulate_ud(ctxt); 3394 3395 if (new_val & cr_reserved_bits[cr]) 3396 return emulate_gp(ctxt, 0); 3397 3398 switch (cr) { 3399 case 0: { 3400 u64 cr4; 3401 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 3402 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 3403 return emulate_gp(ctxt, 0); 3404 3405 cr4 = ctxt->ops->get_cr(ctxt, 4); 3406 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3407 3408 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 3409 !(cr4 & X86_CR4_PAE)) 3410 return emulate_gp(ctxt, 0); 3411 3412 break; 3413 } 3414 case 3: { 3415 u64 rsvd = 0; 3416 3417 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3418 if (efer & EFER_LMA) 3419 rsvd = CR3_L_MODE_RESERVED_BITS; 3420 3421 if (new_val & rsvd) 3422 return emulate_gp(ctxt, 0); 3423 3424 break; 3425 } 3426 case 4: { 3427 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3428 3429 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 3430 return emulate_gp(ctxt, 0); 3431 3432 break; 3433 } 3434 } 3435 3436 return X86EMUL_CONTINUE; 3437 } 3438 3439 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3440 { 3441 unsigned long dr7; 3442 3443 ctxt->ops->get_dr(ctxt, 7, &dr7); 3444 3445 /* Check if DR7.Global_Enable is set */ 3446 return dr7 & (1 << 13); 3447 } 3448 3449 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3450 { 3451 int dr = ctxt->modrm_reg; 3452 u64 cr4; 3453 3454 if (dr > 7) 3455 return emulate_ud(ctxt); 3456 3457 cr4 = ctxt->ops->get_cr(ctxt, 4); 3458 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3459 return emulate_ud(ctxt); 3460 3461 if (check_dr7_gd(ctxt)) 3462 return emulate_db(ctxt); 3463 3464 return X86EMUL_CONTINUE; 3465 } 3466 3467 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3468 { 3469 u64 new_val = ctxt->src.val64; 3470 int dr = ctxt->modrm_reg; 3471 3472 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3473 return emulate_gp(ctxt, 0); 3474 3475 return check_dr_read(ctxt); 3476 } 3477 3478 static int check_svme(struct x86_emulate_ctxt *ctxt) 3479 { 3480 u64 efer; 3481 3482 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3483 3484 if (!(efer & EFER_SVME)) 3485 return emulate_ud(ctxt); 3486 3487 return X86EMUL_CONTINUE; 3488 } 3489 3490 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3491 { 3492 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3493 3494 /* Valid physical address? */ 3495 if (rax & 0xffff000000000000ULL) 3496 return emulate_gp(ctxt, 0); 3497 3498 return check_svme(ctxt); 3499 } 3500 3501 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3502 { 3503 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3504 3505 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3506 return emulate_ud(ctxt); 3507 3508 return X86EMUL_CONTINUE; 3509 } 3510 3511 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3512 { 3513 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3514 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3515 3516 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3517 ctxt->ops->check_pmc(ctxt, rcx)) 3518 return emulate_gp(ctxt, 0); 3519 3520 return X86EMUL_CONTINUE; 3521 } 3522 3523 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3524 { 3525 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3526 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3527 return emulate_gp(ctxt, 0); 3528 3529 return X86EMUL_CONTINUE; 3530 } 3531 3532 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3533 { 3534 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3535 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3536 return emulate_gp(ctxt, 0); 3537 3538 return X86EMUL_CONTINUE; 3539 } 3540 3541 #define D(_y) { .flags = (_y) } 3542 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 3543 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 3544 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3545 #define N D(NotImpl) 3546 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3547 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3548 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3549 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3550 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3551 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 3552 #define II(_f, _e, _i) \ 3553 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 3554 #define IIP(_f, _e, _i, _p) \ 3555 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 3556 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3557 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3558 3559 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3560 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3561 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3562 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 3563 #define I2bvIP(_f, _e, _i, _p) \ 3564 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3565 3566 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3567 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3568 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3569 3570 static const struct opcode group7_rm0[] = { 3571 N, 3572 I(SrcNone | Priv | EmulateOnUD, em_vmcall), 3573 N, N, N, N, N, N, 3574 }; 3575 3576 static const struct opcode group7_rm1[] = { 3577 DI(SrcNone | Priv, monitor), 3578 DI(SrcNone | Priv, mwait), 3579 N, N, N, N, N, N, 3580 }; 3581 3582 static const struct opcode group7_rm3[] = { 3583 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 3584 II(SrcNone | Prot | EmulateOnUD, em_vmmcall, vmmcall), 3585 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 3586 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 3587 DIP(SrcNone | Prot | Priv, stgi, check_svme), 3588 DIP(SrcNone | Prot | Priv, clgi, check_svme), 3589 DIP(SrcNone | Prot | Priv, skinit, check_svme), 3590 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 3591 }; 3592 3593 static const struct opcode group7_rm7[] = { 3594 N, 3595 DIP(SrcNone, rdtscp, check_rdtsc), 3596 N, N, N, N, N, N, 3597 }; 3598 3599 static const struct opcode group1[] = { 3600 F(Lock, em_add), 3601 F(Lock | PageTable, em_or), 3602 F(Lock, em_adc), 3603 F(Lock, em_sbb), 3604 F(Lock | PageTable, em_and), 3605 F(Lock, em_sub), 3606 F(Lock, em_xor), 3607 F(NoWrite, em_cmp), 3608 }; 3609 3610 static const struct opcode group1A[] = { 3611 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, 3612 }; 3613 3614 static const struct opcode group2[] = { 3615 F(DstMem | ModRM, em_rol), 3616 F(DstMem | ModRM, em_ror), 3617 F(DstMem | ModRM, em_rcl), 3618 F(DstMem | ModRM, em_rcr), 3619 F(DstMem | ModRM, em_shl), 3620 F(DstMem | ModRM, em_shr), 3621 F(DstMem | ModRM, em_shl), 3622 F(DstMem | ModRM, em_sar), 3623 }; 3624 3625 static const struct opcode group3[] = { 3626 F(DstMem | SrcImm | NoWrite, em_test), 3627 F(DstMem | SrcImm | NoWrite, em_test), 3628 F(DstMem | SrcNone | Lock, em_not), 3629 F(DstMem | SrcNone | Lock, em_neg), 3630 F(DstXacc | Src2Mem, em_mul_ex), 3631 F(DstXacc | Src2Mem, em_imul_ex), 3632 F(DstXacc | Src2Mem, em_div_ex), 3633 F(DstXacc | Src2Mem, em_idiv_ex), 3634 }; 3635 3636 static const struct opcode group4[] = { 3637 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 3638 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 3639 N, N, N, N, N, N, 3640 }; 3641 3642 static const struct opcode group5[] = { 3643 F(DstMem | SrcNone | Lock, em_inc), 3644 F(DstMem | SrcNone | Lock, em_dec), 3645 I(SrcMem | Stack, em_grp45), 3646 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), 3647 I(SrcMem | Stack, em_grp45), 3648 I(SrcMemFAddr | ImplicitOps, em_grp45), 3649 I(SrcMem | Stack, em_grp45), D(Undefined), 3650 }; 3651 3652 static const struct opcode group6[] = { 3653 DI(Prot, sldt), 3654 DI(Prot, str), 3655 II(Prot | Priv | SrcMem16, em_lldt, lldt), 3656 II(Prot | Priv | SrcMem16, em_ltr, ltr), 3657 N, N, N, N, 3658 }; 3659 3660 static const struct group_dual group7 = { { 3661 II(Mov | DstMem, em_sgdt, sgdt), 3662 II(Mov | DstMem, em_sidt, sidt), 3663 II(SrcMem | Priv, em_lgdt, lgdt), 3664 II(SrcMem | Priv, em_lidt, lidt), 3665 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3666 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3667 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 3668 }, { 3669 EXT(0, group7_rm0), 3670 EXT(0, group7_rm1), 3671 N, EXT(0, group7_rm3), 3672 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3673 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3674 EXT(0, group7_rm7), 3675 } }; 3676 3677 static const struct opcode group8[] = { 3678 N, N, N, N, 3679 F(DstMem | SrcImmByte | NoWrite, em_bt), 3680 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 3681 F(DstMem | SrcImmByte | Lock, em_btr), 3682 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 3683 }; 3684 3685 static const struct group_dual group9 = { { 3686 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 3687 }, { 3688 N, N, N, N, N, N, N, N, 3689 } }; 3690 3691 static const struct opcode group11[] = { 3692 I(DstMem | SrcImm | Mov | PageTable, em_mov), 3693 X7(D(Undefined)), 3694 }; 3695 3696 static const struct gprefix pfx_0f_6f_0f_7f = { 3697 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 3698 }; 3699 3700 static const struct gprefix pfx_0f_2b = { 3701 I(0, em_mov), I(0, em_mov), N, N, 3702 }; 3703 3704 static const struct gprefix pfx_0f_28_0f_29 = { 3705 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 3706 }; 3707 3708 static const struct gprefix pfx_0f_e7 = { 3709 N, I(Sse, em_mov), N, N, 3710 }; 3711 3712 static const struct escape escape_d9 = { { 3713 N, N, N, N, N, N, N, I(DstMem, em_fnstcw), 3714 }, { 3715 /* 0xC0 - 0xC7 */ 3716 N, N, N, N, N, N, N, N, 3717 /* 0xC8 - 0xCF */ 3718 N, N, N, N, N, N, N, N, 3719 /* 0xD0 - 0xC7 */ 3720 N, N, N, N, N, N, N, N, 3721 /* 0xD8 - 0xDF */ 3722 N, N, N, N, N, N, N, N, 3723 /* 0xE0 - 0xE7 */ 3724 N, N, N, N, N, N, N, N, 3725 /* 0xE8 - 0xEF */ 3726 N, N, N, N, N, N, N, N, 3727 /* 0xF0 - 0xF7 */ 3728 N, N, N, N, N, N, N, N, 3729 /* 0xF8 - 0xFF */ 3730 N, N, N, N, N, N, N, N, 3731 } }; 3732 3733 static const struct escape escape_db = { { 3734 N, N, N, N, N, N, N, N, 3735 }, { 3736 /* 0xC0 - 0xC7 */ 3737 N, N, N, N, N, N, N, N, 3738 /* 0xC8 - 0xCF */ 3739 N, N, N, N, N, N, N, N, 3740 /* 0xD0 - 0xC7 */ 3741 N, N, N, N, N, N, N, N, 3742 /* 0xD8 - 0xDF */ 3743 N, N, N, N, N, N, N, N, 3744 /* 0xE0 - 0xE7 */ 3745 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 3746 /* 0xE8 - 0xEF */ 3747 N, N, N, N, N, N, N, N, 3748 /* 0xF0 - 0xF7 */ 3749 N, N, N, N, N, N, N, N, 3750 /* 0xF8 - 0xFF */ 3751 N, N, N, N, N, N, N, N, 3752 } }; 3753 3754 static const struct escape escape_dd = { { 3755 N, N, N, N, N, N, N, I(DstMem, em_fnstsw), 3756 }, { 3757 /* 0xC0 - 0xC7 */ 3758 N, N, N, N, N, N, N, N, 3759 /* 0xC8 - 0xCF */ 3760 N, N, N, N, N, N, N, N, 3761 /* 0xD0 - 0xC7 */ 3762 N, N, N, N, N, N, N, N, 3763 /* 0xD8 - 0xDF */ 3764 N, N, N, N, N, N, N, N, 3765 /* 0xE0 - 0xE7 */ 3766 N, N, N, N, N, N, N, N, 3767 /* 0xE8 - 0xEF */ 3768 N, N, N, N, N, N, N, N, 3769 /* 0xF0 - 0xF7 */ 3770 N, N, N, N, N, N, N, N, 3771 /* 0xF8 - 0xFF */ 3772 N, N, N, N, N, N, N, N, 3773 } }; 3774 3775 static const struct opcode opcode_table[256] = { 3776 /* 0x00 - 0x07 */ 3777 F6ALU(Lock, em_add), 3778 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 3779 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 3780 /* 0x08 - 0x0F */ 3781 F6ALU(Lock | PageTable, em_or), 3782 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 3783 N, 3784 /* 0x10 - 0x17 */ 3785 F6ALU(Lock, em_adc), 3786 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 3787 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 3788 /* 0x18 - 0x1F */ 3789 F6ALU(Lock, em_sbb), 3790 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 3791 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 3792 /* 0x20 - 0x27 */ 3793 F6ALU(Lock | PageTable, em_and), N, N, 3794 /* 0x28 - 0x2F */ 3795 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 3796 /* 0x30 - 0x37 */ 3797 F6ALU(Lock, em_xor), N, N, 3798 /* 0x38 - 0x3F */ 3799 F6ALU(NoWrite, em_cmp), N, N, 3800 /* 0x40 - 0x4F */ 3801 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 3802 /* 0x50 - 0x57 */ 3803 X8(I(SrcReg | Stack, em_push)), 3804 /* 0x58 - 0x5F */ 3805 X8(I(DstReg | Stack, em_pop)), 3806 /* 0x60 - 0x67 */ 3807 I(ImplicitOps | Stack | No64, em_pusha), 3808 I(ImplicitOps | Stack | No64, em_popa), 3809 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , 3810 N, N, N, N, 3811 /* 0x68 - 0x6F */ 3812 I(SrcImm | Mov | Stack, em_push), 3813 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 3814 I(SrcImmByte | Mov | Stack, em_push), 3815 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 3816 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 3817 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 3818 /* 0x70 - 0x7F */ 3819 X16(D(SrcImmByte)), 3820 /* 0x80 - 0x87 */ 3821 G(ByteOp | DstMem | SrcImm, group1), 3822 G(DstMem | SrcImm, group1), 3823 G(ByteOp | DstMem | SrcImm | No64, group1), 3824 G(DstMem | SrcImmByte, group1), 3825 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 3826 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 3827 /* 0x88 - 0x8F */ 3828 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 3829 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 3830 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 3831 D(ModRM | SrcMem | NoAccess | DstReg), 3832 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 3833 G(0, group1A), 3834 /* 0x90 - 0x97 */ 3835 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 3836 /* 0x98 - 0x9F */ 3837 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 3838 I(SrcImmFAddr | No64, em_call_far), N, 3839 II(ImplicitOps | Stack, em_pushf, pushf), 3840 II(ImplicitOps | Stack, em_popf, popf), 3841 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 3842 /* 0xA0 - 0xA7 */ 3843 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 3844 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 3845 I2bv(SrcSI | DstDI | Mov | String, em_mov), 3846 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp), 3847 /* 0xA8 - 0xAF */ 3848 F2bv(DstAcc | SrcImm | NoWrite, em_test), 3849 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 3850 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 3851 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp), 3852 /* 0xB0 - 0xB7 */ 3853 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 3854 /* 0xB8 - 0xBF */ 3855 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 3856 /* 0xC0 - 0xC7 */ 3857 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 3858 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), 3859 I(ImplicitOps | Stack, em_ret), 3860 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 3861 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 3862 G(ByteOp, group11), G(0, group11), 3863 /* 0xC8 - 0xCF */ 3864 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 3865 I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm), 3866 I(ImplicitOps | Stack, em_ret_far), 3867 D(ImplicitOps), DI(SrcImmByte, intn), 3868 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 3869 /* 0xD0 - 0xD7 */ 3870 G(Src2One | ByteOp, group2), G(Src2One, group2), 3871 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 3872 I(DstAcc | SrcImmUByte | No64, em_aam), 3873 I(DstAcc | SrcImmUByte | No64, em_aad), 3874 F(DstAcc | ByteOp | No64, em_salc), 3875 I(DstAcc | SrcXLat | ByteOp, em_mov), 3876 /* 0xD8 - 0xDF */ 3877 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 3878 /* 0xE0 - 0xE7 */ 3879 X3(I(SrcImmByte, em_loop)), 3880 I(SrcImmByte, em_jcxz), 3881 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 3882 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 3883 /* 0xE8 - 0xEF */ 3884 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), 3885 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), 3886 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 3887 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 3888 /* 0xF0 - 0xF7 */ 3889 N, DI(ImplicitOps, icebp), N, N, 3890 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 3891 G(ByteOp, group3), G(0, group3), 3892 /* 0xF8 - 0xFF */ 3893 D(ImplicitOps), D(ImplicitOps), 3894 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 3895 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 3896 }; 3897 3898 static const struct opcode twobyte_table[256] = { 3899 /* 0x00 - 0x0F */ 3900 G(0, group6), GD(0, &group7), N, N, 3901 N, I(ImplicitOps | EmulateOnUD, em_syscall), 3902 II(ImplicitOps | Priv, em_clts, clts), N, 3903 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 3904 N, D(ImplicitOps | ModRM), N, N, 3905 /* 0x10 - 0x1F */ 3906 N, N, N, N, N, N, N, N, 3907 D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM), 3908 /* 0x20 - 0x2F */ 3909 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 3910 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 3911 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 3912 check_cr_write), 3913 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 3914 check_dr_write), 3915 N, N, N, N, 3916 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 3917 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 3918 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 3919 N, N, N, N, 3920 /* 0x30 - 0x3F */ 3921 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 3922 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 3923 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 3924 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 3925 I(ImplicitOps | EmulateOnUD, em_sysenter), 3926 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 3927 N, N, 3928 N, N, N, N, N, N, N, N, 3929 /* 0x40 - 0x4F */ 3930 X16(D(DstReg | SrcMem | ModRM)), 3931 /* 0x50 - 0x5F */ 3932 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3933 /* 0x60 - 0x6F */ 3934 N, N, N, N, 3935 N, N, N, N, 3936 N, N, N, N, 3937 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 3938 /* 0x70 - 0x7F */ 3939 N, N, N, N, 3940 N, N, N, N, 3941 N, N, N, N, 3942 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 3943 /* 0x80 - 0x8F */ 3944 X16(D(SrcImm)), 3945 /* 0x90 - 0x9F */ 3946 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 3947 /* 0xA0 - 0xA7 */ 3948 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 3949 II(ImplicitOps, em_cpuid, cpuid), 3950 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 3951 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 3952 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 3953 /* 0xA8 - 0xAF */ 3954 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 3955 DI(ImplicitOps, rsm), 3956 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 3957 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 3958 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 3959 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul), 3960 /* 0xB0 - 0xB7 */ 3961 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), 3962 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 3963 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 3964 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 3965 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 3966 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3967 /* 0xB8 - 0xBF */ 3968 N, N, 3969 G(BitOp, group8), 3970 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 3971 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr), 3972 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3973 /* 0xC0 - 0xC7 */ 3974 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 3975 N, D(DstMem | SrcReg | ModRM | Mov), 3976 N, N, N, GD(0, &group9), 3977 /* 0xC8 - 0xCF */ 3978 X8(I(DstReg, em_bswap)), 3979 /* 0xD0 - 0xDF */ 3980 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3981 /* 0xE0 - 0xEF */ 3982 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 3983 N, N, N, N, N, N, N, N, 3984 /* 0xF0 - 0xFF */ 3985 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 3986 }; 3987 3988 static const struct gprefix three_byte_0f_38_f0 = { 3989 I(DstReg | SrcMem | Mov, em_movbe), N, N, N 3990 }; 3991 3992 static const struct gprefix three_byte_0f_38_f1 = { 3993 I(DstMem | SrcReg | Mov, em_movbe), N, N, N 3994 }; 3995 3996 /* 3997 * Insns below are selected by the prefix which indexed by the third opcode 3998 * byte. 3999 */ 4000 static const struct opcode opcode_map_0f_38[256] = { 4001 /* 0x00 - 0x7f */ 4002 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4003 /* 0x80 - 0xef */ 4004 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4005 /* 0xf0 - 0xf1 */ 4006 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0), 4007 GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1), 4008 /* 0xf2 - 0xff */ 4009 N, N, X4(N), X8(N) 4010 }; 4011 4012 #undef D 4013 #undef N 4014 #undef G 4015 #undef GD 4016 #undef I 4017 #undef GP 4018 #undef EXT 4019 4020 #undef D2bv 4021 #undef D2bvIP 4022 #undef I2bv 4023 #undef I2bvIP 4024 #undef I6ALU 4025 4026 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4027 { 4028 unsigned size; 4029 4030 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4031 if (size == 8) 4032 size = 4; 4033 return size; 4034 } 4035 4036 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4037 unsigned size, bool sign_extension) 4038 { 4039 int rc = X86EMUL_CONTINUE; 4040 4041 op->type = OP_IMM; 4042 op->bytes = size; 4043 op->addr.mem.ea = ctxt->_eip; 4044 /* NB. Immediates are sign-extended as necessary. */ 4045 switch (op->bytes) { 4046 case 1: 4047 op->val = insn_fetch(s8, ctxt); 4048 break; 4049 case 2: 4050 op->val = insn_fetch(s16, ctxt); 4051 break; 4052 case 4: 4053 op->val = insn_fetch(s32, ctxt); 4054 break; 4055 case 8: 4056 op->val = insn_fetch(s64, ctxt); 4057 break; 4058 } 4059 if (!sign_extension) { 4060 switch (op->bytes) { 4061 case 1: 4062 op->val &= 0xff; 4063 break; 4064 case 2: 4065 op->val &= 0xffff; 4066 break; 4067 case 4: 4068 op->val &= 0xffffffff; 4069 break; 4070 } 4071 } 4072 done: 4073 return rc; 4074 } 4075 4076 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4077 unsigned d) 4078 { 4079 int rc = X86EMUL_CONTINUE; 4080 4081 switch (d) { 4082 case OpReg: 4083 decode_register_operand(ctxt, op); 4084 break; 4085 case OpImmUByte: 4086 rc = decode_imm(ctxt, op, 1, false); 4087 break; 4088 case OpMem: 4089 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4090 mem_common: 4091 *op = ctxt->memop; 4092 ctxt->memopp = op; 4093 if (ctxt->d & BitOp) 4094 fetch_bit_operand(ctxt); 4095 op->orig_val = op->val; 4096 break; 4097 case OpMem64: 4098 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4099 goto mem_common; 4100 case OpAcc: 4101 op->type = OP_REG; 4102 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4103 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4104 fetch_register_operand(op); 4105 op->orig_val = op->val; 4106 break; 4107 case OpAccLo: 4108 op->type = OP_REG; 4109 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4110 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4111 fetch_register_operand(op); 4112 op->orig_val = op->val; 4113 break; 4114 case OpAccHi: 4115 if (ctxt->d & ByteOp) { 4116 op->type = OP_NONE; 4117 break; 4118 } 4119 op->type = OP_REG; 4120 op->bytes = ctxt->op_bytes; 4121 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4122 fetch_register_operand(op); 4123 op->orig_val = op->val; 4124 break; 4125 case OpDI: 4126 op->type = OP_MEM; 4127 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4128 op->addr.mem.ea = 4129 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI)); 4130 op->addr.mem.seg = VCPU_SREG_ES; 4131 op->val = 0; 4132 op->count = 1; 4133 break; 4134 case OpDX: 4135 op->type = OP_REG; 4136 op->bytes = 2; 4137 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4138 fetch_register_operand(op); 4139 break; 4140 case OpCL: 4141 op->bytes = 1; 4142 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4143 break; 4144 case OpImmByte: 4145 rc = decode_imm(ctxt, op, 1, true); 4146 break; 4147 case OpOne: 4148 op->bytes = 1; 4149 op->val = 1; 4150 break; 4151 case OpImm: 4152 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4153 break; 4154 case OpImm64: 4155 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4156 break; 4157 case OpMem8: 4158 ctxt->memop.bytes = 1; 4159 if (ctxt->memop.type == OP_REG) { 4160 ctxt->memop.addr.reg = decode_register(ctxt, 4161 ctxt->modrm_rm, true); 4162 fetch_register_operand(&ctxt->memop); 4163 } 4164 goto mem_common; 4165 case OpMem16: 4166 ctxt->memop.bytes = 2; 4167 goto mem_common; 4168 case OpMem32: 4169 ctxt->memop.bytes = 4; 4170 goto mem_common; 4171 case OpImmU16: 4172 rc = decode_imm(ctxt, op, 2, false); 4173 break; 4174 case OpImmU: 4175 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4176 break; 4177 case OpSI: 4178 op->type = OP_MEM; 4179 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4180 op->addr.mem.ea = 4181 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI)); 4182 op->addr.mem.seg = ctxt->seg_override; 4183 op->val = 0; 4184 op->count = 1; 4185 break; 4186 case OpXLat: 4187 op->type = OP_MEM; 4188 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4189 op->addr.mem.ea = 4190 register_address(ctxt, 4191 reg_read(ctxt, VCPU_REGS_RBX) + 4192 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4193 op->addr.mem.seg = ctxt->seg_override; 4194 op->val = 0; 4195 break; 4196 case OpImmFAddr: 4197 op->type = OP_IMM; 4198 op->addr.mem.ea = ctxt->_eip; 4199 op->bytes = ctxt->op_bytes + 2; 4200 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4201 break; 4202 case OpMemFAddr: 4203 ctxt->memop.bytes = ctxt->op_bytes + 2; 4204 goto mem_common; 4205 case OpES: 4206 op->val = VCPU_SREG_ES; 4207 break; 4208 case OpCS: 4209 op->val = VCPU_SREG_CS; 4210 break; 4211 case OpSS: 4212 op->val = VCPU_SREG_SS; 4213 break; 4214 case OpDS: 4215 op->val = VCPU_SREG_DS; 4216 break; 4217 case OpFS: 4218 op->val = VCPU_SREG_FS; 4219 break; 4220 case OpGS: 4221 op->val = VCPU_SREG_GS; 4222 break; 4223 case OpImplicit: 4224 /* Special instructions do their own operand decoding. */ 4225 default: 4226 op->type = OP_NONE; /* Disable writeback. */ 4227 break; 4228 } 4229 4230 done: 4231 return rc; 4232 } 4233 4234 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 4235 { 4236 int rc = X86EMUL_CONTINUE; 4237 int mode = ctxt->mode; 4238 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4239 bool op_prefix = false; 4240 bool has_seg_override = false; 4241 struct opcode opcode; 4242 4243 ctxt->memop.type = OP_NONE; 4244 ctxt->memopp = NULL; 4245 ctxt->_eip = ctxt->eip; 4246 ctxt->fetch.ptr = ctxt->fetch.data; 4247 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4248 ctxt->opcode_len = 1; 4249 if (insn_len > 0) 4250 memcpy(ctxt->fetch.data, insn, insn_len); 4251 else { 4252 rc = __do_insn_fetch_bytes(ctxt, 1); 4253 if (rc != X86EMUL_CONTINUE) 4254 return rc; 4255 } 4256 4257 switch (mode) { 4258 case X86EMUL_MODE_REAL: 4259 case X86EMUL_MODE_VM86: 4260 case X86EMUL_MODE_PROT16: 4261 def_op_bytes = def_ad_bytes = 2; 4262 break; 4263 case X86EMUL_MODE_PROT32: 4264 def_op_bytes = def_ad_bytes = 4; 4265 break; 4266 #ifdef CONFIG_X86_64 4267 case X86EMUL_MODE_PROT64: 4268 def_op_bytes = 4; 4269 def_ad_bytes = 8; 4270 break; 4271 #endif 4272 default: 4273 return EMULATION_FAILED; 4274 } 4275 4276 ctxt->op_bytes = def_op_bytes; 4277 ctxt->ad_bytes = def_ad_bytes; 4278 4279 /* Legacy prefixes. */ 4280 for (;;) { 4281 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4282 case 0x66: /* operand-size override */ 4283 op_prefix = true; 4284 /* switch between 2/4 bytes */ 4285 ctxt->op_bytes = def_op_bytes ^ 6; 4286 break; 4287 case 0x67: /* address-size override */ 4288 if (mode == X86EMUL_MODE_PROT64) 4289 /* switch between 4/8 bytes */ 4290 ctxt->ad_bytes = def_ad_bytes ^ 12; 4291 else 4292 /* switch between 2/4 bytes */ 4293 ctxt->ad_bytes = def_ad_bytes ^ 6; 4294 break; 4295 case 0x26: /* ES override */ 4296 case 0x2e: /* CS override */ 4297 case 0x36: /* SS override */ 4298 case 0x3e: /* DS override */ 4299 has_seg_override = true; 4300 ctxt->seg_override = (ctxt->b >> 3) & 3; 4301 break; 4302 case 0x64: /* FS override */ 4303 case 0x65: /* GS override */ 4304 has_seg_override = true; 4305 ctxt->seg_override = ctxt->b & 7; 4306 break; 4307 case 0x40 ... 0x4f: /* REX */ 4308 if (mode != X86EMUL_MODE_PROT64) 4309 goto done_prefixes; 4310 ctxt->rex_prefix = ctxt->b; 4311 continue; 4312 case 0xf0: /* LOCK */ 4313 ctxt->lock_prefix = 1; 4314 break; 4315 case 0xf2: /* REPNE/REPNZ */ 4316 case 0xf3: /* REP/REPE/REPZ */ 4317 ctxt->rep_prefix = ctxt->b; 4318 break; 4319 default: 4320 goto done_prefixes; 4321 } 4322 4323 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4324 4325 ctxt->rex_prefix = 0; 4326 } 4327 4328 done_prefixes: 4329 4330 /* REX prefix. */ 4331 if (ctxt->rex_prefix & 8) 4332 ctxt->op_bytes = 8; /* REX.W */ 4333 4334 /* Opcode byte(s). */ 4335 opcode = opcode_table[ctxt->b]; 4336 /* Two-byte opcode? */ 4337 if (ctxt->b == 0x0f) { 4338 ctxt->opcode_len = 2; 4339 ctxt->b = insn_fetch(u8, ctxt); 4340 opcode = twobyte_table[ctxt->b]; 4341 4342 /* 0F_38 opcode map */ 4343 if (ctxt->b == 0x38) { 4344 ctxt->opcode_len = 3; 4345 ctxt->b = insn_fetch(u8, ctxt); 4346 opcode = opcode_map_0f_38[ctxt->b]; 4347 } 4348 } 4349 ctxt->d = opcode.flags; 4350 4351 if (ctxt->d & ModRM) 4352 ctxt->modrm = insn_fetch(u8, ctxt); 4353 4354 /* vex-prefix instructions are not implemented */ 4355 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 4356 (mode == X86EMUL_MODE_PROT64 || 4357 (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) { 4358 ctxt->d = NotImpl; 4359 } 4360 4361 while (ctxt->d & GroupMask) { 4362 switch (ctxt->d & GroupMask) { 4363 case Group: 4364 goffset = (ctxt->modrm >> 3) & 7; 4365 opcode = opcode.u.group[goffset]; 4366 break; 4367 case GroupDual: 4368 goffset = (ctxt->modrm >> 3) & 7; 4369 if ((ctxt->modrm >> 6) == 3) 4370 opcode = opcode.u.gdual->mod3[goffset]; 4371 else 4372 opcode = opcode.u.gdual->mod012[goffset]; 4373 break; 4374 case RMExt: 4375 goffset = ctxt->modrm & 7; 4376 opcode = opcode.u.group[goffset]; 4377 break; 4378 case Prefix: 4379 if (ctxt->rep_prefix && op_prefix) 4380 return EMULATION_FAILED; 4381 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4382 switch (simd_prefix) { 4383 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4384 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4385 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4386 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4387 } 4388 break; 4389 case Escape: 4390 if (ctxt->modrm > 0xbf) 4391 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 4392 else 4393 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4394 break; 4395 default: 4396 return EMULATION_FAILED; 4397 } 4398 4399 ctxt->d &= ~(u64)GroupMask; 4400 ctxt->d |= opcode.flags; 4401 } 4402 4403 /* Unrecognised? */ 4404 if (ctxt->d == 0) 4405 return EMULATION_FAILED; 4406 4407 ctxt->execute = opcode.u.execute; 4408 4409 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 4410 return EMULATION_FAILED; 4411 4412 if (unlikely(ctxt->d & 4413 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) { 4414 /* 4415 * These are copied unconditionally here, and checked unconditionally 4416 * in x86_emulate_insn. 4417 */ 4418 ctxt->check_perm = opcode.check_perm; 4419 ctxt->intercept = opcode.intercept; 4420 4421 if (ctxt->d & NotImpl) 4422 return EMULATION_FAILED; 4423 4424 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) 4425 ctxt->op_bytes = 8; 4426 4427 if (ctxt->d & Op3264) { 4428 if (mode == X86EMUL_MODE_PROT64) 4429 ctxt->op_bytes = 8; 4430 else 4431 ctxt->op_bytes = 4; 4432 } 4433 4434 if (ctxt->d & Sse) 4435 ctxt->op_bytes = 16; 4436 else if (ctxt->d & Mmx) 4437 ctxt->op_bytes = 8; 4438 } 4439 4440 /* ModRM and SIB bytes. */ 4441 if (ctxt->d & ModRM) { 4442 rc = decode_modrm(ctxt, &ctxt->memop); 4443 if (!has_seg_override) { 4444 has_seg_override = true; 4445 ctxt->seg_override = ctxt->modrm_seg; 4446 } 4447 } else if (ctxt->d & MemAbs) 4448 rc = decode_abs(ctxt, &ctxt->memop); 4449 if (rc != X86EMUL_CONTINUE) 4450 goto done; 4451 4452 if (!has_seg_override) 4453 ctxt->seg_override = VCPU_SREG_DS; 4454 4455 ctxt->memop.addr.mem.seg = ctxt->seg_override; 4456 4457 /* 4458 * Decode and fetch the source operand: register, memory 4459 * or immediate. 4460 */ 4461 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 4462 if (rc != X86EMUL_CONTINUE) 4463 goto done; 4464 4465 /* 4466 * Decode and fetch the second source operand: register, memory 4467 * or immediate. 4468 */ 4469 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 4470 if (rc != X86EMUL_CONTINUE) 4471 goto done; 4472 4473 /* Decode and fetch the destination operand: register or memory. */ 4474 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 4475 4476 done: 4477 if (ctxt->rip_relative) 4478 ctxt->memopp->addr.mem.ea += ctxt->_eip; 4479 4480 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 4481 } 4482 4483 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 4484 { 4485 return ctxt->d & PageTable; 4486 } 4487 4488 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 4489 { 4490 /* The second termination condition only applies for REPE 4491 * and REPNE. Test if the repeat string operation prefix is 4492 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 4493 * corresponding termination condition according to: 4494 * - if REPE/REPZ and ZF = 0 then done 4495 * - if REPNE/REPNZ and ZF = 1 then done 4496 */ 4497 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 4498 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 4499 && (((ctxt->rep_prefix == REPE_PREFIX) && 4500 ((ctxt->eflags & EFLG_ZF) == 0)) 4501 || ((ctxt->rep_prefix == REPNE_PREFIX) && 4502 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) 4503 return true; 4504 4505 return false; 4506 } 4507 4508 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 4509 { 4510 bool fault = false; 4511 4512 ctxt->ops->get_fpu(ctxt); 4513 asm volatile("1: fwait \n\t" 4514 "2: \n\t" 4515 ".pushsection .fixup,\"ax\" \n\t" 4516 "3: \n\t" 4517 "movb $1, %[fault] \n\t" 4518 "jmp 2b \n\t" 4519 ".popsection \n\t" 4520 _ASM_EXTABLE(1b, 3b) 4521 : [fault]"+qm"(fault)); 4522 ctxt->ops->put_fpu(ctxt); 4523 4524 if (unlikely(fault)) 4525 return emulate_exception(ctxt, MF_VECTOR, 0, false); 4526 4527 return X86EMUL_CONTINUE; 4528 } 4529 4530 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 4531 struct operand *op) 4532 { 4533 if (op->type == OP_MM) 4534 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 4535 } 4536 4537 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 4538 { 4539 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 4540 if (!(ctxt->d & ByteOp)) 4541 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 4542 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" 4543 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 4544 [fastop]"+S"(fop) 4545 : "c"(ctxt->src2.val)); 4546 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 4547 if (!fop) /* exception is returned in fop variable */ 4548 return emulate_de(ctxt); 4549 return X86EMUL_CONTINUE; 4550 } 4551 4552 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 4553 { 4554 memset(&ctxt->rip_relative, 0, 4555 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 4556 4557 ctxt->io_read.pos = 0; 4558 ctxt->io_read.end = 0; 4559 ctxt->mem_read.end = 0; 4560 } 4561 4562 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 4563 { 4564 const struct x86_emulate_ops *ops = ctxt->ops; 4565 int rc = X86EMUL_CONTINUE; 4566 int saved_dst_type = ctxt->dst.type; 4567 4568 ctxt->mem_read.pos = 0; 4569 4570 /* LOCK prefix is allowed only with some instructions */ 4571 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 4572 rc = emulate_ud(ctxt); 4573 goto done; 4574 } 4575 4576 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 4577 rc = emulate_ud(ctxt); 4578 goto done; 4579 } 4580 4581 if (unlikely(ctxt->d & 4582 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 4583 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 4584 (ctxt->d & Undefined)) { 4585 rc = emulate_ud(ctxt); 4586 goto done; 4587 } 4588 4589 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 4590 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 4591 rc = emulate_ud(ctxt); 4592 goto done; 4593 } 4594 4595 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 4596 rc = emulate_nm(ctxt); 4597 goto done; 4598 } 4599 4600 if (ctxt->d & Mmx) { 4601 rc = flush_pending_x87_faults(ctxt); 4602 if (rc != X86EMUL_CONTINUE) 4603 goto done; 4604 /* 4605 * Now that we know the fpu is exception safe, we can fetch 4606 * operands from it. 4607 */ 4608 fetch_possible_mmx_operand(ctxt, &ctxt->src); 4609 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 4610 if (!(ctxt->d & Mov)) 4611 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 4612 } 4613 4614 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { 4615 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4616 X86_ICPT_PRE_EXCEPT); 4617 if (rc != X86EMUL_CONTINUE) 4618 goto done; 4619 } 4620 4621 /* Privileged instruction can be executed only in CPL=0 */ 4622 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 4623 if (ctxt->d & PrivUD) 4624 rc = emulate_ud(ctxt); 4625 else 4626 rc = emulate_gp(ctxt, 0); 4627 goto done; 4628 } 4629 4630 /* Instruction can only be executed in protected mode */ 4631 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 4632 rc = emulate_ud(ctxt); 4633 goto done; 4634 } 4635 4636 /* Do instruction specific permission checks */ 4637 if (ctxt->d & CheckPerm) { 4638 rc = ctxt->check_perm(ctxt); 4639 if (rc != X86EMUL_CONTINUE) 4640 goto done; 4641 } 4642 4643 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { 4644 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4645 X86_ICPT_POST_EXCEPT); 4646 if (rc != X86EMUL_CONTINUE) 4647 goto done; 4648 } 4649 4650 if (ctxt->rep_prefix && (ctxt->d & String)) { 4651 /* All REP prefixes have the same first termination condition */ 4652 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 4653 ctxt->eip = ctxt->_eip; 4654 ctxt->eflags &= ~EFLG_RF; 4655 goto done; 4656 } 4657 } 4658 } 4659 4660 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 4661 rc = segmented_read(ctxt, ctxt->src.addr.mem, 4662 ctxt->src.valptr, ctxt->src.bytes); 4663 if (rc != X86EMUL_CONTINUE) 4664 goto done; 4665 ctxt->src.orig_val64 = ctxt->src.val64; 4666 } 4667 4668 if (ctxt->src2.type == OP_MEM) { 4669 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 4670 &ctxt->src2.val, ctxt->src2.bytes); 4671 if (rc != X86EMUL_CONTINUE) 4672 goto done; 4673 } 4674 4675 if ((ctxt->d & DstMask) == ImplicitOps) 4676 goto special_insn; 4677 4678 4679 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 4680 /* optimisation - avoid slow emulated read if Mov */ 4681 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 4682 &ctxt->dst.val, ctxt->dst.bytes); 4683 if (rc != X86EMUL_CONTINUE) 4684 goto done; 4685 } 4686 ctxt->dst.orig_val = ctxt->dst.val; 4687 4688 special_insn: 4689 4690 if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) { 4691 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4692 X86_ICPT_POST_MEMACCESS); 4693 if (rc != X86EMUL_CONTINUE) 4694 goto done; 4695 } 4696 4697 if (ctxt->rep_prefix && (ctxt->d & String)) 4698 ctxt->eflags |= EFLG_RF; 4699 else 4700 ctxt->eflags &= ~EFLG_RF; 4701 4702 if (ctxt->execute) { 4703 if (ctxt->d & Fastop) { 4704 void (*fop)(struct fastop *) = (void *)ctxt->execute; 4705 rc = fastop(ctxt, fop); 4706 if (rc != X86EMUL_CONTINUE) 4707 goto done; 4708 goto writeback; 4709 } 4710 rc = ctxt->execute(ctxt); 4711 if (rc != X86EMUL_CONTINUE) 4712 goto done; 4713 goto writeback; 4714 } 4715 4716 if (ctxt->opcode_len == 2) 4717 goto twobyte_insn; 4718 else if (ctxt->opcode_len == 3) 4719 goto threebyte_insn; 4720 4721 switch (ctxt->b) { 4722 case 0x63: /* movsxd */ 4723 if (ctxt->mode != X86EMUL_MODE_PROT64) 4724 goto cannot_emulate; 4725 ctxt->dst.val = (s32) ctxt->src.val; 4726 break; 4727 case 0x70 ... 0x7f: /* jcc (short) */ 4728 if (test_cc(ctxt->b, ctxt->eflags)) 4729 jmp_rel(ctxt, ctxt->src.val); 4730 break; 4731 case 0x8d: /* lea r16/r32, m */ 4732 ctxt->dst.val = ctxt->src.addr.mem.ea; 4733 break; 4734 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 4735 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 4736 ctxt->dst.type = OP_NONE; 4737 else 4738 rc = em_xchg(ctxt); 4739 break; 4740 case 0x98: /* cbw/cwde/cdqe */ 4741 switch (ctxt->op_bytes) { 4742 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 4743 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 4744 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 4745 } 4746 break; 4747 case 0xcc: /* int3 */ 4748 rc = emulate_int(ctxt, 3); 4749 break; 4750 case 0xcd: /* int n */ 4751 rc = emulate_int(ctxt, ctxt->src.val); 4752 break; 4753 case 0xce: /* into */ 4754 if (ctxt->eflags & EFLG_OF) 4755 rc = emulate_int(ctxt, 4); 4756 break; 4757 case 0xe9: /* jmp rel */ 4758 case 0xeb: /* jmp rel short */ 4759 jmp_rel(ctxt, ctxt->src.val); 4760 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 4761 break; 4762 case 0xf4: /* hlt */ 4763 ctxt->ops->halt(ctxt); 4764 break; 4765 case 0xf5: /* cmc */ 4766 /* complement carry flag from eflags reg */ 4767 ctxt->eflags ^= EFLG_CF; 4768 break; 4769 case 0xf8: /* clc */ 4770 ctxt->eflags &= ~EFLG_CF; 4771 break; 4772 case 0xf9: /* stc */ 4773 ctxt->eflags |= EFLG_CF; 4774 break; 4775 case 0xfc: /* cld */ 4776 ctxt->eflags &= ~EFLG_DF; 4777 break; 4778 case 0xfd: /* std */ 4779 ctxt->eflags |= EFLG_DF; 4780 break; 4781 default: 4782 goto cannot_emulate; 4783 } 4784 4785 if (rc != X86EMUL_CONTINUE) 4786 goto done; 4787 4788 writeback: 4789 if (ctxt->d & SrcWrite) { 4790 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 4791 rc = writeback(ctxt, &ctxt->src); 4792 if (rc != X86EMUL_CONTINUE) 4793 goto done; 4794 } 4795 if (!(ctxt->d & NoWrite)) { 4796 rc = writeback(ctxt, &ctxt->dst); 4797 if (rc != X86EMUL_CONTINUE) 4798 goto done; 4799 } 4800 4801 /* 4802 * restore dst type in case the decoding will be reused 4803 * (happens for string instruction ) 4804 */ 4805 ctxt->dst.type = saved_dst_type; 4806 4807 if ((ctxt->d & SrcMask) == SrcSI) 4808 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 4809 4810 if ((ctxt->d & DstMask) == DstDI) 4811 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 4812 4813 if (ctxt->rep_prefix && (ctxt->d & String)) { 4814 unsigned int count; 4815 struct read_cache *r = &ctxt->io_read; 4816 if ((ctxt->d & SrcMask) == SrcSI) 4817 count = ctxt->src.count; 4818 else 4819 count = ctxt->dst.count; 4820 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), 4821 -count); 4822 4823 if (!string_insn_completed(ctxt)) { 4824 /* 4825 * Re-enter guest when pio read ahead buffer is empty 4826 * or, if it is not used, after each 1024 iteration. 4827 */ 4828 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 4829 (r->end == 0 || r->end != r->pos)) { 4830 /* 4831 * Reset read cache. Usually happens before 4832 * decode, but since instruction is restarted 4833 * we have to do it here. 4834 */ 4835 ctxt->mem_read.end = 0; 4836 writeback_registers(ctxt); 4837 return EMULATION_RESTART; 4838 } 4839 goto done; /* skip rip writeback */ 4840 } 4841 ctxt->eflags &= ~EFLG_RF; 4842 } 4843 4844 ctxt->eip = ctxt->_eip; 4845 4846 done: 4847 if (rc == X86EMUL_PROPAGATE_FAULT) { 4848 WARN_ON(ctxt->exception.vector > 0x1f); 4849 ctxt->have_exception = true; 4850 } 4851 if (rc == X86EMUL_INTERCEPTED) 4852 return EMULATION_INTERCEPTED; 4853 4854 if (rc == X86EMUL_CONTINUE) 4855 writeback_registers(ctxt); 4856 4857 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 4858 4859 twobyte_insn: 4860 switch (ctxt->b) { 4861 case 0x09: /* wbinvd */ 4862 (ctxt->ops->wbinvd)(ctxt); 4863 break; 4864 case 0x08: /* invd */ 4865 case 0x0d: /* GrpP (prefetch) */ 4866 case 0x18: /* Grp16 (prefetch/nop) */ 4867 case 0x1f: /* nop */ 4868 break; 4869 case 0x20: /* mov cr, reg */ 4870 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 4871 break; 4872 case 0x21: /* mov from dr to reg */ 4873 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 4874 break; 4875 case 0x40 ... 0x4f: /* cmov */ 4876 if (test_cc(ctxt->b, ctxt->eflags)) 4877 ctxt->dst.val = ctxt->src.val; 4878 else if (ctxt->mode != X86EMUL_MODE_PROT64 || 4879 ctxt->op_bytes != 4) 4880 ctxt->dst.type = OP_NONE; /* no writeback */ 4881 break; 4882 case 0x80 ... 0x8f: /* jnz rel, etc*/ 4883 if (test_cc(ctxt->b, ctxt->eflags)) 4884 jmp_rel(ctxt, ctxt->src.val); 4885 break; 4886 case 0x90 ... 0x9f: /* setcc r/m8 */ 4887 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 4888 break; 4889 case 0xae: /* clflush */ 4890 break; 4891 case 0xb6 ... 0xb7: /* movzx */ 4892 ctxt->dst.bytes = ctxt->op_bytes; 4893 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 4894 : (u16) ctxt->src.val; 4895 break; 4896 case 0xbe ... 0xbf: /* movsx */ 4897 ctxt->dst.bytes = ctxt->op_bytes; 4898 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 4899 (s16) ctxt->src.val; 4900 break; 4901 case 0xc3: /* movnti */ 4902 ctxt->dst.bytes = ctxt->op_bytes; 4903 ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val : 4904 (u32) ctxt->src.val; 4905 break; 4906 default: 4907 goto cannot_emulate; 4908 } 4909 4910 threebyte_insn: 4911 4912 if (rc != X86EMUL_CONTINUE) 4913 goto done; 4914 4915 goto writeback; 4916 4917 cannot_emulate: 4918 return EMULATION_FAILED; 4919 } 4920 4921 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 4922 { 4923 invalidate_registers(ctxt); 4924 } 4925 4926 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 4927 { 4928 writeback_registers(ctxt); 4929 } 4930