1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * 13 * Avi Kivity <avi@qumranet.com> 14 * Yaniv Kamay <yaniv@qumranet.com> 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. See 17 * the COPYING file in the top-level directory. 18 * 19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 20 */ 21 22 #ifndef __KERNEL__ 23 #include <stdio.h> 24 #include <stdint.h> 25 #include <public/xen.h> 26 #define DPRINTF(_f, _a ...) printf(_f , ## _a) 27 #else 28 #include <linux/kvm_host.h> 29 #include "kvm_cache_regs.h" 30 #define DPRINTF(x...) do {} while (0) 31 #endif 32 #include <linux/module.h> 33 #include <asm/kvm_emulate.h> 34 35 #include "x86.h" 36 #include "tss.h" 37 38 /* 39 * Opcode effective-address decode tables. 40 * Note that we only emulate instructions that have at least one memory 41 * operand (excluding implicit stack references). We assume that stack 42 * references and instruction fetches will never occur in special memory 43 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 44 * not be handled. 45 */ 46 47 /* Operand sizes: 8-bit operands or specified/overridden size. */ 48 #define ByteOp (1<<0) /* 8-bit operands. */ 49 /* Destination operand type. */ 50 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ 51 #define DstReg (2<<1) /* Register operand. */ 52 #define DstMem (3<<1) /* Memory operand. */ 53 #define DstAcc (4<<1) /* Destination Accumulator */ 54 #define DstDI (5<<1) /* Destination is in ES:(E)DI */ 55 #define DstMem64 (6<<1) /* 64bit memory operand */ 56 #define DstMask (7<<1) 57 /* Source operand type. */ 58 #define SrcNone (0<<4) /* No source operand. */ 59 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */ 60 #define SrcReg (1<<4) /* Register operand. */ 61 #define SrcMem (2<<4) /* Memory operand. */ 62 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */ 63 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */ 64 #define SrcImm (5<<4) /* Immediate operand. */ 65 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */ 66 #define SrcOne (7<<4) /* Implied '1' */ 67 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */ 68 #define SrcImmU (9<<4) /* Immediate operand, unsigned */ 69 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */ 70 #define SrcMask (0xf<<4) 71 /* Generic ModRM decode. */ 72 #define ModRM (1<<8) 73 /* Destination is only written; never read. */ 74 #define Mov (1<<9) 75 #define BitOp (1<<10) 76 #define MemAbs (1<<11) /* Memory operand is absolute displacement */ 77 #define String (1<<12) /* String instruction (rep capable) */ 78 #define Stack (1<<13) /* Stack instruction (push/pop) */ 79 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */ 80 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */ 81 #define GroupMask 0xff /* Group number stored in bits 0:7 */ 82 /* Misc flags */ 83 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 84 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 85 #define No64 (1<<28) 86 /* Source 2 operand type */ 87 #define Src2None (0<<29) 88 #define Src2CL (1<<29) 89 #define Src2ImmByte (2<<29) 90 #define Src2One (3<<29) 91 #define Src2Imm16 (4<<29) 92 #define Src2Mem16 (5<<29) /* Used for Ep encoding. First argument has to be 93 in memory and second argument is located 94 immediately after the first one in memory. */ 95 #define Src2Mask (7<<29) 96 97 enum { 98 Group1_80, Group1_81, Group1_82, Group1_83, 99 Group1A, Group3_Byte, Group3, Group4, Group5, Group7, 100 Group8, Group9, 101 }; 102 103 static u32 opcode_table[256] = { 104 /* 0x00 - 0x07 */ 105 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 107 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 108 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, 109 /* 0x08 - 0x0F */ 110 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 111 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 112 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 113 ImplicitOps | Stack | No64, 0, 114 /* 0x10 - 0x17 */ 115 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 116 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 117 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 118 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, 119 /* 0x18 - 0x1F */ 120 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 121 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 122 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 123 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, 124 /* 0x20 - 0x27 */ 125 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 126 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 127 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0, 128 /* 0x28 - 0x2F */ 129 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 130 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 131 0, 0, 0, 0, 132 /* 0x30 - 0x37 */ 133 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 134 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 135 0, 0, 0, 0, 136 /* 0x38 - 0x3F */ 137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 138 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, 139 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 140 0, 0, 141 /* 0x40 - 0x47 */ 142 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, 143 /* 0x48 - 0x4F */ 144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, 145 /* 0x50 - 0x57 */ 146 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, 147 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, 148 /* 0x58 - 0x5F */ 149 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, 150 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack, 151 /* 0x60 - 0x67 */ 152 ImplicitOps | Stack | No64, ImplicitOps | Stack | No64, 153 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , 154 0, 0, 0, 0, 155 /* 0x68 - 0x6F */ 156 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0, 157 DstDI | ByteOp | Mov | String, DstDI | Mov | String, /* insb, insw/insd */ 158 SrcSI | ByteOp | ImplicitOps | String, SrcSI | ImplicitOps | String, /* outsb, outsw/outsd */ 159 /* 0x70 - 0x77 */ 160 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, 161 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, 162 /* 0x78 - 0x7F */ 163 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, 164 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte, 165 /* 0x80 - 0x87 */ 166 Group | Group1_80, Group | Group1_81, 167 Group | Group1_82, Group | Group1_83, 168 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 169 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 170 /* 0x88 - 0x8F */ 171 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, 172 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 173 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg, 174 DstReg | SrcMem | ModRM | Mov, Group | Group1A, 175 /* 0x90 - 0x97 */ 176 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, 177 /* 0x98 - 0x9F */ 178 0, 0, SrcImm | Src2Imm16 | No64, 0, 179 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0, 180 /* 0xA0 - 0xA7 */ 181 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs, 182 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs, 183 ByteOp | SrcSI | DstDI | Mov | String, SrcSI | DstDI | Mov | String, 184 ByteOp | SrcSI | DstDI | String, SrcSI | DstDI | String, 185 /* 0xA8 - 0xAF */ 186 0, 0, ByteOp | DstDI | Mov | String, DstDI | Mov | String, 187 ByteOp | SrcSI | DstAcc | Mov | String, SrcSI | DstAcc | Mov | String, 188 ByteOp | DstDI | String, DstDI | String, 189 /* 0xB0 - 0xB7 */ 190 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, 191 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, 192 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, 193 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov, 194 /* 0xB8 - 0xBF */ 195 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, 196 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, 197 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, 198 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov, 199 /* 0xC0 - 0xC7 */ 200 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, 201 0, ImplicitOps | Stack, 0, 0, 202 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, 203 /* 0xC8 - 0xCF */ 204 0, 0, 0, ImplicitOps | Stack, 205 ImplicitOps, SrcImmByte, ImplicitOps | No64, ImplicitOps, 206 /* 0xD0 - 0xD7 */ 207 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, 208 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, 209 0, 0, 0, 0, 210 /* 0xD8 - 0xDF */ 211 0, 0, 0, 0, 0, 0, 0, 0, 212 /* 0xE0 - 0xE7 */ 213 0, 0, 0, 0, 214 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, 215 ByteOp | SrcImmUByte | DstAcc, SrcImmUByte | DstAcc, 216 /* 0xE8 - 0xEF */ 217 SrcImm | Stack, SrcImm | ImplicitOps, 218 SrcImmU | Src2Imm16 | No64, SrcImmByte | ImplicitOps, 219 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, 220 SrcNone | ByteOp | DstAcc, SrcNone | DstAcc, 221 /* 0xF0 - 0xF7 */ 222 0, 0, 0, 0, 223 ImplicitOps | Priv, ImplicitOps, Group | Group3_Byte, Group | Group3, 224 /* 0xF8 - 0xFF */ 225 ImplicitOps, 0, ImplicitOps, ImplicitOps, 226 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5, 227 }; 228 229 static u32 twobyte_table[256] = { 230 /* 0x00 - 0x0F */ 231 0, Group | GroupDual | Group7, 0, 0, 232 0, ImplicitOps, ImplicitOps | Priv, 0, 233 ImplicitOps | Priv, ImplicitOps | Priv, 0, 0, 234 0, ImplicitOps | ModRM, 0, 0, 235 /* 0x10 - 0x1F */ 236 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, 237 /* 0x20 - 0x2F */ 238 ModRM | ImplicitOps | Priv, ModRM | Priv, 239 ModRM | ImplicitOps | Priv, ModRM | Priv, 240 0, 0, 0, 0, 241 0, 0, 0, 0, 0, 0, 0, 0, 242 /* 0x30 - 0x3F */ 243 ImplicitOps | Priv, 0, ImplicitOps | Priv, 0, 244 ImplicitOps, ImplicitOps | Priv, 0, 0, 245 0, 0, 0, 0, 0, 0, 0, 0, 246 /* 0x40 - 0x47 */ 247 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 248 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 249 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 250 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 251 /* 0x48 - 0x4F */ 252 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 253 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 254 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 255 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, 256 /* 0x50 - 0x5F */ 257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 258 /* 0x60 - 0x6F */ 259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 260 /* 0x70 - 0x7F */ 261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 262 /* 0x80 - 0x8F */ 263 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, 264 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, 265 /* 0x90 - 0x9F */ 266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 267 /* 0xA0 - 0xA7 */ 268 ImplicitOps | Stack, ImplicitOps | Stack, 269 0, DstMem | SrcReg | ModRM | BitOp, 270 DstMem | SrcReg | Src2ImmByte | ModRM, 271 DstMem | SrcReg | Src2CL | ModRM, 0, 0, 272 /* 0xA8 - 0xAF */ 273 ImplicitOps | Stack, ImplicitOps | Stack, 274 0, DstMem | SrcReg | ModRM | BitOp | Lock, 275 DstMem | SrcReg | Src2ImmByte | ModRM, 276 DstMem | SrcReg | Src2CL | ModRM, 277 ModRM, 0, 278 /* 0xB0 - 0xB7 */ 279 ByteOp | DstMem | SrcReg | ModRM | Lock, DstMem | SrcReg | ModRM | Lock, 280 0, DstMem | SrcReg | ModRM | BitOp | Lock, 281 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, 282 DstReg | SrcMem16 | ModRM | Mov, 283 /* 0xB8 - 0xBF */ 284 0, 0, 285 Group | Group8, DstMem | SrcReg | ModRM | BitOp | Lock, 286 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, 287 DstReg | SrcMem16 | ModRM | Mov, 288 /* 0xC0 - 0xCF */ 289 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 290 0, 0, 0, Group | GroupDual | Group9, 291 0, 0, 0, 0, 0, 0, 0, 0, 292 /* 0xD0 - 0xDF */ 293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 294 /* 0xE0 - 0xEF */ 295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 296 /* 0xF0 - 0xFF */ 297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 298 }; 299 300 static u32 group_table[] = { 301 [Group1_80*8] = 302 ByteOp | DstMem | SrcImm | ModRM | Lock, 303 ByteOp | DstMem | SrcImm | ModRM | Lock, 304 ByteOp | DstMem | SrcImm | ModRM | Lock, 305 ByteOp | DstMem | SrcImm | ModRM | Lock, 306 ByteOp | DstMem | SrcImm | ModRM | Lock, 307 ByteOp | DstMem | SrcImm | ModRM | Lock, 308 ByteOp | DstMem | SrcImm | ModRM | Lock, 309 ByteOp | DstMem | SrcImm | ModRM, 310 [Group1_81*8] = 311 DstMem | SrcImm | ModRM | Lock, 312 DstMem | SrcImm | ModRM | Lock, 313 DstMem | SrcImm | ModRM | Lock, 314 DstMem | SrcImm | ModRM | Lock, 315 DstMem | SrcImm | ModRM | Lock, 316 DstMem | SrcImm | ModRM | Lock, 317 DstMem | SrcImm | ModRM | Lock, 318 DstMem | SrcImm | ModRM, 319 [Group1_82*8] = 320 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 321 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 322 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 323 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 324 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 325 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 326 ByteOp | DstMem | SrcImm | ModRM | No64 | Lock, 327 ByteOp | DstMem | SrcImm | ModRM | No64, 328 [Group1_83*8] = 329 DstMem | SrcImmByte | ModRM | Lock, 330 DstMem | SrcImmByte | ModRM | Lock, 331 DstMem | SrcImmByte | ModRM | Lock, 332 DstMem | SrcImmByte | ModRM | Lock, 333 DstMem | SrcImmByte | ModRM | Lock, 334 DstMem | SrcImmByte | ModRM | Lock, 335 DstMem | SrcImmByte | ModRM | Lock, 336 DstMem | SrcImmByte | ModRM, 337 [Group1A*8] = 338 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0, 339 [Group3_Byte*8] = 340 ByteOp | SrcImm | DstMem | ModRM, 0, 341 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, 342 0, 0, 0, 0, 343 [Group3*8] = 344 DstMem | SrcImm | ModRM, 0, 345 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 346 0, 0, 0, 0, 347 [Group4*8] = 348 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM, 349 0, 0, 0, 0, 0, 0, 350 [Group5*8] = 351 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 352 SrcMem | ModRM | Stack, 0, 353 SrcMem | ModRM | Stack, SrcMem | ModRM | Src2Mem16 | ImplicitOps, 354 SrcMem | ModRM | Stack, 0, 355 [Group7*8] = 356 0, 0, ModRM | SrcMem | Priv, ModRM | SrcMem | Priv, 357 SrcNone | ModRM | DstMem | Mov, 0, 358 SrcMem16 | ModRM | Mov | Priv, SrcMem | ModRM | ByteOp | Priv, 359 [Group8*8] = 360 0, 0, 0, 0, 361 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM | Lock, 362 DstMem | SrcImmByte | ModRM | Lock, DstMem | SrcImmByte | ModRM | Lock, 363 [Group9*8] = 364 0, DstMem64 | ModRM | Lock, 0, 0, 0, 0, 0, 0, 365 }; 366 367 static u32 group2_table[] = { 368 [Group7*8] = 369 SrcNone | ModRM | Priv, 0, 0, SrcNone | ModRM | Priv, 370 SrcNone | ModRM | DstMem | Mov, 0, 371 SrcMem16 | ModRM | Mov | Priv, 0, 372 [Group9*8] = 373 0, 0, 0, 0, 0, 0, 0, 0, 374 }; 375 376 /* EFLAGS bit definitions. */ 377 #define EFLG_ID (1<<21) 378 #define EFLG_VIP (1<<20) 379 #define EFLG_VIF (1<<19) 380 #define EFLG_AC (1<<18) 381 #define EFLG_VM (1<<17) 382 #define EFLG_RF (1<<16) 383 #define EFLG_IOPL (3<<12) 384 #define EFLG_NT (1<<14) 385 #define EFLG_OF (1<<11) 386 #define EFLG_DF (1<<10) 387 #define EFLG_IF (1<<9) 388 #define EFLG_TF (1<<8) 389 #define EFLG_SF (1<<7) 390 #define EFLG_ZF (1<<6) 391 #define EFLG_AF (1<<4) 392 #define EFLG_PF (1<<2) 393 #define EFLG_CF (1<<0) 394 395 /* 396 * Instruction emulation: 397 * Most instructions are emulated directly via a fragment of inline assembly 398 * code. This allows us to save/restore EFLAGS and thus very easily pick up 399 * any modified flags. 400 */ 401 402 #if defined(CONFIG_X86_64) 403 #define _LO32 "k" /* force 32-bit operand */ 404 #define _STK "%%rsp" /* stack pointer */ 405 #elif defined(__i386__) 406 #define _LO32 "" /* force 32-bit operand */ 407 #define _STK "%%esp" /* stack pointer */ 408 #endif 409 410 /* 411 * These EFLAGS bits are restored from saved value during emulation, and 412 * any changes are written back to the saved value after emulation. 413 */ 414 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) 415 416 /* Before executing instruction: restore necessary bits in EFLAGS. */ 417 #define _PRE_EFLAGS(_sav, _msk, _tmp) \ 418 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ 419 "movl %"_sav",%"_LO32 _tmp"; " \ 420 "push %"_tmp"; " \ 421 "push %"_tmp"; " \ 422 "movl %"_msk",%"_LO32 _tmp"; " \ 423 "andl %"_LO32 _tmp",("_STK"); " \ 424 "pushf; " \ 425 "notl %"_LO32 _tmp"; " \ 426 "andl %"_LO32 _tmp",("_STK"); " \ 427 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ 428 "pop %"_tmp"; " \ 429 "orl %"_LO32 _tmp",("_STK"); " \ 430 "popf; " \ 431 "pop %"_sav"; " 432 433 /* After executing instruction: write-back necessary bits in EFLAGS. */ 434 #define _POST_EFLAGS(_sav, _msk, _tmp) \ 435 /* _sav |= EFLAGS & _msk; */ \ 436 "pushf; " \ 437 "pop %"_tmp"; " \ 438 "andl %"_msk",%"_LO32 _tmp"; " \ 439 "orl %"_LO32 _tmp",%"_sav"; " 440 441 #ifdef CONFIG_X86_64 442 #define ON64(x) x 443 #else 444 #define ON64(x) 445 #endif 446 447 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \ 448 do { \ 449 __asm__ __volatile__ ( \ 450 _PRE_EFLAGS("0", "4", "2") \ 451 _op _suffix " %"_x"3,%1; " \ 452 _POST_EFLAGS("0", "4", "2") \ 453 : "=m" (_eflags), "=m" ((_dst).val), \ 454 "=&r" (_tmp) \ 455 : _y ((_src).val), "i" (EFLAGS_MASK)); \ 456 } while (0) 457 458 459 /* Raw emulation: instruction has two explicit operands. */ 460 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ 461 do { \ 462 unsigned long _tmp; \ 463 \ 464 switch ((_dst).bytes) { \ 465 case 2: \ 466 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \ 467 break; \ 468 case 4: \ 469 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \ 470 break; \ 471 case 8: \ 472 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \ 473 break; \ 474 } \ 475 } while (0) 476 477 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ 478 do { \ 479 unsigned long _tmp; \ 480 switch ((_dst).bytes) { \ 481 case 1: \ 482 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \ 483 break; \ 484 default: \ 485 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ 486 _wx, _wy, _lx, _ly, _qx, _qy); \ 487 break; \ 488 } \ 489 } while (0) 490 491 /* Source operand is byte-sized and may be restricted to just %cl. */ 492 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ 493 __emulate_2op(_op, _src, _dst, _eflags, \ 494 "b", "c", "b", "c", "b", "c", "b", "c") 495 496 /* Source operand is byte, word, long or quad sized. */ 497 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ 498 __emulate_2op(_op, _src, _dst, _eflags, \ 499 "b", "q", "w", "r", _LO32, "r", "", "r") 500 501 /* Source operand is word, long or quad sized. */ 502 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ 503 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ 504 "w", "r", _LO32, "r", "", "r") 505 506 /* Instruction has three operands and one operand is stored in ECX register */ 507 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ 508 do { \ 509 unsigned long _tmp; \ 510 _type _clv = (_cl).val; \ 511 _type _srcv = (_src).val; \ 512 _type _dstv = (_dst).val; \ 513 \ 514 __asm__ __volatile__ ( \ 515 _PRE_EFLAGS("0", "5", "2") \ 516 _op _suffix " %4,%1 \n" \ 517 _POST_EFLAGS("0", "5", "2") \ 518 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ 519 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ 520 ); \ 521 \ 522 (_cl).val = (unsigned long) _clv; \ 523 (_src).val = (unsigned long) _srcv; \ 524 (_dst).val = (unsigned long) _dstv; \ 525 } while (0) 526 527 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ 528 do { \ 529 switch ((_dst).bytes) { \ 530 case 2: \ 531 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ 532 "w", unsigned short); \ 533 break; \ 534 case 4: \ 535 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ 536 "l", unsigned int); \ 537 break; \ 538 case 8: \ 539 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ 540 "q", unsigned long)); \ 541 break; \ 542 } \ 543 } while (0) 544 545 #define __emulate_1op(_op, _dst, _eflags, _suffix) \ 546 do { \ 547 unsigned long _tmp; \ 548 \ 549 __asm__ __volatile__ ( \ 550 _PRE_EFLAGS("0", "3", "2") \ 551 _op _suffix " %1; " \ 552 _POST_EFLAGS("0", "3", "2") \ 553 : "=m" (_eflags), "+m" ((_dst).val), \ 554 "=&r" (_tmp) \ 555 : "i" (EFLAGS_MASK)); \ 556 } while (0) 557 558 /* Instruction has only one explicit operand (no source operand). */ 559 #define emulate_1op(_op, _dst, _eflags) \ 560 do { \ 561 switch ((_dst).bytes) { \ 562 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \ 563 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \ 564 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \ 565 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \ 566 } \ 567 } while (0) 568 569 /* Fetch next part of the instruction being emulated. */ 570 #define insn_fetch(_type, _size, _eip) \ 571 ({ unsigned long _x; \ 572 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \ 573 if (rc != X86EMUL_CONTINUE) \ 574 goto done; \ 575 (_eip) += (_size); \ 576 (_type)_x; \ 577 }) 578 579 static inline unsigned long ad_mask(struct decode_cache *c) 580 { 581 return (1UL << (c->ad_bytes << 3)) - 1; 582 } 583 584 /* Access/update address held in a register, based on addressing mode. */ 585 static inline unsigned long 586 address_mask(struct decode_cache *c, unsigned long reg) 587 { 588 if (c->ad_bytes == sizeof(unsigned long)) 589 return reg; 590 else 591 return reg & ad_mask(c); 592 } 593 594 static inline unsigned long 595 register_address(struct decode_cache *c, unsigned long base, unsigned long reg) 596 { 597 return base + address_mask(c, reg); 598 } 599 600 static inline void 601 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc) 602 { 603 if (c->ad_bytes == sizeof(unsigned long)) 604 *reg += inc; 605 else 606 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c)); 607 } 608 609 static inline void jmp_rel(struct decode_cache *c, int rel) 610 { 611 register_address_increment(c, &c->eip, rel); 612 } 613 614 static void set_seg_override(struct decode_cache *c, int seg) 615 { 616 c->has_seg_override = true; 617 c->seg_override = seg; 618 } 619 620 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 621 { 622 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 623 return 0; 624 625 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg); 626 } 627 628 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt, 629 struct decode_cache *c) 630 { 631 if (!c->has_seg_override) 632 return 0; 633 634 return seg_base(ctxt, c->seg_override); 635 } 636 637 static unsigned long es_base(struct x86_emulate_ctxt *ctxt) 638 { 639 return seg_base(ctxt, VCPU_SREG_ES); 640 } 641 642 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt) 643 { 644 return seg_base(ctxt, VCPU_SREG_SS); 645 } 646 647 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt, 648 struct x86_emulate_ops *ops, 649 unsigned long eip, u8 *dest) 650 { 651 struct fetch_cache *fc = &ctxt->decode.fetch; 652 int rc; 653 int size, cur_size; 654 655 if (eip == fc->end) { 656 cur_size = fc->end - fc->start; 657 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip)); 658 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size, 659 size, ctxt->vcpu, NULL); 660 if (rc != X86EMUL_CONTINUE) 661 return rc; 662 fc->end += size; 663 } 664 *dest = fc->data[eip - fc->start]; 665 return X86EMUL_CONTINUE; 666 } 667 668 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, 669 struct x86_emulate_ops *ops, 670 unsigned long eip, void *dest, unsigned size) 671 { 672 int rc; 673 674 /* x86 instructions are limited to 15 bytes. */ 675 if (eip + size - ctxt->eip > 15) 676 return X86EMUL_UNHANDLEABLE; 677 while (size--) { 678 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++); 679 if (rc != X86EMUL_CONTINUE) 680 return rc; 681 } 682 return X86EMUL_CONTINUE; 683 } 684 685 /* 686 * Given the 'reg' portion of a ModRM byte, and a register block, return a 687 * pointer into the block that addresses the relevant register. 688 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 689 */ 690 static void *decode_register(u8 modrm_reg, unsigned long *regs, 691 int highbyte_regs) 692 { 693 void *p; 694 695 p = ®s[modrm_reg]; 696 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 697 p = (unsigned char *)®s[modrm_reg & 3] + 1; 698 return p; 699 } 700 701 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 702 struct x86_emulate_ops *ops, 703 void *ptr, 704 u16 *size, unsigned long *address, int op_bytes) 705 { 706 int rc; 707 708 if (op_bytes == 2) 709 op_bytes = 3; 710 *address = 0; 711 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, 712 ctxt->vcpu, NULL); 713 if (rc != X86EMUL_CONTINUE) 714 return rc; 715 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, 716 ctxt->vcpu, NULL); 717 return rc; 718 } 719 720 static int test_cc(unsigned int condition, unsigned int flags) 721 { 722 int rc = 0; 723 724 switch ((condition & 15) >> 1) { 725 case 0: /* o */ 726 rc |= (flags & EFLG_OF); 727 break; 728 case 1: /* b/c/nae */ 729 rc |= (flags & EFLG_CF); 730 break; 731 case 2: /* z/e */ 732 rc |= (flags & EFLG_ZF); 733 break; 734 case 3: /* be/na */ 735 rc |= (flags & (EFLG_CF|EFLG_ZF)); 736 break; 737 case 4: /* s */ 738 rc |= (flags & EFLG_SF); 739 break; 740 case 5: /* p/pe */ 741 rc |= (flags & EFLG_PF); 742 break; 743 case 7: /* le/ng */ 744 rc |= (flags & EFLG_ZF); 745 /* fall through */ 746 case 6: /* l/nge */ 747 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); 748 break; 749 } 750 751 /* Odd condition identifiers (lsb == 1) have inverted sense. */ 752 return (!!rc ^ (condition & 1)); 753 } 754 755 static void decode_register_operand(struct operand *op, 756 struct decode_cache *c, 757 int inhibit_bytereg) 758 { 759 unsigned reg = c->modrm_reg; 760 int highbyte_regs = c->rex_prefix == 0; 761 762 if (!(c->d & ModRM)) 763 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3); 764 op->type = OP_REG; 765 if ((c->d & ByteOp) && !inhibit_bytereg) { 766 op->ptr = decode_register(reg, c->regs, highbyte_regs); 767 op->val = *(u8 *)op->ptr; 768 op->bytes = 1; 769 } else { 770 op->ptr = decode_register(reg, c->regs, 0); 771 op->bytes = c->op_bytes; 772 switch (op->bytes) { 773 case 2: 774 op->val = *(u16 *)op->ptr; 775 break; 776 case 4: 777 op->val = *(u32 *)op->ptr; 778 break; 779 case 8: 780 op->val = *(u64 *) op->ptr; 781 break; 782 } 783 } 784 op->orig_val = op->val; 785 } 786 787 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 788 struct x86_emulate_ops *ops) 789 { 790 struct decode_cache *c = &ctxt->decode; 791 u8 sib; 792 int index_reg = 0, base_reg = 0, scale; 793 int rc = X86EMUL_CONTINUE; 794 795 if (c->rex_prefix) { 796 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */ 797 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */ 798 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */ 799 } 800 801 c->modrm = insn_fetch(u8, 1, c->eip); 802 c->modrm_mod |= (c->modrm & 0xc0) >> 6; 803 c->modrm_reg |= (c->modrm & 0x38) >> 3; 804 c->modrm_rm |= (c->modrm & 0x07); 805 c->modrm_ea = 0; 806 c->use_modrm_ea = 1; 807 808 if (c->modrm_mod == 3) { 809 c->modrm_ptr = decode_register(c->modrm_rm, 810 c->regs, c->d & ByteOp); 811 c->modrm_val = *(unsigned long *)c->modrm_ptr; 812 return rc; 813 } 814 815 if (c->ad_bytes == 2) { 816 unsigned bx = c->regs[VCPU_REGS_RBX]; 817 unsigned bp = c->regs[VCPU_REGS_RBP]; 818 unsigned si = c->regs[VCPU_REGS_RSI]; 819 unsigned di = c->regs[VCPU_REGS_RDI]; 820 821 /* 16-bit ModR/M decode. */ 822 switch (c->modrm_mod) { 823 case 0: 824 if (c->modrm_rm == 6) 825 c->modrm_ea += insn_fetch(u16, 2, c->eip); 826 break; 827 case 1: 828 c->modrm_ea += insn_fetch(s8, 1, c->eip); 829 break; 830 case 2: 831 c->modrm_ea += insn_fetch(u16, 2, c->eip); 832 break; 833 } 834 switch (c->modrm_rm) { 835 case 0: 836 c->modrm_ea += bx + si; 837 break; 838 case 1: 839 c->modrm_ea += bx + di; 840 break; 841 case 2: 842 c->modrm_ea += bp + si; 843 break; 844 case 3: 845 c->modrm_ea += bp + di; 846 break; 847 case 4: 848 c->modrm_ea += si; 849 break; 850 case 5: 851 c->modrm_ea += di; 852 break; 853 case 6: 854 if (c->modrm_mod != 0) 855 c->modrm_ea += bp; 856 break; 857 case 7: 858 c->modrm_ea += bx; 859 break; 860 } 861 if (c->modrm_rm == 2 || c->modrm_rm == 3 || 862 (c->modrm_rm == 6 && c->modrm_mod != 0)) 863 if (!c->has_seg_override) 864 set_seg_override(c, VCPU_SREG_SS); 865 c->modrm_ea = (u16)c->modrm_ea; 866 } else { 867 /* 32/64-bit ModR/M decode. */ 868 if ((c->modrm_rm & 7) == 4) { 869 sib = insn_fetch(u8, 1, c->eip); 870 index_reg |= (sib >> 3) & 7; 871 base_reg |= sib & 7; 872 scale = sib >> 6; 873 874 if ((base_reg & 7) == 5 && c->modrm_mod == 0) 875 c->modrm_ea += insn_fetch(s32, 4, c->eip); 876 else 877 c->modrm_ea += c->regs[base_reg]; 878 if (index_reg != 4) 879 c->modrm_ea += c->regs[index_reg] << scale; 880 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) { 881 if (ctxt->mode == X86EMUL_MODE_PROT64) 882 c->rip_relative = 1; 883 } else 884 c->modrm_ea += c->regs[c->modrm_rm]; 885 switch (c->modrm_mod) { 886 case 0: 887 if (c->modrm_rm == 5) 888 c->modrm_ea += insn_fetch(s32, 4, c->eip); 889 break; 890 case 1: 891 c->modrm_ea += insn_fetch(s8, 1, c->eip); 892 break; 893 case 2: 894 c->modrm_ea += insn_fetch(s32, 4, c->eip); 895 break; 896 } 897 } 898 done: 899 return rc; 900 } 901 902 static int decode_abs(struct x86_emulate_ctxt *ctxt, 903 struct x86_emulate_ops *ops) 904 { 905 struct decode_cache *c = &ctxt->decode; 906 int rc = X86EMUL_CONTINUE; 907 908 switch (c->ad_bytes) { 909 case 2: 910 c->modrm_ea = insn_fetch(u16, 2, c->eip); 911 break; 912 case 4: 913 c->modrm_ea = insn_fetch(u32, 4, c->eip); 914 break; 915 case 8: 916 c->modrm_ea = insn_fetch(u64, 8, c->eip); 917 break; 918 } 919 done: 920 return rc; 921 } 922 923 int 924 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) 925 { 926 struct decode_cache *c = &ctxt->decode; 927 int rc = X86EMUL_CONTINUE; 928 int mode = ctxt->mode; 929 int def_op_bytes, def_ad_bytes, group; 930 931 932 /* we cannot decode insn before we complete previous rep insn */ 933 WARN_ON(ctxt->restart); 934 935 /* Shadow copy of register state. Committed on successful emulation. */ 936 memset(c, 0, sizeof(struct decode_cache)); 937 c->eip = ctxt->eip; 938 c->fetch.start = c->fetch.end = c->eip; 939 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS); 940 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); 941 942 switch (mode) { 943 case X86EMUL_MODE_REAL: 944 case X86EMUL_MODE_VM86: 945 case X86EMUL_MODE_PROT16: 946 def_op_bytes = def_ad_bytes = 2; 947 break; 948 case X86EMUL_MODE_PROT32: 949 def_op_bytes = def_ad_bytes = 4; 950 break; 951 #ifdef CONFIG_X86_64 952 case X86EMUL_MODE_PROT64: 953 def_op_bytes = 4; 954 def_ad_bytes = 8; 955 break; 956 #endif 957 default: 958 return -1; 959 } 960 961 c->op_bytes = def_op_bytes; 962 c->ad_bytes = def_ad_bytes; 963 964 /* Legacy prefixes. */ 965 for (;;) { 966 switch (c->b = insn_fetch(u8, 1, c->eip)) { 967 case 0x66: /* operand-size override */ 968 /* switch between 2/4 bytes */ 969 c->op_bytes = def_op_bytes ^ 6; 970 break; 971 case 0x67: /* address-size override */ 972 if (mode == X86EMUL_MODE_PROT64) 973 /* switch between 4/8 bytes */ 974 c->ad_bytes = def_ad_bytes ^ 12; 975 else 976 /* switch between 2/4 bytes */ 977 c->ad_bytes = def_ad_bytes ^ 6; 978 break; 979 case 0x26: /* ES override */ 980 case 0x2e: /* CS override */ 981 case 0x36: /* SS override */ 982 case 0x3e: /* DS override */ 983 set_seg_override(c, (c->b >> 3) & 3); 984 break; 985 case 0x64: /* FS override */ 986 case 0x65: /* GS override */ 987 set_seg_override(c, c->b & 7); 988 break; 989 case 0x40 ... 0x4f: /* REX */ 990 if (mode != X86EMUL_MODE_PROT64) 991 goto done_prefixes; 992 c->rex_prefix = c->b; 993 continue; 994 case 0xf0: /* LOCK */ 995 c->lock_prefix = 1; 996 break; 997 case 0xf2: /* REPNE/REPNZ */ 998 c->rep_prefix = REPNE_PREFIX; 999 break; 1000 case 0xf3: /* REP/REPE/REPZ */ 1001 c->rep_prefix = REPE_PREFIX; 1002 break; 1003 default: 1004 goto done_prefixes; 1005 } 1006 1007 /* Any legacy prefix after a REX prefix nullifies its effect. */ 1008 1009 c->rex_prefix = 0; 1010 } 1011 1012 done_prefixes: 1013 1014 /* REX prefix. */ 1015 if (c->rex_prefix) 1016 if (c->rex_prefix & 8) 1017 c->op_bytes = 8; /* REX.W */ 1018 1019 /* Opcode byte(s). */ 1020 c->d = opcode_table[c->b]; 1021 if (c->d == 0) { 1022 /* Two-byte opcode? */ 1023 if (c->b == 0x0f) { 1024 c->twobyte = 1; 1025 c->b = insn_fetch(u8, 1, c->eip); 1026 c->d = twobyte_table[c->b]; 1027 } 1028 } 1029 1030 if (c->d & Group) { 1031 group = c->d & GroupMask; 1032 c->modrm = insn_fetch(u8, 1, c->eip); 1033 --c->eip; 1034 1035 group = (group << 3) + ((c->modrm >> 3) & 7); 1036 if ((c->d & GroupDual) && (c->modrm >> 6) == 3) 1037 c->d = group2_table[group]; 1038 else 1039 c->d = group_table[group]; 1040 } 1041 1042 /* Unrecognised? */ 1043 if (c->d == 0) { 1044 DPRINTF("Cannot emulate %02x\n", c->b); 1045 return -1; 1046 } 1047 1048 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack)) 1049 c->op_bytes = 8; 1050 1051 /* ModRM and SIB bytes. */ 1052 if (c->d & ModRM) 1053 rc = decode_modrm(ctxt, ops); 1054 else if (c->d & MemAbs) 1055 rc = decode_abs(ctxt, ops); 1056 if (rc != X86EMUL_CONTINUE) 1057 goto done; 1058 1059 if (!c->has_seg_override) 1060 set_seg_override(c, VCPU_SREG_DS); 1061 1062 if (!(!c->twobyte && c->b == 0x8d)) 1063 c->modrm_ea += seg_override_base(ctxt, c); 1064 1065 if (c->ad_bytes != 8) 1066 c->modrm_ea = (u32)c->modrm_ea; 1067 1068 if (c->rip_relative) 1069 c->modrm_ea += c->eip; 1070 1071 /* 1072 * Decode and fetch the source operand: register, memory 1073 * or immediate. 1074 */ 1075 switch (c->d & SrcMask) { 1076 case SrcNone: 1077 break; 1078 case SrcReg: 1079 decode_register_operand(&c->src, c, 0); 1080 break; 1081 case SrcMem16: 1082 c->src.bytes = 2; 1083 goto srcmem_common; 1084 case SrcMem32: 1085 c->src.bytes = 4; 1086 goto srcmem_common; 1087 case SrcMem: 1088 c->src.bytes = (c->d & ByteOp) ? 1 : 1089 c->op_bytes; 1090 /* Don't fetch the address for invlpg: it could be unmapped. */ 1091 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) 1092 break; 1093 srcmem_common: 1094 /* 1095 * For instructions with a ModR/M byte, switch to register 1096 * access if Mod = 3. 1097 */ 1098 if ((c->d & ModRM) && c->modrm_mod == 3) { 1099 c->src.type = OP_REG; 1100 c->src.val = c->modrm_val; 1101 c->src.ptr = c->modrm_ptr; 1102 break; 1103 } 1104 c->src.type = OP_MEM; 1105 c->src.ptr = (unsigned long *)c->modrm_ea; 1106 c->src.val = 0; 1107 break; 1108 case SrcImm: 1109 case SrcImmU: 1110 c->src.type = OP_IMM; 1111 c->src.ptr = (unsigned long *)c->eip; 1112 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1113 if (c->src.bytes == 8) 1114 c->src.bytes = 4; 1115 /* NB. Immediates are sign-extended as necessary. */ 1116 switch (c->src.bytes) { 1117 case 1: 1118 c->src.val = insn_fetch(s8, 1, c->eip); 1119 break; 1120 case 2: 1121 c->src.val = insn_fetch(s16, 2, c->eip); 1122 break; 1123 case 4: 1124 c->src.val = insn_fetch(s32, 4, c->eip); 1125 break; 1126 } 1127 if ((c->d & SrcMask) == SrcImmU) { 1128 switch (c->src.bytes) { 1129 case 1: 1130 c->src.val &= 0xff; 1131 break; 1132 case 2: 1133 c->src.val &= 0xffff; 1134 break; 1135 case 4: 1136 c->src.val &= 0xffffffff; 1137 break; 1138 } 1139 } 1140 break; 1141 case SrcImmByte: 1142 case SrcImmUByte: 1143 c->src.type = OP_IMM; 1144 c->src.ptr = (unsigned long *)c->eip; 1145 c->src.bytes = 1; 1146 if ((c->d & SrcMask) == SrcImmByte) 1147 c->src.val = insn_fetch(s8, 1, c->eip); 1148 else 1149 c->src.val = insn_fetch(u8, 1, c->eip); 1150 break; 1151 case SrcOne: 1152 c->src.bytes = 1; 1153 c->src.val = 1; 1154 break; 1155 case SrcSI: 1156 c->src.type = OP_MEM; 1157 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1158 c->src.ptr = (unsigned long *) 1159 register_address(c, seg_override_base(ctxt, c), 1160 c->regs[VCPU_REGS_RSI]); 1161 c->src.val = 0; 1162 break; 1163 } 1164 1165 /* 1166 * Decode and fetch the second source operand: register, memory 1167 * or immediate. 1168 */ 1169 switch (c->d & Src2Mask) { 1170 case Src2None: 1171 break; 1172 case Src2CL: 1173 c->src2.bytes = 1; 1174 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8; 1175 break; 1176 case Src2ImmByte: 1177 c->src2.type = OP_IMM; 1178 c->src2.ptr = (unsigned long *)c->eip; 1179 c->src2.bytes = 1; 1180 c->src2.val = insn_fetch(u8, 1, c->eip); 1181 break; 1182 case Src2Imm16: 1183 c->src2.type = OP_IMM; 1184 c->src2.ptr = (unsigned long *)c->eip; 1185 c->src2.bytes = 2; 1186 c->src2.val = insn_fetch(u16, 2, c->eip); 1187 break; 1188 case Src2One: 1189 c->src2.bytes = 1; 1190 c->src2.val = 1; 1191 break; 1192 case Src2Mem16: 1193 c->src2.type = OP_MEM; 1194 c->src2.bytes = 2; 1195 c->src2.ptr = (unsigned long *)(c->modrm_ea + c->src.bytes); 1196 c->src2.val = 0; 1197 break; 1198 } 1199 1200 /* Decode and fetch the destination operand: register or memory. */ 1201 switch (c->d & DstMask) { 1202 case ImplicitOps: 1203 /* Special instructions do their own operand decoding. */ 1204 return 0; 1205 case DstReg: 1206 decode_register_operand(&c->dst, c, 1207 c->twobyte && (c->b == 0xb6 || c->b == 0xb7)); 1208 break; 1209 case DstMem: 1210 case DstMem64: 1211 if ((c->d & ModRM) && c->modrm_mod == 3) { 1212 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1213 c->dst.type = OP_REG; 1214 c->dst.val = c->dst.orig_val = c->modrm_val; 1215 c->dst.ptr = c->modrm_ptr; 1216 break; 1217 } 1218 c->dst.type = OP_MEM; 1219 c->dst.ptr = (unsigned long *)c->modrm_ea; 1220 if ((c->d & DstMask) == DstMem64) 1221 c->dst.bytes = 8; 1222 else 1223 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1224 c->dst.val = 0; 1225 if (c->d & BitOp) { 1226 unsigned long mask = ~(c->dst.bytes * 8 - 1); 1227 1228 c->dst.ptr = (void *)c->dst.ptr + 1229 (c->src.val & mask) / 8; 1230 } 1231 break; 1232 case DstAcc: 1233 c->dst.type = OP_REG; 1234 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1235 c->dst.ptr = &c->regs[VCPU_REGS_RAX]; 1236 switch (c->dst.bytes) { 1237 case 1: 1238 c->dst.val = *(u8 *)c->dst.ptr; 1239 break; 1240 case 2: 1241 c->dst.val = *(u16 *)c->dst.ptr; 1242 break; 1243 case 4: 1244 c->dst.val = *(u32 *)c->dst.ptr; 1245 break; 1246 case 8: 1247 c->dst.val = *(u64 *)c->dst.ptr; 1248 break; 1249 } 1250 c->dst.orig_val = c->dst.val; 1251 break; 1252 case DstDI: 1253 c->dst.type = OP_MEM; 1254 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; 1255 c->dst.ptr = (unsigned long *) 1256 register_address(c, es_base(ctxt), 1257 c->regs[VCPU_REGS_RDI]); 1258 c->dst.val = 0; 1259 break; 1260 } 1261 1262 done: 1263 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; 1264 } 1265 1266 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1267 struct x86_emulate_ops *ops, 1268 unsigned int size, unsigned short port, 1269 void *dest) 1270 { 1271 struct read_cache *rc = &ctxt->decode.io_read; 1272 1273 if (rc->pos == rc->end) { /* refill pio read ahead */ 1274 struct decode_cache *c = &ctxt->decode; 1275 unsigned int in_page, n; 1276 unsigned int count = c->rep_prefix ? 1277 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1; 1278 in_page = (ctxt->eflags & EFLG_DF) ? 1279 offset_in_page(c->regs[VCPU_REGS_RDI]) : 1280 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]); 1281 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, 1282 count); 1283 if (n == 0) 1284 n = 1; 1285 rc->pos = rc->end = 0; 1286 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu)) 1287 return 0; 1288 rc->end = n * size; 1289 } 1290 1291 memcpy(dest, rc->data + rc->pos, size); 1292 rc->pos += size; 1293 return 1; 1294 } 1295 1296 static u32 desc_limit_scaled(struct desc_struct *desc) 1297 { 1298 u32 limit = get_desc_limit(desc); 1299 1300 return desc->g ? (limit << 12) | 0xfff : limit; 1301 } 1302 1303 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1304 struct x86_emulate_ops *ops, 1305 u16 selector, struct desc_ptr *dt) 1306 { 1307 if (selector & 1 << 2) { 1308 struct desc_struct desc; 1309 memset (dt, 0, sizeof *dt); 1310 if (!ops->get_cached_descriptor(&desc, VCPU_SREG_LDTR, ctxt->vcpu)) 1311 return; 1312 1313 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1314 dt->address = get_desc_base(&desc); 1315 } else 1316 ops->get_gdt(dt, ctxt->vcpu); 1317 } 1318 1319 /* allowed just for 8 bytes segments */ 1320 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1321 struct x86_emulate_ops *ops, 1322 u16 selector, struct desc_struct *desc) 1323 { 1324 struct desc_ptr dt; 1325 u16 index = selector >> 3; 1326 int ret; 1327 u32 err; 1328 ulong addr; 1329 1330 get_descriptor_table_ptr(ctxt, ops, selector, &dt); 1331 1332 if (dt.size < index * 8 + 7) { 1333 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); 1334 return X86EMUL_PROPAGATE_FAULT; 1335 } 1336 addr = dt.address + index * 8; 1337 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); 1338 if (ret == X86EMUL_PROPAGATE_FAULT) 1339 kvm_inject_page_fault(ctxt->vcpu, addr, err); 1340 1341 return ret; 1342 } 1343 1344 /* allowed just for 8 bytes segments */ 1345 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1346 struct x86_emulate_ops *ops, 1347 u16 selector, struct desc_struct *desc) 1348 { 1349 struct desc_ptr dt; 1350 u16 index = selector >> 3; 1351 u32 err; 1352 ulong addr; 1353 int ret; 1354 1355 get_descriptor_table_ptr(ctxt, ops, selector, &dt); 1356 1357 if (dt.size < index * 8 + 7) { 1358 kvm_inject_gp(ctxt->vcpu, selector & 0xfffc); 1359 return X86EMUL_PROPAGATE_FAULT; 1360 } 1361 1362 addr = dt.address + index * 8; 1363 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu, &err); 1364 if (ret == X86EMUL_PROPAGATE_FAULT) 1365 kvm_inject_page_fault(ctxt->vcpu, addr, err); 1366 1367 return ret; 1368 } 1369 1370 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1371 struct x86_emulate_ops *ops, 1372 u16 selector, int seg) 1373 { 1374 struct desc_struct seg_desc; 1375 u8 dpl, rpl, cpl; 1376 unsigned err_vec = GP_VECTOR; 1377 u32 err_code = 0; 1378 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1379 int ret; 1380 1381 memset(&seg_desc, 0, sizeof seg_desc); 1382 1383 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) 1384 || ctxt->mode == X86EMUL_MODE_REAL) { 1385 /* set real mode segment descriptor */ 1386 set_desc_base(&seg_desc, selector << 4); 1387 set_desc_limit(&seg_desc, 0xffff); 1388 seg_desc.type = 3; 1389 seg_desc.p = 1; 1390 seg_desc.s = 1; 1391 goto load; 1392 } 1393 1394 /* NULL selector is not valid for TR, CS and SS */ 1395 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) 1396 && null_selector) 1397 goto exception; 1398 1399 /* TR should be in GDT only */ 1400 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1401 goto exception; 1402 1403 if (null_selector) /* for NULL selector skip all following checks */ 1404 goto load; 1405 1406 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc); 1407 if (ret != X86EMUL_CONTINUE) 1408 return ret; 1409 1410 err_code = selector & 0xfffc; 1411 err_vec = GP_VECTOR; 1412 1413 /* can't load system descriptor into segment selecor */ 1414 if (seg <= VCPU_SREG_GS && !seg_desc.s) 1415 goto exception; 1416 1417 if (!seg_desc.p) { 1418 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1419 goto exception; 1420 } 1421 1422 rpl = selector & 3; 1423 dpl = seg_desc.dpl; 1424 cpl = ops->cpl(ctxt->vcpu); 1425 1426 switch (seg) { 1427 case VCPU_SREG_SS: 1428 /* 1429 * segment is not a writable data segment or segment 1430 * selector's RPL != CPL or segment selector's RPL != CPL 1431 */ 1432 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1433 goto exception; 1434 break; 1435 case VCPU_SREG_CS: 1436 if (!(seg_desc.type & 8)) 1437 goto exception; 1438 1439 if (seg_desc.type & 4) { 1440 /* conforming */ 1441 if (dpl > cpl) 1442 goto exception; 1443 } else { 1444 /* nonconforming */ 1445 if (rpl > cpl || dpl != cpl) 1446 goto exception; 1447 } 1448 /* CS(RPL) <- CPL */ 1449 selector = (selector & 0xfffc) | cpl; 1450 break; 1451 case VCPU_SREG_TR: 1452 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1453 goto exception; 1454 break; 1455 case VCPU_SREG_LDTR: 1456 if (seg_desc.s || seg_desc.type != 2) 1457 goto exception; 1458 break; 1459 default: /* DS, ES, FS, or GS */ 1460 /* 1461 * segment is not a data or readable code segment or 1462 * ((segment is a data or nonconforming code segment) 1463 * and (both RPL and CPL > DPL)) 1464 */ 1465 if ((seg_desc.type & 0xa) == 0x8 || 1466 (((seg_desc.type & 0xc) != 0xc) && 1467 (rpl > dpl && cpl > dpl))) 1468 goto exception; 1469 break; 1470 } 1471 1472 if (seg_desc.s) { 1473 /* mark segment as accessed */ 1474 seg_desc.type |= 1; 1475 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc); 1476 if (ret != X86EMUL_CONTINUE) 1477 return ret; 1478 } 1479 load: 1480 ops->set_segment_selector(selector, seg, ctxt->vcpu); 1481 ops->set_cached_descriptor(&seg_desc, seg, ctxt->vcpu); 1482 return X86EMUL_CONTINUE; 1483 exception: 1484 kvm_queue_exception_e(ctxt->vcpu, err_vec, err_code); 1485 return X86EMUL_PROPAGATE_FAULT; 1486 } 1487 1488 static inline void emulate_push(struct x86_emulate_ctxt *ctxt) 1489 { 1490 struct decode_cache *c = &ctxt->decode; 1491 1492 c->dst.type = OP_MEM; 1493 c->dst.bytes = c->op_bytes; 1494 c->dst.val = c->src.val; 1495 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes); 1496 c->dst.ptr = (void *) register_address(c, ss_base(ctxt), 1497 c->regs[VCPU_REGS_RSP]); 1498 } 1499 1500 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1501 struct x86_emulate_ops *ops, 1502 void *dest, int len) 1503 { 1504 struct decode_cache *c = &ctxt->decode; 1505 int rc; 1506 1507 rc = ops->read_emulated(register_address(c, ss_base(ctxt), 1508 c->regs[VCPU_REGS_RSP]), 1509 dest, len, ctxt->vcpu); 1510 if (rc != X86EMUL_CONTINUE) 1511 return rc; 1512 1513 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len); 1514 return rc; 1515 } 1516 1517 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1518 struct x86_emulate_ops *ops, 1519 void *dest, int len) 1520 { 1521 int rc; 1522 unsigned long val, change_mask; 1523 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 1524 int cpl = ops->cpl(ctxt->vcpu); 1525 1526 rc = emulate_pop(ctxt, ops, &val, len); 1527 if (rc != X86EMUL_CONTINUE) 1528 return rc; 1529 1530 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF 1531 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; 1532 1533 switch(ctxt->mode) { 1534 case X86EMUL_MODE_PROT64: 1535 case X86EMUL_MODE_PROT32: 1536 case X86EMUL_MODE_PROT16: 1537 if (cpl == 0) 1538 change_mask |= EFLG_IOPL; 1539 if (cpl <= iopl) 1540 change_mask |= EFLG_IF; 1541 break; 1542 case X86EMUL_MODE_VM86: 1543 if (iopl < 3) { 1544 kvm_inject_gp(ctxt->vcpu, 0); 1545 return X86EMUL_PROPAGATE_FAULT; 1546 } 1547 change_mask |= EFLG_IF; 1548 break; 1549 default: /* real mode */ 1550 change_mask |= (EFLG_IOPL | EFLG_IF); 1551 break; 1552 } 1553 1554 *(unsigned long *)dest = 1555 (ctxt->eflags & ~change_mask) | (val & change_mask); 1556 1557 return rc; 1558 } 1559 1560 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg) 1561 { 1562 struct decode_cache *c = &ctxt->decode; 1563 struct kvm_segment segment; 1564 1565 kvm_x86_ops->get_segment(ctxt->vcpu, &segment, seg); 1566 1567 c->src.val = segment.selector; 1568 emulate_push(ctxt); 1569 } 1570 1571 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, 1572 struct x86_emulate_ops *ops, int seg) 1573 { 1574 struct decode_cache *c = &ctxt->decode; 1575 unsigned long selector; 1576 int rc; 1577 1578 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes); 1579 if (rc != X86EMUL_CONTINUE) 1580 return rc; 1581 1582 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg); 1583 return rc; 1584 } 1585 1586 static void emulate_pusha(struct x86_emulate_ctxt *ctxt) 1587 { 1588 struct decode_cache *c = &ctxt->decode; 1589 unsigned long old_esp = c->regs[VCPU_REGS_RSP]; 1590 int reg = VCPU_REGS_RAX; 1591 1592 while (reg <= VCPU_REGS_RDI) { 1593 (reg == VCPU_REGS_RSP) ? 1594 (c->src.val = old_esp) : (c->src.val = c->regs[reg]); 1595 1596 emulate_push(ctxt); 1597 ++reg; 1598 } 1599 } 1600 1601 static int emulate_popa(struct x86_emulate_ctxt *ctxt, 1602 struct x86_emulate_ops *ops) 1603 { 1604 struct decode_cache *c = &ctxt->decode; 1605 int rc = X86EMUL_CONTINUE; 1606 int reg = VCPU_REGS_RDI; 1607 1608 while (reg >= VCPU_REGS_RAX) { 1609 if (reg == VCPU_REGS_RSP) { 1610 register_address_increment(c, &c->regs[VCPU_REGS_RSP], 1611 c->op_bytes); 1612 --reg; 1613 } 1614 1615 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes); 1616 if (rc != X86EMUL_CONTINUE) 1617 break; 1618 --reg; 1619 } 1620 return rc; 1621 } 1622 1623 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, 1624 struct x86_emulate_ops *ops) 1625 { 1626 struct decode_cache *c = &ctxt->decode; 1627 1628 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes); 1629 } 1630 1631 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) 1632 { 1633 struct decode_cache *c = &ctxt->decode; 1634 switch (c->modrm_reg) { 1635 case 0: /* rol */ 1636 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); 1637 break; 1638 case 1: /* ror */ 1639 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); 1640 break; 1641 case 2: /* rcl */ 1642 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); 1643 break; 1644 case 3: /* rcr */ 1645 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); 1646 break; 1647 case 4: /* sal/shl */ 1648 case 6: /* sal/shl */ 1649 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); 1650 break; 1651 case 5: /* shr */ 1652 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); 1653 break; 1654 case 7: /* sar */ 1655 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); 1656 break; 1657 } 1658 } 1659 1660 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, 1661 struct x86_emulate_ops *ops) 1662 { 1663 struct decode_cache *c = &ctxt->decode; 1664 1665 switch (c->modrm_reg) { 1666 case 0 ... 1: /* test */ 1667 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); 1668 break; 1669 case 2: /* not */ 1670 c->dst.val = ~c->dst.val; 1671 break; 1672 case 3: /* neg */ 1673 emulate_1op("neg", c->dst, ctxt->eflags); 1674 break; 1675 default: 1676 return 0; 1677 } 1678 return 1; 1679 } 1680 1681 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, 1682 struct x86_emulate_ops *ops) 1683 { 1684 struct decode_cache *c = &ctxt->decode; 1685 1686 switch (c->modrm_reg) { 1687 case 0: /* inc */ 1688 emulate_1op("inc", c->dst, ctxt->eflags); 1689 break; 1690 case 1: /* dec */ 1691 emulate_1op("dec", c->dst, ctxt->eflags); 1692 break; 1693 case 2: /* call near abs */ { 1694 long int old_eip; 1695 old_eip = c->eip; 1696 c->eip = c->src.val; 1697 c->src.val = old_eip; 1698 emulate_push(ctxt); 1699 break; 1700 } 1701 case 4: /* jmp abs */ 1702 c->eip = c->src.val; 1703 break; 1704 case 6: /* push */ 1705 emulate_push(ctxt); 1706 break; 1707 } 1708 return X86EMUL_CONTINUE; 1709 } 1710 1711 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, 1712 struct x86_emulate_ops *ops) 1713 { 1714 struct decode_cache *c = &ctxt->decode; 1715 u64 old = c->dst.orig_val; 1716 1717 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || 1718 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { 1719 1720 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); 1721 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); 1722 ctxt->eflags &= ~EFLG_ZF; 1723 } else { 1724 c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) | 1725 (u32) c->regs[VCPU_REGS_RBX]; 1726 1727 ctxt->eflags |= EFLG_ZF; 1728 } 1729 return X86EMUL_CONTINUE; 1730 } 1731 1732 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt, 1733 struct x86_emulate_ops *ops) 1734 { 1735 struct decode_cache *c = &ctxt->decode; 1736 int rc; 1737 unsigned long cs; 1738 1739 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes); 1740 if (rc != X86EMUL_CONTINUE) 1741 return rc; 1742 if (c->op_bytes == 4) 1743 c->eip = (u32)c->eip; 1744 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes); 1745 if (rc != X86EMUL_CONTINUE) 1746 return rc; 1747 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS); 1748 return rc; 1749 } 1750 1751 static inline int writeback(struct x86_emulate_ctxt *ctxt, 1752 struct x86_emulate_ops *ops) 1753 { 1754 int rc; 1755 struct decode_cache *c = &ctxt->decode; 1756 1757 switch (c->dst.type) { 1758 case OP_REG: 1759 /* The 4-byte case *is* correct: 1760 * in 64-bit mode we zero-extend. 1761 */ 1762 switch (c->dst.bytes) { 1763 case 1: 1764 *(u8 *)c->dst.ptr = (u8)c->dst.val; 1765 break; 1766 case 2: 1767 *(u16 *)c->dst.ptr = (u16)c->dst.val; 1768 break; 1769 case 4: 1770 *c->dst.ptr = (u32)c->dst.val; 1771 break; /* 64b: zero-ext */ 1772 case 8: 1773 *c->dst.ptr = c->dst.val; 1774 break; 1775 } 1776 break; 1777 case OP_MEM: 1778 if (c->lock_prefix) 1779 rc = ops->cmpxchg_emulated( 1780 (unsigned long)c->dst.ptr, 1781 &c->dst.orig_val, 1782 &c->dst.val, 1783 c->dst.bytes, 1784 ctxt->vcpu); 1785 else 1786 rc = ops->write_emulated( 1787 (unsigned long)c->dst.ptr, 1788 &c->dst.val, 1789 c->dst.bytes, 1790 ctxt->vcpu); 1791 if (rc != X86EMUL_CONTINUE) 1792 return rc; 1793 break; 1794 case OP_NONE: 1795 /* no writeback */ 1796 break; 1797 default: 1798 break; 1799 } 1800 return X86EMUL_CONTINUE; 1801 } 1802 1803 static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask) 1804 { 1805 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(ctxt->vcpu, mask); 1806 /* 1807 * an sti; sti; sequence only disable interrupts for the first 1808 * instruction. So, if the last instruction, be it emulated or 1809 * not, left the system with the INT_STI flag enabled, it 1810 * means that the last instruction is an sti. We should not 1811 * leave the flag on in this case. The same goes for mov ss 1812 */ 1813 if (!(int_shadow & mask)) 1814 ctxt->interruptibility = mask; 1815 } 1816 1817 static inline void 1818 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 1819 struct kvm_segment *cs, struct kvm_segment *ss) 1820 { 1821 memset(cs, 0, sizeof(struct kvm_segment)); 1822 kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS); 1823 memset(ss, 0, sizeof(struct kvm_segment)); 1824 1825 cs->l = 0; /* will be adjusted later */ 1826 cs->base = 0; /* flat segment */ 1827 cs->g = 1; /* 4kb granularity */ 1828 cs->limit = 0xffffffff; /* 4GB limit */ 1829 cs->type = 0x0b; /* Read, Execute, Accessed */ 1830 cs->s = 1; 1831 cs->dpl = 0; /* will be adjusted later */ 1832 cs->present = 1; 1833 cs->db = 1; 1834 1835 ss->unusable = 0; 1836 ss->base = 0; /* flat segment */ 1837 ss->limit = 0xffffffff; /* 4GB limit */ 1838 ss->g = 1; /* 4kb granularity */ 1839 ss->s = 1; 1840 ss->type = 0x03; /* Read/Write, Accessed */ 1841 ss->db = 1; /* 32bit stack segment */ 1842 ss->dpl = 0; 1843 ss->present = 1; 1844 } 1845 1846 static int 1847 emulate_syscall(struct x86_emulate_ctxt *ctxt) 1848 { 1849 struct decode_cache *c = &ctxt->decode; 1850 struct kvm_segment cs, ss; 1851 u64 msr_data; 1852 1853 /* syscall is not available in real mode */ 1854 if (ctxt->mode == X86EMUL_MODE_REAL || 1855 ctxt->mode == X86EMUL_MODE_VM86) { 1856 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 1857 return X86EMUL_PROPAGATE_FAULT; 1858 } 1859 1860 setup_syscalls_segments(ctxt, &cs, &ss); 1861 1862 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); 1863 msr_data >>= 32; 1864 cs.selector = (u16)(msr_data & 0xfffc); 1865 ss.selector = (u16)(msr_data + 8); 1866 1867 if (is_long_mode(ctxt->vcpu)) { 1868 cs.db = 0; 1869 cs.l = 1; 1870 } 1871 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); 1872 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); 1873 1874 c->regs[VCPU_REGS_RCX] = c->eip; 1875 if (is_long_mode(ctxt->vcpu)) { 1876 #ifdef CONFIG_X86_64 1877 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; 1878 1879 kvm_x86_ops->get_msr(ctxt->vcpu, 1880 ctxt->mode == X86EMUL_MODE_PROT64 ? 1881 MSR_LSTAR : MSR_CSTAR, &msr_data); 1882 c->eip = msr_data; 1883 1884 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data); 1885 ctxt->eflags &= ~(msr_data | EFLG_RF); 1886 #endif 1887 } else { 1888 /* legacy mode */ 1889 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data); 1890 c->eip = (u32)msr_data; 1891 1892 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 1893 } 1894 1895 return X86EMUL_CONTINUE; 1896 } 1897 1898 static int 1899 emulate_sysenter(struct x86_emulate_ctxt *ctxt) 1900 { 1901 struct decode_cache *c = &ctxt->decode; 1902 struct kvm_segment cs, ss; 1903 u64 msr_data; 1904 1905 /* inject #GP if in real mode */ 1906 if (ctxt->mode == X86EMUL_MODE_REAL) { 1907 kvm_inject_gp(ctxt->vcpu, 0); 1908 return X86EMUL_PROPAGATE_FAULT; 1909 } 1910 1911 /* XXX sysenter/sysexit have not been tested in 64bit mode. 1912 * Therefore, we inject an #UD. 1913 */ 1914 if (ctxt->mode == X86EMUL_MODE_PROT64) { 1915 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 1916 return X86EMUL_PROPAGATE_FAULT; 1917 } 1918 1919 setup_syscalls_segments(ctxt, &cs, &ss); 1920 1921 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); 1922 switch (ctxt->mode) { 1923 case X86EMUL_MODE_PROT32: 1924 if ((msr_data & 0xfffc) == 0x0) { 1925 kvm_inject_gp(ctxt->vcpu, 0); 1926 return X86EMUL_PROPAGATE_FAULT; 1927 } 1928 break; 1929 case X86EMUL_MODE_PROT64: 1930 if (msr_data == 0x0) { 1931 kvm_inject_gp(ctxt->vcpu, 0); 1932 return X86EMUL_PROPAGATE_FAULT; 1933 } 1934 break; 1935 } 1936 1937 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 1938 cs.selector = (u16)msr_data; 1939 cs.selector &= ~SELECTOR_RPL_MASK; 1940 ss.selector = cs.selector + 8; 1941 ss.selector &= ~SELECTOR_RPL_MASK; 1942 if (ctxt->mode == X86EMUL_MODE_PROT64 1943 || is_long_mode(ctxt->vcpu)) { 1944 cs.db = 0; 1945 cs.l = 1; 1946 } 1947 1948 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); 1949 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); 1950 1951 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data); 1952 c->eip = msr_data; 1953 1954 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data); 1955 c->regs[VCPU_REGS_RSP] = msr_data; 1956 1957 return X86EMUL_CONTINUE; 1958 } 1959 1960 static int 1961 emulate_sysexit(struct x86_emulate_ctxt *ctxt) 1962 { 1963 struct decode_cache *c = &ctxt->decode; 1964 struct kvm_segment cs, ss; 1965 u64 msr_data; 1966 int usermode; 1967 1968 /* inject #GP if in real mode or Virtual 8086 mode */ 1969 if (ctxt->mode == X86EMUL_MODE_REAL || 1970 ctxt->mode == X86EMUL_MODE_VM86) { 1971 kvm_inject_gp(ctxt->vcpu, 0); 1972 return X86EMUL_PROPAGATE_FAULT; 1973 } 1974 1975 setup_syscalls_segments(ctxt, &cs, &ss); 1976 1977 if ((c->rex_prefix & 0x8) != 0x0) 1978 usermode = X86EMUL_MODE_PROT64; 1979 else 1980 usermode = X86EMUL_MODE_PROT32; 1981 1982 cs.dpl = 3; 1983 ss.dpl = 3; 1984 kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data); 1985 switch (usermode) { 1986 case X86EMUL_MODE_PROT32: 1987 cs.selector = (u16)(msr_data + 16); 1988 if ((msr_data & 0xfffc) == 0x0) { 1989 kvm_inject_gp(ctxt->vcpu, 0); 1990 return X86EMUL_PROPAGATE_FAULT; 1991 } 1992 ss.selector = (u16)(msr_data + 24); 1993 break; 1994 case X86EMUL_MODE_PROT64: 1995 cs.selector = (u16)(msr_data + 32); 1996 if (msr_data == 0x0) { 1997 kvm_inject_gp(ctxt->vcpu, 0); 1998 return X86EMUL_PROPAGATE_FAULT; 1999 } 2000 ss.selector = cs.selector + 8; 2001 cs.db = 0; 2002 cs.l = 1; 2003 break; 2004 } 2005 cs.selector |= SELECTOR_RPL_MASK; 2006 ss.selector |= SELECTOR_RPL_MASK; 2007 2008 kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS); 2009 kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS); 2010 2011 c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX]; 2012 c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX]; 2013 2014 return X86EMUL_CONTINUE; 2015 } 2016 2017 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt, 2018 struct x86_emulate_ops *ops) 2019 { 2020 int iopl; 2021 if (ctxt->mode == X86EMUL_MODE_REAL) 2022 return false; 2023 if (ctxt->mode == X86EMUL_MODE_VM86) 2024 return true; 2025 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 2026 return ops->cpl(ctxt->vcpu) > iopl; 2027 } 2028 2029 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2030 struct x86_emulate_ops *ops, 2031 u16 port, u16 len) 2032 { 2033 struct kvm_segment tr_seg; 2034 int r; 2035 u16 io_bitmap_ptr; 2036 u8 perm, bit_idx = port & 0x7; 2037 unsigned mask = (1 << len) - 1; 2038 2039 kvm_get_segment(ctxt->vcpu, &tr_seg, VCPU_SREG_TR); 2040 if (tr_seg.unusable) 2041 return false; 2042 if (tr_seg.limit < 103) 2043 return false; 2044 r = ops->read_std(tr_seg.base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, 2045 NULL); 2046 if (r != X86EMUL_CONTINUE) 2047 return false; 2048 if (io_bitmap_ptr + port/8 > tr_seg.limit) 2049 return false; 2050 r = ops->read_std(tr_seg.base + io_bitmap_ptr + port/8, &perm, 1, 2051 ctxt->vcpu, NULL); 2052 if (r != X86EMUL_CONTINUE) 2053 return false; 2054 if ((perm >> bit_idx) & mask) 2055 return false; 2056 return true; 2057 } 2058 2059 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2060 struct x86_emulate_ops *ops, 2061 u16 port, u16 len) 2062 { 2063 if (emulator_bad_iopl(ctxt, ops)) 2064 if (!emulator_io_port_access_allowed(ctxt, ops, port, len)) 2065 return false; 2066 return true; 2067 } 2068 2069 static u32 get_cached_descriptor_base(struct x86_emulate_ctxt *ctxt, 2070 struct x86_emulate_ops *ops, 2071 int seg) 2072 { 2073 struct desc_struct desc; 2074 if (ops->get_cached_descriptor(&desc, seg, ctxt->vcpu)) 2075 return get_desc_base(&desc); 2076 else 2077 return ~0; 2078 } 2079 2080 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2081 struct x86_emulate_ops *ops, 2082 struct tss_segment_16 *tss) 2083 { 2084 struct decode_cache *c = &ctxt->decode; 2085 2086 tss->ip = c->eip; 2087 tss->flag = ctxt->eflags; 2088 tss->ax = c->regs[VCPU_REGS_RAX]; 2089 tss->cx = c->regs[VCPU_REGS_RCX]; 2090 tss->dx = c->regs[VCPU_REGS_RDX]; 2091 tss->bx = c->regs[VCPU_REGS_RBX]; 2092 tss->sp = c->regs[VCPU_REGS_RSP]; 2093 tss->bp = c->regs[VCPU_REGS_RBP]; 2094 tss->si = c->regs[VCPU_REGS_RSI]; 2095 tss->di = c->regs[VCPU_REGS_RDI]; 2096 2097 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); 2098 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); 2099 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); 2100 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); 2101 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); 2102 } 2103 2104 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2105 struct x86_emulate_ops *ops, 2106 struct tss_segment_16 *tss) 2107 { 2108 struct decode_cache *c = &ctxt->decode; 2109 int ret; 2110 2111 c->eip = tss->ip; 2112 ctxt->eflags = tss->flag | 2; 2113 c->regs[VCPU_REGS_RAX] = tss->ax; 2114 c->regs[VCPU_REGS_RCX] = tss->cx; 2115 c->regs[VCPU_REGS_RDX] = tss->dx; 2116 c->regs[VCPU_REGS_RBX] = tss->bx; 2117 c->regs[VCPU_REGS_RSP] = tss->sp; 2118 c->regs[VCPU_REGS_RBP] = tss->bp; 2119 c->regs[VCPU_REGS_RSI] = tss->si; 2120 c->regs[VCPU_REGS_RDI] = tss->di; 2121 2122 /* 2123 * SDM says that segment selectors are loaded before segment 2124 * descriptors 2125 */ 2126 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu); 2127 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); 2128 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); 2129 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); 2130 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); 2131 2132 /* 2133 * Now load segment descriptors. If fault happenes at this stage 2134 * it is handled in a context of new task 2135 */ 2136 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR); 2137 if (ret != X86EMUL_CONTINUE) 2138 return ret; 2139 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); 2140 if (ret != X86EMUL_CONTINUE) 2141 return ret; 2142 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); 2143 if (ret != X86EMUL_CONTINUE) 2144 return ret; 2145 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); 2146 if (ret != X86EMUL_CONTINUE) 2147 return ret; 2148 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); 2149 if (ret != X86EMUL_CONTINUE) 2150 return ret; 2151 2152 return X86EMUL_CONTINUE; 2153 } 2154 2155 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2156 struct x86_emulate_ops *ops, 2157 u16 tss_selector, u16 old_tss_sel, 2158 ulong old_tss_base, struct desc_struct *new_desc) 2159 { 2160 struct tss_segment_16 tss_seg; 2161 int ret; 2162 u32 err, new_tss_base = get_desc_base(new_desc); 2163 2164 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2165 &err); 2166 if (ret == X86EMUL_PROPAGATE_FAULT) { 2167 /* FIXME: need to provide precise fault address */ 2168 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); 2169 return ret; 2170 } 2171 2172 save_state_to_tss16(ctxt, ops, &tss_seg); 2173 2174 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2175 &err); 2176 if (ret == X86EMUL_PROPAGATE_FAULT) { 2177 /* FIXME: need to provide precise fault address */ 2178 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); 2179 return ret; 2180 } 2181 2182 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2183 &err); 2184 if (ret == X86EMUL_PROPAGATE_FAULT) { 2185 /* FIXME: need to provide precise fault address */ 2186 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); 2187 return ret; 2188 } 2189 2190 if (old_tss_sel != 0xffff) { 2191 tss_seg.prev_task_link = old_tss_sel; 2192 2193 ret = ops->write_std(new_tss_base, 2194 &tss_seg.prev_task_link, 2195 sizeof tss_seg.prev_task_link, 2196 ctxt->vcpu, &err); 2197 if (ret == X86EMUL_PROPAGATE_FAULT) { 2198 /* FIXME: need to provide precise fault address */ 2199 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); 2200 return ret; 2201 } 2202 } 2203 2204 return load_state_from_tss16(ctxt, ops, &tss_seg); 2205 } 2206 2207 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2208 struct x86_emulate_ops *ops, 2209 struct tss_segment_32 *tss) 2210 { 2211 struct decode_cache *c = &ctxt->decode; 2212 2213 tss->cr3 = ops->get_cr(3, ctxt->vcpu); 2214 tss->eip = c->eip; 2215 tss->eflags = ctxt->eflags; 2216 tss->eax = c->regs[VCPU_REGS_RAX]; 2217 tss->ecx = c->regs[VCPU_REGS_RCX]; 2218 tss->edx = c->regs[VCPU_REGS_RDX]; 2219 tss->ebx = c->regs[VCPU_REGS_RBX]; 2220 tss->esp = c->regs[VCPU_REGS_RSP]; 2221 tss->ebp = c->regs[VCPU_REGS_RBP]; 2222 tss->esi = c->regs[VCPU_REGS_RSI]; 2223 tss->edi = c->regs[VCPU_REGS_RDI]; 2224 2225 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu); 2226 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu); 2227 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu); 2228 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu); 2229 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu); 2230 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu); 2231 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu); 2232 } 2233 2234 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2235 struct x86_emulate_ops *ops, 2236 struct tss_segment_32 *tss) 2237 { 2238 struct decode_cache *c = &ctxt->decode; 2239 int ret; 2240 2241 ops->set_cr(3, tss->cr3, ctxt->vcpu); 2242 c->eip = tss->eip; 2243 ctxt->eflags = tss->eflags | 2; 2244 c->regs[VCPU_REGS_RAX] = tss->eax; 2245 c->regs[VCPU_REGS_RCX] = tss->ecx; 2246 c->regs[VCPU_REGS_RDX] = tss->edx; 2247 c->regs[VCPU_REGS_RBX] = tss->ebx; 2248 c->regs[VCPU_REGS_RSP] = tss->esp; 2249 c->regs[VCPU_REGS_RBP] = tss->ebp; 2250 c->regs[VCPU_REGS_RSI] = tss->esi; 2251 c->regs[VCPU_REGS_RDI] = tss->edi; 2252 2253 /* 2254 * SDM says that segment selectors are loaded before segment 2255 * descriptors 2256 */ 2257 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu); 2258 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu); 2259 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu); 2260 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu); 2261 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu); 2262 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu); 2263 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu); 2264 2265 /* 2266 * Now load segment descriptors. If fault happenes at this stage 2267 * it is handled in a context of new task 2268 */ 2269 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR); 2270 if (ret != X86EMUL_CONTINUE) 2271 return ret; 2272 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES); 2273 if (ret != X86EMUL_CONTINUE) 2274 return ret; 2275 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS); 2276 if (ret != X86EMUL_CONTINUE) 2277 return ret; 2278 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS); 2279 if (ret != X86EMUL_CONTINUE) 2280 return ret; 2281 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS); 2282 if (ret != X86EMUL_CONTINUE) 2283 return ret; 2284 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS); 2285 if (ret != X86EMUL_CONTINUE) 2286 return ret; 2287 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS); 2288 if (ret != X86EMUL_CONTINUE) 2289 return ret; 2290 2291 return X86EMUL_CONTINUE; 2292 } 2293 2294 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 2295 struct x86_emulate_ops *ops, 2296 u16 tss_selector, u16 old_tss_sel, 2297 ulong old_tss_base, struct desc_struct *new_desc) 2298 { 2299 struct tss_segment_32 tss_seg; 2300 int ret; 2301 u32 err, new_tss_base = get_desc_base(new_desc); 2302 2303 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2304 &err); 2305 if (ret == X86EMUL_PROPAGATE_FAULT) { 2306 /* FIXME: need to provide precise fault address */ 2307 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); 2308 return ret; 2309 } 2310 2311 save_state_to_tss32(ctxt, ops, &tss_seg); 2312 2313 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2314 &err); 2315 if (ret == X86EMUL_PROPAGATE_FAULT) { 2316 /* FIXME: need to provide precise fault address */ 2317 kvm_inject_page_fault(ctxt->vcpu, old_tss_base, err); 2318 return ret; 2319 } 2320 2321 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu, 2322 &err); 2323 if (ret == X86EMUL_PROPAGATE_FAULT) { 2324 /* FIXME: need to provide precise fault address */ 2325 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); 2326 return ret; 2327 } 2328 2329 if (old_tss_sel != 0xffff) { 2330 tss_seg.prev_task_link = old_tss_sel; 2331 2332 ret = ops->write_std(new_tss_base, 2333 &tss_seg.prev_task_link, 2334 sizeof tss_seg.prev_task_link, 2335 ctxt->vcpu, &err); 2336 if (ret == X86EMUL_PROPAGATE_FAULT) { 2337 /* FIXME: need to provide precise fault address */ 2338 kvm_inject_page_fault(ctxt->vcpu, new_tss_base, err); 2339 return ret; 2340 } 2341 } 2342 2343 return load_state_from_tss32(ctxt, ops, &tss_seg); 2344 } 2345 2346 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2347 struct x86_emulate_ops *ops, 2348 u16 tss_selector, int reason, 2349 bool has_error_code, u32 error_code) 2350 { 2351 struct desc_struct curr_tss_desc, next_tss_desc; 2352 int ret; 2353 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu); 2354 ulong old_tss_base = 2355 get_cached_descriptor_base(ctxt, ops, VCPU_SREG_TR); 2356 u32 desc_limit; 2357 2358 /* FIXME: old_tss_base == ~0 ? */ 2359 2360 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc); 2361 if (ret != X86EMUL_CONTINUE) 2362 return ret; 2363 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc); 2364 if (ret != X86EMUL_CONTINUE) 2365 return ret; 2366 2367 /* FIXME: check that next_tss_desc is tss */ 2368 2369 if (reason != TASK_SWITCH_IRET) { 2370 if ((tss_selector & 3) > next_tss_desc.dpl || 2371 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl) { 2372 kvm_inject_gp(ctxt->vcpu, 0); 2373 return X86EMUL_PROPAGATE_FAULT; 2374 } 2375 } 2376 2377 desc_limit = desc_limit_scaled(&next_tss_desc); 2378 if (!next_tss_desc.p || 2379 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2380 desc_limit < 0x2b)) { 2381 kvm_queue_exception_e(ctxt->vcpu, TS_VECTOR, 2382 tss_selector & 0xfffc); 2383 return X86EMUL_PROPAGATE_FAULT; 2384 } 2385 2386 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2387 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2388 write_segment_descriptor(ctxt, ops, old_tss_sel, 2389 &curr_tss_desc); 2390 } 2391 2392 if (reason == TASK_SWITCH_IRET) 2393 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2394 2395 /* set back link to prev task only if NT bit is set in eflags 2396 note that old_tss_sel is not used afetr this point */ 2397 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2398 old_tss_sel = 0xffff; 2399 2400 if (next_tss_desc.type & 8) 2401 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel, 2402 old_tss_base, &next_tss_desc); 2403 else 2404 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel, 2405 old_tss_base, &next_tss_desc); 2406 if (ret != X86EMUL_CONTINUE) 2407 return ret; 2408 2409 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2410 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2411 2412 if (reason != TASK_SWITCH_IRET) { 2413 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2414 write_segment_descriptor(ctxt, ops, tss_selector, 2415 &next_tss_desc); 2416 } 2417 2418 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu); 2419 ops->set_cached_descriptor(&next_tss_desc, VCPU_SREG_TR, ctxt->vcpu); 2420 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu); 2421 2422 if (has_error_code) { 2423 struct decode_cache *c = &ctxt->decode; 2424 2425 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2426 c->lock_prefix = 0; 2427 c->src.val = (unsigned long) error_code; 2428 emulate_push(ctxt); 2429 } 2430 2431 return ret; 2432 } 2433 2434 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2435 struct x86_emulate_ops *ops, 2436 u16 tss_selector, int reason, 2437 bool has_error_code, u32 error_code) 2438 { 2439 struct decode_cache *c = &ctxt->decode; 2440 int rc; 2441 2442 memset(c, 0, sizeof(struct decode_cache)); 2443 c->eip = ctxt->eip; 2444 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); 2445 c->dst.type = OP_NONE; 2446 2447 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason, 2448 has_error_code, error_code); 2449 2450 if (rc == X86EMUL_CONTINUE) { 2451 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); 2452 kvm_rip_write(ctxt->vcpu, c->eip); 2453 rc = writeback(ctxt, ops); 2454 } 2455 2456 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; 2457 } 2458 2459 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned long base, 2460 int reg, struct operand *op) 2461 { 2462 struct decode_cache *c = &ctxt->decode; 2463 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; 2464 2465 register_address_increment(c, &c->regs[reg], df * op->bytes); 2466 op->ptr = (unsigned long *)register_address(c, base, c->regs[reg]); 2467 } 2468 2469 int 2470 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) 2471 { 2472 u64 msr_data; 2473 struct decode_cache *c = &ctxt->decode; 2474 int rc = X86EMUL_CONTINUE; 2475 int saved_dst_type = c->dst.type; 2476 2477 ctxt->interruptibility = 0; 2478 2479 /* Shadow copy of register state. Committed on successful emulation. 2480 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't 2481 * modify them. 2482 */ 2483 2484 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs); 2485 2486 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) { 2487 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 2488 goto done; 2489 } 2490 2491 /* LOCK prefix is allowed only with some instructions */ 2492 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) { 2493 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 2494 goto done; 2495 } 2496 2497 /* Privileged instruction can be executed only in CPL=0 */ 2498 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) { 2499 kvm_inject_gp(ctxt->vcpu, 0); 2500 goto done; 2501 } 2502 2503 if (c->rep_prefix && (c->d & String)) { 2504 ctxt->restart = true; 2505 /* All REP prefixes have the same first termination condition */ 2506 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) { 2507 string_done: 2508 ctxt->restart = false; 2509 kvm_rip_write(ctxt->vcpu, c->eip); 2510 goto done; 2511 } 2512 /* The second termination condition only applies for REPE 2513 * and REPNE. Test if the repeat string operation prefix is 2514 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 2515 * corresponding termination condition according to: 2516 * - if REPE/REPZ and ZF = 0 then done 2517 * - if REPNE/REPNZ and ZF = 1 then done 2518 */ 2519 if ((c->b == 0xa6) || (c->b == 0xa7) || 2520 (c->b == 0xae) || (c->b == 0xaf)) { 2521 if ((c->rep_prefix == REPE_PREFIX) && 2522 ((ctxt->eflags & EFLG_ZF) == 0)) 2523 goto string_done; 2524 if ((c->rep_prefix == REPNE_PREFIX) && 2525 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) 2526 goto string_done; 2527 } 2528 c->eip = ctxt->eip; 2529 } 2530 2531 if (c->src.type == OP_MEM) { 2532 rc = ops->read_emulated((unsigned long)c->src.ptr, 2533 &c->src.val, 2534 c->src.bytes, 2535 ctxt->vcpu); 2536 if (rc != X86EMUL_CONTINUE) 2537 goto done; 2538 c->src.orig_val = c->src.val; 2539 } 2540 2541 if (c->src2.type == OP_MEM) { 2542 rc = ops->read_emulated((unsigned long)c->src2.ptr, 2543 &c->src2.val, 2544 c->src2.bytes, 2545 ctxt->vcpu); 2546 if (rc != X86EMUL_CONTINUE) 2547 goto done; 2548 } 2549 2550 if ((c->d & DstMask) == ImplicitOps) 2551 goto special_insn; 2552 2553 2554 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) { 2555 /* optimisation - avoid slow emulated read if Mov */ 2556 rc = ops->read_emulated((unsigned long)c->dst.ptr, &c->dst.val, 2557 c->dst.bytes, ctxt->vcpu); 2558 if (rc != X86EMUL_CONTINUE) 2559 goto done; 2560 } 2561 c->dst.orig_val = c->dst.val; 2562 2563 special_insn: 2564 2565 if (c->twobyte) 2566 goto twobyte_insn; 2567 2568 switch (c->b) { 2569 case 0x00 ... 0x05: 2570 add: /* add */ 2571 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); 2572 break; 2573 case 0x06: /* push es */ 2574 emulate_push_sreg(ctxt, VCPU_SREG_ES); 2575 break; 2576 case 0x07: /* pop es */ 2577 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES); 2578 if (rc != X86EMUL_CONTINUE) 2579 goto done; 2580 break; 2581 case 0x08 ... 0x0d: 2582 or: /* or */ 2583 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); 2584 break; 2585 case 0x0e: /* push cs */ 2586 emulate_push_sreg(ctxt, VCPU_SREG_CS); 2587 break; 2588 case 0x10 ... 0x15: 2589 adc: /* adc */ 2590 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); 2591 break; 2592 case 0x16: /* push ss */ 2593 emulate_push_sreg(ctxt, VCPU_SREG_SS); 2594 break; 2595 case 0x17: /* pop ss */ 2596 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS); 2597 if (rc != X86EMUL_CONTINUE) 2598 goto done; 2599 break; 2600 case 0x18 ... 0x1d: 2601 sbb: /* sbb */ 2602 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); 2603 break; 2604 case 0x1e: /* push ds */ 2605 emulate_push_sreg(ctxt, VCPU_SREG_DS); 2606 break; 2607 case 0x1f: /* pop ds */ 2608 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS); 2609 if (rc != X86EMUL_CONTINUE) 2610 goto done; 2611 break; 2612 case 0x20 ... 0x25: 2613 and: /* and */ 2614 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); 2615 break; 2616 case 0x28 ... 0x2d: 2617 sub: /* sub */ 2618 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); 2619 break; 2620 case 0x30 ... 0x35: 2621 xor: /* xor */ 2622 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); 2623 break; 2624 case 0x38 ... 0x3d: 2625 cmp: /* cmp */ 2626 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); 2627 break; 2628 case 0x40 ... 0x47: /* inc r16/r32 */ 2629 emulate_1op("inc", c->dst, ctxt->eflags); 2630 break; 2631 case 0x48 ... 0x4f: /* dec r16/r32 */ 2632 emulate_1op("dec", c->dst, ctxt->eflags); 2633 break; 2634 case 0x50 ... 0x57: /* push reg */ 2635 emulate_push(ctxt); 2636 break; 2637 case 0x58 ... 0x5f: /* pop reg */ 2638 pop_instruction: 2639 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes); 2640 if (rc != X86EMUL_CONTINUE) 2641 goto done; 2642 break; 2643 case 0x60: /* pusha */ 2644 emulate_pusha(ctxt); 2645 break; 2646 case 0x61: /* popa */ 2647 rc = emulate_popa(ctxt, ops); 2648 if (rc != X86EMUL_CONTINUE) 2649 goto done; 2650 break; 2651 case 0x63: /* movsxd */ 2652 if (ctxt->mode != X86EMUL_MODE_PROT64) 2653 goto cannot_emulate; 2654 c->dst.val = (s32) c->src.val; 2655 break; 2656 case 0x68: /* push imm */ 2657 case 0x6a: /* push imm8 */ 2658 emulate_push(ctxt); 2659 break; 2660 case 0x6c: /* insb */ 2661 case 0x6d: /* insw/insd */ 2662 c->dst.bytes = min(c->dst.bytes, 4u); 2663 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], 2664 c->dst.bytes)) { 2665 kvm_inject_gp(ctxt->vcpu, 0); 2666 goto done; 2667 } 2668 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, 2669 c->regs[VCPU_REGS_RDX], &c->dst.val)) 2670 goto done; /* IO is needed, skip writeback */ 2671 break; 2672 case 0x6e: /* outsb */ 2673 case 0x6f: /* outsw/outsd */ 2674 c->src.bytes = min(c->src.bytes, 4u); 2675 if (!emulator_io_permited(ctxt, ops, c->regs[VCPU_REGS_RDX], 2676 c->src.bytes)) { 2677 kvm_inject_gp(ctxt->vcpu, 0); 2678 goto done; 2679 } 2680 ops->pio_out_emulated(c->src.bytes, c->regs[VCPU_REGS_RDX], 2681 &c->src.val, 1, ctxt->vcpu); 2682 2683 c->dst.type = OP_NONE; /* nothing to writeback */ 2684 break; 2685 case 0x70 ... 0x7f: /* jcc (short) */ 2686 if (test_cc(c->b, ctxt->eflags)) 2687 jmp_rel(c, c->src.val); 2688 break; 2689 case 0x80 ... 0x83: /* Grp1 */ 2690 switch (c->modrm_reg) { 2691 case 0: 2692 goto add; 2693 case 1: 2694 goto or; 2695 case 2: 2696 goto adc; 2697 case 3: 2698 goto sbb; 2699 case 4: 2700 goto and; 2701 case 5: 2702 goto sub; 2703 case 6: 2704 goto xor; 2705 case 7: 2706 goto cmp; 2707 } 2708 break; 2709 case 0x84 ... 0x85: 2710 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); 2711 break; 2712 case 0x86 ... 0x87: /* xchg */ 2713 xchg: 2714 /* Write back the register source. */ 2715 switch (c->dst.bytes) { 2716 case 1: 2717 *(u8 *) c->src.ptr = (u8) c->dst.val; 2718 break; 2719 case 2: 2720 *(u16 *) c->src.ptr = (u16) c->dst.val; 2721 break; 2722 case 4: 2723 *c->src.ptr = (u32) c->dst.val; 2724 break; /* 64b reg: zero-extend */ 2725 case 8: 2726 *c->src.ptr = c->dst.val; 2727 break; 2728 } 2729 /* 2730 * Write back the memory destination with implicit LOCK 2731 * prefix. 2732 */ 2733 c->dst.val = c->src.val; 2734 c->lock_prefix = 1; 2735 break; 2736 case 0x88 ... 0x8b: /* mov */ 2737 goto mov; 2738 case 0x8c: { /* mov r/m, sreg */ 2739 struct kvm_segment segreg; 2740 2741 if (c->modrm_reg <= VCPU_SREG_GS) 2742 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg); 2743 else { 2744 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 2745 goto done; 2746 } 2747 c->dst.val = segreg.selector; 2748 break; 2749 } 2750 case 0x8d: /* lea r16/r32, m */ 2751 c->dst.val = c->modrm_ea; 2752 break; 2753 case 0x8e: { /* mov seg, r/m16 */ 2754 uint16_t sel; 2755 2756 sel = c->src.val; 2757 2758 if (c->modrm_reg == VCPU_SREG_CS || 2759 c->modrm_reg > VCPU_SREG_GS) { 2760 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 2761 goto done; 2762 } 2763 2764 if (c->modrm_reg == VCPU_SREG_SS) 2765 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_MOV_SS); 2766 2767 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg); 2768 2769 c->dst.type = OP_NONE; /* Disable writeback. */ 2770 break; 2771 } 2772 case 0x8f: /* pop (sole member of Grp1a) */ 2773 rc = emulate_grp1a(ctxt, ops); 2774 if (rc != X86EMUL_CONTINUE) 2775 goto done; 2776 break; 2777 case 0x90: /* nop / xchg r8,rax */ 2778 if (!(c->rex_prefix & 1)) { /* nop */ 2779 c->dst.type = OP_NONE; 2780 break; 2781 } 2782 case 0x91 ... 0x97: /* xchg reg,rax */ 2783 c->src.type = c->dst.type = OP_REG; 2784 c->src.bytes = c->dst.bytes = c->op_bytes; 2785 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX]; 2786 c->src.val = *(c->src.ptr); 2787 goto xchg; 2788 case 0x9c: /* pushf */ 2789 c->src.val = (unsigned long) ctxt->eflags; 2790 emulate_push(ctxt); 2791 break; 2792 case 0x9d: /* popf */ 2793 c->dst.type = OP_REG; 2794 c->dst.ptr = (unsigned long *) &ctxt->eflags; 2795 c->dst.bytes = c->op_bytes; 2796 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes); 2797 if (rc != X86EMUL_CONTINUE) 2798 goto done; 2799 break; 2800 case 0xa0 ... 0xa1: /* mov */ 2801 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; 2802 c->dst.val = c->src.val; 2803 break; 2804 case 0xa2 ... 0xa3: /* mov */ 2805 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; 2806 break; 2807 case 0xa4 ... 0xa5: /* movs */ 2808 goto mov; 2809 case 0xa6 ... 0xa7: /* cmps */ 2810 c->dst.type = OP_NONE; /* Disable writeback. */ 2811 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr); 2812 goto cmp; 2813 case 0xaa ... 0xab: /* stos */ 2814 c->dst.val = c->regs[VCPU_REGS_RAX]; 2815 break; 2816 case 0xac ... 0xad: /* lods */ 2817 goto mov; 2818 case 0xae ... 0xaf: /* scas */ 2819 DPRINTF("Urk! I don't handle SCAS.\n"); 2820 goto cannot_emulate; 2821 case 0xb0 ... 0xbf: /* mov r, imm */ 2822 goto mov; 2823 case 0xc0 ... 0xc1: 2824 emulate_grp2(ctxt); 2825 break; 2826 case 0xc3: /* ret */ 2827 c->dst.type = OP_REG; 2828 c->dst.ptr = &c->eip; 2829 c->dst.bytes = c->op_bytes; 2830 goto pop_instruction; 2831 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ 2832 mov: 2833 c->dst.val = c->src.val; 2834 break; 2835 case 0xcb: /* ret far */ 2836 rc = emulate_ret_far(ctxt, ops); 2837 if (rc != X86EMUL_CONTINUE) 2838 goto done; 2839 break; 2840 case 0xd0 ... 0xd1: /* Grp2 */ 2841 c->src.val = 1; 2842 emulate_grp2(ctxt); 2843 break; 2844 case 0xd2 ... 0xd3: /* Grp2 */ 2845 c->src.val = c->regs[VCPU_REGS_RCX]; 2846 emulate_grp2(ctxt); 2847 break; 2848 case 0xe4: /* inb */ 2849 case 0xe5: /* in */ 2850 goto do_io_in; 2851 case 0xe6: /* outb */ 2852 case 0xe7: /* out */ 2853 goto do_io_out; 2854 case 0xe8: /* call (near) */ { 2855 long int rel = c->src.val; 2856 c->src.val = (unsigned long) c->eip; 2857 jmp_rel(c, rel); 2858 emulate_push(ctxt); 2859 break; 2860 } 2861 case 0xe9: /* jmp rel */ 2862 goto jmp; 2863 case 0xea: /* jmp far */ 2864 jump_far: 2865 if (load_segment_descriptor(ctxt, ops, c->src2.val, 2866 VCPU_SREG_CS)) 2867 goto done; 2868 2869 c->eip = c->src.val; 2870 break; 2871 case 0xeb: 2872 jmp: /* jmp rel short */ 2873 jmp_rel(c, c->src.val); 2874 c->dst.type = OP_NONE; /* Disable writeback. */ 2875 break; 2876 case 0xec: /* in al,dx */ 2877 case 0xed: /* in (e/r)ax,dx */ 2878 c->src.val = c->regs[VCPU_REGS_RDX]; 2879 do_io_in: 2880 c->dst.bytes = min(c->dst.bytes, 4u); 2881 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { 2882 kvm_inject_gp(ctxt->vcpu, 0); 2883 goto done; 2884 } 2885 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val, 2886 &c->dst.val)) 2887 goto done; /* IO is needed */ 2888 break; 2889 case 0xee: /* out al,dx */ 2890 case 0xef: /* out (e/r)ax,dx */ 2891 c->src.val = c->regs[VCPU_REGS_RDX]; 2892 do_io_out: 2893 c->dst.bytes = min(c->dst.bytes, 4u); 2894 if (!emulator_io_permited(ctxt, ops, c->src.val, c->dst.bytes)) { 2895 kvm_inject_gp(ctxt->vcpu, 0); 2896 goto done; 2897 } 2898 ops->pio_out_emulated(c->dst.bytes, c->src.val, &c->dst.val, 1, 2899 ctxt->vcpu); 2900 c->dst.type = OP_NONE; /* Disable writeback. */ 2901 break; 2902 case 0xf4: /* hlt */ 2903 ctxt->vcpu->arch.halt_request = 1; 2904 break; 2905 case 0xf5: /* cmc */ 2906 /* complement carry flag from eflags reg */ 2907 ctxt->eflags ^= EFLG_CF; 2908 c->dst.type = OP_NONE; /* Disable writeback. */ 2909 break; 2910 case 0xf6 ... 0xf7: /* Grp3 */ 2911 if (!emulate_grp3(ctxt, ops)) 2912 goto cannot_emulate; 2913 break; 2914 case 0xf8: /* clc */ 2915 ctxt->eflags &= ~EFLG_CF; 2916 c->dst.type = OP_NONE; /* Disable writeback. */ 2917 break; 2918 case 0xfa: /* cli */ 2919 if (emulator_bad_iopl(ctxt, ops)) 2920 kvm_inject_gp(ctxt->vcpu, 0); 2921 else { 2922 ctxt->eflags &= ~X86_EFLAGS_IF; 2923 c->dst.type = OP_NONE; /* Disable writeback. */ 2924 } 2925 break; 2926 case 0xfb: /* sti */ 2927 if (emulator_bad_iopl(ctxt, ops)) 2928 kvm_inject_gp(ctxt->vcpu, 0); 2929 else { 2930 toggle_interruptibility(ctxt, KVM_X86_SHADOW_INT_STI); 2931 ctxt->eflags |= X86_EFLAGS_IF; 2932 c->dst.type = OP_NONE; /* Disable writeback. */ 2933 } 2934 break; 2935 case 0xfc: /* cld */ 2936 ctxt->eflags &= ~EFLG_DF; 2937 c->dst.type = OP_NONE; /* Disable writeback. */ 2938 break; 2939 case 0xfd: /* std */ 2940 ctxt->eflags |= EFLG_DF; 2941 c->dst.type = OP_NONE; /* Disable writeback. */ 2942 break; 2943 case 0xfe: /* Grp4 */ 2944 grp45: 2945 rc = emulate_grp45(ctxt, ops); 2946 if (rc != X86EMUL_CONTINUE) 2947 goto done; 2948 break; 2949 case 0xff: /* Grp5 */ 2950 if (c->modrm_reg == 5) 2951 goto jump_far; 2952 goto grp45; 2953 } 2954 2955 writeback: 2956 rc = writeback(ctxt, ops); 2957 if (rc != X86EMUL_CONTINUE) 2958 goto done; 2959 2960 /* 2961 * restore dst type in case the decoding will be reused 2962 * (happens for string instruction ) 2963 */ 2964 c->dst.type = saved_dst_type; 2965 2966 if ((c->d & SrcMask) == SrcSI) 2967 string_addr_inc(ctxt, seg_override_base(ctxt, c), VCPU_REGS_RSI, 2968 &c->src); 2969 2970 if ((c->d & DstMask) == DstDI) 2971 string_addr_inc(ctxt, es_base(ctxt), VCPU_REGS_RDI, &c->dst); 2972 2973 if (c->rep_prefix && (c->d & String)) { 2974 struct read_cache *rc = &ctxt->decode.io_read; 2975 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1); 2976 /* 2977 * Re-enter guest when pio read ahead buffer is empty or, 2978 * if it is not used, after each 1024 iteration. 2979 */ 2980 if ((rc->end == 0 && !(c->regs[VCPU_REGS_RCX] & 0x3ff)) || 2981 (rc->end != 0 && rc->end == rc->pos)) 2982 ctxt->restart = false; 2983 } 2984 2985 /* Commit shadow register state. */ 2986 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs); 2987 kvm_rip_write(ctxt->vcpu, c->eip); 2988 ops->set_rflags(ctxt->vcpu, ctxt->eflags); 2989 2990 done: 2991 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; 2992 2993 twobyte_insn: 2994 switch (c->b) { 2995 case 0x01: /* lgdt, lidt, lmsw */ 2996 switch (c->modrm_reg) { 2997 u16 size; 2998 unsigned long address; 2999 3000 case 0: /* vmcall */ 3001 if (c->modrm_mod != 3 || c->modrm_rm != 1) 3002 goto cannot_emulate; 3003 3004 rc = kvm_fix_hypercall(ctxt->vcpu); 3005 if (rc != X86EMUL_CONTINUE) 3006 goto done; 3007 3008 /* Let the processor re-execute the fixed hypercall */ 3009 c->eip = ctxt->eip; 3010 /* Disable writeback. */ 3011 c->dst.type = OP_NONE; 3012 break; 3013 case 2: /* lgdt */ 3014 rc = read_descriptor(ctxt, ops, c->src.ptr, 3015 &size, &address, c->op_bytes); 3016 if (rc != X86EMUL_CONTINUE) 3017 goto done; 3018 realmode_lgdt(ctxt->vcpu, size, address); 3019 /* Disable writeback. */ 3020 c->dst.type = OP_NONE; 3021 break; 3022 case 3: /* lidt/vmmcall */ 3023 if (c->modrm_mod == 3) { 3024 switch (c->modrm_rm) { 3025 case 1: 3026 rc = kvm_fix_hypercall(ctxt->vcpu); 3027 if (rc != X86EMUL_CONTINUE) 3028 goto done; 3029 break; 3030 default: 3031 goto cannot_emulate; 3032 } 3033 } else { 3034 rc = read_descriptor(ctxt, ops, c->src.ptr, 3035 &size, &address, 3036 c->op_bytes); 3037 if (rc != X86EMUL_CONTINUE) 3038 goto done; 3039 realmode_lidt(ctxt->vcpu, size, address); 3040 } 3041 /* Disable writeback. */ 3042 c->dst.type = OP_NONE; 3043 break; 3044 case 4: /* smsw */ 3045 c->dst.bytes = 2; 3046 c->dst.val = ops->get_cr(0, ctxt->vcpu); 3047 break; 3048 case 6: /* lmsw */ 3049 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0ful) | 3050 (c->src.val & 0x0f), ctxt->vcpu); 3051 c->dst.type = OP_NONE; 3052 break; 3053 case 5: /* not defined */ 3054 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 3055 goto done; 3056 case 7: /* invlpg*/ 3057 emulate_invlpg(ctxt->vcpu, c->modrm_ea); 3058 /* Disable writeback. */ 3059 c->dst.type = OP_NONE; 3060 break; 3061 default: 3062 goto cannot_emulate; 3063 } 3064 break; 3065 case 0x05: /* syscall */ 3066 rc = emulate_syscall(ctxt); 3067 if (rc != X86EMUL_CONTINUE) 3068 goto done; 3069 else 3070 goto writeback; 3071 break; 3072 case 0x06: 3073 emulate_clts(ctxt->vcpu); 3074 c->dst.type = OP_NONE; 3075 break; 3076 case 0x08: /* invd */ 3077 case 0x09: /* wbinvd */ 3078 case 0x0d: /* GrpP (prefetch) */ 3079 case 0x18: /* Grp16 (prefetch/nop) */ 3080 c->dst.type = OP_NONE; 3081 break; 3082 case 0x20: /* mov cr, reg */ 3083 switch (c->modrm_reg) { 3084 case 1: 3085 case 5 ... 7: 3086 case 9 ... 15: 3087 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 3088 goto done; 3089 } 3090 c->regs[c->modrm_rm] = ops->get_cr(c->modrm_reg, ctxt->vcpu); 3091 c->dst.type = OP_NONE; /* no writeback */ 3092 break; 3093 case 0x21: /* mov from dr to reg */ 3094 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && 3095 (c->modrm_reg == 4 || c->modrm_reg == 5)) { 3096 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 3097 goto done; 3098 } 3099 emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); 3100 c->dst.type = OP_NONE; /* no writeback */ 3101 break; 3102 case 0x22: /* mov reg, cr */ 3103 ops->set_cr(c->modrm_reg, c->modrm_val, ctxt->vcpu); 3104 c->dst.type = OP_NONE; 3105 break; 3106 case 0x23: /* mov from reg to dr */ 3107 if ((ops->get_cr(4, ctxt->vcpu) & X86_CR4_DE) && 3108 (c->modrm_reg == 4 || c->modrm_reg == 5)) { 3109 kvm_queue_exception(ctxt->vcpu, UD_VECTOR); 3110 goto done; 3111 } 3112 emulator_set_dr(ctxt, c->modrm_reg, c->regs[c->modrm_rm]); 3113 c->dst.type = OP_NONE; /* no writeback */ 3114 break; 3115 case 0x30: 3116 /* wrmsr */ 3117 msr_data = (u32)c->regs[VCPU_REGS_RAX] 3118 | ((u64)c->regs[VCPU_REGS_RDX] << 32); 3119 if (kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) { 3120 kvm_inject_gp(ctxt->vcpu, 0); 3121 goto done; 3122 } 3123 rc = X86EMUL_CONTINUE; 3124 c->dst.type = OP_NONE; 3125 break; 3126 case 0x32: 3127 /* rdmsr */ 3128 if (kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) { 3129 kvm_inject_gp(ctxt->vcpu, 0); 3130 goto done; 3131 } else { 3132 c->regs[VCPU_REGS_RAX] = (u32)msr_data; 3133 c->regs[VCPU_REGS_RDX] = msr_data >> 32; 3134 } 3135 rc = X86EMUL_CONTINUE; 3136 c->dst.type = OP_NONE; 3137 break; 3138 case 0x34: /* sysenter */ 3139 rc = emulate_sysenter(ctxt); 3140 if (rc != X86EMUL_CONTINUE) 3141 goto done; 3142 else 3143 goto writeback; 3144 break; 3145 case 0x35: /* sysexit */ 3146 rc = emulate_sysexit(ctxt); 3147 if (rc != X86EMUL_CONTINUE) 3148 goto done; 3149 else 3150 goto writeback; 3151 break; 3152 case 0x40 ... 0x4f: /* cmov */ 3153 c->dst.val = c->dst.orig_val = c->src.val; 3154 if (!test_cc(c->b, ctxt->eflags)) 3155 c->dst.type = OP_NONE; /* no writeback */ 3156 break; 3157 case 0x80 ... 0x8f: /* jnz rel, etc*/ 3158 if (test_cc(c->b, ctxt->eflags)) 3159 jmp_rel(c, c->src.val); 3160 c->dst.type = OP_NONE; 3161 break; 3162 case 0xa0: /* push fs */ 3163 emulate_push_sreg(ctxt, VCPU_SREG_FS); 3164 break; 3165 case 0xa1: /* pop fs */ 3166 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS); 3167 if (rc != X86EMUL_CONTINUE) 3168 goto done; 3169 break; 3170 case 0xa3: 3171 bt: /* bt */ 3172 c->dst.type = OP_NONE; 3173 /* only subword offset */ 3174 c->src.val &= (c->dst.bytes << 3) - 1; 3175 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); 3176 break; 3177 case 0xa4: /* shld imm8, r, r/m */ 3178 case 0xa5: /* shld cl, r, r/m */ 3179 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags); 3180 break; 3181 case 0xa8: /* push gs */ 3182 emulate_push_sreg(ctxt, VCPU_SREG_GS); 3183 break; 3184 case 0xa9: /* pop gs */ 3185 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS); 3186 if (rc != X86EMUL_CONTINUE) 3187 goto done; 3188 break; 3189 case 0xab: 3190 bts: /* bts */ 3191 /* only subword offset */ 3192 c->src.val &= (c->dst.bytes << 3) - 1; 3193 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); 3194 break; 3195 case 0xac: /* shrd imm8, r, r/m */ 3196 case 0xad: /* shrd cl, r, r/m */ 3197 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags); 3198 break; 3199 case 0xae: /* clflush */ 3200 break; 3201 case 0xb0 ... 0xb1: /* cmpxchg */ 3202 /* 3203 * Save real source value, then compare EAX against 3204 * destination. 3205 */ 3206 c->src.orig_val = c->src.val; 3207 c->src.val = c->regs[VCPU_REGS_RAX]; 3208 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); 3209 if (ctxt->eflags & EFLG_ZF) { 3210 /* Success: write back to memory. */ 3211 c->dst.val = c->src.orig_val; 3212 } else { 3213 /* Failure: write the value we saw to EAX. */ 3214 c->dst.type = OP_REG; 3215 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; 3216 } 3217 break; 3218 case 0xb3: 3219 btr: /* btr */ 3220 /* only subword offset */ 3221 c->src.val &= (c->dst.bytes << 3) - 1; 3222 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); 3223 break; 3224 case 0xb6 ... 0xb7: /* movzx */ 3225 c->dst.bytes = c->op_bytes; 3226 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val 3227 : (u16) c->src.val; 3228 break; 3229 case 0xba: /* Grp8 */ 3230 switch (c->modrm_reg & 3) { 3231 case 0: 3232 goto bt; 3233 case 1: 3234 goto bts; 3235 case 2: 3236 goto btr; 3237 case 3: 3238 goto btc; 3239 } 3240 break; 3241 case 0xbb: 3242 btc: /* btc */ 3243 /* only subword offset */ 3244 c->src.val &= (c->dst.bytes << 3) - 1; 3245 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); 3246 break; 3247 case 0xbe ... 0xbf: /* movsx */ 3248 c->dst.bytes = c->op_bytes; 3249 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : 3250 (s16) c->src.val; 3251 break; 3252 case 0xc3: /* movnti */ 3253 c->dst.bytes = c->op_bytes; 3254 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : 3255 (u64) c->src.val; 3256 break; 3257 case 0xc7: /* Grp9 (cmpxchg8b) */ 3258 rc = emulate_grp9(ctxt, ops); 3259 if (rc != X86EMUL_CONTINUE) 3260 goto done; 3261 break; 3262 } 3263 goto writeback; 3264 3265 cannot_emulate: 3266 DPRINTF("Cannot emulate %02x\n", c->b); 3267 return -1; 3268 } 3269