1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <asm/kvm_emulate.h> 26 #include <linux/stringify.h> 27 #include <asm/debugreg.h> 28 #include <asm/nospec-branch.h> 29 30 #include "x86.h" 31 #include "tss.h" 32 #include "mmu.h" 33 #include "pmu.h" 34 35 /* 36 * Operand types 37 */ 38 #define OpNone 0ull 39 #define OpImplicit 1ull /* No generic decode */ 40 #define OpReg 2ull /* Register */ 41 #define OpMem 3ull /* Memory */ 42 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 43 #define OpDI 5ull /* ES:DI/EDI/RDI */ 44 #define OpMem64 6ull /* Memory, 64-bit */ 45 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 46 #define OpDX 8ull /* DX register */ 47 #define OpCL 9ull /* CL register (for shifts) */ 48 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 49 #define OpOne 11ull /* Implied 1 */ 50 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 51 #define OpMem16 13ull /* Memory operand (16-bit). */ 52 #define OpMem32 14ull /* Memory operand (32-bit). */ 53 #define OpImmU 15ull /* Immediate operand, zero extended */ 54 #define OpSI 16ull /* SI/ESI/RSI */ 55 #define OpImmFAddr 17ull /* Immediate far address */ 56 #define OpMemFAddr 18ull /* Far address in memory */ 57 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 58 #define OpES 20ull /* ES */ 59 #define OpCS 21ull /* CS */ 60 #define OpSS 22ull /* SS */ 61 #define OpDS 23ull /* DS */ 62 #define OpFS 24ull /* FS */ 63 #define OpGS 25ull /* GS */ 64 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 65 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 66 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 67 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 68 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 69 70 #define OpBits 5 /* Width of operand field */ 71 #define OpMask ((1ull << OpBits) - 1) 72 73 /* 74 * Opcode effective-address decode tables. 75 * Note that we only emulate instructions that have at least one memory 76 * operand (excluding implicit stack references). We assume that stack 77 * references and instruction fetches will never occur in special memory 78 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 79 * not be handled. 80 */ 81 82 /* Operand sizes: 8-bit operands or specified/overridden size. */ 83 #define ByteOp (1<<0) /* 8-bit operands. */ 84 /* Destination operand type. */ 85 #define DstShift 1 86 #define ImplicitOps (OpImplicit << DstShift) 87 #define DstReg (OpReg << DstShift) 88 #define DstMem (OpMem << DstShift) 89 #define DstAcc (OpAcc << DstShift) 90 #define DstDI (OpDI << DstShift) 91 #define DstMem64 (OpMem64 << DstShift) 92 #define DstMem16 (OpMem16 << DstShift) 93 #define DstImmUByte (OpImmUByte << DstShift) 94 #define DstDX (OpDX << DstShift) 95 #define DstAccLo (OpAccLo << DstShift) 96 #define DstMask (OpMask << DstShift) 97 /* Source operand type. */ 98 #define SrcShift 6 99 #define SrcNone (OpNone << SrcShift) 100 #define SrcReg (OpReg << SrcShift) 101 #define SrcMem (OpMem << SrcShift) 102 #define SrcMem16 (OpMem16 << SrcShift) 103 #define SrcMem32 (OpMem32 << SrcShift) 104 #define SrcImm (OpImm << SrcShift) 105 #define SrcImmByte (OpImmByte << SrcShift) 106 #define SrcOne (OpOne << SrcShift) 107 #define SrcImmUByte (OpImmUByte << SrcShift) 108 #define SrcImmU (OpImmU << SrcShift) 109 #define SrcSI (OpSI << SrcShift) 110 #define SrcXLat (OpXLat << SrcShift) 111 #define SrcImmFAddr (OpImmFAddr << SrcShift) 112 #define SrcMemFAddr (OpMemFAddr << SrcShift) 113 #define SrcAcc (OpAcc << SrcShift) 114 #define SrcImmU16 (OpImmU16 << SrcShift) 115 #define SrcImm64 (OpImm64 << SrcShift) 116 #define SrcDX (OpDX << SrcShift) 117 #define SrcMem8 (OpMem8 << SrcShift) 118 #define SrcAccHi (OpAccHi << SrcShift) 119 #define SrcMask (OpMask << SrcShift) 120 #define BitOp (1<<11) 121 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 122 #define String (1<<13) /* String instruction (rep capable) */ 123 #define Stack (1<<14) /* Stack instruction (push/pop) */ 124 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 125 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 126 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 127 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 128 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 129 #define Escape (5<<15) /* Escape to coprocessor instruction */ 130 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 131 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 132 #define Sse (1<<18) /* SSE Vector instruction */ 133 /* Generic ModRM decode. */ 134 #define ModRM (1<<19) 135 /* Destination is only written; never read. */ 136 #define Mov (1<<20) 137 /* Misc flags */ 138 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 139 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 140 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 141 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 142 #define Undefined (1<<25) /* No Such Instruction */ 143 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 144 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 145 #define No64 (1<<28) 146 #define PageTable (1 << 29) /* instruction used to write page table */ 147 #define NotImpl (1 << 30) /* instruction is not implemented */ 148 /* Source 2 operand type */ 149 #define Src2Shift (31) 150 #define Src2None (OpNone << Src2Shift) 151 #define Src2Mem (OpMem << Src2Shift) 152 #define Src2CL (OpCL << Src2Shift) 153 #define Src2ImmByte (OpImmByte << Src2Shift) 154 #define Src2One (OpOne << Src2Shift) 155 #define Src2Imm (OpImm << Src2Shift) 156 #define Src2ES (OpES << Src2Shift) 157 #define Src2CS (OpCS << Src2Shift) 158 #define Src2SS (OpSS << Src2Shift) 159 #define Src2DS (OpDS << Src2Shift) 160 #define Src2FS (OpFS << Src2Shift) 161 #define Src2GS (OpGS << Src2Shift) 162 #define Src2Mask (OpMask << Src2Shift) 163 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 164 #define AlignMask ((u64)7 << 41) 165 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 166 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 167 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 168 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 169 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 170 #define NoWrite ((u64)1 << 45) /* No writeback */ 171 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 172 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 173 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 174 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 175 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 176 #define NearBranch ((u64)1 << 52) /* Near branches */ 177 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 178 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 179 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 180 181 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 182 183 #define X2(x...) x, x 184 #define X3(x...) X2(x), x 185 #define X4(x...) X2(x), X2(x) 186 #define X5(x...) X4(x), x 187 #define X6(x...) X4(x), X2(x) 188 #define X7(x...) X4(x), X3(x) 189 #define X8(x...) X4(x), X4(x) 190 #define X16(x...) X8(x), X8(x) 191 192 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 193 #define FASTOP_SIZE 8 194 195 /* 196 * fastop functions have a special calling convention: 197 * 198 * dst: rax (in/out) 199 * src: rdx (in/out) 200 * src2: rcx (in) 201 * flags: rflags (in/out) 202 * ex: rsi (in:fastop pointer, out:zero if exception) 203 * 204 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 205 * different operand sizes can be reached by calculation, rather than a jump 206 * table (which would be bigger than the code). 207 * 208 * fastop functions are declared as taking a never-defined fastop parameter, 209 * so they can't be called from C directly. 210 */ 211 212 struct fastop; 213 214 struct opcode { 215 u64 flags : 56; 216 u64 intercept : 8; 217 union { 218 int (*execute)(struct x86_emulate_ctxt *ctxt); 219 const struct opcode *group; 220 const struct group_dual *gdual; 221 const struct gprefix *gprefix; 222 const struct escape *esc; 223 const struct instr_dual *idual; 224 const struct mode_dual *mdual; 225 void (*fastop)(struct fastop *fake); 226 } u; 227 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 228 }; 229 230 struct group_dual { 231 struct opcode mod012[8]; 232 struct opcode mod3[8]; 233 }; 234 235 struct gprefix { 236 struct opcode pfx_no; 237 struct opcode pfx_66; 238 struct opcode pfx_f2; 239 struct opcode pfx_f3; 240 }; 241 242 struct escape { 243 struct opcode op[8]; 244 struct opcode high[64]; 245 }; 246 247 struct instr_dual { 248 struct opcode mod012; 249 struct opcode mod3; 250 }; 251 252 struct mode_dual { 253 struct opcode mode32; 254 struct opcode mode64; 255 }; 256 257 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 258 259 enum x86_transfer_type { 260 X86_TRANSFER_NONE, 261 X86_TRANSFER_CALL_JMP, 262 X86_TRANSFER_RET, 263 X86_TRANSFER_TASK_SWITCH, 264 }; 265 266 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 267 { 268 if (!(ctxt->regs_valid & (1 << nr))) { 269 ctxt->regs_valid |= 1 << nr; 270 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 271 } 272 return ctxt->_regs[nr]; 273 } 274 275 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 276 { 277 ctxt->regs_valid |= 1 << nr; 278 ctxt->regs_dirty |= 1 << nr; 279 return &ctxt->_regs[nr]; 280 } 281 282 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 283 { 284 reg_read(ctxt, nr); 285 return reg_write(ctxt, nr); 286 } 287 288 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 289 { 290 unsigned reg; 291 292 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 293 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 294 } 295 296 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 297 { 298 ctxt->regs_dirty = 0; 299 ctxt->regs_valid = 0; 300 } 301 302 /* 303 * These EFLAGS bits are restored from saved value during emulation, and 304 * any changes are written back to the saved value after emulation. 305 */ 306 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 307 X86_EFLAGS_PF|X86_EFLAGS_CF) 308 309 #ifdef CONFIG_X86_64 310 #define ON64(x) x 311 #else 312 #define ON64(x) 313 #endif 314 315 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 316 317 #define FOP_FUNC(name) \ 318 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 319 ".type " name ", @function \n\t" \ 320 name ":\n\t" 321 322 #define FOP_RET "ret \n\t" 323 324 #define FOP_START(op) \ 325 extern void em_##op(struct fastop *fake); \ 326 asm(".pushsection .text, \"ax\" \n\t" \ 327 ".global em_" #op " \n\t" \ 328 FOP_FUNC("em_" #op) 329 330 #define FOP_END \ 331 ".popsection") 332 333 #define FOPNOP() \ 334 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \ 335 FOP_RET 336 337 #define FOP1E(op, dst) \ 338 FOP_FUNC(#op "_" #dst) \ 339 "10: " #op " %" #dst " \n\t" FOP_RET 340 341 #define FOP1EEX(op, dst) \ 342 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 343 344 #define FASTOP1(op) \ 345 FOP_START(op) \ 346 FOP1E(op##b, al) \ 347 FOP1E(op##w, ax) \ 348 FOP1E(op##l, eax) \ 349 ON64(FOP1E(op##q, rax)) \ 350 FOP_END 351 352 /* 1-operand, using src2 (for MUL/DIV r/m) */ 353 #define FASTOP1SRC2(op, name) \ 354 FOP_START(name) \ 355 FOP1E(op, cl) \ 356 FOP1E(op, cx) \ 357 FOP1E(op, ecx) \ 358 ON64(FOP1E(op, rcx)) \ 359 FOP_END 360 361 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 362 #define FASTOP1SRC2EX(op, name) \ 363 FOP_START(name) \ 364 FOP1EEX(op, cl) \ 365 FOP1EEX(op, cx) \ 366 FOP1EEX(op, ecx) \ 367 ON64(FOP1EEX(op, rcx)) \ 368 FOP_END 369 370 #define FOP2E(op, dst, src) \ 371 FOP_FUNC(#op "_" #dst "_" #src) \ 372 #op " %" #src ", %" #dst " \n\t" FOP_RET 373 374 #define FASTOP2(op) \ 375 FOP_START(op) \ 376 FOP2E(op##b, al, dl) \ 377 FOP2E(op##w, ax, dx) \ 378 FOP2E(op##l, eax, edx) \ 379 ON64(FOP2E(op##q, rax, rdx)) \ 380 FOP_END 381 382 /* 2 operand, word only */ 383 #define FASTOP2W(op) \ 384 FOP_START(op) \ 385 FOPNOP() \ 386 FOP2E(op##w, ax, dx) \ 387 FOP2E(op##l, eax, edx) \ 388 ON64(FOP2E(op##q, rax, rdx)) \ 389 FOP_END 390 391 /* 2 operand, src is CL */ 392 #define FASTOP2CL(op) \ 393 FOP_START(op) \ 394 FOP2E(op##b, al, cl) \ 395 FOP2E(op##w, ax, cl) \ 396 FOP2E(op##l, eax, cl) \ 397 ON64(FOP2E(op##q, rax, cl)) \ 398 FOP_END 399 400 /* 2 operand, src and dest are reversed */ 401 #define FASTOP2R(op, name) \ 402 FOP_START(name) \ 403 FOP2E(op##b, dl, al) \ 404 FOP2E(op##w, dx, ax) \ 405 FOP2E(op##l, edx, eax) \ 406 ON64(FOP2E(op##q, rdx, rax)) \ 407 FOP_END 408 409 #define FOP3E(op, dst, src, src2) \ 410 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 411 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 412 413 /* 3-operand, word-only, src2=cl */ 414 #define FASTOP3WCL(op) \ 415 FOP_START(op) \ 416 FOPNOP() \ 417 FOP3E(op##w, ax, dx, cl) \ 418 FOP3E(op##l, eax, edx, cl) \ 419 ON64(FOP3E(op##q, rax, rdx, cl)) \ 420 FOP_END 421 422 /* Special case for SETcc - 1 instruction per cc */ 423 #define FOP_SETCC(op) \ 424 ".align 4 \n\t" \ 425 ".type " #op ", @function \n\t" \ 426 #op ": \n\t" \ 427 #op " %al \n\t" \ 428 FOP_RET 429 430 asm(".pushsection .fixup, \"ax\"\n" 431 ".global kvm_fastop_exception \n" 432 "kvm_fastop_exception: xor %esi, %esi; ret\n" 433 ".popsection"); 434 435 FOP_START(setcc) 436 FOP_SETCC(seto) 437 FOP_SETCC(setno) 438 FOP_SETCC(setc) 439 FOP_SETCC(setnc) 440 FOP_SETCC(setz) 441 FOP_SETCC(setnz) 442 FOP_SETCC(setbe) 443 FOP_SETCC(setnbe) 444 FOP_SETCC(sets) 445 FOP_SETCC(setns) 446 FOP_SETCC(setp) 447 FOP_SETCC(setnp) 448 FOP_SETCC(setl) 449 FOP_SETCC(setnl) 450 FOP_SETCC(setle) 451 FOP_SETCC(setnle) 452 FOP_END; 453 454 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 455 FOP_END; 456 457 /* 458 * XXX: inoutclob user must know where the argument is being expanded. 459 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault. 460 */ 461 #define asm_safe(insn, inoutclob...) \ 462 ({ \ 463 int _fault = 0; \ 464 \ 465 asm volatile("1:" insn "\n" \ 466 "2:\n" \ 467 ".pushsection .fixup, \"ax\"\n" \ 468 "3: movl $1, %[_fault]\n" \ 469 " jmp 2b\n" \ 470 ".popsection\n" \ 471 _ASM_EXTABLE(1b, 3b) \ 472 : [_fault] "+qm"(_fault) inoutclob ); \ 473 \ 474 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 475 }) 476 477 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 478 enum x86_intercept intercept, 479 enum x86_intercept_stage stage) 480 { 481 struct x86_instruction_info info = { 482 .intercept = intercept, 483 .rep_prefix = ctxt->rep_prefix, 484 .modrm_mod = ctxt->modrm_mod, 485 .modrm_reg = ctxt->modrm_reg, 486 .modrm_rm = ctxt->modrm_rm, 487 .src_val = ctxt->src.val64, 488 .dst_val = ctxt->dst.val64, 489 .src_bytes = ctxt->src.bytes, 490 .dst_bytes = ctxt->dst.bytes, 491 .ad_bytes = ctxt->ad_bytes, 492 .next_rip = ctxt->eip, 493 }; 494 495 return ctxt->ops->intercept(ctxt, &info, stage); 496 } 497 498 static void assign_masked(ulong *dest, ulong src, ulong mask) 499 { 500 *dest = (*dest & ~mask) | (src & mask); 501 } 502 503 static void assign_register(unsigned long *reg, u64 val, int bytes) 504 { 505 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 506 switch (bytes) { 507 case 1: 508 *(u8 *)reg = (u8)val; 509 break; 510 case 2: 511 *(u16 *)reg = (u16)val; 512 break; 513 case 4: 514 *reg = (u32)val; 515 break; /* 64b: zero-extend */ 516 case 8: 517 *reg = val; 518 break; 519 } 520 } 521 522 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 523 { 524 return (1UL << (ctxt->ad_bytes << 3)) - 1; 525 } 526 527 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 528 { 529 u16 sel; 530 struct desc_struct ss; 531 532 if (ctxt->mode == X86EMUL_MODE_PROT64) 533 return ~0UL; 534 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 535 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 536 } 537 538 static int stack_size(struct x86_emulate_ctxt *ctxt) 539 { 540 return (__fls(stack_mask(ctxt)) + 1) >> 3; 541 } 542 543 /* Access/update address held in a register, based on addressing mode. */ 544 static inline unsigned long 545 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 546 { 547 if (ctxt->ad_bytes == sizeof(unsigned long)) 548 return reg; 549 else 550 return reg & ad_mask(ctxt); 551 } 552 553 static inline unsigned long 554 register_address(struct x86_emulate_ctxt *ctxt, int reg) 555 { 556 return address_mask(ctxt, reg_read(ctxt, reg)); 557 } 558 559 static void masked_increment(ulong *reg, ulong mask, int inc) 560 { 561 assign_masked(reg, *reg + inc, mask); 562 } 563 564 static inline void 565 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 566 { 567 ulong *preg = reg_rmw(ctxt, reg); 568 569 assign_register(preg, *preg + inc, ctxt->ad_bytes); 570 } 571 572 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 573 { 574 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 575 } 576 577 static u32 desc_limit_scaled(struct desc_struct *desc) 578 { 579 u32 limit = get_desc_limit(desc); 580 581 return desc->g ? (limit << 12) | 0xfff : limit; 582 } 583 584 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 585 { 586 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 587 return 0; 588 589 return ctxt->ops->get_cached_segment_base(ctxt, seg); 590 } 591 592 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 593 u32 error, bool valid) 594 { 595 WARN_ON(vec > 0x1f); 596 ctxt->exception.vector = vec; 597 ctxt->exception.error_code = error; 598 ctxt->exception.error_code_valid = valid; 599 return X86EMUL_PROPAGATE_FAULT; 600 } 601 602 static int emulate_db(struct x86_emulate_ctxt *ctxt) 603 { 604 return emulate_exception(ctxt, DB_VECTOR, 0, false); 605 } 606 607 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 608 { 609 return emulate_exception(ctxt, GP_VECTOR, err, true); 610 } 611 612 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 613 { 614 return emulate_exception(ctxt, SS_VECTOR, err, true); 615 } 616 617 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 618 { 619 return emulate_exception(ctxt, UD_VECTOR, 0, false); 620 } 621 622 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 623 { 624 return emulate_exception(ctxt, TS_VECTOR, err, true); 625 } 626 627 static int emulate_de(struct x86_emulate_ctxt *ctxt) 628 { 629 return emulate_exception(ctxt, DE_VECTOR, 0, false); 630 } 631 632 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 633 { 634 return emulate_exception(ctxt, NM_VECTOR, 0, false); 635 } 636 637 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 638 { 639 u16 selector; 640 struct desc_struct desc; 641 642 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 643 return selector; 644 } 645 646 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 647 unsigned seg) 648 { 649 u16 dummy; 650 u32 base3; 651 struct desc_struct desc; 652 653 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 654 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 655 } 656 657 /* 658 * x86 defines three classes of vector instructions: explicitly 659 * aligned, explicitly unaligned, and the rest, which change behaviour 660 * depending on whether they're AVX encoded or not. 661 * 662 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 663 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 664 * 512 bytes of data must be aligned to a 16 byte boundary. 665 */ 666 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 667 { 668 u64 alignment = ctxt->d & AlignMask; 669 670 if (likely(size < 16)) 671 return 1; 672 673 switch (alignment) { 674 case Unaligned: 675 case Avx: 676 return 1; 677 case Aligned16: 678 return 16; 679 case Aligned: 680 default: 681 return size; 682 } 683 } 684 685 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 686 struct segmented_address addr, 687 unsigned *max_size, unsigned size, 688 bool write, bool fetch, 689 enum x86emul_mode mode, ulong *linear) 690 { 691 struct desc_struct desc; 692 bool usable; 693 ulong la; 694 u32 lim; 695 u16 sel; 696 u8 va_bits; 697 698 la = seg_base(ctxt, addr.seg) + addr.ea; 699 *max_size = 0; 700 switch (mode) { 701 case X86EMUL_MODE_PROT64: 702 *linear = la; 703 va_bits = ctxt_virt_addr_bits(ctxt); 704 if (get_canonical(la, va_bits) != la) 705 goto bad; 706 707 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 708 if (size > *max_size) 709 goto bad; 710 break; 711 default: 712 *linear = la = (u32)la; 713 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 714 addr.seg); 715 if (!usable) 716 goto bad; 717 /* code segment in protected mode or read-only data segment */ 718 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 719 || !(desc.type & 2)) && write) 720 goto bad; 721 /* unreadable code segment */ 722 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 723 goto bad; 724 lim = desc_limit_scaled(&desc); 725 if (!(desc.type & 8) && (desc.type & 4)) { 726 /* expand-down segment */ 727 if (addr.ea <= lim) 728 goto bad; 729 lim = desc.d ? 0xffffffff : 0xffff; 730 } 731 if (addr.ea > lim) 732 goto bad; 733 if (lim == 0xffffffff) 734 *max_size = ~0u; 735 else { 736 *max_size = (u64)lim + 1 - addr.ea; 737 if (size > *max_size) 738 goto bad; 739 } 740 break; 741 } 742 if (la & (insn_alignment(ctxt, size) - 1)) 743 return emulate_gp(ctxt, 0); 744 return X86EMUL_CONTINUE; 745 bad: 746 if (addr.seg == VCPU_SREG_SS) 747 return emulate_ss(ctxt, 0); 748 else 749 return emulate_gp(ctxt, 0); 750 } 751 752 static int linearize(struct x86_emulate_ctxt *ctxt, 753 struct segmented_address addr, 754 unsigned size, bool write, 755 ulong *linear) 756 { 757 unsigned max_size; 758 return __linearize(ctxt, addr, &max_size, size, write, false, 759 ctxt->mode, linear); 760 } 761 762 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, 763 enum x86emul_mode mode) 764 { 765 ulong linear; 766 int rc; 767 unsigned max_size; 768 struct segmented_address addr = { .seg = VCPU_SREG_CS, 769 .ea = dst }; 770 771 if (ctxt->op_bytes != sizeof(unsigned long)) 772 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 773 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); 774 if (rc == X86EMUL_CONTINUE) 775 ctxt->_eip = addr.ea; 776 return rc; 777 } 778 779 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 780 { 781 return assign_eip(ctxt, dst, ctxt->mode); 782 } 783 784 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, 785 const struct desc_struct *cs_desc) 786 { 787 enum x86emul_mode mode = ctxt->mode; 788 int rc; 789 790 #ifdef CONFIG_X86_64 791 if (ctxt->mode >= X86EMUL_MODE_PROT16) { 792 if (cs_desc->l) { 793 u64 efer = 0; 794 795 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 796 if (efer & EFER_LMA) 797 mode = X86EMUL_MODE_PROT64; 798 } else 799 mode = X86EMUL_MODE_PROT32; /* temporary value */ 800 } 801 #endif 802 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) 803 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 804 rc = assign_eip(ctxt, dst, mode); 805 if (rc == X86EMUL_CONTINUE) 806 ctxt->mode = mode; 807 return rc; 808 } 809 810 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 811 { 812 return assign_eip_near(ctxt, ctxt->_eip + rel); 813 } 814 815 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 816 void *data, unsigned size) 817 { 818 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 819 } 820 821 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 822 ulong linear, void *data, 823 unsigned int size) 824 { 825 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 826 } 827 828 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 829 struct segmented_address addr, 830 void *data, 831 unsigned size) 832 { 833 int rc; 834 ulong linear; 835 836 rc = linearize(ctxt, addr, size, false, &linear); 837 if (rc != X86EMUL_CONTINUE) 838 return rc; 839 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 840 } 841 842 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 843 struct segmented_address addr, 844 void *data, 845 unsigned int size) 846 { 847 int rc; 848 ulong linear; 849 850 rc = linearize(ctxt, addr, size, true, &linear); 851 if (rc != X86EMUL_CONTINUE) 852 return rc; 853 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 854 } 855 856 /* 857 * Prefetch the remaining bytes of the instruction without crossing page 858 * boundary if they are not in fetch_cache yet. 859 */ 860 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 861 { 862 int rc; 863 unsigned size, max_size; 864 unsigned long linear; 865 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 866 struct segmented_address addr = { .seg = VCPU_SREG_CS, 867 .ea = ctxt->eip + cur_size }; 868 869 /* 870 * We do not know exactly how many bytes will be needed, and 871 * __linearize is expensive, so fetch as much as possible. We 872 * just have to avoid going beyond the 15 byte limit, the end 873 * of the segment, or the end of the page. 874 * 875 * __linearize is called with size 0 so that it does not do any 876 * boundary check itself. Instead, we use max_size to check 877 * against op_size. 878 */ 879 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 880 &linear); 881 if (unlikely(rc != X86EMUL_CONTINUE)) 882 return rc; 883 884 size = min_t(unsigned, 15UL ^ cur_size, max_size); 885 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 886 887 /* 888 * One instruction can only straddle two pages, 889 * and one has been loaded at the beginning of 890 * x86_decode_insn. So, if not enough bytes 891 * still, we must have hit the 15-byte boundary. 892 */ 893 if (unlikely(size < op_size)) 894 return emulate_gp(ctxt, 0); 895 896 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 897 size, &ctxt->exception); 898 if (unlikely(rc != X86EMUL_CONTINUE)) 899 return rc; 900 ctxt->fetch.end += size; 901 return X86EMUL_CONTINUE; 902 } 903 904 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 905 unsigned size) 906 { 907 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 908 909 if (unlikely(done_size < size)) 910 return __do_insn_fetch_bytes(ctxt, size - done_size); 911 else 912 return X86EMUL_CONTINUE; 913 } 914 915 /* Fetch next part of the instruction being emulated. */ 916 #define insn_fetch(_type, _ctxt) \ 917 ({ _type _x; \ 918 \ 919 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 920 if (rc != X86EMUL_CONTINUE) \ 921 goto done; \ 922 ctxt->_eip += sizeof(_type); \ 923 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 924 ctxt->fetch.ptr += sizeof(_type); \ 925 _x; \ 926 }) 927 928 #define insn_fetch_arr(_arr, _size, _ctxt) \ 929 ({ \ 930 rc = do_insn_fetch_bytes(_ctxt, _size); \ 931 if (rc != X86EMUL_CONTINUE) \ 932 goto done; \ 933 ctxt->_eip += (_size); \ 934 memcpy(_arr, ctxt->fetch.ptr, _size); \ 935 ctxt->fetch.ptr += (_size); \ 936 }) 937 938 /* 939 * Given the 'reg' portion of a ModRM byte, and a register block, return a 940 * pointer into the block that addresses the relevant register. 941 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 942 */ 943 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 944 int byteop) 945 { 946 void *p; 947 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 948 949 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 950 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 951 else 952 p = reg_rmw(ctxt, modrm_reg); 953 return p; 954 } 955 956 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 957 struct segmented_address addr, 958 u16 *size, unsigned long *address, int op_bytes) 959 { 960 int rc; 961 962 if (op_bytes == 2) 963 op_bytes = 3; 964 *address = 0; 965 rc = segmented_read_std(ctxt, addr, size, 2); 966 if (rc != X86EMUL_CONTINUE) 967 return rc; 968 addr.ea += 2; 969 rc = segmented_read_std(ctxt, addr, address, op_bytes); 970 return rc; 971 } 972 973 FASTOP2(add); 974 FASTOP2(or); 975 FASTOP2(adc); 976 FASTOP2(sbb); 977 FASTOP2(and); 978 FASTOP2(sub); 979 FASTOP2(xor); 980 FASTOP2(cmp); 981 FASTOP2(test); 982 983 FASTOP1SRC2(mul, mul_ex); 984 FASTOP1SRC2(imul, imul_ex); 985 FASTOP1SRC2EX(div, div_ex); 986 FASTOP1SRC2EX(idiv, idiv_ex); 987 988 FASTOP3WCL(shld); 989 FASTOP3WCL(shrd); 990 991 FASTOP2W(imul); 992 993 FASTOP1(not); 994 FASTOP1(neg); 995 FASTOP1(inc); 996 FASTOP1(dec); 997 998 FASTOP2CL(rol); 999 FASTOP2CL(ror); 1000 FASTOP2CL(rcl); 1001 FASTOP2CL(rcr); 1002 FASTOP2CL(shl); 1003 FASTOP2CL(shr); 1004 FASTOP2CL(sar); 1005 1006 FASTOP2W(bsf); 1007 FASTOP2W(bsr); 1008 FASTOP2W(bt); 1009 FASTOP2W(bts); 1010 FASTOP2W(btr); 1011 FASTOP2W(btc); 1012 1013 FASTOP2(xadd); 1014 1015 FASTOP2R(cmp, cmp_r); 1016 1017 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1018 { 1019 /* If src is zero, do not writeback, but update flags */ 1020 if (ctxt->src.val == 0) 1021 ctxt->dst.type = OP_NONE; 1022 return fastop(ctxt, em_bsf); 1023 } 1024 1025 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1026 { 1027 /* If src is zero, do not writeback, but update flags */ 1028 if (ctxt->src.val == 0) 1029 ctxt->dst.type = OP_NONE; 1030 return fastop(ctxt, em_bsr); 1031 } 1032 1033 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1034 { 1035 u8 rc; 1036 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 1037 1038 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1039 asm("push %[flags]; popf; " CALL_NOSPEC 1040 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1041 return rc; 1042 } 1043 1044 static void fetch_register_operand(struct operand *op) 1045 { 1046 switch (op->bytes) { 1047 case 1: 1048 op->val = *(u8 *)op->addr.reg; 1049 break; 1050 case 2: 1051 op->val = *(u16 *)op->addr.reg; 1052 break; 1053 case 4: 1054 op->val = *(u32 *)op->addr.reg; 1055 break; 1056 case 8: 1057 op->val = *(u64 *)op->addr.reg; 1058 break; 1059 } 1060 } 1061 1062 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 1063 { 1064 switch (reg) { 1065 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 1066 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 1067 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 1068 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 1069 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 1070 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 1071 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 1072 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1073 #ifdef CONFIG_X86_64 1074 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1075 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1076 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1077 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1078 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1079 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1080 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1081 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1082 #endif 1083 default: BUG(); 1084 } 1085 } 1086 1087 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 1088 int reg) 1089 { 1090 switch (reg) { 1091 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1092 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1093 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1094 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1095 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1096 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1097 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1098 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1099 #ifdef CONFIG_X86_64 1100 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1101 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1102 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1103 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1104 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1105 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1106 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1107 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1108 #endif 1109 default: BUG(); 1110 } 1111 } 1112 1113 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1114 { 1115 switch (reg) { 1116 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1117 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1118 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1119 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1120 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1121 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1122 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1123 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1124 default: BUG(); 1125 } 1126 } 1127 1128 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1129 { 1130 switch (reg) { 1131 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1132 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1133 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1134 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1135 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1136 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1137 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1138 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1139 default: BUG(); 1140 } 1141 } 1142 1143 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1144 { 1145 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1146 return emulate_nm(ctxt); 1147 1148 asm volatile("fninit"); 1149 return X86EMUL_CONTINUE; 1150 } 1151 1152 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1153 { 1154 u16 fcw; 1155 1156 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1157 return emulate_nm(ctxt); 1158 1159 asm volatile("fnstcw %0": "+m"(fcw)); 1160 1161 ctxt->dst.val = fcw; 1162 1163 return X86EMUL_CONTINUE; 1164 } 1165 1166 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1167 { 1168 u16 fsw; 1169 1170 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1171 return emulate_nm(ctxt); 1172 1173 asm volatile("fnstsw %0": "+m"(fsw)); 1174 1175 ctxt->dst.val = fsw; 1176 1177 return X86EMUL_CONTINUE; 1178 } 1179 1180 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1181 struct operand *op) 1182 { 1183 unsigned reg = ctxt->modrm_reg; 1184 1185 if (!(ctxt->d & ModRM)) 1186 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1187 1188 if (ctxt->d & Sse) { 1189 op->type = OP_XMM; 1190 op->bytes = 16; 1191 op->addr.xmm = reg; 1192 read_sse_reg(ctxt, &op->vec_val, reg); 1193 return; 1194 } 1195 if (ctxt->d & Mmx) { 1196 reg &= 7; 1197 op->type = OP_MM; 1198 op->bytes = 8; 1199 op->addr.mm = reg; 1200 return; 1201 } 1202 1203 op->type = OP_REG; 1204 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1205 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1206 1207 fetch_register_operand(op); 1208 op->orig_val = op->val; 1209 } 1210 1211 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1212 { 1213 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1214 ctxt->modrm_seg = VCPU_SREG_SS; 1215 } 1216 1217 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1218 struct operand *op) 1219 { 1220 u8 sib; 1221 int index_reg, base_reg, scale; 1222 int rc = X86EMUL_CONTINUE; 1223 ulong modrm_ea = 0; 1224 1225 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1226 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1227 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1228 1229 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1230 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1231 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1232 ctxt->modrm_seg = VCPU_SREG_DS; 1233 1234 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1235 op->type = OP_REG; 1236 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1237 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1238 ctxt->d & ByteOp); 1239 if (ctxt->d & Sse) { 1240 op->type = OP_XMM; 1241 op->bytes = 16; 1242 op->addr.xmm = ctxt->modrm_rm; 1243 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1244 return rc; 1245 } 1246 if (ctxt->d & Mmx) { 1247 op->type = OP_MM; 1248 op->bytes = 8; 1249 op->addr.mm = ctxt->modrm_rm & 7; 1250 return rc; 1251 } 1252 fetch_register_operand(op); 1253 return rc; 1254 } 1255 1256 op->type = OP_MEM; 1257 1258 if (ctxt->ad_bytes == 2) { 1259 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1260 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1261 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1262 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1263 1264 /* 16-bit ModR/M decode. */ 1265 switch (ctxt->modrm_mod) { 1266 case 0: 1267 if (ctxt->modrm_rm == 6) 1268 modrm_ea += insn_fetch(u16, ctxt); 1269 break; 1270 case 1: 1271 modrm_ea += insn_fetch(s8, ctxt); 1272 break; 1273 case 2: 1274 modrm_ea += insn_fetch(u16, ctxt); 1275 break; 1276 } 1277 switch (ctxt->modrm_rm) { 1278 case 0: 1279 modrm_ea += bx + si; 1280 break; 1281 case 1: 1282 modrm_ea += bx + di; 1283 break; 1284 case 2: 1285 modrm_ea += bp + si; 1286 break; 1287 case 3: 1288 modrm_ea += bp + di; 1289 break; 1290 case 4: 1291 modrm_ea += si; 1292 break; 1293 case 5: 1294 modrm_ea += di; 1295 break; 1296 case 6: 1297 if (ctxt->modrm_mod != 0) 1298 modrm_ea += bp; 1299 break; 1300 case 7: 1301 modrm_ea += bx; 1302 break; 1303 } 1304 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1305 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1306 ctxt->modrm_seg = VCPU_SREG_SS; 1307 modrm_ea = (u16)modrm_ea; 1308 } else { 1309 /* 32/64-bit ModR/M decode. */ 1310 if ((ctxt->modrm_rm & 7) == 4) { 1311 sib = insn_fetch(u8, ctxt); 1312 index_reg |= (sib >> 3) & 7; 1313 base_reg |= sib & 7; 1314 scale = sib >> 6; 1315 1316 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1317 modrm_ea += insn_fetch(s32, ctxt); 1318 else { 1319 modrm_ea += reg_read(ctxt, base_reg); 1320 adjust_modrm_seg(ctxt, base_reg); 1321 /* Increment ESP on POP [ESP] */ 1322 if ((ctxt->d & IncSP) && 1323 base_reg == VCPU_REGS_RSP) 1324 modrm_ea += ctxt->op_bytes; 1325 } 1326 if (index_reg != 4) 1327 modrm_ea += reg_read(ctxt, index_reg) << scale; 1328 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1329 modrm_ea += insn_fetch(s32, ctxt); 1330 if (ctxt->mode == X86EMUL_MODE_PROT64) 1331 ctxt->rip_relative = 1; 1332 } else { 1333 base_reg = ctxt->modrm_rm; 1334 modrm_ea += reg_read(ctxt, base_reg); 1335 adjust_modrm_seg(ctxt, base_reg); 1336 } 1337 switch (ctxt->modrm_mod) { 1338 case 1: 1339 modrm_ea += insn_fetch(s8, ctxt); 1340 break; 1341 case 2: 1342 modrm_ea += insn_fetch(s32, ctxt); 1343 break; 1344 } 1345 } 1346 op->addr.mem.ea = modrm_ea; 1347 if (ctxt->ad_bytes != 8) 1348 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1349 1350 done: 1351 return rc; 1352 } 1353 1354 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1355 struct operand *op) 1356 { 1357 int rc = X86EMUL_CONTINUE; 1358 1359 op->type = OP_MEM; 1360 switch (ctxt->ad_bytes) { 1361 case 2: 1362 op->addr.mem.ea = insn_fetch(u16, ctxt); 1363 break; 1364 case 4: 1365 op->addr.mem.ea = insn_fetch(u32, ctxt); 1366 break; 1367 case 8: 1368 op->addr.mem.ea = insn_fetch(u64, ctxt); 1369 break; 1370 } 1371 done: 1372 return rc; 1373 } 1374 1375 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1376 { 1377 long sv = 0, mask; 1378 1379 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1380 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1381 1382 if (ctxt->src.bytes == 2) 1383 sv = (s16)ctxt->src.val & (s16)mask; 1384 else if (ctxt->src.bytes == 4) 1385 sv = (s32)ctxt->src.val & (s32)mask; 1386 else 1387 sv = (s64)ctxt->src.val & (s64)mask; 1388 1389 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1390 ctxt->dst.addr.mem.ea + (sv >> 3)); 1391 } 1392 1393 /* only subword offset */ 1394 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1395 } 1396 1397 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1398 unsigned long addr, void *dest, unsigned size) 1399 { 1400 int rc; 1401 struct read_cache *mc = &ctxt->mem_read; 1402 1403 if (mc->pos < mc->end) 1404 goto read_cached; 1405 1406 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1407 1408 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1409 &ctxt->exception); 1410 if (rc != X86EMUL_CONTINUE) 1411 return rc; 1412 1413 mc->end += size; 1414 1415 read_cached: 1416 memcpy(dest, mc->data + mc->pos, size); 1417 mc->pos += size; 1418 return X86EMUL_CONTINUE; 1419 } 1420 1421 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1422 struct segmented_address addr, 1423 void *data, 1424 unsigned size) 1425 { 1426 int rc; 1427 ulong linear; 1428 1429 rc = linearize(ctxt, addr, size, false, &linear); 1430 if (rc != X86EMUL_CONTINUE) 1431 return rc; 1432 return read_emulated(ctxt, linear, data, size); 1433 } 1434 1435 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1436 struct segmented_address addr, 1437 const void *data, 1438 unsigned size) 1439 { 1440 int rc; 1441 ulong linear; 1442 1443 rc = linearize(ctxt, addr, size, true, &linear); 1444 if (rc != X86EMUL_CONTINUE) 1445 return rc; 1446 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1447 &ctxt->exception); 1448 } 1449 1450 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1451 struct segmented_address addr, 1452 const void *orig_data, const void *data, 1453 unsigned size) 1454 { 1455 int rc; 1456 ulong linear; 1457 1458 rc = linearize(ctxt, addr, size, true, &linear); 1459 if (rc != X86EMUL_CONTINUE) 1460 return rc; 1461 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1462 size, &ctxt->exception); 1463 } 1464 1465 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1466 unsigned int size, unsigned short port, 1467 void *dest) 1468 { 1469 struct read_cache *rc = &ctxt->io_read; 1470 1471 if (rc->pos == rc->end) { /* refill pio read ahead */ 1472 unsigned int in_page, n; 1473 unsigned int count = ctxt->rep_prefix ? 1474 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1475 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1476 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1477 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1478 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1479 if (n == 0) 1480 n = 1; 1481 rc->pos = rc->end = 0; 1482 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1483 return 0; 1484 rc->end = n * size; 1485 } 1486 1487 if (ctxt->rep_prefix && (ctxt->d & String) && 1488 !(ctxt->eflags & X86_EFLAGS_DF)) { 1489 ctxt->dst.data = rc->data + rc->pos; 1490 ctxt->dst.type = OP_MEM_STR; 1491 ctxt->dst.count = (rc->end - rc->pos) / size; 1492 rc->pos = rc->end; 1493 } else { 1494 memcpy(dest, rc->data + rc->pos, size); 1495 rc->pos += size; 1496 } 1497 return 1; 1498 } 1499 1500 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1501 u16 index, struct desc_struct *desc) 1502 { 1503 struct desc_ptr dt; 1504 ulong addr; 1505 1506 ctxt->ops->get_idt(ctxt, &dt); 1507 1508 if (dt.size < index * 8 + 7) 1509 return emulate_gp(ctxt, index << 3 | 0x2); 1510 1511 addr = dt.address + index * 8; 1512 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1513 } 1514 1515 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1516 u16 selector, struct desc_ptr *dt) 1517 { 1518 const struct x86_emulate_ops *ops = ctxt->ops; 1519 u32 base3 = 0; 1520 1521 if (selector & 1 << 2) { 1522 struct desc_struct desc; 1523 u16 sel; 1524 1525 memset(dt, 0, sizeof(*dt)); 1526 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1527 VCPU_SREG_LDTR)) 1528 return; 1529 1530 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1531 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1532 } else 1533 ops->get_gdt(ctxt, dt); 1534 } 1535 1536 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1537 u16 selector, ulong *desc_addr_p) 1538 { 1539 struct desc_ptr dt; 1540 u16 index = selector >> 3; 1541 ulong addr; 1542 1543 get_descriptor_table_ptr(ctxt, selector, &dt); 1544 1545 if (dt.size < index * 8 + 7) 1546 return emulate_gp(ctxt, selector & 0xfffc); 1547 1548 addr = dt.address + index * 8; 1549 1550 #ifdef CONFIG_X86_64 1551 if (addr >> 32 != 0) { 1552 u64 efer = 0; 1553 1554 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1555 if (!(efer & EFER_LMA)) 1556 addr &= (u32)-1; 1557 } 1558 #endif 1559 1560 *desc_addr_p = addr; 1561 return X86EMUL_CONTINUE; 1562 } 1563 1564 /* allowed just for 8 bytes segments */ 1565 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1566 u16 selector, struct desc_struct *desc, 1567 ulong *desc_addr_p) 1568 { 1569 int rc; 1570 1571 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1572 if (rc != X86EMUL_CONTINUE) 1573 return rc; 1574 1575 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1576 } 1577 1578 /* allowed just for 8 bytes segments */ 1579 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1580 u16 selector, struct desc_struct *desc) 1581 { 1582 int rc; 1583 ulong addr; 1584 1585 rc = get_descriptor_ptr(ctxt, selector, &addr); 1586 if (rc != X86EMUL_CONTINUE) 1587 return rc; 1588 1589 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1590 } 1591 1592 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1593 u16 selector, int seg, u8 cpl, 1594 enum x86_transfer_type transfer, 1595 struct desc_struct *desc) 1596 { 1597 struct desc_struct seg_desc, old_desc; 1598 u8 dpl, rpl; 1599 unsigned err_vec = GP_VECTOR; 1600 u32 err_code = 0; 1601 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1602 ulong desc_addr; 1603 int ret; 1604 u16 dummy; 1605 u32 base3 = 0; 1606 1607 memset(&seg_desc, 0, sizeof(seg_desc)); 1608 1609 if (ctxt->mode == X86EMUL_MODE_REAL) { 1610 /* set real mode segment descriptor (keep limit etc. for 1611 * unreal mode) */ 1612 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1613 set_desc_base(&seg_desc, selector << 4); 1614 goto load; 1615 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1616 /* VM86 needs a clean new segment descriptor */ 1617 set_desc_base(&seg_desc, selector << 4); 1618 set_desc_limit(&seg_desc, 0xffff); 1619 seg_desc.type = 3; 1620 seg_desc.p = 1; 1621 seg_desc.s = 1; 1622 seg_desc.dpl = 3; 1623 goto load; 1624 } 1625 1626 rpl = selector & 3; 1627 1628 /* TR should be in GDT only */ 1629 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1630 goto exception; 1631 1632 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1633 if (null_selector) { 1634 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1635 goto exception; 1636 1637 if (seg == VCPU_SREG_SS) { 1638 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1639 goto exception; 1640 1641 /* 1642 * ctxt->ops->set_segment expects the CPL to be in 1643 * SS.DPL, so fake an expand-up 32-bit data segment. 1644 */ 1645 seg_desc.type = 3; 1646 seg_desc.p = 1; 1647 seg_desc.s = 1; 1648 seg_desc.dpl = cpl; 1649 seg_desc.d = 1; 1650 seg_desc.g = 1; 1651 } 1652 1653 /* Skip all following checks */ 1654 goto load; 1655 } 1656 1657 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1658 if (ret != X86EMUL_CONTINUE) 1659 return ret; 1660 1661 err_code = selector & 0xfffc; 1662 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1663 GP_VECTOR; 1664 1665 /* can't load system descriptor into segment selector */ 1666 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1667 if (transfer == X86_TRANSFER_CALL_JMP) 1668 return X86EMUL_UNHANDLEABLE; 1669 goto exception; 1670 } 1671 1672 if (!seg_desc.p) { 1673 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1674 goto exception; 1675 } 1676 1677 dpl = seg_desc.dpl; 1678 1679 switch (seg) { 1680 case VCPU_SREG_SS: 1681 /* 1682 * segment is not a writable data segment or segment 1683 * selector's RPL != CPL or segment selector's RPL != CPL 1684 */ 1685 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1686 goto exception; 1687 break; 1688 case VCPU_SREG_CS: 1689 if (!(seg_desc.type & 8)) 1690 goto exception; 1691 1692 if (seg_desc.type & 4) { 1693 /* conforming */ 1694 if (dpl > cpl) 1695 goto exception; 1696 } else { 1697 /* nonconforming */ 1698 if (rpl > cpl || dpl != cpl) 1699 goto exception; 1700 } 1701 /* in long-mode d/b must be clear if l is set */ 1702 if (seg_desc.d && seg_desc.l) { 1703 u64 efer = 0; 1704 1705 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1706 if (efer & EFER_LMA) 1707 goto exception; 1708 } 1709 1710 /* CS(RPL) <- CPL */ 1711 selector = (selector & 0xfffc) | cpl; 1712 break; 1713 case VCPU_SREG_TR: 1714 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1715 goto exception; 1716 old_desc = seg_desc; 1717 seg_desc.type |= 2; /* busy */ 1718 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1719 sizeof(seg_desc), &ctxt->exception); 1720 if (ret != X86EMUL_CONTINUE) 1721 return ret; 1722 break; 1723 case VCPU_SREG_LDTR: 1724 if (seg_desc.s || seg_desc.type != 2) 1725 goto exception; 1726 break; 1727 default: /* DS, ES, FS, or GS */ 1728 /* 1729 * segment is not a data or readable code segment or 1730 * ((segment is a data or nonconforming code segment) 1731 * and (both RPL and CPL > DPL)) 1732 */ 1733 if ((seg_desc.type & 0xa) == 0x8 || 1734 (((seg_desc.type & 0xc) != 0xc) && 1735 (rpl > dpl && cpl > dpl))) 1736 goto exception; 1737 break; 1738 } 1739 1740 if (seg_desc.s) { 1741 /* mark segment as accessed */ 1742 if (!(seg_desc.type & 1)) { 1743 seg_desc.type |= 1; 1744 ret = write_segment_descriptor(ctxt, selector, 1745 &seg_desc); 1746 if (ret != X86EMUL_CONTINUE) 1747 return ret; 1748 } 1749 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1750 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1751 if (ret != X86EMUL_CONTINUE) 1752 return ret; 1753 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1754 ((u64)base3 << 32), ctxt)) 1755 return emulate_gp(ctxt, 0); 1756 } 1757 load: 1758 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1759 if (desc) 1760 *desc = seg_desc; 1761 return X86EMUL_CONTINUE; 1762 exception: 1763 return emulate_exception(ctxt, err_vec, err_code, true); 1764 } 1765 1766 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1767 u16 selector, int seg) 1768 { 1769 u8 cpl = ctxt->ops->cpl(ctxt); 1770 1771 /* 1772 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1773 * they can load it at CPL<3 (Intel's manual says only LSS can, 1774 * but it's wrong). 1775 * 1776 * However, the Intel manual says that putting IST=1/DPL=3 in 1777 * an interrupt gate will result in SS=3 (the AMD manual instead 1778 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1779 * and only forbid it here. 1780 */ 1781 if (seg == VCPU_SREG_SS && selector == 3 && 1782 ctxt->mode == X86EMUL_MODE_PROT64) 1783 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1784 1785 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1786 X86_TRANSFER_NONE, NULL); 1787 } 1788 1789 static void write_register_operand(struct operand *op) 1790 { 1791 return assign_register(op->addr.reg, op->val, op->bytes); 1792 } 1793 1794 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1795 { 1796 switch (op->type) { 1797 case OP_REG: 1798 write_register_operand(op); 1799 break; 1800 case OP_MEM: 1801 if (ctxt->lock_prefix) 1802 return segmented_cmpxchg(ctxt, 1803 op->addr.mem, 1804 &op->orig_val, 1805 &op->val, 1806 op->bytes); 1807 else 1808 return segmented_write(ctxt, 1809 op->addr.mem, 1810 &op->val, 1811 op->bytes); 1812 break; 1813 case OP_MEM_STR: 1814 return segmented_write(ctxt, 1815 op->addr.mem, 1816 op->data, 1817 op->bytes * op->count); 1818 break; 1819 case OP_XMM: 1820 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); 1821 break; 1822 case OP_MM: 1823 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 1824 break; 1825 case OP_NONE: 1826 /* no writeback */ 1827 break; 1828 default: 1829 break; 1830 } 1831 return X86EMUL_CONTINUE; 1832 } 1833 1834 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1835 { 1836 struct segmented_address addr; 1837 1838 rsp_increment(ctxt, -bytes); 1839 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1840 addr.seg = VCPU_SREG_SS; 1841 1842 return segmented_write(ctxt, addr, data, bytes); 1843 } 1844 1845 static int em_push(struct x86_emulate_ctxt *ctxt) 1846 { 1847 /* Disable writeback. */ 1848 ctxt->dst.type = OP_NONE; 1849 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1850 } 1851 1852 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1853 void *dest, int len) 1854 { 1855 int rc; 1856 struct segmented_address addr; 1857 1858 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1859 addr.seg = VCPU_SREG_SS; 1860 rc = segmented_read(ctxt, addr, dest, len); 1861 if (rc != X86EMUL_CONTINUE) 1862 return rc; 1863 1864 rsp_increment(ctxt, len); 1865 return rc; 1866 } 1867 1868 static int em_pop(struct x86_emulate_ctxt *ctxt) 1869 { 1870 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1871 } 1872 1873 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1874 void *dest, int len) 1875 { 1876 int rc; 1877 unsigned long val, change_mask; 1878 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1879 int cpl = ctxt->ops->cpl(ctxt); 1880 1881 rc = emulate_pop(ctxt, &val, len); 1882 if (rc != X86EMUL_CONTINUE) 1883 return rc; 1884 1885 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1886 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1887 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1888 X86_EFLAGS_AC | X86_EFLAGS_ID; 1889 1890 switch(ctxt->mode) { 1891 case X86EMUL_MODE_PROT64: 1892 case X86EMUL_MODE_PROT32: 1893 case X86EMUL_MODE_PROT16: 1894 if (cpl == 0) 1895 change_mask |= X86_EFLAGS_IOPL; 1896 if (cpl <= iopl) 1897 change_mask |= X86_EFLAGS_IF; 1898 break; 1899 case X86EMUL_MODE_VM86: 1900 if (iopl < 3) 1901 return emulate_gp(ctxt, 0); 1902 change_mask |= X86_EFLAGS_IF; 1903 break; 1904 default: /* real mode */ 1905 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1906 break; 1907 } 1908 1909 *(unsigned long *)dest = 1910 (ctxt->eflags & ~change_mask) | (val & change_mask); 1911 1912 return rc; 1913 } 1914 1915 static int em_popf(struct x86_emulate_ctxt *ctxt) 1916 { 1917 ctxt->dst.type = OP_REG; 1918 ctxt->dst.addr.reg = &ctxt->eflags; 1919 ctxt->dst.bytes = ctxt->op_bytes; 1920 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1921 } 1922 1923 static int em_enter(struct x86_emulate_ctxt *ctxt) 1924 { 1925 int rc; 1926 unsigned frame_size = ctxt->src.val; 1927 unsigned nesting_level = ctxt->src2.val & 31; 1928 ulong rbp; 1929 1930 if (nesting_level) 1931 return X86EMUL_UNHANDLEABLE; 1932 1933 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1934 rc = push(ctxt, &rbp, stack_size(ctxt)); 1935 if (rc != X86EMUL_CONTINUE) 1936 return rc; 1937 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1938 stack_mask(ctxt)); 1939 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1940 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1941 stack_mask(ctxt)); 1942 return X86EMUL_CONTINUE; 1943 } 1944 1945 static int em_leave(struct x86_emulate_ctxt *ctxt) 1946 { 1947 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1948 stack_mask(ctxt)); 1949 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1950 } 1951 1952 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1953 { 1954 int seg = ctxt->src2.val; 1955 1956 ctxt->src.val = get_segment_selector(ctxt, seg); 1957 if (ctxt->op_bytes == 4) { 1958 rsp_increment(ctxt, -2); 1959 ctxt->op_bytes = 2; 1960 } 1961 1962 return em_push(ctxt); 1963 } 1964 1965 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1966 { 1967 int seg = ctxt->src2.val; 1968 unsigned long selector; 1969 int rc; 1970 1971 rc = emulate_pop(ctxt, &selector, 2); 1972 if (rc != X86EMUL_CONTINUE) 1973 return rc; 1974 1975 if (ctxt->modrm_reg == VCPU_SREG_SS) 1976 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1977 if (ctxt->op_bytes > 2) 1978 rsp_increment(ctxt, ctxt->op_bytes - 2); 1979 1980 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1981 return rc; 1982 } 1983 1984 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1985 { 1986 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1987 int rc = X86EMUL_CONTINUE; 1988 int reg = VCPU_REGS_RAX; 1989 1990 while (reg <= VCPU_REGS_RDI) { 1991 (reg == VCPU_REGS_RSP) ? 1992 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1993 1994 rc = em_push(ctxt); 1995 if (rc != X86EMUL_CONTINUE) 1996 return rc; 1997 1998 ++reg; 1999 } 2000 2001 return rc; 2002 } 2003 2004 static int em_pushf(struct x86_emulate_ctxt *ctxt) 2005 { 2006 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 2007 return em_push(ctxt); 2008 } 2009 2010 static int em_popa(struct x86_emulate_ctxt *ctxt) 2011 { 2012 int rc = X86EMUL_CONTINUE; 2013 int reg = VCPU_REGS_RDI; 2014 u32 val; 2015 2016 while (reg >= VCPU_REGS_RAX) { 2017 if (reg == VCPU_REGS_RSP) { 2018 rsp_increment(ctxt, ctxt->op_bytes); 2019 --reg; 2020 } 2021 2022 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2023 if (rc != X86EMUL_CONTINUE) 2024 break; 2025 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2026 --reg; 2027 } 2028 return rc; 2029 } 2030 2031 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2032 { 2033 const struct x86_emulate_ops *ops = ctxt->ops; 2034 int rc; 2035 struct desc_ptr dt; 2036 gva_t cs_addr; 2037 gva_t eip_addr; 2038 u16 cs, eip; 2039 2040 /* TODO: Add limit checks */ 2041 ctxt->src.val = ctxt->eflags; 2042 rc = em_push(ctxt); 2043 if (rc != X86EMUL_CONTINUE) 2044 return rc; 2045 2046 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2047 2048 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2049 rc = em_push(ctxt); 2050 if (rc != X86EMUL_CONTINUE) 2051 return rc; 2052 2053 ctxt->src.val = ctxt->_eip; 2054 rc = em_push(ctxt); 2055 if (rc != X86EMUL_CONTINUE) 2056 return rc; 2057 2058 ops->get_idt(ctxt, &dt); 2059 2060 eip_addr = dt.address + (irq << 2); 2061 cs_addr = dt.address + (irq << 2) + 2; 2062 2063 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2064 if (rc != X86EMUL_CONTINUE) 2065 return rc; 2066 2067 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2068 if (rc != X86EMUL_CONTINUE) 2069 return rc; 2070 2071 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2072 if (rc != X86EMUL_CONTINUE) 2073 return rc; 2074 2075 ctxt->_eip = eip; 2076 2077 return rc; 2078 } 2079 2080 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2081 { 2082 int rc; 2083 2084 invalidate_registers(ctxt); 2085 rc = __emulate_int_real(ctxt, irq); 2086 if (rc == X86EMUL_CONTINUE) 2087 writeback_registers(ctxt); 2088 return rc; 2089 } 2090 2091 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2092 { 2093 switch(ctxt->mode) { 2094 case X86EMUL_MODE_REAL: 2095 return __emulate_int_real(ctxt, irq); 2096 case X86EMUL_MODE_VM86: 2097 case X86EMUL_MODE_PROT16: 2098 case X86EMUL_MODE_PROT32: 2099 case X86EMUL_MODE_PROT64: 2100 default: 2101 /* Protected mode interrupts unimplemented yet */ 2102 return X86EMUL_UNHANDLEABLE; 2103 } 2104 } 2105 2106 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2107 { 2108 int rc = X86EMUL_CONTINUE; 2109 unsigned long temp_eip = 0; 2110 unsigned long temp_eflags = 0; 2111 unsigned long cs = 0; 2112 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2113 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2114 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2115 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2116 X86_EFLAGS_AC | X86_EFLAGS_ID | 2117 X86_EFLAGS_FIXED; 2118 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2119 X86_EFLAGS_VIP; 2120 2121 /* TODO: Add stack limit check */ 2122 2123 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2124 2125 if (rc != X86EMUL_CONTINUE) 2126 return rc; 2127 2128 if (temp_eip & ~0xffff) 2129 return emulate_gp(ctxt, 0); 2130 2131 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2132 2133 if (rc != X86EMUL_CONTINUE) 2134 return rc; 2135 2136 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2137 2138 if (rc != X86EMUL_CONTINUE) 2139 return rc; 2140 2141 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2142 2143 if (rc != X86EMUL_CONTINUE) 2144 return rc; 2145 2146 ctxt->_eip = temp_eip; 2147 2148 if (ctxt->op_bytes == 4) 2149 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2150 else if (ctxt->op_bytes == 2) { 2151 ctxt->eflags &= ~0xffff; 2152 ctxt->eflags |= temp_eflags; 2153 } 2154 2155 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2156 ctxt->eflags |= X86_EFLAGS_FIXED; 2157 ctxt->ops->set_nmi_mask(ctxt, false); 2158 2159 return rc; 2160 } 2161 2162 static int em_iret(struct x86_emulate_ctxt *ctxt) 2163 { 2164 switch(ctxt->mode) { 2165 case X86EMUL_MODE_REAL: 2166 return emulate_iret_real(ctxt); 2167 case X86EMUL_MODE_VM86: 2168 case X86EMUL_MODE_PROT16: 2169 case X86EMUL_MODE_PROT32: 2170 case X86EMUL_MODE_PROT64: 2171 default: 2172 /* iret from protected mode unimplemented yet */ 2173 return X86EMUL_UNHANDLEABLE; 2174 } 2175 } 2176 2177 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2178 { 2179 int rc; 2180 unsigned short sel; 2181 struct desc_struct new_desc; 2182 u8 cpl = ctxt->ops->cpl(ctxt); 2183 2184 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2185 2186 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2187 X86_TRANSFER_CALL_JMP, 2188 &new_desc); 2189 if (rc != X86EMUL_CONTINUE) 2190 return rc; 2191 2192 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 2193 /* Error handling is not implemented. */ 2194 if (rc != X86EMUL_CONTINUE) 2195 return X86EMUL_UNHANDLEABLE; 2196 2197 return rc; 2198 } 2199 2200 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2201 { 2202 return assign_eip_near(ctxt, ctxt->src.val); 2203 } 2204 2205 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2206 { 2207 int rc; 2208 long int old_eip; 2209 2210 old_eip = ctxt->_eip; 2211 rc = assign_eip_near(ctxt, ctxt->src.val); 2212 if (rc != X86EMUL_CONTINUE) 2213 return rc; 2214 ctxt->src.val = old_eip; 2215 rc = em_push(ctxt); 2216 return rc; 2217 } 2218 2219 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2220 { 2221 u64 old = ctxt->dst.orig_val64; 2222 2223 if (ctxt->dst.bytes == 16) 2224 return X86EMUL_UNHANDLEABLE; 2225 2226 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2227 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2228 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2229 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2230 ctxt->eflags &= ~X86_EFLAGS_ZF; 2231 } else { 2232 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2233 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2234 2235 ctxt->eflags |= X86_EFLAGS_ZF; 2236 } 2237 return X86EMUL_CONTINUE; 2238 } 2239 2240 static int em_ret(struct x86_emulate_ctxt *ctxt) 2241 { 2242 int rc; 2243 unsigned long eip; 2244 2245 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2246 if (rc != X86EMUL_CONTINUE) 2247 return rc; 2248 2249 return assign_eip_near(ctxt, eip); 2250 } 2251 2252 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2253 { 2254 int rc; 2255 unsigned long eip, cs; 2256 int cpl = ctxt->ops->cpl(ctxt); 2257 struct desc_struct new_desc; 2258 2259 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2260 if (rc != X86EMUL_CONTINUE) 2261 return rc; 2262 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2263 if (rc != X86EMUL_CONTINUE) 2264 return rc; 2265 /* Outer-privilege level return is not implemented */ 2266 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2267 return X86EMUL_UNHANDLEABLE; 2268 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2269 X86_TRANSFER_RET, 2270 &new_desc); 2271 if (rc != X86EMUL_CONTINUE) 2272 return rc; 2273 rc = assign_eip_far(ctxt, eip, &new_desc); 2274 /* Error handling is not implemented. */ 2275 if (rc != X86EMUL_CONTINUE) 2276 return X86EMUL_UNHANDLEABLE; 2277 2278 return rc; 2279 } 2280 2281 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2282 { 2283 int rc; 2284 2285 rc = em_ret_far(ctxt); 2286 if (rc != X86EMUL_CONTINUE) 2287 return rc; 2288 rsp_increment(ctxt, ctxt->src.val); 2289 return X86EMUL_CONTINUE; 2290 } 2291 2292 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2293 { 2294 /* Save real source value, then compare EAX against destination. */ 2295 ctxt->dst.orig_val = ctxt->dst.val; 2296 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2297 ctxt->src.orig_val = ctxt->src.val; 2298 ctxt->src.val = ctxt->dst.orig_val; 2299 fastop(ctxt, em_cmp); 2300 2301 if (ctxt->eflags & X86_EFLAGS_ZF) { 2302 /* Success: write back to memory; no update of EAX */ 2303 ctxt->src.type = OP_NONE; 2304 ctxt->dst.val = ctxt->src.orig_val; 2305 } else { 2306 /* Failure: write the value we saw to EAX. */ 2307 ctxt->src.type = OP_REG; 2308 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2309 ctxt->src.val = ctxt->dst.orig_val; 2310 /* Create write-cycle to dest by writing the same value */ 2311 ctxt->dst.val = ctxt->dst.orig_val; 2312 } 2313 return X86EMUL_CONTINUE; 2314 } 2315 2316 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2317 { 2318 int seg = ctxt->src2.val; 2319 unsigned short sel; 2320 int rc; 2321 2322 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2323 2324 rc = load_segment_descriptor(ctxt, sel, seg); 2325 if (rc != X86EMUL_CONTINUE) 2326 return rc; 2327 2328 ctxt->dst.val = ctxt->src.val; 2329 return rc; 2330 } 2331 2332 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2333 { 2334 u32 eax, ebx, ecx, edx; 2335 2336 eax = 0x80000001; 2337 ecx = 0; 2338 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2339 return edx & bit(X86_FEATURE_LM); 2340 } 2341 2342 #define GET_SMSTATE(type, smbase, offset) \ 2343 ({ \ 2344 type __val; \ 2345 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \ 2346 sizeof(__val)); \ 2347 if (r != X86EMUL_CONTINUE) \ 2348 return X86EMUL_UNHANDLEABLE; \ 2349 __val; \ 2350 }) 2351 2352 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2353 { 2354 desc->g = (flags >> 23) & 1; 2355 desc->d = (flags >> 22) & 1; 2356 desc->l = (flags >> 21) & 1; 2357 desc->avl = (flags >> 20) & 1; 2358 desc->p = (flags >> 15) & 1; 2359 desc->dpl = (flags >> 13) & 3; 2360 desc->s = (flags >> 12) & 1; 2361 desc->type = (flags >> 8) & 15; 2362 } 2363 2364 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2365 { 2366 struct desc_struct desc; 2367 int offset; 2368 u16 selector; 2369 2370 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4); 2371 2372 if (n < 3) 2373 offset = 0x7f84 + n * 12; 2374 else 2375 offset = 0x7f2c + (n - 3) * 12; 2376 2377 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2378 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2379 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset)); 2380 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2381 return X86EMUL_CONTINUE; 2382 } 2383 2384 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2385 { 2386 struct desc_struct desc; 2387 int offset; 2388 u16 selector; 2389 u32 base3; 2390 2391 offset = 0x7e00 + n * 16; 2392 2393 selector = GET_SMSTATE(u16, smbase, offset); 2394 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8); 2395 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2396 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2397 base3 = GET_SMSTATE(u32, smbase, offset + 12); 2398 2399 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2400 return X86EMUL_CONTINUE; 2401 } 2402 2403 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2404 u64 cr0, u64 cr3, u64 cr4) 2405 { 2406 int bad; 2407 u64 pcid; 2408 2409 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */ 2410 pcid = 0; 2411 if (cr4 & X86_CR4_PCIDE) { 2412 pcid = cr3 & 0xfff; 2413 cr3 &= ~0xfff; 2414 } 2415 2416 bad = ctxt->ops->set_cr(ctxt, 3, cr3); 2417 if (bad) 2418 return X86EMUL_UNHANDLEABLE; 2419 2420 /* 2421 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2422 * Then enable protected mode. However, PCID cannot be enabled 2423 * if EFER.LMA=0, so set it separately. 2424 */ 2425 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2426 if (bad) 2427 return X86EMUL_UNHANDLEABLE; 2428 2429 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2430 if (bad) 2431 return X86EMUL_UNHANDLEABLE; 2432 2433 if (cr4 & X86_CR4_PCIDE) { 2434 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2435 if (bad) 2436 return X86EMUL_UNHANDLEABLE; 2437 if (pcid) { 2438 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid); 2439 if (bad) 2440 return X86EMUL_UNHANDLEABLE; 2441 } 2442 2443 } 2444 2445 return X86EMUL_CONTINUE; 2446 } 2447 2448 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase) 2449 { 2450 struct desc_struct desc; 2451 struct desc_ptr dt; 2452 u16 selector; 2453 u32 val, cr0, cr3, cr4; 2454 int i; 2455 2456 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc); 2457 cr3 = GET_SMSTATE(u32, smbase, 0x7ff8); 2458 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED; 2459 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0); 2460 2461 for (i = 0; i < 8; i++) 2462 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4); 2463 2464 val = GET_SMSTATE(u32, smbase, 0x7fcc); 2465 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2466 val = GET_SMSTATE(u32, smbase, 0x7fc8); 2467 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2468 2469 selector = GET_SMSTATE(u32, smbase, 0x7fc4); 2470 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64)); 2471 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60)); 2472 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c)); 2473 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2474 2475 selector = GET_SMSTATE(u32, smbase, 0x7fc0); 2476 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80)); 2477 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c)); 2478 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78)); 2479 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2480 2481 dt.address = GET_SMSTATE(u32, smbase, 0x7f74); 2482 dt.size = GET_SMSTATE(u32, smbase, 0x7f70); 2483 ctxt->ops->set_gdt(ctxt, &dt); 2484 2485 dt.address = GET_SMSTATE(u32, smbase, 0x7f58); 2486 dt.size = GET_SMSTATE(u32, smbase, 0x7f54); 2487 ctxt->ops->set_idt(ctxt, &dt); 2488 2489 for (i = 0; i < 6; i++) { 2490 int r = rsm_load_seg_32(ctxt, smbase, i); 2491 if (r != X86EMUL_CONTINUE) 2492 return r; 2493 } 2494 2495 cr4 = GET_SMSTATE(u32, smbase, 0x7f14); 2496 2497 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8)); 2498 2499 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2500 } 2501 2502 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase) 2503 { 2504 struct desc_struct desc; 2505 struct desc_ptr dt; 2506 u64 val, cr0, cr3, cr4; 2507 u32 base3; 2508 u16 selector; 2509 int i, r; 2510 2511 for (i = 0; i < 16; i++) 2512 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8); 2513 2514 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78); 2515 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED; 2516 2517 val = GET_SMSTATE(u32, smbase, 0x7f68); 2518 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2519 val = GET_SMSTATE(u32, smbase, 0x7f60); 2520 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2521 2522 cr0 = GET_SMSTATE(u64, smbase, 0x7f58); 2523 cr3 = GET_SMSTATE(u64, smbase, 0x7f50); 2524 cr4 = GET_SMSTATE(u64, smbase, 0x7f48); 2525 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00)); 2526 val = GET_SMSTATE(u64, smbase, 0x7ed0); 2527 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA); 2528 2529 selector = GET_SMSTATE(u32, smbase, 0x7e90); 2530 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8); 2531 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94)); 2532 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98)); 2533 base3 = GET_SMSTATE(u32, smbase, 0x7e9c); 2534 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2535 2536 dt.size = GET_SMSTATE(u32, smbase, 0x7e84); 2537 dt.address = GET_SMSTATE(u64, smbase, 0x7e88); 2538 ctxt->ops->set_idt(ctxt, &dt); 2539 2540 selector = GET_SMSTATE(u32, smbase, 0x7e70); 2541 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8); 2542 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74)); 2543 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78)); 2544 base3 = GET_SMSTATE(u32, smbase, 0x7e7c); 2545 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2546 2547 dt.size = GET_SMSTATE(u32, smbase, 0x7e64); 2548 dt.address = GET_SMSTATE(u64, smbase, 0x7e68); 2549 ctxt->ops->set_gdt(ctxt, &dt); 2550 2551 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2552 if (r != X86EMUL_CONTINUE) 2553 return r; 2554 2555 for (i = 0; i < 6; i++) { 2556 r = rsm_load_seg_64(ctxt, smbase, i); 2557 if (r != X86EMUL_CONTINUE) 2558 return r; 2559 } 2560 2561 return X86EMUL_CONTINUE; 2562 } 2563 2564 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2565 { 2566 unsigned long cr0, cr4, efer; 2567 u64 smbase; 2568 int ret; 2569 2570 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2571 return emulate_ud(ctxt); 2572 2573 /* 2574 * Get back to real mode, to prepare a safe state in which to load 2575 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU 2576 * supports long mode. 2577 */ 2578 cr4 = ctxt->ops->get_cr(ctxt, 4); 2579 if (emulator_has_longmode(ctxt)) { 2580 struct desc_struct cs_desc; 2581 2582 /* Zero CR4.PCIDE before CR0.PG. */ 2583 if (cr4 & X86_CR4_PCIDE) { 2584 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2585 cr4 &= ~X86_CR4_PCIDE; 2586 } 2587 2588 /* A 32-bit code segment is required to clear EFER.LMA. */ 2589 memset(&cs_desc, 0, sizeof(cs_desc)); 2590 cs_desc.type = 0xb; 2591 cs_desc.s = cs_desc.g = cs_desc.p = 1; 2592 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS); 2593 } 2594 2595 /* For the 64-bit case, this will clear EFER.LMA. */ 2596 cr0 = ctxt->ops->get_cr(ctxt, 0); 2597 if (cr0 & X86_CR0_PE) 2598 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2599 2600 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */ 2601 if (cr4 & X86_CR4_PAE) 2602 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2603 2604 /* And finally go back to 32-bit mode. */ 2605 efer = 0; 2606 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2607 2608 smbase = ctxt->ops->get_smbase(ctxt); 2609 2610 /* 2611 * Give pre_leave_smm() a chance to make ISA-specific changes to the 2612 * vCPU state (e.g. enter guest mode) before loading state from the SMM 2613 * state-save area. 2614 */ 2615 if (ctxt->ops->pre_leave_smm(ctxt, smbase)) 2616 return X86EMUL_UNHANDLEABLE; 2617 2618 if (emulator_has_longmode(ctxt)) 2619 ret = rsm_load_state_64(ctxt, smbase + 0x8000); 2620 else 2621 ret = rsm_load_state_32(ctxt, smbase + 0x8000); 2622 2623 if (ret != X86EMUL_CONTINUE) { 2624 /* FIXME: should triple fault */ 2625 return X86EMUL_UNHANDLEABLE; 2626 } 2627 2628 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2629 ctxt->ops->set_nmi_mask(ctxt, false); 2630 2631 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) & 2632 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK)); 2633 return X86EMUL_CONTINUE; 2634 } 2635 2636 static void 2637 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2638 struct desc_struct *cs, struct desc_struct *ss) 2639 { 2640 cs->l = 0; /* will be adjusted later */ 2641 set_desc_base(cs, 0); /* flat segment */ 2642 cs->g = 1; /* 4kb granularity */ 2643 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2644 cs->type = 0x0b; /* Read, Execute, Accessed */ 2645 cs->s = 1; 2646 cs->dpl = 0; /* will be adjusted later */ 2647 cs->p = 1; 2648 cs->d = 1; 2649 cs->avl = 0; 2650 2651 set_desc_base(ss, 0); /* flat segment */ 2652 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2653 ss->g = 1; /* 4kb granularity */ 2654 ss->s = 1; 2655 ss->type = 0x03; /* Read/Write, Accessed */ 2656 ss->d = 1; /* 32bit stack segment */ 2657 ss->dpl = 0; 2658 ss->p = 1; 2659 ss->l = 0; 2660 ss->avl = 0; 2661 } 2662 2663 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2664 { 2665 u32 eax, ebx, ecx, edx; 2666 2667 eax = ecx = 0; 2668 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2669 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2670 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2671 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2672 } 2673 2674 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2675 { 2676 const struct x86_emulate_ops *ops = ctxt->ops; 2677 u32 eax, ebx, ecx, edx; 2678 2679 /* 2680 * syscall should always be enabled in longmode - so only become 2681 * vendor specific (cpuid) if other modes are active... 2682 */ 2683 if (ctxt->mode == X86EMUL_MODE_PROT64) 2684 return true; 2685 2686 eax = 0x00000000; 2687 ecx = 0x00000000; 2688 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2689 /* 2690 * Intel ("GenuineIntel") 2691 * remark: Intel CPUs only support "syscall" in 64bit 2692 * longmode. Also an 64bit guest with a 2693 * 32bit compat-app running will #UD !! While this 2694 * behaviour can be fixed (by emulating) into AMD 2695 * response - CPUs of AMD can't behave like Intel. 2696 */ 2697 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2698 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2699 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2700 return false; 2701 2702 /* AMD ("AuthenticAMD") */ 2703 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2704 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2705 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2706 return true; 2707 2708 /* AMD ("AMDisbetter!") */ 2709 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2710 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2711 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2712 return true; 2713 2714 /* Hygon ("HygonGenuine") */ 2715 if (ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx && 2716 ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx && 2717 edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx) 2718 return true; 2719 2720 /* 2721 * default: (not Intel, not AMD, not Hygon), apply Intel's 2722 * stricter rules... 2723 */ 2724 return false; 2725 } 2726 2727 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2728 { 2729 const struct x86_emulate_ops *ops = ctxt->ops; 2730 struct desc_struct cs, ss; 2731 u64 msr_data; 2732 u16 cs_sel, ss_sel; 2733 u64 efer = 0; 2734 2735 /* syscall is not available in real mode */ 2736 if (ctxt->mode == X86EMUL_MODE_REAL || 2737 ctxt->mode == X86EMUL_MODE_VM86) 2738 return emulate_ud(ctxt); 2739 2740 if (!(em_syscall_is_enabled(ctxt))) 2741 return emulate_ud(ctxt); 2742 2743 ops->get_msr(ctxt, MSR_EFER, &efer); 2744 setup_syscalls_segments(ctxt, &cs, &ss); 2745 2746 if (!(efer & EFER_SCE)) 2747 return emulate_ud(ctxt); 2748 2749 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2750 msr_data >>= 32; 2751 cs_sel = (u16)(msr_data & 0xfffc); 2752 ss_sel = (u16)(msr_data + 8); 2753 2754 if (efer & EFER_LMA) { 2755 cs.d = 0; 2756 cs.l = 1; 2757 } 2758 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2759 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2760 2761 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2762 if (efer & EFER_LMA) { 2763 #ifdef CONFIG_X86_64 2764 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2765 2766 ops->get_msr(ctxt, 2767 ctxt->mode == X86EMUL_MODE_PROT64 ? 2768 MSR_LSTAR : MSR_CSTAR, &msr_data); 2769 ctxt->_eip = msr_data; 2770 2771 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2772 ctxt->eflags &= ~msr_data; 2773 ctxt->eflags |= X86_EFLAGS_FIXED; 2774 #endif 2775 } else { 2776 /* legacy mode */ 2777 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2778 ctxt->_eip = (u32)msr_data; 2779 2780 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2781 } 2782 2783 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2784 return X86EMUL_CONTINUE; 2785 } 2786 2787 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2788 { 2789 const struct x86_emulate_ops *ops = ctxt->ops; 2790 struct desc_struct cs, ss; 2791 u64 msr_data; 2792 u16 cs_sel, ss_sel; 2793 u64 efer = 0; 2794 2795 ops->get_msr(ctxt, MSR_EFER, &efer); 2796 /* inject #GP if in real mode */ 2797 if (ctxt->mode == X86EMUL_MODE_REAL) 2798 return emulate_gp(ctxt, 0); 2799 2800 /* 2801 * Not recognized on AMD in compat mode (but is recognized in legacy 2802 * mode). 2803 */ 2804 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2805 && !vendor_intel(ctxt)) 2806 return emulate_ud(ctxt); 2807 2808 /* sysenter/sysexit have not been tested in 64bit mode. */ 2809 if (ctxt->mode == X86EMUL_MODE_PROT64) 2810 return X86EMUL_UNHANDLEABLE; 2811 2812 setup_syscalls_segments(ctxt, &cs, &ss); 2813 2814 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2815 if ((msr_data & 0xfffc) == 0x0) 2816 return emulate_gp(ctxt, 0); 2817 2818 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2819 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2820 ss_sel = cs_sel + 8; 2821 if (efer & EFER_LMA) { 2822 cs.d = 0; 2823 cs.l = 1; 2824 } 2825 2826 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2827 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2828 2829 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2830 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2831 2832 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2833 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2834 (u32)msr_data; 2835 2836 return X86EMUL_CONTINUE; 2837 } 2838 2839 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2840 { 2841 const struct x86_emulate_ops *ops = ctxt->ops; 2842 struct desc_struct cs, ss; 2843 u64 msr_data, rcx, rdx; 2844 int usermode; 2845 u16 cs_sel = 0, ss_sel = 0; 2846 2847 /* inject #GP if in real mode or Virtual 8086 mode */ 2848 if (ctxt->mode == X86EMUL_MODE_REAL || 2849 ctxt->mode == X86EMUL_MODE_VM86) 2850 return emulate_gp(ctxt, 0); 2851 2852 setup_syscalls_segments(ctxt, &cs, &ss); 2853 2854 if ((ctxt->rex_prefix & 0x8) != 0x0) 2855 usermode = X86EMUL_MODE_PROT64; 2856 else 2857 usermode = X86EMUL_MODE_PROT32; 2858 2859 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2860 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2861 2862 cs.dpl = 3; 2863 ss.dpl = 3; 2864 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2865 switch (usermode) { 2866 case X86EMUL_MODE_PROT32: 2867 cs_sel = (u16)(msr_data + 16); 2868 if ((msr_data & 0xfffc) == 0x0) 2869 return emulate_gp(ctxt, 0); 2870 ss_sel = (u16)(msr_data + 24); 2871 rcx = (u32)rcx; 2872 rdx = (u32)rdx; 2873 break; 2874 case X86EMUL_MODE_PROT64: 2875 cs_sel = (u16)(msr_data + 32); 2876 if (msr_data == 0x0) 2877 return emulate_gp(ctxt, 0); 2878 ss_sel = cs_sel + 8; 2879 cs.d = 0; 2880 cs.l = 1; 2881 if (emul_is_noncanonical_address(rcx, ctxt) || 2882 emul_is_noncanonical_address(rdx, ctxt)) 2883 return emulate_gp(ctxt, 0); 2884 break; 2885 } 2886 cs_sel |= SEGMENT_RPL_MASK; 2887 ss_sel |= SEGMENT_RPL_MASK; 2888 2889 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2890 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2891 2892 ctxt->_eip = rdx; 2893 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2894 2895 return X86EMUL_CONTINUE; 2896 } 2897 2898 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2899 { 2900 int iopl; 2901 if (ctxt->mode == X86EMUL_MODE_REAL) 2902 return false; 2903 if (ctxt->mode == X86EMUL_MODE_VM86) 2904 return true; 2905 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2906 return ctxt->ops->cpl(ctxt) > iopl; 2907 } 2908 2909 #define VMWARE_PORT_VMPORT (0x5658) 2910 #define VMWARE_PORT_VMRPC (0x5659) 2911 2912 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2913 u16 port, u16 len) 2914 { 2915 const struct x86_emulate_ops *ops = ctxt->ops; 2916 struct desc_struct tr_seg; 2917 u32 base3; 2918 int r; 2919 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2920 unsigned mask = (1 << len) - 1; 2921 unsigned long base; 2922 2923 /* 2924 * VMware allows access to these ports even if denied 2925 * by TSS I/O permission bitmap. Mimic behavior. 2926 */ 2927 if (enable_vmware_backdoor && 2928 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2929 return true; 2930 2931 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2932 if (!tr_seg.p) 2933 return false; 2934 if (desc_limit_scaled(&tr_seg) < 103) 2935 return false; 2936 base = get_desc_base(&tr_seg); 2937 #ifdef CONFIG_X86_64 2938 base |= ((u64)base3) << 32; 2939 #endif 2940 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2941 if (r != X86EMUL_CONTINUE) 2942 return false; 2943 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2944 return false; 2945 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2946 if (r != X86EMUL_CONTINUE) 2947 return false; 2948 if ((perm >> bit_idx) & mask) 2949 return false; 2950 return true; 2951 } 2952 2953 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2954 u16 port, u16 len) 2955 { 2956 if (ctxt->perm_ok) 2957 return true; 2958 2959 if (emulator_bad_iopl(ctxt)) 2960 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2961 return false; 2962 2963 ctxt->perm_ok = true; 2964 2965 return true; 2966 } 2967 2968 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2969 { 2970 /* 2971 * Intel CPUs mask the counter and pointers in quite strange 2972 * manner when ECX is zero due to REP-string optimizations. 2973 */ 2974 #ifdef CONFIG_X86_64 2975 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2976 return; 2977 2978 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2979 2980 switch (ctxt->b) { 2981 case 0xa4: /* movsb */ 2982 case 0xa5: /* movsd/w */ 2983 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2984 /* fall through */ 2985 case 0xaa: /* stosb */ 2986 case 0xab: /* stosd/w */ 2987 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2988 } 2989 #endif 2990 } 2991 2992 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2993 struct tss_segment_16 *tss) 2994 { 2995 tss->ip = ctxt->_eip; 2996 tss->flag = ctxt->eflags; 2997 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2998 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2999 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 3000 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 3001 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 3002 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 3003 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 3004 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 3005 3006 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3007 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3008 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3009 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3010 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 3011 } 3012 3013 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 3014 struct tss_segment_16 *tss) 3015 { 3016 int ret; 3017 u8 cpl; 3018 3019 ctxt->_eip = tss->ip; 3020 ctxt->eflags = tss->flag | 2; 3021 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 3022 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 3023 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 3024 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 3025 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 3026 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 3027 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 3028 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 3029 3030 /* 3031 * SDM says that segment selectors are loaded before segment 3032 * descriptors 3033 */ 3034 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 3035 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3036 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3037 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3038 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3039 3040 cpl = tss->cs & 3; 3041 3042 /* 3043 * Now load segment descriptors. If fault happens at this stage 3044 * it is handled in a context of new task 3045 */ 3046 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 3047 X86_TRANSFER_TASK_SWITCH, NULL); 3048 if (ret != X86EMUL_CONTINUE) 3049 return ret; 3050 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3051 X86_TRANSFER_TASK_SWITCH, NULL); 3052 if (ret != X86EMUL_CONTINUE) 3053 return ret; 3054 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3055 X86_TRANSFER_TASK_SWITCH, NULL); 3056 if (ret != X86EMUL_CONTINUE) 3057 return ret; 3058 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3059 X86_TRANSFER_TASK_SWITCH, NULL); 3060 if (ret != X86EMUL_CONTINUE) 3061 return ret; 3062 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3063 X86_TRANSFER_TASK_SWITCH, NULL); 3064 if (ret != X86EMUL_CONTINUE) 3065 return ret; 3066 3067 return X86EMUL_CONTINUE; 3068 } 3069 3070 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 3071 u16 tss_selector, u16 old_tss_sel, 3072 ulong old_tss_base, struct desc_struct *new_desc) 3073 { 3074 struct tss_segment_16 tss_seg; 3075 int ret; 3076 u32 new_tss_base = get_desc_base(new_desc); 3077 3078 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3079 if (ret != X86EMUL_CONTINUE) 3080 return ret; 3081 3082 save_state_to_tss16(ctxt, &tss_seg); 3083 3084 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3085 if (ret != X86EMUL_CONTINUE) 3086 return ret; 3087 3088 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3089 if (ret != X86EMUL_CONTINUE) 3090 return ret; 3091 3092 if (old_tss_sel != 0xffff) { 3093 tss_seg.prev_task_link = old_tss_sel; 3094 3095 ret = linear_write_system(ctxt, new_tss_base, 3096 &tss_seg.prev_task_link, 3097 sizeof(tss_seg.prev_task_link)); 3098 if (ret != X86EMUL_CONTINUE) 3099 return ret; 3100 } 3101 3102 return load_state_from_tss16(ctxt, &tss_seg); 3103 } 3104 3105 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 3106 struct tss_segment_32 *tss) 3107 { 3108 /* CR3 and ldt selector are not saved intentionally */ 3109 tss->eip = ctxt->_eip; 3110 tss->eflags = ctxt->eflags; 3111 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 3112 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 3113 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 3114 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 3115 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 3116 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 3117 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 3118 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 3119 3120 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3121 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3122 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3123 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3124 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 3125 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 3126 } 3127 3128 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 3129 struct tss_segment_32 *tss) 3130 { 3131 int ret; 3132 u8 cpl; 3133 3134 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3135 return emulate_gp(ctxt, 0); 3136 ctxt->_eip = tss->eip; 3137 ctxt->eflags = tss->eflags | 2; 3138 3139 /* General purpose registers */ 3140 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3141 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3142 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3143 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3144 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3145 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3146 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3147 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3148 3149 /* 3150 * SDM says that segment selectors are loaded before segment 3151 * descriptors. This is important because CPL checks will 3152 * use CS.RPL. 3153 */ 3154 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3155 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3156 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3157 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3158 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3159 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3160 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3161 3162 /* 3163 * If we're switching between Protected Mode and VM86, we need to make 3164 * sure to update the mode before loading the segment descriptors so 3165 * that the selectors are interpreted correctly. 3166 */ 3167 if (ctxt->eflags & X86_EFLAGS_VM) { 3168 ctxt->mode = X86EMUL_MODE_VM86; 3169 cpl = 3; 3170 } else { 3171 ctxt->mode = X86EMUL_MODE_PROT32; 3172 cpl = tss->cs & 3; 3173 } 3174 3175 /* 3176 * Now load segment descriptors. If fault happenes at this stage 3177 * it is handled in a context of new task 3178 */ 3179 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3180 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3181 if (ret != X86EMUL_CONTINUE) 3182 return ret; 3183 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3184 X86_TRANSFER_TASK_SWITCH, NULL); 3185 if (ret != X86EMUL_CONTINUE) 3186 return ret; 3187 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3188 X86_TRANSFER_TASK_SWITCH, NULL); 3189 if (ret != X86EMUL_CONTINUE) 3190 return ret; 3191 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3192 X86_TRANSFER_TASK_SWITCH, NULL); 3193 if (ret != X86EMUL_CONTINUE) 3194 return ret; 3195 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3196 X86_TRANSFER_TASK_SWITCH, NULL); 3197 if (ret != X86EMUL_CONTINUE) 3198 return ret; 3199 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3200 X86_TRANSFER_TASK_SWITCH, NULL); 3201 if (ret != X86EMUL_CONTINUE) 3202 return ret; 3203 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3204 X86_TRANSFER_TASK_SWITCH, NULL); 3205 3206 return ret; 3207 } 3208 3209 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 3210 u16 tss_selector, u16 old_tss_sel, 3211 ulong old_tss_base, struct desc_struct *new_desc) 3212 { 3213 struct tss_segment_32 tss_seg; 3214 int ret; 3215 u32 new_tss_base = get_desc_base(new_desc); 3216 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3217 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3218 3219 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3220 if (ret != X86EMUL_CONTINUE) 3221 return ret; 3222 3223 save_state_to_tss32(ctxt, &tss_seg); 3224 3225 /* Only GP registers and segment selectors are saved */ 3226 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3227 ldt_sel_offset - eip_offset); 3228 if (ret != X86EMUL_CONTINUE) 3229 return ret; 3230 3231 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3232 if (ret != X86EMUL_CONTINUE) 3233 return ret; 3234 3235 if (old_tss_sel != 0xffff) { 3236 tss_seg.prev_task_link = old_tss_sel; 3237 3238 ret = linear_write_system(ctxt, new_tss_base, 3239 &tss_seg.prev_task_link, 3240 sizeof(tss_seg.prev_task_link)); 3241 if (ret != X86EMUL_CONTINUE) 3242 return ret; 3243 } 3244 3245 return load_state_from_tss32(ctxt, &tss_seg); 3246 } 3247 3248 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3249 u16 tss_selector, int idt_index, int reason, 3250 bool has_error_code, u32 error_code) 3251 { 3252 const struct x86_emulate_ops *ops = ctxt->ops; 3253 struct desc_struct curr_tss_desc, next_tss_desc; 3254 int ret; 3255 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3256 ulong old_tss_base = 3257 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3258 u32 desc_limit; 3259 ulong desc_addr, dr7; 3260 3261 /* FIXME: old_tss_base == ~0 ? */ 3262 3263 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3264 if (ret != X86EMUL_CONTINUE) 3265 return ret; 3266 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3267 if (ret != X86EMUL_CONTINUE) 3268 return ret; 3269 3270 /* FIXME: check that next_tss_desc is tss */ 3271 3272 /* 3273 * Check privileges. The three cases are task switch caused by... 3274 * 3275 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3276 * 2. Exception/IRQ/iret: No check is performed 3277 * 3. jmp/call to TSS/task-gate: No check is performed since the 3278 * hardware checks it before exiting. 3279 */ 3280 if (reason == TASK_SWITCH_GATE) { 3281 if (idt_index != -1) { 3282 /* Software interrupts */ 3283 struct desc_struct task_gate_desc; 3284 int dpl; 3285 3286 ret = read_interrupt_descriptor(ctxt, idt_index, 3287 &task_gate_desc); 3288 if (ret != X86EMUL_CONTINUE) 3289 return ret; 3290 3291 dpl = task_gate_desc.dpl; 3292 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3293 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3294 } 3295 } 3296 3297 desc_limit = desc_limit_scaled(&next_tss_desc); 3298 if (!next_tss_desc.p || 3299 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3300 desc_limit < 0x2b)) { 3301 return emulate_ts(ctxt, tss_selector & 0xfffc); 3302 } 3303 3304 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3305 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3306 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3307 } 3308 3309 if (reason == TASK_SWITCH_IRET) 3310 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3311 3312 /* set back link to prev task only if NT bit is set in eflags 3313 note that old_tss_sel is not used after this point */ 3314 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3315 old_tss_sel = 0xffff; 3316 3317 if (next_tss_desc.type & 8) 3318 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 3319 old_tss_base, &next_tss_desc); 3320 else 3321 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 3322 old_tss_base, &next_tss_desc); 3323 if (ret != X86EMUL_CONTINUE) 3324 return ret; 3325 3326 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3327 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3328 3329 if (reason != TASK_SWITCH_IRET) { 3330 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3331 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3332 } 3333 3334 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3335 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3336 3337 if (has_error_code) { 3338 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3339 ctxt->lock_prefix = 0; 3340 ctxt->src.val = (unsigned long) error_code; 3341 ret = em_push(ctxt); 3342 } 3343 3344 ops->get_dr(ctxt, 7, &dr7); 3345 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3346 3347 return ret; 3348 } 3349 3350 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3351 u16 tss_selector, int idt_index, int reason, 3352 bool has_error_code, u32 error_code) 3353 { 3354 int rc; 3355 3356 invalidate_registers(ctxt); 3357 ctxt->_eip = ctxt->eip; 3358 ctxt->dst.type = OP_NONE; 3359 3360 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3361 has_error_code, error_code); 3362 3363 if (rc == X86EMUL_CONTINUE) { 3364 ctxt->eip = ctxt->_eip; 3365 writeback_registers(ctxt); 3366 } 3367 3368 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3369 } 3370 3371 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3372 struct operand *op) 3373 { 3374 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3375 3376 register_address_increment(ctxt, reg, df * op->bytes); 3377 op->addr.mem.ea = register_address(ctxt, reg); 3378 } 3379 3380 static int em_das(struct x86_emulate_ctxt *ctxt) 3381 { 3382 u8 al, old_al; 3383 bool af, cf, old_cf; 3384 3385 cf = ctxt->eflags & X86_EFLAGS_CF; 3386 al = ctxt->dst.val; 3387 3388 old_al = al; 3389 old_cf = cf; 3390 cf = false; 3391 af = ctxt->eflags & X86_EFLAGS_AF; 3392 if ((al & 0x0f) > 9 || af) { 3393 al -= 6; 3394 cf = old_cf | (al >= 250); 3395 af = true; 3396 } else { 3397 af = false; 3398 } 3399 if (old_al > 0x99 || old_cf) { 3400 al -= 0x60; 3401 cf = true; 3402 } 3403 3404 ctxt->dst.val = al; 3405 /* Set PF, ZF, SF */ 3406 ctxt->src.type = OP_IMM; 3407 ctxt->src.val = 0; 3408 ctxt->src.bytes = 1; 3409 fastop(ctxt, em_or); 3410 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3411 if (cf) 3412 ctxt->eflags |= X86_EFLAGS_CF; 3413 if (af) 3414 ctxt->eflags |= X86_EFLAGS_AF; 3415 return X86EMUL_CONTINUE; 3416 } 3417 3418 static int em_aam(struct x86_emulate_ctxt *ctxt) 3419 { 3420 u8 al, ah; 3421 3422 if (ctxt->src.val == 0) 3423 return emulate_de(ctxt); 3424 3425 al = ctxt->dst.val & 0xff; 3426 ah = al / ctxt->src.val; 3427 al %= ctxt->src.val; 3428 3429 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3430 3431 /* Set PF, ZF, SF */ 3432 ctxt->src.type = OP_IMM; 3433 ctxt->src.val = 0; 3434 ctxt->src.bytes = 1; 3435 fastop(ctxt, em_or); 3436 3437 return X86EMUL_CONTINUE; 3438 } 3439 3440 static int em_aad(struct x86_emulate_ctxt *ctxt) 3441 { 3442 u8 al = ctxt->dst.val & 0xff; 3443 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3444 3445 al = (al + (ah * ctxt->src.val)) & 0xff; 3446 3447 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3448 3449 /* Set PF, ZF, SF */ 3450 ctxt->src.type = OP_IMM; 3451 ctxt->src.val = 0; 3452 ctxt->src.bytes = 1; 3453 fastop(ctxt, em_or); 3454 3455 return X86EMUL_CONTINUE; 3456 } 3457 3458 static int em_call(struct x86_emulate_ctxt *ctxt) 3459 { 3460 int rc; 3461 long rel = ctxt->src.val; 3462 3463 ctxt->src.val = (unsigned long)ctxt->_eip; 3464 rc = jmp_rel(ctxt, rel); 3465 if (rc != X86EMUL_CONTINUE) 3466 return rc; 3467 return em_push(ctxt); 3468 } 3469 3470 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3471 { 3472 u16 sel, old_cs; 3473 ulong old_eip; 3474 int rc; 3475 struct desc_struct old_desc, new_desc; 3476 const struct x86_emulate_ops *ops = ctxt->ops; 3477 int cpl = ctxt->ops->cpl(ctxt); 3478 enum x86emul_mode prev_mode = ctxt->mode; 3479 3480 old_eip = ctxt->_eip; 3481 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3482 3483 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3484 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3485 X86_TRANSFER_CALL_JMP, &new_desc); 3486 if (rc != X86EMUL_CONTINUE) 3487 return rc; 3488 3489 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 3490 if (rc != X86EMUL_CONTINUE) 3491 goto fail; 3492 3493 ctxt->src.val = old_cs; 3494 rc = em_push(ctxt); 3495 if (rc != X86EMUL_CONTINUE) 3496 goto fail; 3497 3498 ctxt->src.val = old_eip; 3499 rc = em_push(ctxt); 3500 /* If we failed, we tainted the memory, but the very least we should 3501 restore cs */ 3502 if (rc != X86EMUL_CONTINUE) { 3503 pr_warn_once("faulting far call emulation tainted memory\n"); 3504 goto fail; 3505 } 3506 return rc; 3507 fail: 3508 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3509 ctxt->mode = prev_mode; 3510 return rc; 3511 3512 } 3513 3514 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3515 { 3516 int rc; 3517 unsigned long eip; 3518 3519 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3520 if (rc != X86EMUL_CONTINUE) 3521 return rc; 3522 rc = assign_eip_near(ctxt, eip); 3523 if (rc != X86EMUL_CONTINUE) 3524 return rc; 3525 rsp_increment(ctxt, ctxt->src.val); 3526 return X86EMUL_CONTINUE; 3527 } 3528 3529 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3530 { 3531 /* Write back the register source. */ 3532 ctxt->src.val = ctxt->dst.val; 3533 write_register_operand(&ctxt->src); 3534 3535 /* Write back the memory destination with implicit LOCK prefix. */ 3536 ctxt->dst.val = ctxt->src.orig_val; 3537 ctxt->lock_prefix = 1; 3538 return X86EMUL_CONTINUE; 3539 } 3540 3541 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3542 { 3543 ctxt->dst.val = ctxt->src2.val; 3544 return fastop(ctxt, em_imul); 3545 } 3546 3547 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3548 { 3549 ctxt->dst.type = OP_REG; 3550 ctxt->dst.bytes = ctxt->src.bytes; 3551 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3552 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3553 3554 return X86EMUL_CONTINUE; 3555 } 3556 3557 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3558 { 3559 u64 tsc_aux = 0; 3560 3561 if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux)) 3562 return emulate_gp(ctxt, 0); 3563 ctxt->dst.val = tsc_aux; 3564 return X86EMUL_CONTINUE; 3565 } 3566 3567 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3568 { 3569 u64 tsc = 0; 3570 3571 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3572 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3573 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3574 return X86EMUL_CONTINUE; 3575 } 3576 3577 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3578 { 3579 u64 pmc; 3580 3581 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3582 return emulate_gp(ctxt, 0); 3583 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3584 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3585 return X86EMUL_CONTINUE; 3586 } 3587 3588 static int em_mov(struct x86_emulate_ctxt *ctxt) 3589 { 3590 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3591 return X86EMUL_CONTINUE; 3592 } 3593 3594 #define FFL(x) bit(X86_FEATURE_##x) 3595 3596 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3597 { 3598 u32 ebx, ecx, edx, eax = 1; 3599 u16 tmp; 3600 3601 /* 3602 * Check MOVBE is set in the guest-visible CPUID leaf. 3603 */ 3604 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3605 if (!(ecx & FFL(MOVBE))) 3606 return emulate_ud(ctxt); 3607 3608 switch (ctxt->op_bytes) { 3609 case 2: 3610 /* 3611 * From MOVBE definition: "...When the operand size is 16 bits, 3612 * the upper word of the destination register remains unchanged 3613 * ..." 3614 * 3615 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3616 * rules so we have to do the operation almost per hand. 3617 */ 3618 tmp = (u16)ctxt->src.val; 3619 ctxt->dst.val &= ~0xffffUL; 3620 ctxt->dst.val |= (unsigned long)swab16(tmp); 3621 break; 3622 case 4: 3623 ctxt->dst.val = swab32((u32)ctxt->src.val); 3624 break; 3625 case 8: 3626 ctxt->dst.val = swab64(ctxt->src.val); 3627 break; 3628 default: 3629 BUG(); 3630 } 3631 return X86EMUL_CONTINUE; 3632 } 3633 3634 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3635 { 3636 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3637 return emulate_gp(ctxt, 0); 3638 3639 /* Disable writeback. */ 3640 ctxt->dst.type = OP_NONE; 3641 return X86EMUL_CONTINUE; 3642 } 3643 3644 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3645 { 3646 unsigned long val; 3647 3648 if (ctxt->mode == X86EMUL_MODE_PROT64) 3649 val = ctxt->src.val & ~0ULL; 3650 else 3651 val = ctxt->src.val & ~0U; 3652 3653 /* #UD condition is already handled. */ 3654 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3655 return emulate_gp(ctxt, 0); 3656 3657 /* Disable writeback. */ 3658 ctxt->dst.type = OP_NONE; 3659 return X86EMUL_CONTINUE; 3660 } 3661 3662 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3663 { 3664 u64 msr_data; 3665 3666 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3667 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3668 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3669 return emulate_gp(ctxt, 0); 3670 3671 return X86EMUL_CONTINUE; 3672 } 3673 3674 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3675 { 3676 u64 msr_data; 3677 3678 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3679 return emulate_gp(ctxt, 0); 3680 3681 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3682 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3683 return X86EMUL_CONTINUE; 3684 } 3685 3686 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3687 { 3688 if (segment > VCPU_SREG_GS && 3689 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3690 ctxt->ops->cpl(ctxt) > 0) 3691 return emulate_gp(ctxt, 0); 3692 3693 ctxt->dst.val = get_segment_selector(ctxt, segment); 3694 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3695 ctxt->dst.bytes = 2; 3696 return X86EMUL_CONTINUE; 3697 } 3698 3699 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3700 { 3701 if (ctxt->modrm_reg > VCPU_SREG_GS) 3702 return emulate_ud(ctxt); 3703 3704 return em_store_sreg(ctxt, ctxt->modrm_reg); 3705 } 3706 3707 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3708 { 3709 u16 sel = ctxt->src.val; 3710 3711 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3712 return emulate_ud(ctxt); 3713 3714 if (ctxt->modrm_reg == VCPU_SREG_SS) 3715 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3716 3717 /* Disable writeback. */ 3718 ctxt->dst.type = OP_NONE; 3719 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3720 } 3721 3722 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3723 { 3724 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3725 } 3726 3727 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3728 { 3729 u16 sel = ctxt->src.val; 3730 3731 /* Disable writeback. */ 3732 ctxt->dst.type = OP_NONE; 3733 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3734 } 3735 3736 static int em_str(struct x86_emulate_ctxt *ctxt) 3737 { 3738 return em_store_sreg(ctxt, VCPU_SREG_TR); 3739 } 3740 3741 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3742 { 3743 u16 sel = ctxt->src.val; 3744 3745 /* Disable writeback. */ 3746 ctxt->dst.type = OP_NONE; 3747 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3748 } 3749 3750 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3751 { 3752 int rc; 3753 ulong linear; 3754 3755 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3756 if (rc == X86EMUL_CONTINUE) 3757 ctxt->ops->invlpg(ctxt, linear); 3758 /* Disable writeback. */ 3759 ctxt->dst.type = OP_NONE; 3760 return X86EMUL_CONTINUE; 3761 } 3762 3763 static int em_clts(struct x86_emulate_ctxt *ctxt) 3764 { 3765 ulong cr0; 3766 3767 cr0 = ctxt->ops->get_cr(ctxt, 0); 3768 cr0 &= ~X86_CR0_TS; 3769 ctxt->ops->set_cr(ctxt, 0, cr0); 3770 return X86EMUL_CONTINUE; 3771 } 3772 3773 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3774 { 3775 int rc = ctxt->ops->fix_hypercall(ctxt); 3776 3777 if (rc != X86EMUL_CONTINUE) 3778 return rc; 3779 3780 /* Let the processor re-execute the fixed hypercall */ 3781 ctxt->_eip = ctxt->eip; 3782 /* Disable writeback. */ 3783 ctxt->dst.type = OP_NONE; 3784 return X86EMUL_CONTINUE; 3785 } 3786 3787 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3788 void (*get)(struct x86_emulate_ctxt *ctxt, 3789 struct desc_ptr *ptr)) 3790 { 3791 struct desc_ptr desc_ptr; 3792 3793 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3794 ctxt->ops->cpl(ctxt) > 0) 3795 return emulate_gp(ctxt, 0); 3796 3797 if (ctxt->mode == X86EMUL_MODE_PROT64) 3798 ctxt->op_bytes = 8; 3799 get(ctxt, &desc_ptr); 3800 if (ctxt->op_bytes == 2) { 3801 ctxt->op_bytes = 4; 3802 desc_ptr.address &= 0x00ffffff; 3803 } 3804 /* Disable writeback. */ 3805 ctxt->dst.type = OP_NONE; 3806 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3807 &desc_ptr, 2 + ctxt->op_bytes); 3808 } 3809 3810 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3811 { 3812 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3813 } 3814 3815 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3816 { 3817 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3818 } 3819 3820 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3821 { 3822 struct desc_ptr desc_ptr; 3823 int rc; 3824 3825 if (ctxt->mode == X86EMUL_MODE_PROT64) 3826 ctxt->op_bytes = 8; 3827 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3828 &desc_ptr.size, &desc_ptr.address, 3829 ctxt->op_bytes); 3830 if (rc != X86EMUL_CONTINUE) 3831 return rc; 3832 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3833 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3834 return emulate_gp(ctxt, 0); 3835 if (lgdt) 3836 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3837 else 3838 ctxt->ops->set_idt(ctxt, &desc_ptr); 3839 /* Disable writeback. */ 3840 ctxt->dst.type = OP_NONE; 3841 return X86EMUL_CONTINUE; 3842 } 3843 3844 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3845 { 3846 return em_lgdt_lidt(ctxt, true); 3847 } 3848 3849 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3850 { 3851 return em_lgdt_lidt(ctxt, false); 3852 } 3853 3854 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3855 { 3856 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3857 ctxt->ops->cpl(ctxt) > 0) 3858 return emulate_gp(ctxt, 0); 3859 3860 if (ctxt->dst.type == OP_MEM) 3861 ctxt->dst.bytes = 2; 3862 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3863 return X86EMUL_CONTINUE; 3864 } 3865 3866 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3867 { 3868 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3869 | (ctxt->src.val & 0x0f)); 3870 ctxt->dst.type = OP_NONE; 3871 return X86EMUL_CONTINUE; 3872 } 3873 3874 static int em_loop(struct x86_emulate_ctxt *ctxt) 3875 { 3876 int rc = X86EMUL_CONTINUE; 3877 3878 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3879 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3880 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3881 rc = jmp_rel(ctxt, ctxt->src.val); 3882 3883 return rc; 3884 } 3885 3886 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3887 { 3888 int rc = X86EMUL_CONTINUE; 3889 3890 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3891 rc = jmp_rel(ctxt, ctxt->src.val); 3892 3893 return rc; 3894 } 3895 3896 static int em_in(struct x86_emulate_ctxt *ctxt) 3897 { 3898 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3899 &ctxt->dst.val)) 3900 return X86EMUL_IO_NEEDED; 3901 3902 return X86EMUL_CONTINUE; 3903 } 3904 3905 static int em_out(struct x86_emulate_ctxt *ctxt) 3906 { 3907 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3908 &ctxt->src.val, 1); 3909 /* Disable writeback. */ 3910 ctxt->dst.type = OP_NONE; 3911 return X86EMUL_CONTINUE; 3912 } 3913 3914 static int em_cli(struct x86_emulate_ctxt *ctxt) 3915 { 3916 if (emulator_bad_iopl(ctxt)) 3917 return emulate_gp(ctxt, 0); 3918 3919 ctxt->eflags &= ~X86_EFLAGS_IF; 3920 return X86EMUL_CONTINUE; 3921 } 3922 3923 static int em_sti(struct x86_emulate_ctxt *ctxt) 3924 { 3925 if (emulator_bad_iopl(ctxt)) 3926 return emulate_gp(ctxt, 0); 3927 3928 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3929 ctxt->eflags |= X86_EFLAGS_IF; 3930 return X86EMUL_CONTINUE; 3931 } 3932 3933 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3934 { 3935 u32 eax, ebx, ecx, edx; 3936 u64 msr = 0; 3937 3938 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3939 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3940 ctxt->ops->cpl(ctxt)) { 3941 return emulate_gp(ctxt, 0); 3942 } 3943 3944 eax = reg_read(ctxt, VCPU_REGS_RAX); 3945 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3946 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 3947 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3948 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3949 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3950 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3951 return X86EMUL_CONTINUE; 3952 } 3953 3954 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3955 { 3956 u32 flags; 3957 3958 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3959 X86_EFLAGS_SF; 3960 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3961 3962 ctxt->eflags &= ~0xffUL; 3963 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3964 return X86EMUL_CONTINUE; 3965 } 3966 3967 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3968 { 3969 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3970 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3971 return X86EMUL_CONTINUE; 3972 } 3973 3974 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3975 { 3976 switch (ctxt->op_bytes) { 3977 #ifdef CONFIG_X86_64 3978 case 8: 3979 asm("bswap %0" : "+r"(ctxt->dst.val)); 3980 break; 3981 #endif 3982 default: 3983 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3984 break; 3985 } 3986 return X86EMUL_CONTINUE; 3987 } 3988 3989 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3990 { 3991 /* emulating clflush regardless of cpuid */ 3992 return X86EMUL_CONTINUE; 3993 } 3994 3995 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3996 { 3997 ctxt->dst.val = (s32) ctxt->src.val; 3998 return X86EMUL_CONTINUE; 3999 } 4000 4001 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 4002 { 4003 u32 eax = 1, ebx, ecx = 0, edx; 4004 4005 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 4006 if (!(edx & FFL(FXSR))) 4007 return emulate_ud(ctxt); 4008 4009 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 4010 return emulate_nm(ctxt); 4011 4012 /* 4013 * Don't emulate a case that should never be hit, instead of working 4014 * around a lack of fxsave64/fxrstor64 on old compilers. 4015 */ 4016 if (ctxt->mode >= X86EMUL_MODE_PROT64) 4017 return X86EMUL_UNHANDLEABLE; 4018 4019 return X86EMUL_CONTINUE; 4020 } 4021 4022 /* 4023 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 4024 * and restore MXCSR. 4025 */ 4026 static size_t __fxstate_size(int nregs) 4027 { 4028 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 4029 } 4030 4031 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 4032 { 4033 bool cr4_osfxsr; 4034 if (ctxt->mode == X86EMUL_MODE_PROT64) 4035 return __fxstate_size(16); 4036 4037 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 4038 return __fxstate_size(cr4_osfxsr ? 8 : 0); 4039 } 4040 4041 /* 4042 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 4043 * 1) 16 bit mode 4044 * 2) 32 bit mode 4045 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 4046 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 4047 * save and restore 4048 * 3) 64-bit mode with REX.W prefix 4049 * - like (2), but XMM 8-15 are being saved and restored 4050 * 4) 64-bit mode without REX.W prefix 4051 * - like (3), but FIP and FDP are 64 bit 4052 * 4053 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 4054 * desired result. (4) is not emulated. 4055 * 4056 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 4057 * and FPU DS) should match. 4058 */ 4059 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 4060 { 4061 struct fxregs_state fx_state; 4062 int rc; 4063 4064 rc = check_fxsr(ctxt); 4065 if (rc != X86EMUL_CONTINUE) 4066 return rc; 4067 4068 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 4069 4070 if (rc != X86EMUL_CONTINUE) 4071 return rc; 4072 4073 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 4074 fxstate_size(ctxt)); 4075 } 4076 4077 /* 4078 * FXRSTOR might restore XMM registers not provided by the guest. Fill 4079 * in the host registers (via FXSAVE) instead, so they won't be modified. 4080 * (preemption has to stay disabled until FXRSTOR). 4081 * 4082 * Use noinline to keep the stack for other functions called by callers small. 4083 */ 4084 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 4085 const size_t used_size) 4086 { 4087 struct fxregs_state fx_tmp; 4088 int rc; 4089 4090 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 4091 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 4092 __fxstate_size(16) - used_size); 4093 4094 return rc; 4095 } 4096 4097 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 4098 { 4099 struct fxregs_state fx_state; 4100 int rc; 4101 size_t size; 4102 4103 rc = check_fxsr(ctxt); 4104 if (rc != X86EMUL_CONTINUE) 4105 return rc; 4106 4107 size = fxstate_size(ctxt); 4108 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 4109 if (rc != X86EMUL_CONTINUE) 4110 return rc; 4111 4112 if (size < __fxstate_size(16)) { 4113 rc = fxregs_fixup(&fx_state, size); 4114 if (rc != X86EMUL_CONTINUE) 4115 goto out; 4116 } 4117 4118 if (fx_state.mxcsr >> 16) { 4119 rc = emulate_gp(ctxt, 0); 4120 goto out; 4121 } 4122 4123 if (rc == X86EMUL_CONTINUE) 4124 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 4125 4126 out: 4127 return rc; 4128 } 4129 4130 static bool valid_cr(int nr) 4131 { 4132 switch (nr) { 4133 case 0: 4134 case 2 ... 4: 4135 case 8: 4136 return true; 4137 default: 4138 return false; 4139 } 4140 } 4141 4142 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 4143 { 4144 if (!valid_cr(ctxt->modrm_reg)) 4145 return emulate_ud(ctxt); 4146 4147 return X86EMUL_CONTINUE; 4148 } 4149 4150 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 4151 { 4152 u64 new_val = ctxt->src.val64; 4153 int cr = ctxt->modrm_reg; 4154 u64 efer = 0; 4155 4156 static u64 cr_reserved_bits[] = { 4157 0xffffffff00000000ULL, 4158 0, 0, 0, /* CR3 checked later */ 4159 CR4_RESERVED_BITS, 4160 0, 0, 0, 4161 CR8_RESERVED_BITS, 4162 }; 4163 4164 if (!valid_cr(cr)) 4165 return emulate_ud(ctxt); 4166 4167 if (new_val & cr_reserved_bits[cr]) 4168 return emulate_gp(ctxt, 0); 4169 4170 switch (cr) { 4171 case 0: { 4172 u64 cr4; 4173 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 4174 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 4175 return emulate_gp(ctxt, 0); 4176 4177 cr4 = ctxt->ops->get_cr(ctxt, 4); 4178 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4179 4180 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 4181 !(cr4 & X86_CR4_PAE)) 4182 return emulate_gp(ctxt, 0); 4183 4184 break; 4185 } 4186 case 3: { 4187 u64 rsvd = 0; 4188 4189 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4190 if (efer & EFER_LMA) { 4191 u64 maxphyaddr; 4192 u32 eax, ebx, ecx, edx; 4193 4194 eax = 0x80000008; 4195 ecx = 0; 4196 if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, 4197 &edx, false)) 4198 maxphyaddr = eax & 0xff; 4199 else 4200 maxphyaddr = 36; 4201 rsvd = rsvd_bits(maxphyaddr, 63); 4202 if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE) 4203 rsvd &= ~X86_CR3_PCID_NOFLUSH; 4204 } 4205 4206 if (new_val & rsvd) 4207 return emulate_gp(ctxt, 0); 4208 4209 break; 4210 } 4211 case 4: { 4212 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4213 4214 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 4215 return emulate_gp(ctxt, 0); 4216 4217 break; 4218 } 4219 } 4220 4221 return X86EMUL_CONTINUE; 4222 } 4223 4224 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 4225 { 4226 unsigned long dr7; 4227 4228 ctxt->ops->get_dr(ctxt, 7, &dr7); 4229 4230 /* Check if DR7.Global_Enable is set */ 4231 return dr7 & (1 << 13); 4232 } 4233 4234 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 4235 { 4236 int dr = ctxt->modrm_reg; 4237 u64 cr4; 4238 4239 if (dr > 7) 4240 return emulate_ud(ctxt); 4241 4242 cr4 = ctxt->ops->get_cr(ctxt, 4); 4243 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 4244 return emulate_ud(ctxt); 4245 4246 if (check_dr7_gd(ctxt)) { 4247 ulong dr6; 4248 4249 ctxt->ops->get_dr(ctxt, 6, &dr6); 4250 dr6 &= ~15; 4251 dr6 |= DR6_BD | DR6_RTM; 4252 ctxt->ops->set_dr(ctxt, 6, dr6); 4253 return emulate_db(ctxt); 4254 } 4255 4256 return X86EMUL_CONTINUE; 4257 } 4258 4259 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 4260 { 4261 u64 new_val = ctxt->src.val64; 4262 int dr = ctxt->modrm_reg; 4263 4264 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 4265 return emulate_gp(ctxt, 0); 4266 4267 return check_dr_read(ctxt); 4268 } 4269 4270 static int check_svme(struct x86_emulate_ctxt *ctxt) 4271 { 4272 u64 efer = 0; 4273 4274 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4275 4276 if (!(efer & EFER_SVME)) 4277 return emulate_ud(ctxt); 4278 4279 return X86EMUL_CONTINUE; 4280 } 4281 4282 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 4283 { 4284 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 4285 4286 /* Valid physical address? */ 4287 if (rax & 0xffff000000000000ULL) 4288 return emulate_gp(ctxt, 0); 4289 4290 return check_svme(ctxt); 4291 } 4292 4293 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 4294 { 4295 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4296 4297 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 4298 return emulate_ud(ctxt); 4299 4300 return X86EMUL_CONTINUE; 4301 } 4302 4303 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 4304 { 4305 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4306 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 4307 4308 /* 4309 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 4310 * in Ring3 when CR4.PCE=0. 4311 */ 4312 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 4313 return X86EMUL_CONTINUE; 4314 4315 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 4316 ctxt->ops->check_pmc(ctxt, rcx)) 4317 return emulate_gp(ctxt, 0); 4318 4319 return X86EMUL_CONTINUE; 4320 } 4321 4322 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4323 { 4324 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4325 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4326 return emulate_gp(ctxt, 0); 4327 4328 return X86EMUL_CONTINUE; 4329 } 4330 4331 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4332 { 4333 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4334 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4335 return emulate_gp(ctxt, 0); 4336 4337 return X86EMUL_CONTINUE; 4338 } 4339 4340 #define D(_y) { .flags = (_y) } 4341 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4342 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4343 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4344 #define N D(NotImpl) 4345 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4346 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4347 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4348 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4349 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4350 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4351 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4352 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4353 #define II(_f, _e, _i) \ 4354 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4355 #define IIP(_f, _e, _i, _p) \ 4356 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4357 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4358 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4359 4360 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4361 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4362 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4363 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4364 #define I2bvIP(_f, _e, _i, _p) \ 4365 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4366 4367 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4368 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4369 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4370 4371 static const struct opcode group7_rm0[] = { 4372 N, 4373 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4374 N, N, N, N, N, N, 4375 }; 4376 4377 static const struct opcode group7_rm1[] = { 4378 DI(SrcNone | Priv, monitor), 4379 DI(SrcNone | Priv, mwait), 4380 N, N, N, N, N, N, 4381 }; 4382 4383 static const struct opcode group7_rm3[] = { 4384 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4385 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4386 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4387 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4388 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4389 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4390 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4391 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4392 }; 4393 4394 static const struct opcode group7_rm7[] = { 4395 N, 4396 DIP(SrcNone, rdtscp, check_rdtsc), 4397 N, N, N, N, N, N, 4398 }; 4399 4400 static const struct opcode group1[] = { 4401 F(Lock, em_add), 4402 F(Lock | PageTable, em_or), 4403 F(Lock, em_adc), 4404 F(Lock, em_sbb), 4405 F(Lock | PageTable, em_and), 4406 F(Lock, em_sub), 4407 F(Lock, em_xor), 4408 F(NoWrite, em_cmp), 4409 }; 4410 4411 static const struct opcode group1A[] = { 4412 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4413 }; 4414 4415 static const struct opcode group2[] = { 4416 F(DstMem | ModRM, em_rol), 4417 F(DstMem | ModRM, em_ror), 4418 F(DstMem | ModRM, em_rcl), 4419 F(DstMem | ModRM, em_rcr), 4420 F(DstMem | ModRM, em_shl), 4421 F(DstMem | ModRM, em_shr), 4422 F(DstMem | ModRM, em_shl), 4423 F(DstMem | ModRM, em_sar), 4424 }; 4425 4426 static const struct opcode group3[] = { 4427 F(DstMem | SrcImm | NoWrite, em_test), 4428 F(DstMem | SrcImm | NoWrite, em_test), 4429 F(DstMem | SrcNone | Lock, em_not), 4430 F(DstMem | SrcNone | Lock, em_neg), 4431 F(DstXacc | Src2Mem, em_mul_ex), 4432 F(DstXacc | Src2Mem, em_imul_ex), 4433 F(DstXacc | Src2Mem, em_div_ex), 4434 F(DstXacc | Src2Mem, em_idiv_ex), 4435 }; 4436 4437 static const struct opcode group4[] = { 4438 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4439 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4440 N, N, N, N, N, N, 4441 }; 4442 4443 static const struct opcode group5[] = { 4444 F(DstMem | SrcNone | Lock, em_inc), 4445 F(DstMem | SrcNone | Lock, em_dec), 4446 I(SrcMem | NearBranch, em_call_near_abs), 4447 I(SrcMemFAddr | ImplicitOps, em_call_far), 4448 I(SrcMem | NearBranch, em_jmp_abs), 4449 I(SrcMemFAddr | ImplicitOps, em_jmp_far), 4450 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4451 }; 4452 4453 static const struct opcode group6[] = { 4454 II(Prot | DstMem, em_sldt, sldt), 4455 II(Prot | DstMem, em_str, str), 4456 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4457 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4458 N, N, N, N, 4459 }; 4460 4461 static const struct group_dual group7 = { { 4462 II(Mov | DstMem, em_sgdt, sgdt), 4463 II(Mov | DstMem, em_sidt, sidt), 4464 II(SrcMem | Priv, em_lgdt, lgdt), 4465 II(SrcMem | Priv, em_lidt, lidt), 4466 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4467 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4468 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4469 }, { 4470 EXT(0, group7_rm0), 4471 EXT(0, group7_rm1), 4472 N, EXT(0, group7_rm3), 4473 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4474 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4475 EXT(0, group7_rm7), 4476 } }; 4477 4478 static const struct opcode group8[] = { 4479 N, N, N, N, 4480 F(DstMem | SrcImmByte | NoWrite, em_bt), 4481 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4482 F(DstMem | SrcImmByte | Lock, em_btr), 4483 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4484 }; 4485 4486 /* 4487 * The "memory" destination is actually always a register, since we come 4488 * from the register case of group9. 4489 */ 4490 static const struct gprefix pfx_0f_c7_7 = { 4491 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp), 4492 }; 4493 4494 4495 static const struct group_dual group9 = { { 4496 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4497 }, { 4498 N, N, N, N, N, N, N, 4499 GP(0, &pfx_0f_c7_7), 4500 } }; 4501 4502 static const struct opcode group11[] = { 4503 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4504 X7(D(Undefined)), 4505 }; 4506 4507 static const struct gprefix pfx_0f_ae_7 = { 4508 I(SrcMem | ByteOp, em_clflush), N, N, N, 4509 }; 4510 4511 static const struct group_dual group15 = { { 4512 I(ModRM | Aligned16, em_fxsave), 4513 I(ModRM | Aligned16, em_fxrstor), 4514 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4515 }, { 4516 N, N, N, N, N, N, N, N, 4517 } }; 4518 4519 static const struct gprefix pfx_0f_6f_0f_7f = { 4520 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4521 }; 4522 4523 static const struct instr_dual instr_dual_0f_2b = { 4524 I(0, em_mov), N 4525 }; 4526 4527 static const struct gprefix pfx_0f_2b = { 4528 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4529 }; 4530 4531 static const struct gprefix pfx_0f_10_0f_11 = { 4532 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4533 }; 4534 4535 static const struct gprefix pfx_0f_28_0f_29 = { 4536 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4537 }; 4538 4539 static const struct gprefix pfx_0f_e7 = { 4540 N, I(Sse, em_mov), N, N, 4541 }; 4542 4543 static const struct escape escape_d9 = { { 4544 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4545 }, { 4546 /* 0xC0 - 0xC7 */ 4547 N, N, N, N, N, N, N, N, 4548 /* 0xC8 - 0xCF */ 4549 N, N, N, N, N, N, N, N, 4550 /* 0xD0 - 0xC7 */ 4551 N, N, N, N, N, N, N, N, 4552 /* 0xD8 - 0xDF */ 4553 N, N, N, N, N, N, N, N, 4554 /* 0xE0 - 0xE7 */ 4555 N, N, N, N, N, N, N, N, 4556 /* 0xE8 - 0xEF */ 4557 N, N, N, N, N, N, N, N, 4558 /* 0xF0 - 0xF7 */ 4559 N, N, N, N, N, N, N, N, 4560 /* 0xF8 - 0xFF */ 4561 N, N, N, N, N, N, N, N, 4562 } }; 4563 4564 static const struct escape escape_db = { { 4565 N, N, N, N, N, N, N, N, 4566 }, { 4567 /* 0xC0 - 0xC7 */ 4568 N, N, N, N, N, N, N, N, 4569 /* 0xC8 - 0xCF */ 4570 N, N, N, N, N, N, N, N, 4571 /* 0xD0 - 0xC7 */ 4572 N, N, N, N, N, N, N, N, 4573 /* 0xD8 - 0xDF */ 4574 N, N, N, N, N, N, N, N, 4575 /* 0xE0 - 0xE7 */ 4576 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4577 /* 0xE8 - 0xEF */ 4578 N, N, N, N, N, N, N, N, 4579 /* 0xF0 - 0xF7 */ 4580 N, N, N, N, N, N, N, N, 4581 /* 0xF8 - 0xFF */ 4582 N, N, N, N, N, N, N, N, 4583 } }; 4584 4585 static const struct escape escape_dd = { { 4586 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4587 }, { 4588 /* 0xC0 - 0xC7 */ 4589 N, N, N, N, N, N, N, N, 4590 /* 0xC8 - 0xCF */ 4591 N, N, N, N, N, N, N, N, 4592 /* 0xD0 - 0xC7 */ 4593 N, N, N, N, N, N, N, N, 4594 /* 0xD8 - 0xDF */ 4595 N, N, N, N, N, N, N, N, 4596 /* 0xE0 - 0xE7 */ 4597 N, N, N, N, N, N, N, N, 4598 /* 0xE8 - 0xEF */ 4599 N, N, N, N, N, N, N, N, 4600 /* 0xF0 - 0xF7 */ 4601 N, N, N, N, N, N, N, N, 4602 /* 0xF8 - 0xFF */ 4603 N, N, N, N, N, N, N, N, 4604 } }; 4605 4606 static const struct instr_dual instr_dual_0f_c3 = { 4607 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4608 }; 4609 4610 static const struct mode_dual mode_dual_63 = { 4611 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4612 }; 4613 4614 static const struct opcode opcode_table[256] = { 4615 /* 0x00 - 0x07 */ 4616 F6ALU(Lock, em_add), 4617 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4618 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4619 /* 0x08 - 0x0F */ 4620 F6ALU(Lock | PageTable, em_or), 4621 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4622 N, 4623 /* 0x10 - 0x17 */ 4624 F6ALU(Lock, em_adc), 4625 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4626 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4627 /* 0x18 - 0x1F */ 4628 F6ALU(Lock, em_sbb), 4629 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4630 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4631 /* 0x20 - 0x27 */ 4632 F6ALU(Lock | PageTable, em_and), N, N, 4633 /* 0x28 - 0x2F */ 4634 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4635 /* 0x30 - 0x37 */ 4636 F6ALU(Lock, em_xor), N, N, 4637 /* 0x38 - 0x3F */ 4638 F6ALU(NoWrite, em_cmp), N, N, 4639 /* 0x40 - 0x4F */ 4640 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4641 /* 0x50 - 0x57 */ 4642 X8(I(SrcReg | Stack, em_push)), 4643 /* 0x58 - 0x5F */ 4644 X8(I(DstReg | Stack, em_pop)), 4645 /* 0x60 - 0x67 */ 4646 I(ImplicitOps | Stack | No64, em_pusha), 4647 I(ImplicitOps | Stack | No64, em_popa), 4648 N, MD(ModRM, &mode_dual_63), 4649 N, N, N, N, 4650 /* 0x68 - 0x6F */ 4651 I(SrcImm | Mov | Stack, em_push), 4652 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4653 I(SrcImmByte | Mov | Stack, em_push), 4654 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4655 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4656 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4657 /* 0x70 - 0x7F */ 4658 X16(D(SrcImmByte | NearBranch)), 4659 /* 0x80 - 0x87 */ 4660 G(ByteOp | DstMem | SrcImm, group1), 4661 G(DstMem | SrcImm, group1), 4662 G(ByteOp | DstMem | SrcImm | No64, group1), 4663 G(DstMem | SrcImmByte, group1), 4664 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4665 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4666 /* 0x88 - 0x8F */ 4667 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4668 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4669 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4670 D(ModRM | SrcMem | NoAccess | DstReg), 4671 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4672 G(0, group1A), 4673 /* 0x90 - 0x97 */ 4674 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4675 /* 0x98 - 0x9F */ 4676 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4677 I(SrcImmFAddr | No64, em_call_far), N, 4678 II(ImplicitOps | Stack, em_pushf, pushf), 4679 II(ImplicitOps | Stack, em_popf, popf), 4680 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4681 /* 0xA0 - 0xA7 */ 4682 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4683 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4684 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4685 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4686 /* 0xA8 - 0xAF */ 4687 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4688 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4689 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4690 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4691 /* 0xB0 - 0xB7 */ 4692 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4693 /* 0xB8 - 0xBF */ 4694 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4695 /* 0xC0 - 0xC7 */ 4696 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4697 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), 4698 I(ImplicitOps | NearBranch, em_ret), 4699 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4700 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4701 G(ByteOp, group11), G(0, group11), 4702 /* 0xC8 - 0xCF */ 4703 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 4704 I(ImplicitOps | SrcImmU16, em_ret_far_imm), 4705 I(ImplicitOps, em_ret_far), 4706 D(ImplicitOps), DI(SrcImmByte, intn), 4707 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 4708 /* 0xD0 - 0xD7 */ 4709 G(Src2One | ByteOp, group2), G(Src2One, group2), 4710 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4711 I(DstAcc | SrcImmUByte | No64, em_aam), 4712 I(DstAcc | SrcImmUByte | No64, em_aad), 4713 F(DstAcc | ByteOp | No64, em_salc), 4714 I(DstAcc | SrcXLat | ByteOp, em_mov), 4715 /* 0xD8 - 0xDF */ 4716 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4717 /* 0xE0 - 0xE7 */ 4718 X3(I(SrcImmByte | NearBranch, em_loop)), 4719 I(SrcImmByte | NearBranch, em_jcxz), 4720 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4721 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4722 /* 0xE8 - 0xEF */ 4723 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), 4724 I(SrcImmFAddr | No64, em_jmp_far), 4725 D(SrcImmByte | ImplicitOps | NearBranch), 4726 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4727 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4728 /* 0xF0 - 0xF7 */ 4729 N, DI(ImplicitOps, icebp), N, N, 4730 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4731 G(ByteOp, group3), G(0, group3), 4732 /* 0xF8 - 0xFF */ 4733 D(ImplicitOps), D(ImplicitOps), 4734 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4735 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4736 }; 4737 4738 static const struct opcode twobyte_table[256] = { 4739 /* 0x00 - 0x0F */ 4740 G(0, group6), GD(0, &group7), N, N, 4741 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4742 II(ImplicitOps | Priv, em_clts, clts), N, 4743 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4744 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4745 /* 0x10 - 0x1F */ 4746 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4747 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4748 N, N, N, N, N, N, 4749 D(ImplicitOps | ModRM | SrcMem | NoAccess), 4750 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), 4751 /* 0x20 - 0x2F */ 4752 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 4753 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4754 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4755 check_cr_write), 4756 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4757 check_dr_write), 4758 N, N, N, N, 4759 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4760 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4761 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4762 N, N, N, N, 4763 /* 0x30 - 0x3F */ 4764 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4765 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4766 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4767 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4768 I(ImplicitOps | EmulateOnUD, em_sysenter), 4769 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 4770 N, N, 4771 N, N, N, N, N, N, N, N, 4772 /* 0x40 - 0x4F */ 4773 X16(D(DstReg | SrcMem | ModRM)), 4774 /* 0x50 - 0x5F */ 4775 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4776 /* 0x60 - 0x6F */ 4777 N, N, N, N, 4778 N, N, N, N, 4779 N, N, N, N, 4780 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4781 /* 0x70 - 0x7F */ 4782 N, N, N, N, 4783 N, N, N, N, 4784 N, N, N, N, 4785 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4786 /* 0x80 - 0x8F */ 4787 X16(D(SrcImm | NearBranch)), 4788 /* 0x90 - 0x9F */ 4789 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4790 /* 0xA0 - 0xA7 */ 4791 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4792 II(ImplicitOps, em_cpuid, cpuid), 4793 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4794 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4795 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4796 /* 0xA8 - 0xAF */ 4797 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4798 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4799 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4800 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4801 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4802 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4803 /* 0xB0 - 0xB7 */ 4804 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4805 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4806 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4807 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4808 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4809 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4810 /* 0xB8 - 0xBF */ 4811 N, N, 4812 G(BitOp, group8), 4813 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4814 I(DstReg | SrcMem | ModRM, em_bsf_c), 4815 I(DstReg | SrcMem | ModRM, em_bsr_c), 4816 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4817 /* 0xC0 - 0xC7 */ 4818 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4819 N, ID(0, &instr_dual_0f_c3), 4820 N, N, N, GD(0, &group9), 4821 /* 0xC8 - 0xCF */ 4822 X8(I(DstReg, em_bswap)), 4823 /* 0xD0 - 0xDF */ 4824 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4825 /* 0xE0 - 0xEF */ 4826 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4827 N, N, N, N, N, N, N, N, 4828 /* 0xF0 - 0xFF */ 4829 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4830 }; 4831 4832 static const struct instr_dual instr_dual_0f_38_f0 = { 4833 I(DstReg | SrcMem | Mov, em_movbe), N 4834 }; 4835 4836 static const struct instr_dual instr_dual_0f_38_f1 = { 4837 I(DstMem | SrcReg | Mov, em_movbe), N 4838 }; 4839 4840 static const struct gprefix three_byte_0f_38_f0 = { 4841 ID(0, &instr_dual_0f_38_f0), N, N, N 4842 }; 4843 4844 static const struct gprefix three_byte_0f_38_f1 = { 4845 ID(0, &instr_dual_0f_38_f1), N, N, N 4846 }; 4847 4848 /* 4849 * Insns below are selected by the prefix which indexed by the third opcode 4850 * byte. 4851 */ 4852 static const struct opcode opcode_map_0f_38[256] = { 4853 /* 0x00 - 0x7f */ 4854 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4855 /* 0x80 - 0xef */ 4856 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4857 /* 0xf0 - 0xf1 */ 4858 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4859 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4860 /* 0xf2 - 0xff */ 4861 N, N, X4(N), X8(N) 4862 }; 4863 4864 #undef D 4865 #undef N 4866 #undef G 4867 #undef GD 4868 #undef I 4869 #undef GP 4870 #undef EXT 4871 #undef MD 4872 #undef ID 4873 4874 #undef D2bv 4875 #undef D2bvIP 4876 #undef I2bv 4877 #undef I2bvIP 4878 #undef I6ALU 4879 4880 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4881 { 4882 unsigned size; 4883 4884 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4885 if (size == 8) 4886 size = 4; 4887 return size; 4888 } 4889 4890 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4891 unsigned size, bool sign_extension) 4892 { 4893 int rc = X86EMUL_CONTINUE; 4894 4895 op->type = OP_IMM; 4896 op->bytes = size; 4897 op->addr.mem.ea = ctxt->_eip; 4898 /* NB. Immediates are sign-extended as necessary. */ 4899 switch (op->bytes) { 4900 case 1: 4901 op->val = insn_fetch(s8, ctxt); 4902 break; 4903 case 2: 4904 op->val = insn_fetch(s16, ctxt); 4905 break; 4906 case 4: 4907 op->val = insn_fetch(s32, ctxt); 4908 break; 4909 case 8: 4910 op->val = insn_fetch(s64, ctxt); 4911 break; 4912 } 4913 if (!sign_extension) { 4914 switch (op->bytes) { 4915 case 1: 4916 op->val &= 0xff; 4917 break; 4918 case 2: 4919 op->val &= 0xffff; 4920 break; 4921 case 4: 4922 op->val &= 0xffffffff; 4923 break; 4924 } 4925 } 4926 done: 4927 return rc; 4928 } 4929 4930 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4931 unsigned d) 4932 { 4933 int rc = X86EMUL_CONTINUE; 4934 4935 switch (d) { 4936 case OpReg: 4937 decode_register_operand(ctxt, op); 4938 break; 4939 case OpImmUByte: 4940 rc = decode_imm(ctxt, op, 1, false); 4941 break; 4942 case OpMem: 4943 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4944 mem_common: 4945 *op = ctxt->memop; 4946 ctxt->memopp = op; 4947 if (ctxt->d & BitOp) 4948 fetch_bit_operand(ctxt); 4949 op->orig_val = op->val; 4950 break; 4951 case OpMem64: 4952 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4953 goto mem_common; 4954 case OpAcc: 4955 op->type = OP_REG; 4956 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4957 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4958 fetch_register_operand(op); 4959 op->orig_val = op->val; 4960 break; 4961 case OpAccLo: 4962 op->type = OP_REG; 4963 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4964 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4965 fetch_register_operand(op); 4966 op->orig_val = op->val; 4967 break; 4968 case OpAccHi: 4969 if (ctxt->d & ByteOp) { 4970 op->type = OP_NONE; 4971 break; 4972 } 4973 op->type = OP_REG; 4974 op->bytes = ctxt->op_bytes; 4975 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4976 fetch_register_operand(op); 4977 op->orig_val = op->val; 4978 break; 4979 case OpDI: 4980 op->type = OP_MEM; 4981 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4982 op->addr.mem.ea = 4983 register_address(ctxt, VCPU_REGS_RDI); 4984 op->addr.mem.seg = VCPU_SREG_ES; 4985 op->val = 0; 4986 op->count = 1; 4987 break; 4988 case OpDX: 4989 op->type = OP_REG; 4990 op->bytes = 2; 4991 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4992 fetch_register_operand(op); 4993 break; 4994 case OpCL: 4995 op->type = OP_IMM; 4996 op->bytes = 1; 4997 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4998 break; 4999 case OpImmByte: 5000 rc = decode_imm(ctxt, op, 1, true); 5001 break; 5002 case OpOne: 5003 op->type = OP_IMM; 5004 op->bytes = 1; 5005 op->val = 1; 5006 break; 5007 case OpImm: 5008 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 5009 break; 5010 case OpImm64: 5011 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 5012 break; 5013 case OpMem8: 5014 ctxt->memop.bytes = 1; 5015 if (ctxt->memop.type == OP_REG) { 5016 ctxt->memop.addr.reg = decode_register(ctxt, 5017 ctxt->modrm_rm, true); 5018 fetch_register_operand(&ctxt->memop); 5019 } 5020 goto mem_common; 5021 case OpMem16: 5022 ctxt->memop.bytes = 2; 5023 goto mem_common; 5024 case OpMem32: 5025 ctxt->memop.bytes = 4; 5026 goto mem_common; 5027 case OpImmU16: 5028 rc = decode_imm(ctxt, op, 2, false); 5029 break; 5030 case OpImmU: 5031 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 5032 break; 5033 case OpSI: 5034 op->type = OP_MEM; 5035 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5036 op->addr.mem.ea = 5037 register_address(ctxt, VCPU_REGS_RSI); 5038 op->addr.mem.seg = ctxt->seg_override; 5039 op->val = 0; 5040 op->count = 1; 5041 break; 5042 case OpXLat: 5043 op->type = OP_MEM; 5044 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5045 op->addr.mem.ea = 5046 address_mask(ctxt, 5047 reg_read(ctxt, VCPU_REGS_RBX) + 5048 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 5049 op->addr.mem.seg = ctxt->seg_override; 5050 op->val = 0; 5051 break; 5052 case OpImmFAddr: 5053 op->type = OP_IMM; 5054 op->addr.mem.ea = ctxt->_eip; 5055 op->bytes = ctxt->op_bytes + 2; 5056 insn_fetch_arr(op->valptr, op->bytes, ctxt); 5057 break; 5058 case OpMemFAddr: 5059 ctxt->memop.bytes = ctxt->op_bytes + 2; 5060 goto mem_common; 5061 case OpES: 5062 op->type = OP_IMM; 5063 op->val = VCPU_SREG_ES; 5064 break; 5065 case OpCS: 5066 op->type = OP_IMM; 5067 op->val = VCPU_SREG_CS; 5068 break; 5069 case OpSS: 5070 op->type = OP_IMM; 5071 op->val = VCPU_SREG_SS; 5072 break; 5073 case OpDS: 5074 op->type = OP_IMM; 5075 op->val = VCPU_SREG_DS; 5076 break; 5077 case OpFS: 5078 op->type = OP_IMM; 5079 op->val = VCPU_SREG_FS; 5080 break; 5081 case OpGS: 5082 op->type = OP_IMM; 5083 op->val = VCPU_SREG_GS; 5084 break; 5085 case OpImplicit: 5086 /* Special instructions do their own operand decoding. */ 5087 default: 5088 op->type = OP_NONE; /* Disable writeback. */ 5089 break; 5090 } 5091 5092 done: 5093 return rc; 5094 } 5095 5096 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 5097 { 5098 int rc = X86EMUL_CONTINUE; 5099 int mode = ctxt->mode; 5100 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 5101 bool op_prefix = false; 5102 bool has_seg_override = false; 5103 struct opcode opcode; 5104 u16 dummy; 5105 struct desc_struct desc; 5106 5107 ctxt->memop.type = OP_NONE; 5108 ctxt->memopp = NULL; 5109 ctxt->_eip = ctxt->eip; 5110 ctxt->fetch.ptr = ctxt->fetch.data; 5111 ctxt->fetch.end = ctxt->fetch.data + insn_len; 5112 ctxt->opcode_len = 1; 5113 if (insn_len > 0) 5114 memcpy(ctxt->fetch.data, insn, insn_len); 5115 else { 5116 rc = __do_insn_fetch_bytes(ctxt, 1); 5117 if (rc != X86EMUL_CONTINUE) 5118 return rc; 5119 } 5120 5121 switch (mode) { 5122 case X86EMUL_MODE_REAL: 5123 case X86EMUL_MODE_VM86: 5124 def_op_bytes = def_ad_bytes = 2; 5125 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 5126 if (desc.d) 5127 def_op_bytes = def_ad_bytes = 4; 5128 break; 5129 case X86EMUL_MODE_PROT16: 5130 def_op_bytes = def_ad_bytes = 2; 5131 break; 5132 case X86EMUL_MODE_PROT32: 5133 def_op_bytes = def_ad_bytes = 4; 5134 break; 5135 #ifdef CONFIG_X86_64 5136 case X86EMUL_MODE_PROT64: 5137 def_op_bytes = 4; 5138 def_ad_bytes = 8; 5139 break; 5140 #endif 5141 default: 5142 return EMULATION_FAILED; 5143 } 5144 5145 ctxt->op_bytes = def_op_bytes; 5146 ctxt->ad_bytes = def_ad_bytes; 5147 5148 /* Legacy prefixes. */ 5149 for (;;) { 5150 switch (ctxt->b = insn_fetch(u8, ctxt)) { 5151 case 0x66: /* operand-size override */ 5152 op_prefix = true; 5153 /* switch between 2/4 bytes */ 5154 ctxt->op_bytes = def_op_bytes ^ 6; 5155 break; 5156 case 0x67: /* address-size override */ 5157 if (mode == X86EMUL_MODE_PROT64) 5158 /* switch between 4/8 bytes */ 5159 ctxt->ad_bytes = def_ad_bytes ^ 12; 5160 else 5161 /* switch between 2/4 bytes */ 5162 ctxt->ad_bytes = def_ad_bytes ^ 6; 5163 break; 5164 case 0x26: /* ES override */ 5165 case 0x2e: /* CS override */ 5166 case 0x36: /* SS override */ 5167 case 0x3e: /* DS override */ 5168 has_seg_override = true; 5169 ctxt->seg_override = (ctxt->b >> 3) & 3; 5170 break; 5171 case 0x64: /* FS override */ 5172 case 0x65: /* GS override */ 5173 has_seg_override = true; 5174 ctxt->seg_override = ctxt->b & 7; 5175 break; 5176 case 0x40 ... 0x4f: /* REX */ 5177 if (mode != X86EMUL_MODE_PROT64) 5178 goto done_prefixes; 5179 ctxt->rex_prefix = ctxt->b; 5180 continue; 5181 case 0xf0: /* LOCK */ 5182 ctxt->lock_prefix = 1; 5183 break; 5184 case 0xf2: /* REPNE/REPNZ */ 5185 case 0xf3: /* REP/REPE/REPZ */ 5186 ctxt->rep_prefix = ctxt->b; 5187 break; 5188 default: 5189 goto done_prefixes; 5190 } 5191 5192 /* Any legacy prefix after a REX prefix nullifies its effect. */ 5193 5194 ctxt->rex_prefix = 0; 5195 } 5196 5197 done_prefixes: 5198 5199 /* REX prefix. */ 5200 if (ctxt->rex_prefix & 8) 5201 ctxt->op_bytes = 8; /* REX.W */ 5202 5203 /* Opcode byte(s). */ 5204 opcode = opcode_table[ctxt->b]; 5205 /* Two-byte opcode? */ 5206 if (ctxt->b == 0x0f) { 5207 ctxt->opcode_len = 2; 5208 ctxt->b = insn_fetch(u8, ctxt); 5209 opcode = twobyte_table[ctxt->b]; 5210 5211 /* 0F_38 opcode map */ 5212 if (ctxt->b == 0x38) { 5213 ctxt->opcode_len = 3; 5214 ctxt->b = insn_fetch(u8, ctxt); 5215 opcode = opcode_map_0f_38[ctxt->b]; 5216 } 5217 } 5218 ctxt->d = opcode.flags; 5219 5220 if (ctxt->d & ModRM) 5221 ctxt->modrm = insn_fetch(u8, ctxt); 5222 5223 /* vex-prefix instructions are not implemented */ 5224 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 5225 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 5226 ctxt->d = NotImpl; 5227 } 5228 5229 while (ctxt->d & GroupMask) { 5230 switch (ctxt->d & GroupMask) { 5231 case Group: 5232 goffset = (ctxt->modrm >> 3) & 7; 5233 opcode = opcode.u.group[goffset]; 5234 break; 5235 case GroupDual: 5236 goffset = (ctxt->modrm >> 3) & 7; 5237 if ((ctxt->modrm >> 6) == 3) 5238 opcode = opcode.u.gdual->mod3[goffset]; 5239 else 5240 opcode = opcode.u.gdual->mod012[goffset]; 5241 break; 5242 case RMExt: 5243 goffset = ctxt->modrm & 7; 5244 opcode = opcode.u.group[goffset]; 5245 break; 5246 case Prefix: 5247 if (ctxt->rep_prefix && op_prefix) 5248 return EMULATION_FAILED; 5249 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 5250 switch (simd_prefix) { 5251 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5252 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5253 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5254 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5255 } 5256 break; 5257 case Escape: 5258 if (ctxt->modrm > 0xbf) 5259 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 5260 else 5261 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5262 break; 5263 case InstrDual: 5264 if ((ctxt->modrm >> 6) == 3) 5265 opcode = opcode.u.idual->mod3; 5266 else 5267 opcode = opcode.u.idual->mod012; 5268 break; 5269 case ModeDual: 5270 if (ctxt->mode == X86EMUL_MODE_PROT64) 5271 opcode = opcode.u.mdual->mode64; 5272 else 5273 opcode = opcode.u.mdual->mode32; 5274 break; 5275 default: 5276 return EMULATION_FAILED; 5277 } 5278 5279 ctxt->d &= ~(u64)GroupMask; 5280 ctxt->d |= opcode.flags; 5281 } 5282 5283 /* Unrecognised? */ 5284 if (ctxt->d == 0) 5285 return EMULATION_FAILED; 5286 5287 ctxt->execute = opcode.u.execute; 5288 5289 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 5290 return EMULATION_FAILED; 5291 5292 if (unlikely(ctxt->d & 5293 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5294 No16))) { 5295 /* 5296 * These are copied unconditionally here, and checked unconditionally 5297 * in x86_emulate_insn. 5298 */ 5299 ctxt->check_perm = opcode.check_perm; 5300 ctxt->intercept = opcode.intercept; 5301 5302 if (ctxt->d & NotImpl) 5303 return EMULATION_FAILED; 5304 5305 if (mode == X86EMUL_MODE_PROT64) { 5306 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5307 ctxt->op_bytes = 8; 5308 else if (ctxt->d & NearBranch) 5309 ctxt->op_bytes = 8; 5310 } 5311 5312 if (ctxt->d & Op3264) { 5313 if (mode == X86EMUL_MODE_PROT64) 5314 ctxt->op_bytes = 8; 5315 else 5316 ctxt->op_bytes = 4; 5317 } 5318 5319 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5320 ctxt->op_bytes = 4; 5321 5322 if (ctxt->d & Sse) 5323 ctxt->op_bytes = 16; 5324 else if (ctxt->d & Mmx) 5325 ctxt->op_bytes = 8; 5326 } 5327 5328 /* ModRM and SIB bytes. */ 5329 if (ctxt->d & ModRM) { 5330 rc = decode_modrm(ctxt, &ctxt->memop); 5331 if (!has_seg_override) { 5332 has_seg_override = true; 5333 ctxt->seg_override = ctxt->modrm_seg; 5334 } 5335 } else if (ctxt->d & MemAbs) 5336 rc = decode_abs(ctxt, &ctxt->memop); 5337 if (rc != X86EMUL_CONTINUE) 5338 goto done; 5339 5340 if (!has_seg_override) 5341 ctxt->seg_override = VCPU_SREG_DS; 5342 5343 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5344 5345 /* 5346 * Decode and fetch the source operand: register, memory 5347 * or immediate. 5348 */ 5349 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5350 if (rc != X86EMUL_CONTINUE) 5351 goto done; 5352 5353 /* 5354 * Decode and fetch the second source operand: register, memory 5355 * or immediate. 5356 */ 5357 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5358 if (rc != X86EMUL_CONTINUE) 5359 goto done; 5360 5361 /* Decode and fetch the destination operand: register or memory. */ 5362 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5363 5364 if (ctxt->rip_relative && likely(ctxt->memopp)) 5365 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5366 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5367 5368 done: 5369 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5370 } 5371 5372 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5373 { 5374 return ctxt->d & PageTable; 5375 } 5376 5377 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5378 { 5379 /* The second termination condition only applies for REPE 5380 * and REPNE. Test if the repeat string operation prefix is 5381 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5382 * corresponding termination condition according to: 5383 * - if REPE/REPZ and ZF = 0 then done 5384 * - if REPNE/REPNZ and ZF = 1 then done 5385 */ 5386 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5387 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5388 && (((ctxt->rep_prefix == REPE_PREFIX) && 5389 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5390 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5391 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5392 return true; 5393 5394 return false; 5395 } 5396 5397 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5398 { 5399 int rc; 5400 5401 rc = asm_safe("fwait"); 5402 5403 if (unlikely(rc != X86EMUL_CONTINUE)) 5404 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5405 5406 return X86EMUL_CONTINUE; 5407 } 5408 5409 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 5410 struct operand *op) 5411 { 5412 if (op->type == OP_MM) 5413 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 5414 } 5415 5416 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 5417 { 5418 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5419 5420 if (!(ctxt->d & ByteOp)) 5421 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5422 5423 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5424 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5425 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5426 : "c"(ctxt->src2.val)); 5427 5428 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5429 if (!fop) /* exception is returned in fop variable */ 5430 return emulate_de(ctxt); 5431 return X86EMUL_CONTINUE; 5432 } 5433 5434 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5435 { 5436 memset(&ctxt->rip_relative, 0, 5437 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 5438 5439 ctxt->io_read.pos = 0; 5440 ctxt->io_read.end = 0; 5441 ctxt->mem_read.end = 0; 5442 } 5443 5444 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5445 { 5446 const struct x86_emulate_ops *ops = ctxt->ops; 5447 int rc = X86EMUL_CONTINUE; 5448 int saved_dst_type = ctxt->dst.type; 5449 unsigned emul_flags; 5450 5451 ctxt->mem_read.pos = 0; 5452 5453 /* LOCK prefix is allowed only with some instructions */ 5454 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5455 rc = emulate_ud(ctxt); 5456 goto done; 5457 } 5458 5459 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5460 rc = emulate_ud(ctxt); 5461 goto done; 5462 } 5463 5464 emul_flags = ctxt->ops->get_hflags(ctxt); 5465 if (unlikely(ctxt->d & 5466 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5467 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5468 (ctxt->d & Undefined)) { 5469 rc = emulate_ud(ctxt); 5470 goto done; 5471 } 5472 5473 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5474 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5475 rc = emulate_ud(ctxt); 5476 goto done; 5477 } 5478 5479 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5480 rc = emulate_nm(ctxt); 5481 goto done; 5482 } 5483 5484 if (ctxt->d & Mmx) { 5485 rc = flush_pending_x87_faults(ctxt); 5486 if (rc != X86EMUL_CONTINUE) 5487 goto done; 5488 /* 5489 * Now that we know the fpu is exception safe, we can fetch 5490 * operands from it. 5491 */ 5492 fetch_possible_mmx_operand(ctxt, &ctxt->src); 5493 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 5494 if (!(ctxt->d & Mov)) 5495 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 5496 } 5497 5498 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5499 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5500 X86_ICPT_PRE_EXCEPT); 5501 if (rc != X86EMUL_CONTINUE) 5502 goto done; 5503 } 5504 5505 /* Instruction can only be executed in protected mode */ 5506 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5507 rc = emulate_ud(ctxt); 5508 goto done; 5509 } 5510 5511 /* Privileged instruction can be executed only in CPL=0 */ 5512 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5513 if (ctxt->d & PrivUD) 5514 rc = emulate_ud(ctxt); 5515 else 5516 rc = emulate_gp(ctxt, 0); 5517 goto done; 5518 } 5519 5520 /* Do instruction specific permission checks */ 5521 if (ctxt->d & CheckPerm) { 5522 rc = ctxt->check_perm(ctxt); 5523 if (rc != X86EMUL_CONTINUE) 5524 goto done; 5525 } 5526 5527 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5528 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5529 X86_ICPT_POST_EXCEPT); 5530 if (rc != X86EMUL_CONTINUE) 5531 goto done; 5532 } 5533 5534 if (ctxt->rep_prefix && (ctxt->d & String)) { 5535 /* All REP prefixes have the same first termination condition */ 5536 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5537 string_registers_quirk(ctxt); 5538 ctxt->eip = ctxt->_eip; 5539 ctxt->eflags &= ~X86_EFLAGS_RF; 5540 goto done; 5541 } 5542 } 5543 } 5544 5545 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5546 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5547 ctxt->src.valptr, ctxt->src.bytes); 5548 if (rc != X86EMUL_CONTINUE) 5549 goto done; 5550 ctxt->src.orig_val64 = ctxt->src.val64; 5551 } 5552 5553 if (ctxt->src2.type == OP_MEM) { 5554 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5555 &ctxt->src2.val, ctxt->src2.bytes); 5556 if (rc != X86EMUL_CONTINUE) 5557 goto done; 5558 } 5559 5560 if ((ctxt->d & DstMask) == ImplicitOps) 5561 goto special_insn; 5562 5563 5564 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5565 /* optimisation - avoid slow emulated read if Mov */ 5566 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5567 &ctxt->dst.val, ctxt->dst.bytes); 5568 if (rc != X86EMUL_CONTINUE) { 5569 if (!(ctxt->d & NoWrite) && 5570 rc == X86EMUL_PROPAGATE_FAULT && 5571 ctxt->exception.vector == PF_VECTOR) 5572 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5573 goto done; 5574 } 5575 } 5576 /* Copy full 64-bit value for CMPXCHG8B. */ 5577 ctxt->dst.orig_val64 = ctxt->dst.val64; 5578 5579 special_insn: 5580 5581 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5582 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5583 X86_ICPT_POST_MEMACCESS); 5584 if (rc != X86EMUL_CONTINUE) 5585 goto done; 5586 } 5587 5588 if (ctxt->rep_prefix && (ctxt->d & String)) 5589 ctxt->eflags |= X86_EFLAGS_RF; 5590 else 5591 ctxt->eflags &= ~X86_EFLAGS_RF; 5592 5593 if (ctxt->execute) { 5594 if (ctxt->d & Fastop) { 5595 void (*fop)(struct fastop *) = (void *)ctxt->execute; 5596 rc = fastop(ctxt, fop); 5597 if (rc != X86EMUL_CONTINUE) 5598 goto done; 5599 goto writeback; 5600 } 5601 rc = ctxt->execute(ctxt); 5602 if (rc != X86EMUL_CONTINUE) 5603 goto done; 5604 goto writeback; 5605 } 5606 5607 if (ctxt->opcode_len == 2) 5608 goto twobyte_insn; 5609 else if (ctxt->opcode_len == 3) 5610 goto threebyte_insn; 5611 5612 switch (ctxt->b) { 5613 case 0x70 ... 0x7f: /* jcc (short) */ 5614 if (test_cc(ctxt->b, ctxt->eflags)) 5615 rc = jmp_rel(ctxt, ctxt->src.val); 5616 break; 5617 case 0x8d: /* lea r16/r32, m */ 5618 ctxt->dst.val = ctxt->src.addr.mem.ea; 5619 break; 5620 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5621 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5622 ctxt->dst.type = OP_NONE; 5623 else 5624 rc = em_xchg(ctxt); 5625 break; 5626 case 0x98: /* cbw/cwde/cdqe */ 5627 switch (ctxt->op_bytes) { 5628 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5629 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5630 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5631 } 5632 break; 5633 case 0xcc: /* int3 */ 5634 rc = emulate_int(ctxt, 3); 5635 break; 5636 case 0xcd: /* int n */ 5637 rc = emulate_int(ctxt, ctxt->src.val); 5638 break; 5639 case 0xce: /* into */ 5640 if (ctxt->eflags & X86_EFLAGS_OF) 5641 rc = emulate_int(ctxt, 4); 5642 break; 5643 case 0xe9: /* jmp rel */ 5644 case 0xeb: /* jmp rel short */ 5645 rc = jmp_rel(ctxt, ctxt->src.val); 5646 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5647 break; 5648 case 0xf4: /* hlt */ 5649 ctxt->ops->halt(ctxt); 5650 break; 5651 case 0xf5: /* cmc */ 5652 /* complement carry flag from eflags reg */ 5653 ctxt->eflags ^= X86_EFLAGS_CF; 5654 break; 5655 case 0xf8: /* clc */ 5656 ctxt->eflags &= ~X86_EFLAGS_CF; 5657 break; 5658 case 0xf9: /* stc */ 5659 ctxt->eflags |= X86_EFLAGS_CF; 5660 break; 5661 case 0xfc: /* cld */ 5662 ctxt->eflags &= ~X86_EFLAGS_DF; 5663 break; 5664 case 0xfd: /* std */ 5665 ctxt->eflags |= X86_EFLAGS_DF; 5666 break; 5667 default: 5668 goto cannot_emulate; 5669 } 5670 5671 if (rc != X86EMUL_CONTINUE) 5672 goto done; 5673 5674 writeback: 5675 if (ctxt->d & SrcWrite) { 5676 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5677 rc = writeback(ctxt, &ctxt->src); 5678 if (rc != X86EMUL_CONTINUE) 5679 goto done; 5680 } 5681 if (!(ctxt->d & NoWrite)) { 5682 rc = writeback(ctxt, &ctxt->dst); 5683 if (rc != X86EMUL_CONTINUE) 5684 goto done; 5685 } 5686 5687 /* 5688 * restore dst type in case the decoding will be reused 5689 * (happens for string instruction ) 5690 */ 5691 ctxt->dst.type = saved_dst_type; 5692 5693 if ((ctxt->d & SrcMask) == SrcSI) 5694 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5695 5696 if ((ctxt->d & DstMask) == DstDI) 5697 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5698 5699 if (ctxt->rep_prefix && (ctxt->d & String)) { 5700 unsigned int count; 5701 struct read_cache *r = &ctxt->io_read; 5702 if ((ctxt->d & SrcMask) == SrcSI) 5703 count = ctxt->src.count; 5704 else 5705 count = ctxt->dst.count; 5706 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5707 5708 if (!string_insn_completed(ctxt)) { 5709 /* 5710 * Re-enter guest when pio read ahead buffer is empty 5711 * or, if it is not used, after each 1024 iteration. 5712 */ 5713 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5714 (r->end == 0 || r->end != r->pos)) { 5715 /* 5716 * Reset read cache. Usually happens before 5717 * decode, but since instruction is restarted 5718 * we have to do it here. 5719 */ 5720 ctxt->mem_read.end = 0; 5721 writeback_registers(ctxt); 5722 return EMULATION_RESTART; 5723 } 5724 goto done; /* skip rip writeback */ 5725 } 5726 ctxt->eflags &= ~X86_EFLAGS_RF; 5727 } 5728 5729 ctxt->eip = ctxt->_eip; 5730 5731 done: 5732 if (rc == X86EMUL_PROPAGATE_FAULT) { 5733 WARN_ON(ctxt->exception.vector > 0x1f); 5734 ctxt->have_exception = true; 5735 } 5736 if (rc == X86EMUL_INTERCEPTED) 5737 return EMULATION_INTERCEPTED; 5738 5739 if (rc == X86EMUL_CONTINUE) 5740 writeback_registers(ctxt); 5741 5742 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5743 5744 twobyte_insn: 5745 switch (ctxt->b) { 5746 case 0x09: /* wbinvd */ 5747 (ctxt->ops->wbinvd)(ctxt); 5748 break; 5749 case 0x08: /* invd */ 5750 case 0x0d: /* GrpP (prefetch) */ 5751 case 0x18: /* Grp16 (prefetch/nop) */ 5752 case 0x1f: /* nop */ 5753 break; 5754 case 0x20: /* mov cr, reg */ 5755 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5756 break; 5757 case 0x21: /* mov from dr to reg */ 5758 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5759 break; 5760 case 0x40 ... 0x4f: /* cmov */ 5761 if (test_cc(ctxt->b, ctxt->eflags)) 5762 ctxt->dst.val = ctxt->src.val; 5763 else if (ctxt->op_bytes != 4) 5764 ctxt->dst.type = OP_NONE; /* no writeback */ 5765 break; 5766 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5767 if (test_cc(ctxt->b, ctxt->eflags)) 5768 rc = jmp_rel(ctxt, ctxt->src.val); 5769 break; 5770 case 0x90 ... 0x9f: /* setcc r/m8 */ 5771 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5772 break; 5773 case 0xb6 ... 0xb7: /* movzx */ 5774 ctxt->dst.bytes = ctxt->op_bytes; 5775 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5776 : (u16) ctxt->src.val; 5777 break; 5778 case 0xbe ... 0xbf: /* movsx */ 5779 ctxt->dst.bytes = ctxt->op_bytes; 5780 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5781 (s16) ctxt->src.val; 5782 break; 5783 default: 5784 goto cannot_emulate; 5785 } 5786 5787 threebyte_insn: 5788 5789 if (rc != X86EMUL_CONTINUE) 5790 goto done; 5791 5792 goto writeback; 5793 5794 cannot_emulate: 5795 return EMULATION_FAILED; 5796 } 5797 5798 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5799 { 5800 invalidate_registers(ctxt); 5801 } 5802 5803 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5804 { 5805 writeback_registers(ctxt); 5806 } 5807 5808 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5809 { 5810 if (ctxt->rep_prefix && (ctxt->d & String)) 5811 return false; 5812 5813 if (ctxt->d & TwoMemOp) 5814 return false; 5815 5816 return true; 5817 } 5818