1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <linux/pgtable.h> 17#include <asm/segment.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26#include <asm/nospec-branch.h> 27#include <asm/fixmap.h> 28 29/* 30 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 31 * because we need identity-mapped pages. 32 */ 33#define l4_index(x) (((x) >> 39) & 511) 34#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 35 36L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 37L4_START_KERNEL = l4_index(__START_KERNEL_map) 38 39L3_START_KERNEL = pud_index(__START_KERNEL_map) 40 41 .text 42 __HEAD 43 .code64 44SYM_CODE_START_NOALIGN(startup_64) 45 UNWIND_HINT_EMPTY 46 /* 47 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 48 * and someone has loaded an identity mapped page table 49 * for us. These identity mapped page tables map all of the 50 * kernel pages and possibly all of memory. 51 * 52 * %rsi holds a physical pointer to real_mode_data. 53 * 54 * We come here either directly from a 64bit bootloader, or from 55 * arch/x86/boot/compressed/head_64.S. 56 * 57 * We only come here initially at boot nothing else comes here. 58 * 59 * Since we may be loaded at an address different from what we were 60 * compiled to run at we first fixup the physical addresses in our page 61 * tables and then reload them. 62 */ 63 64 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 65 leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp 66 67 leaq _text(%rip), %rdi 68 69 /* 70 * initial_gs points to initial fixed_percpu_data struct with storage for 71 * the stack protector canary. Global pointer fixups are needed at this 72 * stage, so apply them as is done in fixup_pointer(), and initialize %gs 73 * such that the canary can be accessed at %gs:40 for subsequent C calls. 74 */ 75 movl $MSR_GS_BASE, %ecx 76 movq initial_gs(%rip), %rax 77 movq $_text, %rdx 78 subq %rdx, %rax 79 addq %rdi, %rax 80 movq %rax, %rdx 81 shrq $32, %rdx 82 wrmsr 83 84 pushq %rsi 85 call startup_64_setup_env 86 popq %rsi 87 88#ifdef CONFIG_AMD_MEM_ENCRYPT 89 /* 90 * Activate SEV/SME memory encryption if supported/enabled. This needs to 91 * be done now, since this also includes setup of the SEV-SNP CPUID table, 92 * which needs to be done before any CPUID instructions are executed in 93 * subsequent code. 94 */ 95 movq %rsi, %rdi 96 pushq %rsi 97 call sme_enable 98 popq %rsi 99#endif 100 101 /* Now switch to __KERNEL_CS so IRET works reliably */ 102 pushq $__KERNEL_CS 103 leaq .Lon_kernel_cs(%rip), %rax 104 pushq %rax 105 lretq 106 107.Lon_kernel_cs: 108 UNWIND_HINT_EMPTY 109 110 /* Sanitize CPU configuration */ 111 call verify_cpu 112 113 /* 114 * Perform pagetable fixups. Additionally, if SME is active, encrypt 115 * the kernel and retrieve the modifier (SME encryption mask if SME 116 * is active) to be added to the initial pgdir entry that will be 117 * programmed into CR3. 118 */ 119 leaq _text(%rip), %rdi 120 pushq %rsi 121 call __startup_64 122 popq %rsi 123 124 /* Form the CR3 value being sure to include the CR3 modifier */ 125 addq $(early_top_pgt - __START_KERNEL_map), %rax 126 jmp 1f 127SYM_CODE_END(startup_64) 128 129SYM_CODE_START(secondary_startup_64) 130 UNWIND_HINT_EMPTY 131 ANNOTATE_NOENDBR 132 /* 133 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 134 * and someone has loaded a mapped page table. 135 * 136 * %rsi holds a physical pointer to real_mode_data. 137 * 138 * We come here either from startup_64 (using physical addresses) 139 * or from trampoline.S (using virtual addresses). 140 * 141 * Using virtual addresses from trampoline.S removes the need 142 * to have any identity mapped pages in the kernel page table 143 * after the boot processor executes this code. 144 */ 145 146 /* Sanitize CPU configuration */ 147 call verify_cpu 148 149 /* 150 * The secondary_startup_64_no_verify entry point is only used by 151 * SEV-ES guests. In those guests the call to verify_cpu() would cause 152 * #VC exceptions which can not be handled at this stage of secondary 153 * CPU bringup. 154 * 155 * All non SEV-ES systems, especially Intel systems, need to execute 156 * verify_cpu() above to make sure NX is enabled. 157 */ 158SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 159 UNWIND_HINT_EMPTY 160 ANNOTATE_NOENDBR 161 162 /* 163 * Retrieve the modifier (SME encryption mask if SME is active) to be 164 * added to the initial pgdir entry that will be programmed into CR3. 165 */ 166#ifdef CONFIG_AMD_MEM_ENCRYPT 167 movq sme_me_mask, %rax 168#else 169 xorq %rax, %rax 170#endif 171 172 /* Form the CR3 value being sure to include the CR3 modifier */ 173 addq $(init_top_pgt - __START_KERNEL_map), %rax 1741: 175 176 /* Enable PAE mode, PGE and LA57 */ 177 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 178#ifdef CONFIG_X86_5LEVEL 179 testl $1, __pgtable_l5_enabled(%rip) 180 jz 1f 181 orl $X86_CR4_LA57, %ecx 1821: 183#endif 184 movq %rcx, %cr4 185 186 /* Setup early boot stage 4-/5-level pagetables. */ 187 addq phys_base(%rip), %rax 188 189 /* 190 * For SEV guests: Verify that the C-bit is correct. A malicious 191 * hypervisor could lie about the C-bit position to perform a ROP 192 * attack on the guest by writing to the unencrypted stack and wait for 193 * the next RET instruction. 194 * %rsi carries pointer to realmode data and is callee-clobbered. Save 195 * and restore it. 196 */ 197 pushq %rsi 198 movq %rax, %rdi 199 call sev_verify_cbit 200 popq %rsi 201 202 /* 203 * Switch to new page-table 204 * 205 * For the boot CPU this switches to early_top_pgt which still has the 206 * indentity mappings present. The secondary CPUs will switch to the 207 * init_top_pgt here, away from the trampoline_pgd and unmap the 208 * indentity mapped ranges. 209 */ 210 movq %rax, %cr3 211 212 /* 213 * Do a global TLB flush after the CR3 switch to make sure the TLB 214 * entries from the identity mapping are flushed. 215 */ 216 movq %cr4, %rcx 217 movq %rcx, %rax 218 xorq $X86_CR4_PGE, %rcx 219 movq %rcx, %cr4 220 movq %rax, %cr4 221 222 /* Ensure I am executing from virtual addresses */ 223 movq $1f, %rax 224 ANNOTATE_RETPOLINE_SAFE 225 jmp *%rax 2261: 227 UNWIND_HINT_EMPTY 228 ANNOTATE_NOENDBR // above 229 230 /* 231 * We must switch to a new descriptor in kernel space for the GDT 232 * because soon the kernel won't have access anymore to the userspace 233 * addresses where we're currently running on. We have to do that here 234 * because in 32bit we couldn't load a 64bit linear address. 235 */ 236 lgdt early_gdt_descr(%rip) 237 238 /* set up data segments */ 239 xorl %eax,%eax 240 movl %eax,%ds 241 movl %eax,%ss 242 movl %eax,%es 243 244 /* 245 * We don't really need to load %fs or %gs, but load them anyway 246 * to kill any stale realmode selectors. This allows execution 247 * under VT hardware. 248 */ 249 movl %eax,%fs 250 movl %eax,%gs 251 252 /* Set up %gs. 253 * 254 * The base of %gs always points to fixed_percpu_data. If the 255 * stack protector canary is enabled, it is located at %gs:40. 256 * Note that, on SMP, the boot cpu uses init data section until 257 * the per cpu areas are set up. 258 */ 259 movl $MSR_GS_BASE,%ecx 260 movl initial_gs(%rip),%eax 261 movl initial_gs+4(%rip),%edx 262 wrmsr 263 264 /* 265 * Setup a boot time stack - Any secondary CPU will have lost its stack 266 * by now because the cr3-switch above unmaps the real-mode stack 267 */ 268 movq initial_stack(%rip), %rsp 269 270 /* Setup and Load IDT */ 271 pushq %rsi 272 call early_setup_idt 273 popq %rsi 274 275 /* Check if nx is implemented */ 276 movl $0x80000001, %eax 277 cpuid 278 movl %edx,%edi 279 280 /* Setup EFER (Extended Feature Enable Register) */ 281 movl $MSR_EFER, %ecx 282 rdmsr 283 btsl $_EFER_SCE, %eax /* Enable System Call */ 284 btl $20,%edi /* No Execute supported? */ 285 jnc 1f 286 btsl $_EFER_NX, %eax 287 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2881: wrmsr /* Make changes effective */ 289 290 /* Setup cr0 */ 291 movl $CR0_STATE, %eax 292 /* Make changes effective */ 293 movq %rax, %cr0 294 295 /* zero EFLAGS after setting rsp */ 296 pushq $0 297 popfq 298 299 /* rsi is pointer to real mode structure with interesting info. 300 pass it to C */ 301 movq %rsi, %rdi 302 303.Ljump_to_C_code: 304 /* 305 * Jump to run C code and to be on a real kernel address. 306 * Since we are running on identity-mapped space we have to jump 307 * to the full 64bit address, this is only possible as indirect 308 * jump. In addition we need to ensure %cs is set so we make this 309 * a far return. 310 * 311 * Note: do not change to far jump indirect with 64bit offset. 312 * 313 * AMD does not support far jump indirect with 64bit offset. 314 * AMD64 Architecture Programmer's Manual, Volume 3: states only 315 * JMP FAR mem16:16 FF /5 Far jump indirect, 316 * with the target specified by a far pointer in memory. 317 * JMP FAR mem16:32 FF /5 Far jump indirect, 318 * with the target specified by a far pointer in memory. 319 * 320 * Intel64 does support 64bit offset. 321 * Software Developer Manual Vol 2: states: 322 * FF /5 JMP m16:16 Jump far, absolute indirect, 323 * address given in m16:16 324 * FF /5 JMP m16:32 Jump far, absolute indirect, 325 * address given in m16:32. 326 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 327 * address given in m16:64. 328 */ 329 pushq $.Lafter_lret # put return address on stack for unwinder 330 xorl %ebp, %ebp # clear frame pointer 331 movq initial_code(%rip), %rax 332 pushq $__KERNEL_CS # set correct cs 333 pushq %rax # target address in negative space 334 lretq 335.Lafter_lret: 336 ANNOTATE_NOENDBR 337SYM_CODE_END(secondary_startup_64) 338 339#include "verify_cpu.S" 340#include "sev_verify_cbit.S" 341 342#ifdef CONFIG_HOTPLUG_CPU 343/* 344 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 345 * up already except stack. We just set up stack here. Then call 346 * start_secondary() via .Ljump_to_C_code. 347 */ 348SYM_CODE_START(start_cpu0) 349 UNWIND_HINT_EMPTY 350 movq initial_stack(%rip), %rsp 351 jmp .Ljump_to_C_code 352SYM_CODE_END(start_cpu0) 353#endif 354 355#ifdef CONFIG_AMD_MEM_ENCRYPT 356/* 357 * VC Exception handler used during early boot when running on kernel 358 * addresses, but before the switch to the idt_table can be made. 359 * The early_idt_handler_array can't be used here because it calls into a lot 360 * of __init code and this handler is also used during CPU offlining/onlining. 361 * Therefore this handler ends up in the .text section so that it stays around 362 * when .init.text is freed. 363 */ 364SYM_CODE_START_NOALIGN(vc_boot_ghcb) 365 UNWIND_HINT_IRET_REGS offset=8 366 ENDBR 367 368 /* Build pt_regs */ 369 PUSH_AND_CLEAR_REGS 370 371 /* Call C handler */ 372 movq %rsp, %rdi 373 movq ORIG_RAX(%rsp), %rsi 374 movq initial_vc_handler(%rip), %rax 375 ANNOTATE_RETPOLINE_SAFE 376 call *%rax 377 378 /* Unwind pt_regs */ 379 POP_REGS 380 381 /* Remove Error Code */ 382 addq $8, %rsp 383 384 iretq 385SYM_CODE_END(vc_boot_ghcb) 386#endif 387 388 /* Both SMP bootup and ACPI suspend change these variables */ 389 __REFDATA 390 .balign 8 391SYM_DATA(initial_code, .quad x86_64_start_kernel) 392SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 393#ifdef CONFIG_AMD_MEM_ENCRYPT 394SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 395#endif 396 397/* 398 * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder 399 * reliably detect the end of the stack. 400 */ 401SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) 402 __FINITDATA 403 404 __INIT 405SYM_CODE_START(early_idt_handler_array) 406 i = 0 407 .rept NUM_EXCEPTION_VECTORS 408 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 409 UNWIND_HINT_IRET_REGS 410 ENDBR 411 pushq $0 # Dummy error code, to make stack frame uniform 412 .else 413 UNWIND_HINT_IRET_REGS offset=8 414 ENDBR 415 .endif 416 pushq $i # 72(%rsp) Vector number 417 jmp early_idt_handler_common 418 UNWIND_HINT_IRET_REGS 419 i = i + 1 420 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 421 .endr 422SYM_CODE_END(early_idt_handler_array) 423 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 424 425SYM_CODE_START_LOCAL(early_idt_handler_common) 426 UNWIND_HINT_IRET_REGS offset=16 427 /* 428 * The stack is the hardware frame, an error code or zero, and the 429 * vector number. 430 */ 431 cld 432 433 incl early_recursion_flag(%rip) 434 435 /* The vector number is currently in the pt_regs->di slot. */ 436 pushq %rsi /* pt_regs->si */ 437 movq 8(%rsp), %rsi /* RSI = vector number */ 438 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 439 pushq %rdx /* pt_regs->dx */ 440 pushq %rcx /* pt_regs->cx */ 441 pushq %rax /* pt_regs->ax */ 442 pushq %r8 /* pt_regs->r8 */ 443 pushq %r9 /* pt_regs->r9 */ 444 pushq %r10 /* pt_regs->r10 */ 445 pushq %r11 /* pt_regs->r11 */ 446 pushq %rbx /* pt_regs->bx */ 447 pushq %rbp /* pt_regs->bp */ 448 pushq %r12 /* pt_regs->r12 */ 449 pushq %r13 /* pt_regs->r13 */ 450 pushq %r14 /* pt_regs->r14 */ 451 pushq %r15 /* pt_regs->r15 */ 452 UNWIND_HINT_REGS 453 454 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 455 call do_early_exception 456 457 decl early_recursion_flag(%rip) 458 jmp restore_regs_and_return_to_kernel 459SYM_CODE_END(early_idt_handler_common) 460 461#ifdef CONFIG_AMD_MEM_ENCRYPT 462/* 463 * VC Exception handler used during very early boot. The 464 * early_idt_handler_array can't be used because it returns via the 465 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 466 * 467 * XXX it does, fix this. 468 * 469 * This handler will end up in the .init.text section and not be 470 * available to boot secondary CPUs. 471 */ 472SYM_CODE_START_NOALIGN(vc_no_ghcb) 473 UNWIND_HINT_IRET_REGS offset=8 474 ENDBR 475 476 /* Build pt_regs */ 477 PUSH_AND_CLEAR_REGS 478 479 /* Call C handler */ 480 movq %rsp, %rdi 481 movq ORIG_RAX(%rsp), %rsi 482 call do_vc_no_ghcb 483 484 /* Unwind pt_regs */ 485 POP_REGS 486 487 /* Remove Error Code */ 488 addq $8, %rsp 489 490 /* Pure iret required here - don't use INTERRUPT_RETURN */ 491 iretq 492SYM_CODE_END(vc_no_ghcb) 493#endif 494 495#define SYM_DATA_START_PAGE_ALIGNED(name) \ 496 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 497 498#ifdef CONFIG_PAGE_TABLE_ISOLATION 499/* 500 * Each PGD needs to be 8k long and 8k aligned. We do not 501 * ever go out to userspace with these, so we do not 502 * strictly *need* the second page, but this allows us to 503 * have a single set_pgd() implementation that does not 504 * need to worry about whether it has 4k or 8k to work 505 * with. 506 * 507 * This ensures PGDs are 8k long: 508 */ 509#define PTI_USER_PGD_FILL 512 510/* This ensures they are 8k-aligned: */ 511#define SYM_DATA_START_PTI_ALIGNED(name) \ 512 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 513#else 514#define SYM_DATA_START_PTI_ALIGNED(name) \ 515 SYM_DATA_START_PAGE_ALIGNED(name) 516#define PTI_USER_PGD_FILL 0 517#endif 518 519/* Automate the creation of 1 to 1 mapping pmd entries */ 520#define PMDS(START, PERM, COUNT) \ 521 i = 0 ; \ 522 .rept (COUNT) ; \ 523 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 524 i = i + 1 ; \ 525 .endr 526 527 __INITDATA 528 .balign 4 529 530SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 531 .fill 512,8,0 532 .fill PTI_USER_PGD_FILL,8,0 533SYM_DATA_END(early_top_pgt) 534 535SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 536 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 537SYM_DATA_END(early_dynamic_pgts) 538 539SYM_DATA(early_recursion_flag, .long 0) 540 541 .data 542 543#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 544SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 545 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 546 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 547 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 548 .org init_top_pgt + L4_START_KERNEL*8, 0 549 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 550 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 551 .fill PTI_USER_PGD_FILL,8,0 552SYM_DATA_END(init_top_pgt) 553 554SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 555 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 556 .fill 511, 8, 0 557SYM_DATA_END(level3_ident_pgt) 558SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 559 /* 560 * Since I easily can, map the first 1G. 561 * Don't set NX because code runs from these pages. 562 * 563 * Note: This sets _PAGE_GLOBAL despite whether 564 * the CPU supports it or it is enabled. But, 565 * the CPU should ignore the bit. 566 */ 567 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 568SYM_DATA_END(level2_ident_pgt) 569#else 570SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 571 .fill 512,8,0 572 .fill PTI_USER_PGD_FILL,8,0 573SYM_DATA_END(init_top_pgt) 574#endif 575 576#ifdef CONFIG_X86_5LEVEL 577SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 578 .fill 511,8,0 579 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 580SYM_DATA_END(level4_kernel_pgt) 581#endif 582 583SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 584 .fill L3_START_KERNEL,8,0 585 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 586 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 587 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 588SYM_DATA_END(level3_kernel_pgt) 589 590SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 591 /* 592 * Kernel high mapping. 593 * 594 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 595 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 596 * 512 MiB otherwise. 597 * 598 * (NOTE: after that starts the module area, see MODULES_VADDR.) 599 * 600 * This table is eventually used by the kernel during normal runtime. 601 * Care must be taken to clear out undesired bits later, like _PAGE_RW 602 * or _PAGE_GLOBAL in some cases. 603 */ 604 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 605SYM_DATA_END(level2_kernel_pgt) 606 607SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 608 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 609 pgtno = 0 610 .rept (FIXMAP_PMD_NUM) 611 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 612 + _PAGE_TABLE_NOENC; 613 pgtno = pgtno + 1 614 .endr 615 /* 6 MB reserved space + a 2MB hole */ 616 .fill 4,8,0 617SYM_DATA_END(level2_fixmap_pgt) 618 619SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 620 .rept (FIXMAP_PMD_NUM) 621 .fill 512,8,0 622 .endr 623SYM_DATA_END(level1_fixmap_pgt) 624 625#undef PMDS 626 627 .data 628 .align 16 629 630SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 631SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 632 633 .align 16 634/* This must match the first entry in level2_kernel_pgt */ 635SYM_DATA(phys_base, .quad 0x0) 636EXPORT_SYMBOL(phys_base) 637 638#include "../../x86/xen/xen-head.S" 639 640 __PAGE_ALIGNED_BSS 641SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 642 .skip PAGE_SIZE 643SYM_DATA_END(empty_zero_page) 644EXPORT_SYMBOL(empty_zero_page) 645 646