1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <asm/segment.h> 17#include <asm/pgtable.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26 27#ifdef CONFIG_PARAVIRT 28#include <asm/asm-offsets.h> 29#include <asm/paravirt.h> 30#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 31#else 32#define GET_CR2_INTO(reg) movq %cr2, reg 33#define INTERRUPT_RETURN iretq 34#endif 35 36/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 37 * because we need identity-mapped pages. 38 * 39 */ 40 41#define l4_index(x) (((x) >> 39) & 511) 42#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 43 44L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 45L4_START_KERNEL = l4_index(__START_KERNEL_map) 46 47L3_START_KERNEL = pud_index(__START_KERNEL_map) 48 49 .text 50 __HEAD 51 .code64 52 .globl startup_64 53startup_64: 54 UNWIND_HINT_EMPTY 55 /* 56 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 57 * and someone has loaded an identity mapped page table 58 * for us. These identity mapped page tables map all of the 59 * kernel pages and possibly all of memory. 60 * 61 * %rsi holds a physical pointer to real_mode_data. 62 * 63 * We come here either directly from a 64bit bootloader, or from 64 * arch/x86/boot/compressed/head_64.S. 65 * 66 * We only come here initially at boot nothing else comes here. 67 * 68 * Since we may be loaded at an address different from what we were 69 * compiled to run at we first fixup the physical addresses in our page 70 * tables and then reload them. 71 */ 72 73 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 74 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp 75 76 /* Sanitize CPU configuration */ 77 call verify_cpu 78 79 /* 80 * Perform pagetable fixups. Additionally, if SME is active, encrypt 81 * the kernel and retrieve the modifier (SME encryption mask if SME 82 * is active) to be added to the initial pgdir entry that will be 83 * programmed into CR3. 84 */ 85 leaq _text(%rip), %rdi 86 pushq %rsi 87 call __startup_64 88 popq %rsi 89 90 /* Form the CR3 value being sure to include the CR3 modifier */ 91 addq $(early_top_pgt - __START_KERNEL_map), %rax 92 jmp 1f 93ENTRY(secondary_startup_64) 94 UNWIND_HINT_EMPTY 95 /* 96 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 97 * and someone has loaded a mapped page table. 98 * 99 * %rsi holds a physical pointer to real_mode_data. 100 * 101 * We come here either from startup_64 (using physical addresses) 102 * or from trampoline.S (using virtual addresses). 103 * 104 * Using virtual addresses from trampoline.S removes the need 105 * to have any identity mapped pages in the kernel page table 106 * after the boot processor executes this code. 107 */ 108 109 /* Sanitize CPU configuration */ 110 call verify_cpu 111 112 /* 113 * Retrieve the modifier (SME encryption mask if SME is active) to be 114 * added to the initial pgdir entry that will be programmed into CR3. 115 */ 116 pushq %rsi 117 call __startup_secondary_64 118 popq %rsi 119 120 /* Form the CR3 value being sure to include the CR3 modifier */ 121 addq $(init_top_pgt - __START_KERNEL_map), %rax 1221: 123 124 /* Enable PAE mode, PGE and LA57 */ 125 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 126#ifdef CONFIG_X86_5LEVEL 127 testl $1, pgtable_l5_enabled(%rip) 128 jz 1f 129 orl $X86_CR4_LA57, %ecx 1301: 131#endif 132 movq %rcx, %cr4 133 134 /* Setup early boot stage 4-/5-level pagetables. */ 135 addq phys_base(%rip), %rax 136 movq %rax, %cr3 137 138 /* Ensure I am executing from virtual addresses */ 139 movq $1f, %rax 140 jmp *%rax 1411: 142 UNWIND_HINT_EMPTY 143 144 /* Check if nx is implemented */ 145 movl $0x80000001, %eax 146 cpuid 147 movl %edx,%edi 148 149 /* Setup EFER (Extended Feature Enable Register) */ 150 movl $MSR_EFER, %ecx 151 rdmsr 152 btsl $_EFER_SCE, %eax /* Enable System Call */ 153 btl $20,%edi /* No Execute supported? */ 154 jnc 1f 155 btsl $_EFER_NX, %eax 156 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 1571: wrmsr /* Make changes effective */ 158 159 /* Setup cr0 */ 160 movl $CR0_STATE, %eax 161 /* Make changes effective */ 162 movq %rax, %cr0 163 164 /* Setup a boot time stack */ 165 movq initial_stack(%rip), %rsp 166 167 /* zero EFLAGS after setting rsp */ 168 pushq $0 169 popfq 170 171 /* 172 * We must switch to a new descriptor in kernel space for the GDT 173 * because soon the kernel won't have access anymore to the userspace 174 * addresses where we're currently running on. We have to do that here 175 * because in 32bit we couldn't load a 64bit linear address. 176 */ 177 lgdt early_gdt_descr(%rip) 178 179 /* set up data segments */ 180 xorl %eax,%eax 181 movl %eax,%ds 182 movl %eax,%ss 183 movl %eax,%es 184 185 /* 186 * We don't really need to load %fs or %gs, but load them anyway 187 * to kill any stale realmode selectors. This allows execution 188 * under VT hardware. 189 */ 190 movl %eax,%fs 191 movl %eax,%gs 192 193 /* Set up %gs. 194 * 195 * The base of %gs always points to the bottom of the irqstack 196 * union. If the stack protector canary is enabled, it is 197 * located at %gs:40. Note that, on SMP, the boot cpu uses 198 * init data section till per cpu areas are set up. 199 */ 200 movl $MSR_GS_BASE,%ecx 201 movl initial_gs(%rip),%eax 202 movl initial_gs+4(%rip),%edx 203 wrmsr 204 205 /* rsi is pointer to real mode structure with interesting info. 206 pass it to C */ 207 movq %rsi, %rdi 208 209.Ljump_to_C_code: 210 /* 211 * Jump to run C code and to be on a real kernel address. 212 * Since we are running on identity-mapped space we have to jump 213 * to the full 64bit address, this is only possible as indirect 214 * jump. In addition we need to ensure %cs is set so we make this 215 * a far return. 216 * 217 * Note: do not change to far jump indirect with 64bit offset. 218 * 219 * AMD does not support far jump indirect with 64bit offset. 220 * AMD64 Architecture Programmer's Manual, Volume 3: states only 221 * JMP FAR mem16:16 FF /5 Far jump indirect, 222 * with the target specified by a far pointer in memory. 223 * JMP FAR mem16:32 FF /5 Far jump indirect, 224 * with the target specified by a far pointer in memory. 225 * 226 * Intel64 does support 64bit offset. 227 * Software Developer Manual Vol 2: states: 228 * FF /5 JMP m16:16 Jump far, absolute indirect, 229 * address given in m16:16 230 * FF /5 JMP m16:32 Jump far, absolute indirect, 231 * address given in m16:32. 232 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 233 * address given in m16:64. 234 */ 235 pushq $.Lafter_lret # put return address on stack for unwinder 236 xorq %rbp, %rbp # clear frame pointer 237 movq initial_code(%rip), %rax 238 pushq $__KERNEL_CS # set correct cs 239 pushq %rax # target address in negative space 240 lretq 241.Lafter_lret: 242END(secondary_startup_64) 243 244#include "verify_cpu.S" 245 246#ifdef CONFIG_HOTPLUG_CPU 247/* 248 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 249 * up already except stack. We just set up stack here. Then call 250 * start_secondary() via .Ljump_to_C_code. 251 */ 252ENTRY(start_cpu0) 253 movq initial_stack(%rip), %rsp 254 UNWIND_HINT_EMPTY 255 jmp .Ljump_to_C_code 256ENDPROC(start_cpu0) 257#endif 258 259 /* Both SMP bootup and ACPI suspend change these variables */ 260 __REFDATA 261 .balign 8 262 GLOBAL(initial_code) 263 .quad x86_64_start_kernel 264 GLOBAL(initial_gs) 265 .quad INIT_PER_CPU_VAR(irq_stack_union) 266 GLOBAL(initial_stack) 267 /* 268 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel 269 * unwinder reliably detect the end of the stack. 270 */ 271 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS 272 __FINITDATA 273 274 __INIT 275ENTRY(early_idt_handler_array) 276 i = 0 277 .rept NUM_EXCEPTION_VECTORS 278 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 279 UNWIND_HINT_IRET_REGS 280 pushq $0 # Dummy error code, to make stack frame uniform 281 .else 282 UNWIND_HINT_IRET_REGS offset=8 283 .endif 284 pushq $i # 72(%rsp) Vector number 285 jmp early_idt_handler_common 286 UNWIND_HINT_IRET_REGS 287 i = i + 1 288 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 289 .endr 290 UNWIND_HINT_IRET_REGS offset=16 291END(early_idt_handler_array) 292 293early_idt_handler_common: 294 /* 295 * The stack is the hardware frame, an error code or zero, and the 296 * vector number. 297 */ 298 cld 299 300 incl early_recursion_flag(%rip) 301 302 /* The vector number is currently in the pt_regs->di slot. */ 303 pushq %rsi /* pt_regs->si */ 304 movq 8(%rsp), %rsi /* RSI = vector number */ 305 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 306 pushq %rdx /* pt_regs->dx */ 307 pushq %rcx /* pt_regs->cx */ 308 pushq %rax /* pt_regs->ax */ 309 pushq %r8 /* pt_regs->r8 */ 310 pushq %r9 /* pt_regs->r9 */ 311 pushq %r10 /* pt_regs->r10 */ 312 pushq %r11 /* pt_regs->r11 */ 313 pushq %rbx /* pt_regs->bx */ 314 pushq %rbp /* pt_regs->bp */ 315 pushq %r12 /* pt_regs->r12 */ 316 pushq %r13 /* pt_regs->r13 */ 317 pushq %r14 /* pt_regs->r14 */ 318 pushq %r15 /* pt_regs->r15 */ 319 UNWIND_HINT_REGS 320 321 cmpq $14,%rsi /* Page fault? */ 322 jnz 10f 323 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 324 call early_make_pgtable 325 andl %eax,%eax 326 jz 20f /* All good */ 327 32810: 329 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 330 call early_fixup_exception 331 33220: 333 decl early_recursion_flag(%rip) 334 jmp restore_regs_and_return_to_kernel 335END(early_idt_handler_common) 336 337 __INITDATA 338 339 .balign 4 340GLOBAL(early_recursion_flag) 341 .long 0 342 343#define NEXT_PAGE(name) \ 344 .balign PAGE_SIZE; \ 345GLOBAL(name) 346 347#ifdef CONFIG_PAGE_TABLE_ISOLATION 348/* 349 * Each PGD needs to be 8k long and 8k aligned. We do not 350 * ever go out to userspace with these, so we do not 351 * strictly *need* the second page, but this allows us to 352 * have a single set_pgd() implementation that does not 353 * need to worry about whether it has 4k or 8k to work 354 * with. 355 * 356 * This ensures PGDs are 8k long: 357 */ 358#define PTI_USER_PGD_FILL 512 359/* This ensures they are 8k-aligned: */ 360#define NEXT_PGD_PAGE(name) \ 361 .balign 2 * PAGE_SIZE; \ 362GLOBAL(name) 363#else 364#define NEXT_PGD_PAGE(name) NEXT_PAGE(name) 365#define PTI_USER_PGD_FILL 0 366#endif 367 368/* Automate the creation of 1 to 1 mapping pmd entries */ 369#define PMDS(START, PERM, COUNT) \ 370 i = 0 ; \ 371 .rept (COUNT) ; \ 372 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 373 i = i + 1 ; \ 374 .endr 375 376 __INITDATA 377NEXT_PGD_PAGE(early_top_pgt) 378 .fill 512,8,0 379 .fill PTI_USER_PGD_FILL,8,0 380 381NEXT_PAGE(early_dynamic_pgts) 382 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 383 384 .data 385 386#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) 387NEXT_PGD_PAGE(init_top_pgt) 388 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 389 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 390 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 391 .org init_top_pgt + L4_START_KERNEL*8, 0 392 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 393 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 394 .fill PTI_USER_PGD_FILL,8,0 395 396NEXT_PAGE(level3_ident_pgt) 397 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 398 .fill 511, 8, 0 399NEXT_PAGE(level2_ident_pgt) 400 /* Since I easily can, map the first 1G. 401 * Don't set NX because code runs from these pages. 402 */ 403 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 404#else 405NEXT_PGD_PAGE(init_top_pgt) 406 .fill 512,8,0 407 .fill PTI_USER_PGD_FILL,8,0 408#endif 409 410#ifdef CONFIG_X86_5LEVEL 411NEXT_PAGE(level4_kernel_pgt) 412 .fill 511,8,0 413 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 414#endif 415 416NEXT_PAGE(level3_kernel_pgt) 417 .fill L3_START_KERNEL,8,0 418 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 419 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 420 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 421 422NEXT_PAGE(level2_kernel_pgt) 423 /* 424 * 512 MB kernel mapping. We spend a full page on this pagetable 425 * anyway. 426 * 427 * The kernel code+data+bss must not be bigger than that. 428 * 429 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 430 * If you want to increase this then increase MODULES_VADDR 431 * too.) 432 */ 433 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 434 KERNEL_IMAGE_SIZE/PMD_SIZE) 435 436NEXT_PAGE(level2_fixmap_pgt) 437 .fill 506,8,0 438 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 439 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 440 .fill 5,8,0 441 442NEXT_PAGE(level1_fixmap_pgt) 443 .fill 512,8,0 444 445#undef PMDS 446 447 .data 448 .align 16 449 .globl early_gdt_descr 450early_gdt_descr: 451 .word GDT_ENTRIES*8-1 452early_gdt_descr_base: 453 .quad INIT_PER_CPU_VAR(gdt_page) 454 455ENTRY(phys_base) 456 /* This must match the first entry in level2_kernel_pgt */ 457 .quad 0x0000000000000000 458EXPORT_SYMBOL(phys_base) 459 460#include "../../x86/xen/xen-head.S" 461 462 __PAGE_ALIGNED_BSS 463NEXT_PAGE(empty_zero_page) 464 .skip PAGE_SIZE 465EXPORT_SYMBOL(empty_zero_page) 466 467