xref: /openbmc/linux/arch/x86/kernel/head_64.S (revision b8a94bfb) 
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *  linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <linux/pgtable.h>
17#include <asm/segment.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27#include <asm/fixmap.h>
28
29/*
30 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
31 * because we need identity-mapped pages.
32 */
33#define l4_index(x)	(((x) >> 39) & 511)
34#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
35
36L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
37L4_START_KERNEL = l4_index(__START_KERNEL_map)
38
39L3_START_KERNEL = pud_index(__START_KERNEL_map)
40
41	.text
42	__HEAD
43	.code64
44SYM_CODE_START_NOALIGN(startup_64)
45	UNWIND_HINT_EMPTY
46	/*
47	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
48	 * and someone has loaded an identity mapped page table
49	 * for us.  These identity mapped page tables map all of the
50	 * kernel pages and possibly all of memory.
51	 *
52	 * %rsi holds a physical pointer to real_mode_data.
53	 *
54	 * We come here either directly from a 64bit bootloader, or from
55	 * arch/x86/boot/compressed/head_64.S.
56	 *
57	 * We only come here initially at boot nothing else comes here.
58	 *
59	 * Since we may be loaded at an address different from what we were
60	 * compiled to run at we first fixup the physical addresses in our page
61	 * tables and then reload them.
62	 */
63
64	/* Set up the stack for verify_cpu(), similar to initial_stack below */
65	leaq	(__end_init_task - FRAME_SIZE)(%rip), %rsp
66
67	leaq	_text(%rip), %rdi
68
69	/*
70	 * initial_gs points to initial fixed_percpu_data struct with storage for
71	 * the stack protector canary. Global pointer fixups are needed at this
72	 * stage, so apply them as is done in fixup_pointer(), and initialize %gs
73	 * such that the canary can be accessed at %gs:40 for subsequent C calls.
74	 */
75	movl	$MSR_GS_BASE, %ecx
76	movq	initial_gs(%rip), %rax
77	movq	$_text, %rdx
78	subq	%rdx, %rax
79	addq	%rdi, %rax
80	movq	%rax, %rdx
81	shrq	$32,  %rdx
82	wrmsr
83
84	pushq	%rsi
85	call	startup_64_setup_env
86	popq	%rsi
87
88#ifdef CONFIG_AMD_MEM_ENCRYPT
89	/*
90	 * Activate SEV/SME memory encryption if supported/enabled. This needs to
91	 * be done now, since this also includes setup of the SEV-SNP CPUID table,
92	 * which needs to be done before any CPUID instructions are executed in
93	 * subsequent code.
94	 */
95	movq	%rsi, %rdi
96	pushq	%rsi
97	call	sme_enable
98	popq	%rsi
99#endif
100
101	/* Now switch to __KERNEL_CS so IRET works reliably */
102	pushq	$__KERNEL_CS
103	leaq	.Lon_kernel_cs(%rip), %rax
104	pushq	%rax
105	lretq
106
107.Lon_kernel_cs:
108	UNWIND_HINT_EMPTY
109
110	/* Sanitize CPU configuration */
111	call verify_cpu
112
113	/*
114	 * Perform pagetable fixups. Additionally, if SME is active, encrypt
115	 * the kernel and retrieve the modifier (SME encryption mask if SME
116	 * is active) to be added to the initial pgdir entry that will be
117	 * programmed into CR3.
118	 */
119	leaq	_text(%rip), %rdi
120	pushq	%rsi
121	call	__startup_64
122	popq	%rsi
123
124	/* Form the CR3 value being sure to include the CR3 modifier */
125	addq	$(early_top_pgt - __START_KERNEL_map), %rax
126	jmp 1f
127SYM_CODE_END(startup_64)
128
129SYM_CODE_START(secondary_startup_64)
130	UNWIND_HINT_EMPTY
131	ANNOTATE_NOENDBR
132	/*
133	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
134	 * and someone has loaded a mapped page table.
135	 *
136	 * %rsi holds a physical pointer to real_mode_data.
137	 *
138	 * We come here either from startup_64 (using physical addresses)
139	 * or from trampoline.S (using virtual addresses).
140	 *
141	 * Using virtual addresses from trampoline.S removes the need
142	 * to have any identity mapped pages in the kernel page table
143	 * after the boot processor executes this code.
144	 */
145
146	/* Sanitize CPU configuration */
147	call verify_cpu
148
149	/*
150	 * The secondary_startup_64_no_verify entry point is only used by
151	 * SEV-ES guests. In those guests the call to verify_cpu() would cause
152	 * #VC exceptions which can not be handled at this stage of secondary
153	 * CPU bringup.
154	 *
155	 * All non SEV-ES systems, especially Intel systems, need to execute
156	 * verify_cpu() above to make sure NX is enabled.
157	 */
158SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
159	UNWIND_HINT_EMPTY
160	ANNOTATE_NOENDBR
161
162	/*
163	 * Retrieve the modifier (SME encryption mask if SME is active) to be
164	 * added to the initial pgdir entry that will be programmed into CR3.
165	 */
166#ifdef CONFIG_AMD_MEM_ENCRYPT
167	movq	sme_me_mask, %rax
168#else
169	xorq	%rax, %rax
170#endif
171
172	/* Form the CR3 value being sure to include the CR3 modifier */
173	addq	$(init_top_pgt - __START_KERNEL_map), %rax
1741:
175
176#ifdef CONFIG_X86_MCE
177	/*
178	 * Preserve CR4.MCE if the kernel will enable #MC support.
179	 * Clearing MCE may fault in some environments (that also force #MC
180	 * support). Any machine check that occurs before #MC support is fully
181	 * configured will crash the system regardless of the CR4.MCE value set
182	 * here.
183	 */
184	movq	%cr4, %rcx
185	andl	$X86_CR4_MCE, %ecx
186#else
187	movl	$0, %ecx
188#endif
189
190	/* Enable PAE mode, PGE and LA57 */
191	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
192#ifdef CONFIG_X86_5LEVEL
193	testl	$1, __pgtable_l5_enabled(%rip)
194	jz	1f
195	orl	$X86_CR4_LA57, %ecx
1961:
197#endif
198	movq	%rcx, %cr4
199
200	/* Setup early boot stage 4-/5-level pagetables. */
201	addq	phys_base(%rip), %rax
202
203	/*
204	 * For SEV guests: Verify that the C-bit is correct. A malicious
205	 * hypervisor could lie about the C-bit position to perform a ROP
206	 * attack on the guest by writing to the unencrypted stack and wait for
207	 * the next RET instruction.
208	 * %rsi carries pointer to realmode data and is callee-clobbered. Save
209	 * and restore it.
210	 */
211	pushq	%rsi
212	movq	%rax, %rdi
213	call	sev_verify_cbit
214	popq	%rsi
215
216	/*
217	 * Switch to new page-table
218	 *
219	 * For the boot CPU this switches to early_top_pgt which still has the
220	 * indentity mappings present. The secondary CPUs will switch to the
221	 * init_top_pgt here, away from the trampoline_pgd and unmap the
222	 * indentity mapped ranges.
223	 */
224	movq	%rax, %cr3
225
226	/*
227	 * Do a global TLB flush after the CR3 switch to make sure the TLB
228	 * entries from the identity mapping are flushed.
229	 */
230	movq	%cr4, %rcx
231	movq	%rcx, %rax
232	xorq	$X86_CR4_PGE, %rcx
233	movq	%rcx, %cr4
234	movq	%rax, %cr4
235
236	/* Ensure I am executing from virtual addresses */
237	movq	$1f, %rax
238	ANNOTATE_RETPOLINE_SAFE
239	jmp	*%rax
2401:
241	UNWIND_HINT_EMPTY
242	ANNOTATE_NOENDBR // above
243
244	/*
245	 * We must switch to a new descriptor in kernel space for the GDT
246	 * because soon the kernel won't have access anymore to the userspace
247	 * addresses where we're currently running on. We have to do that here
248	 * because in 32bit we couldn't load a 64bit linear address.
249	 */
250	lgdt	early_gdt_descr(%rip)
251
252	/* set up data segments */
253	xorl %eax,%eax
254	movl %eax,%ds
255	movl %eax,%ss
256	movl %eax,%es
257
258	/*
259	 * We don't really need to load %fs or %gs, but load them anyway
260	 * to kill any stale realmode selectors.  This allows execution
261	 * under VT hardware.
262	 */
263	movl %eax,%fs
264	movl %eax,%gs
265
266	/* Set up %gs.
267	 *
268	 * The base of %gs always points to fixed_percpu_data. If the
269	 * stack protector canary is enabled, it is located at %gs:40.
270	 * Note that, on SMP, the boot cpu uses init data section until
271	 * the per cpu areas are set up.
272	 */
273	movl	$MSR_GS_BASE,%ecx
274	movl	initial_gs(%rip),%eax
275	movl	initial_gs+4(%rip),%edx
276	wrmsr
277
278	/*
279	 * Setup a boot time stack - Any secondary CPU will have lost its stack
280	 * by now because the cr3-switch above unmaps the real-mode stack
281	 */
282	movq initial_stack(%rip), %rsp
283
284	/* Setup and Load IDT */
285	pushq	%rsi
286	call	early_setup_idt
287	popq	%rsi
288
289	/* Check if nx is implemented */
290	movl	$0x80000001, %eax
291	cpuid
292	movl	%edx,%edi
293
294	/* Setup EFER (Extended Feature Enable Register) */
295	movl	$MSR_EFER, %ecx
296	rdmsr
297	/*
298	 * Preserve current value of EFER for comparison and to skip
299	 * EFER writes if no change was made (for TDX guest)
300	 */
301	movl    %eax, %edx
302	btsl	$_EFER_SCE, %eax	/* Enable System Call */
303	btl	$20,%edi		/* No Execute supported? */
304	jnc     1f
305	btsl	$_EFER_NX, %eax
306	btsq	$_PAGE_BIT_NX,early_pmd_flags(%rip)
307
308	/* Avoid writing EFER if no change was made (for TDX guest) */
3091:	cmpl	%edx, %eax
310	je	1f
311	xor	%edx, %edx
312	wrmsr				/* Make changes effective */
3131:
314	/* Setup cr0 */
315	movl	$CR0_STATE, %eax
316	/* Make changes effective */
317	movq	%rax, %cr0
318
319	/* zero EFLAGS after setting rsp */
320	pushq $0
321	popfq
322
323	/* rsi is pointer to real mode structure with interesting info.
324	   pass it to C */
325	movq	%rsi, %rdi
326
327.Ljump_to_C_code:
328	/*
329	 * Jump to run C code and to be on a real kernel address.
330	 * Since we are running on identity-mapped space we have to jump
331	 * to the full 64bit address, this is only possible as indirect
332	 * jump.  In addition we need to ensure %cs is set so we make this
333	 * a far return.
334	 *
335	 * Note: do not change to far jump indirect with 64bit offset.
336	 *
337	 * AMD does not support far jump indirect with 64bit offset.
338	 * AMD64 Architecture Programmer's Manual, Volume 3: states only
339	 *	JMP FAR mem16:16 FF /5 Far jump indirect,
340	 *		with the target specified by a far pointer in memory.
341	 *	JMP FAR mem16:32 FF /5 Far jump indirect,
342	 *		with the target specified by a far pointer in memory.
343	 *
344	 * Intel64 does support 64bit offset.
345	 * Software Developer Manual Vol 2: states:
346	 *	FF /5 JMP m16:16 Jump far, absolute indirect,
347	 *		address given in m16:16
348	 *	FF /5 JMP m16:32 Jump far, absolute indirect,
349	 *		address given in m16:32.
350	 *	REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
351	 *		address given in m16:64.
352	 */
353	pushq	$.Lafter_lret	# put return address on stack for unwinder
354	xorl	%ebp, %ebp	# clear frame pointer
355	movq	initial_code(%rip), %rax
356	pushq	$__KERNEL_CS	# set correct cs
357	pushq	%rax		# target address in negative space
358	lretq
359.Lafter_lret:
360	ANNOTATE_NOENDBR
361SYM_CODE_END(secondary_startup_64)
362
363#include "verify_cpu.S"
364#include "sev_verify_cbit.S"
365
366#ifdef CONFIG_HOTPLUG_CPU
367/*
368 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
369 * up already except stack. We just set up stack here. Then call
370 * start_secondary() via .Ljump_to_C_code.
371 */
372SYM_CODE_START(start_cpu0)
373	UNWIND_HINT_EMPTY
374	movq	initial_stack(%rip), %rsp
375	jmp	.Ljump_to_C_code
376SYM_CODE_END(start_cpu0)
377#endif
378
379#ifdef CONFIG_AMD_MEM_ENCRYPT
380/*
381 * VC Exception handler used during early boot when running on kernel
382 * addresses, but before the switch to the idt_table can be made.
383 * The early_idt_handler_array can't be used here because it calls into a lot
384 * of __init code and this handler is also used during CPU offlining/onlining.
385 * Therefore this handler ends up in the .text section so that it stays around
386 * when .init.text is freed.
387 */
388SYM_CODE_START_NOALIGN(vc_boot_ghcb)
389	UNWIND_HINT_IRET_REGS offset=8
390	ENDBR
391
392	ANNOTATE_UNRET_END
393
394	/* Build pt_regs */
395	PUSH_AND_CLEAR_REGS
396
397	/* Call C handler */
398	movq    %rsp, %rdi
399	movq	ORIG_RAX(%rsp), %rsi
400	movq	initial_vc_handler(%rip), %rax
401	ANNOTATE_RETPOLINE_SAFE
402	call	*%rax
403
404	/* Unwind pt_regs */
405	POP_REGS
406
407	/* Remove Error Code */
408	addq    $8, %rsp
409
410	iretq
411SYM_CODE_END(vc_boot_ghcb)
412#endif
413
414	/* Both SMP bootup and ACPI suspend change these variables */
415	__REFDATA
416	.balign	8
417SYM_DATA(initial_code,	.quad x86_64_start_kernel)
418SYM_DATA(initial_gs,	.quad INIT_PER_CPU_VAR(fixed_percpu_data))
419#ifdef CONFIG_AMD_MEM_ENCRYPT
420SYM_DATA(initial_vc_handler,	.quad handle_vc_boot_ghcb)
421#endif
422
423/*
424 * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder
425 * reliably detect the end of the stack.
426 */
427SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE)
428	__FINITDATA
429
430	__INIT
431SYM_CODE_START(early_idt_handler_array)
432	i = 0
433	.rept NUM_EXCEPTION_VECTORS
434	.if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
435		UNWIND_HINT_IRET_REGS
436		ENDBR
437		pushq $0	# Dummy error code, to make stack frame uniform
438	.else
439		UNWIND_HINT_IRET_REGS offset=8
440		ENDBR
441	.endif
442	pushq $i		# 72(%rsp) Vector number
443	jmp early_idt_handler_common
444	UNWIND_HINT_IRET_REGS
445	i = i + 1
446	.fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
447	.endr
448SYM_CODE_END(early_idt_handler_array)
449	ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS]
450
451SYM_CODE_START_LOCAL(early_idt_handler_common)
452	UNWIND_HINT_IRET_REGS offset=16
453	ANNOTATE_UNRET_END
454	/*
455	 * The stack is the hardware frame, an error code or zero, and the
456	 * vector number.
457	 */
458	cld
459
460	incl early_recursion_flag(%rip)
461
462	/* The vector number is currently in the pt_regs->di slot. */
463	pushq %rsi				/* pt_regs->si */
464	movq 8(%rsp), %rsi			/* RSI = vector number */
465	movq %rdi, 8(%rsp)			/* pt_regs->di = RDI */
466	pushq %rdx				/* pt_regs->dx */
467	pushq %rcx				/* pt_regs->cx */
468	pushq %rax				/* pt_regs->ax */
469	pushq %r8				/* pt_regs->r8 */
470	pushq %r9				/* pt_regs->r9 */
471	pushq %r10				/* pt_regs->r10 */
472	pushq %r11				/* pt_regs->r11 */
473	pushq %rbx				/* pt_regs->bx */
474	pushq %rbp				/* pt_regs->bp */
475	pushq %r12				/* pt_regs->r12 */
476	pushq %r13				/* pt_regs->r13 */
477	pushq %r14				/* pt_regs->r14 */
478	pushq %r15				/* pt_regs->r15 */
479	UNWIND_HINT_REGS
480
481	movq %rsp,%rdi		/* RDI = pt_regs; RSI is already trapnr */
482	call do_early_exception
483
484	decl early_recursion_flag(%rip)
485	jmp restore_regs_and_return_to_kernel
486SYM_CODE_END(early_idt_handler_common)
487
488#ifdef CONFIG_AMD_MEM_ENCRYPT
489/*
490 * VC Exception handler used during very early boot. The
491 * early_idt_handler_array can't be used because it returns via the
492 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
493 *
494 * XXX it does, fix this.
495 *
496 * This handler will end up in the .init.text section and not be
497 * available to boot secondary CPUs.
498 */
499SYM_CODE_START_NOALIGN(vc_no_ghcb)
500	UNWIND_HINT_IRET_REGS offset=8
501	ENDBR
502
503	ANNOTATE_UNRET_END
504
505	/* Build pt_regs */
506	PUSH_AND_CLEAR_REGS
507
508	/* Call C handler */
509	movq    %rsp, %rdi
510	movq	ORIG_RAX(%rsp), %rsi
511	call    do_vc_no_ghcb
512
513	/* Unwind pt_regs */
514	POP_REGS
515
516	/* Remove Error Code */
517	addq    $8, %rsp
518
519	/* Pure iret required here - don't use INTERRUPT_RETURN */
520	iretq
521SYM_CODE_END(vc_no_ghcb)
522#endif
523
524#define SYM_DATA_START_PAGE_ALIGNED(name)			\
525	SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
526
527#ifdef CONFIG_PAGE_TABLE_ISOLATION
528/*
529 * Each PGD needs to be 8k long and 8k aligned.  We do not
530 * ever go out to userspace with these, so we do not
531 * strictly *need* the second page, but this allows us to
532 * have a single set_pgd() implementation that does not
533 * need to worry about whether it has 4k or 8k to work
534 * with.
535 *
536 * This ensures PGDs are 8k long:
537 */
538#define PTI_USER_PGD_FILL	512
539/* This ensures they are 8k-aligned: */
540#define SYM_DATA_START_PTI_ALIGNED(name) \
541	SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
542#else
543#define SYM_DATA_START_PTI_ALIGNED(name) \
544	SYM_DATA_START_PAGE_ALIGNED(name)
545#define PTI_USER_PGD_FILL	0
546#endif
547
548/* Automate the creation of 1 to 1 mapping pmd entries */
549#define PMDS(START, PERM, COUNT)			\
550	i = 0 ;						\
551	.rept (COUNT) ;					\
552	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
553	i = i + 1 ;					\
554	.endr
555
556	__INITDATA
557	.balign 4
558
559SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
560	.fill	512,8,0
561	.fill	PTI_USER_PGD_FILL,8,0
562SYM_DATA_END(early_top_pgt)
563
564SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
565	.fill	512*EARLY_DYNAMIC_PAGE_TABLES,8,0
566SYM_DATA_END(early_dynamic_pgts)
567
568SYM_DATA(early_recursion_flag, .long 0)
569
570	.data
571
572#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
573SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
574	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
575	.org    init_top_pgt + L4_PAGE_OFFSET*8, 0
576	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
577	.org    init_top_pgt + L4_START_KERNEL*8, 0
578	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
579	.quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
580	.fill	PTI_USER_PGD_FILL,8,0
581SYM_DATA_END(init_top_pgt)
582
583SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
584	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
585	.fill	511, 8, 0
586SYM_DATA_END(level3_ident_pgt)
587SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
588	/*
589	 * Since I easily can, map the first 1G.
590	 * Don't set NX because code runs from these pages.
591	 *
592	 * Note: This sets _PAGE_GLOBAL despite whether
593	 * the CPU supports it or it is enabled.  But,
594	 * the CPU should ignore the bit.
595	 */
596	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
597SYM_DATA_END(level2_ident_pgt)
598#else
599SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
600	.fill	512,8,0
601	.fill	PTI_USER_PGD_FILL,8,0
602SYM_DATA_END(init_top_pgt)
603#endif
604
605#ifdef CONFIG_X86_5LEVEL
606SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
607	.fill	511,8,0
608	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
609SYM_DATA_END(level4_kernel_pgt)
610#endif
611
612SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
613	.fill	L3_START_KERNEL,8,0
614	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
615	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
616	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
617SYM_DATA_END(level3_kernel_pgt)
618
619SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
620	/*
621	 * Kernel high mapping.
622	 *
623	 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in
624	 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled,
625	 * 512 MiB otherwise.
626	 *
627	 * (NOTE: after that starts the module area, see MODULES_VADDR.)
628	 *
629	 * This table is eventually used by the kernel during normal runtime.
630	 * Care must be taken to clear out undesired bits later, like _PAGE_RW
631	 * or _PAGE_GLOBAL in some cases.
632	 */
633	PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
634SYM_DATA_END(level2_kernel_pgt)
635
636SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
637	.fill	(512 - 4 - FIXMAP_PMD_NUM),8,0
638	pgtno = 0
639	.rept (FIXMAP_PMD_NUM)
640	.quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
641		+ _PAGE_TABLE_NOENC;
642	pgtno = pgtno + 1
643	.endr
644	/* 6 MB reserved space + a 2MB hole */
645	.fill	4,8,0
646SYM_DATA_END(level2_fixmap_pgt)
647
648SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
649	.rept (FIXMAP_PMD_NUM)
650	.fill	512,8,0
651	.endr
652SYM_DATA_END(level1_fixmap_pgt)
653
654#undef PMDS
655
656	.data
657	.align 16
658
659SYM_DATA(early_gdt_descr,		.word GDT_ENTRIES*8-1)
660SYM_DATA_LOCAL(early_gdt_descr_base,	.quad INIT_PER_CPU_VAR(gdt_page))
661
662	.align 16
663/* This must match the first entry in level2_kernel_pgt */
664SYM_DATA(phys_base, .quad 0x0)
665EXPORT_SYMBOL(phys_base)
666
667#include "../../x86/xen/xen-head.S"
668
669	__PAGE_ALIGNED_BSS
670SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
671	.skip PAGE_SIZE
672SYM_DATA_END(empty_zero_page)
673EXPORT_SYMBOL(empty_zero_page)
674
675