1/* 2 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 3 * 4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9 */ 10 11 12#include <linux/linkage.h> 13#include <linux/threads.h> 14#include <linux/init.h> 15#include <asm/segment.h> 16#include <asm/pgtable.h> 17#include <asm/page.h> 18#include <asm/msr.h> 19#include <asm/cache.h> 20#include <asm/processor-flags.h> 21#include <asm/percpu.h> 22#include <asm/nops.h> 23#include "../entry/calling.h" 24 25#ifdef CONFIG_PARAVIRT 26#include <asm/asm-offsets.h> 27#include <asm/paravirt.h> 28#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 29#else 30#define GET_CR2_INTO(reg) movq %cr2, reg 31#define INTERRUPT_RETURN iretq 32#endif 33 34/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 35 * because we need identity-mapped pages. 36 * 37 */ 38 39#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 40 41L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) 42L4_START_KERNEL = pgd_index(__START_KERNEL_map) 43L3_START_KERNEL = pud_index(__START_KERNEL_map) 44 45 .text 46 __HEAD 47 .code64 48 .globl startup_64 49startup_64: 50 /* 51 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 52 * and someone has loaded an identity mapped page table 53 * for us. These identity mapped page tables map all of the 54 * kernel pages and possibly all of memory. 55 * 56 * %rsi holds a physical pointer to real_mode_data. 57 * 58 * We come here either directly from a 64bit bootloader, or from 59 * arch/x86/boot/compressed/head_64.S. 60 * 61 * We only come here initially at boot nothing else comes here. 62 * 63 * Since we may be loaded at an address different from what we were 64 * compiled to run at we first fixup the physical addresses in our page 65 * tables and then reload them. 66 */ 67 68 /* 69 * Setup stack for verify_cpu(). "-8" because initial_stack is defined 70 * this way, see below. Our best guess is a NULL ptr for stack 71 * termination heuristics and we don't want to break anything which 72 * might depend on it (kgdb, ...). 73 */ 74 leaq (__end_init_task - 8)(%rip), %rsp 75 76 /* Sanitize CPU configuration */ 77 call verify_cpu 78 79 /* 80 * Compute the delta between the address I am compiled to run at and the 81 * address I am actually running at. 82 */ 83 leaq _text(%rip), %rbp 84 subq $_text - __START_KERNEL_map, %rbp 85 86 /* Is the address not 2M aligned? */ 87 testl $~PMD_PAGE_MASK, %ebp 88 jnz bad_address 89 90 /* 91 * Is the address too large? 92 */ 93 leaq _text(%rip), %rax 94 shrq $MAX_PHYSMEM_BITS, %rax 95 jnz bad_address 96 97 /* 98 * Fixup the physical addresses in the page table 99 */ 100 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) 101 102 addq %rbp, level3_kernel_pgt + (510*8)(%rip) 103 addq %rbp, level3_kernel_pgt + (511*8)(%rip) 104 105 addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 106 107 /* 108 * Set up the identity mapping for the switchover. These 109 * entries should *NOT* have the global bit set! This also 110 * creates a bunch of nonsense entries but that is fine -- 111 * it avoids problems around wraparound. 112 */ 113 leaq _text(%rip), %rdi 114 leaq early_level4_pgt(%rip), %rbx 115 116 movq %rdi, %rax 117 shrq $PGDIR_SHIFT, %rax 118 119 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx 120 movq %rdx, 0(%rbx,%rax,8) 121 movq %rdx, 8(%rbx,%rax,8) 122 123 addq $4096, %rdx 124 movq %rdi, %rax 125 shrq $PUD_SHIFT, %rax 126 andl $(PTRS_PER_PUD-1), %eax 127 movq %rdx, 4096(%rbx,%rax,8) 128 incl %eax 129 andl $(PTRS_PER_PUD-1), %eax 130 movq %rdx, 4096(%rbx,%rax,8) 131 132 addq $8192, %rbx 133 movq %rdi, %rax 134 shrq $PMD_SHIFT, %rdi 135 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax 136 leaq (_end - 1)(%rip), %rcx 137 shrq $PMD_SHIFT, %rcx 138 subq %rdi, %rcx 139 incl %ecx 140 1411: 142 andq $(PTRS_PER_PMD - 1), %rdi 143 movq %rax, (%rbx,%rdi,8) 144 incq %rdi 145 addq $PMD_SIZE, %rax 146 decl %ecx 147 jnz 1b 148 149 /* 150 * Fixup the kernel text+data virtual addresses. Note that 151 * we might write invalid pmds, when the kernel is relocated 152 * cleanup_highmap() fixes this up along with the mappings 153 * beyond _end. 154 */ 155 leaq level2_kernel_pgt(%rip), %rdi 156 leaq 4096(%rdi), %r8 157 /* See if it is a valid page table entry */ 1581: testb $1, 0(%rdi) 159 jz 2f 160 addq %rbp, 0(%rdi) 161 /* Go to the next page */ 1622: addq $8, %rdi 163 cmp %r8, %rdi 164 jne 1b 165 166 /* Fixup phys_base */ 167 addq %rbp, phys_base(%rip) 168 169 movq $(early_level4_pgt - __START_KERNEL_map), %rax 170 jmp 1f 171ENTRY(secondary_startup_64) 172 /* 173 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 174 * and someone has loaded a mapped page table. 175 * 176 * %rsi holds a physical pointer to real_mode_data. 177 * 178 * We come here either from startup_64 (using physical addresses) 179 * or from trampoline.S (using virtual addresses). 180 * 181 * Using virtual addresses from trampoline.S removes the need 182 * to have any identity mapped pages in the kernel page table 183 * after the boot processor executes this code. 184 */ 185 186 /* Sanitize CPU configuration */ 187 call verify_cpu 188 189 movq $(init_level4_pgt - __START_KERNEL_map), %rax 1901: 191 192 /* Enable PAE mode and PGE */ 193 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 194 movq %rcx, %cr4 195 196 /* Setup early boot stage 4 level pagetables. */ 197 addq phys_base(%rip), %rax 198 movq %rax, %cr3 199 200 /* Ensure I am executing from virtual addresses */ 201 movq $1f, %rax 202 jmp *%rax 2031: 204 205 /* Check if nx is implemented */ 206 movl $0x80000001, %eax 207 cpuid 208 movl %edx,%edi 209 210 /* Setup EFER (Extended Feature Enable Register) */ 211 movl $MSR_EFER, %ecx 212 rdmsr 213 btsl $_EFER_SCE, %eax /* Enable System Call */ 214 btl $20,%edi /* No Execute supported? */ 215 jnc 1f 216 btsl $_EFER_NX, %eax 217 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2181: wrmsr /* Make changes effective */ 219 220 /* Setup cr0 */ 221#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 222 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 223 X86_CR0_PG) 224 movl $CR0_STATE, %eax 225 /* Make changes effective */ 226 movq %rax, %cr0 227 228 /* Setup a boot time stack */ 229 movq initial_stack(%rip), %rsp 230 231 /* zero EFLAGS after setting rsp */ 232 pushq $0 233 popfq 234 235 /* 236 * We must switch to a new descriptor in kernel space for the GDT 237 * because soon the kernel won't have access anymore to the userspace 238 * addresses where we're currently running on. We have to do that here 239 * because in 32bit we couldn't load a 64bit linear address. 240 */ 241 lgdt early_gdt_descr(%rip) 242 243 /* set up data segments */ 244 xorl %eax,%eax 245 movl %eax,%ds 246 movl %eax,%ss 247 movl %eax,%es 248 249 /* 250 * We don't really need to load %fs or %gs, but load them anyway 251 * to kill any stale realmode selectors. This allows execution 252 * under VT hardware. 253 */ 254 movl %eax,%fs 255 movl %eax,%gs 256 257 /* Set up %gs. 258 * 259 * The base of %gs always points to the bottom of the irqstack 260 * union. If the stack protector canary is enabled, it is 261 * located at %gs:40. Note that, on SMP, the boot cpu uses 262 * init data section till per cpu areas are set up. 263 */ 264 movl $MSR_GS_BASE,%ecx 265 movl initial_gs(%rip),%eax 266 movl initial_gs+4(%rip),%edx 267 wrmsr 268 269 /* rsi is pointer to real mode structure with interesting info. 270 pass it to C */ 271 movq %rsi, %rdi 272 273 /* Finally jump to run C code and to be on real kernel address 274 * Since we are running on identity-mapped space we have to jump 275 * to the full 64bit address, this is only possible as indirect 276 * jump. In addition we need to ensure %cs is set so we make this 277 * a far return. 278 * 279 * Note: do not change to far jump indirect with 64bit offset. 280 * 281 * AMD does not support far jump indirect with 64bit offset. 282 * AMD64 Architecture Programmer's Manual, Volume 3: states only 283 * JMP FAR mem16:16 FF /5 Far jump indirect, 284 * with the target specified by a far pointer in memory. 285 * JMP FAR mem16:32 FF /5 Far jump indirect, 286 * with the target specified by a far pointer in memory. 287 * 288 * Intel64 does support 64bit offset. 289 * Software Developer Manual Vol 2: states: 290 * FF /5 JMP m16:16 Jump far, absolute indirect, 291 * address given in m16:16 292 * FF /5 JMP m16:32 Jump far, absolute indirect, 293 * address given in m16:32. 294 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 295 * address given in m16:64. 296 */ 297 movq initial_code(%rip),%rax 298 pushq $0 # fake return address to stop unwinder 299 pushq $__KERNEL_CS # set correct cs 300 pushq %rax # target address in negative space 301 lretq 302ENDPROC(secondary_startup_64) 303 304#include "verify_cpu.S" 305 306#ifdef CONFIG_HOTPLUG_CPU 307/* 308 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 309 * up already except stack. We just set up stack here. Then call 310 * start_secondary(). 311 */ 312ENTRY(start_cpu0) 313 movq initial_stack(%rip),%rsp 314 movq initial_code(%rip),%rax 315 pushq $0 # fake return address to stop unwinder 316 pushq $__KERNEL_CS # set correct cs 317 pushq %rax # target address in negative space 318 lretq 319ENDPROC(start_cpu0) 320#endif 321 322 /* Both SMP bootup and ACPI suspend change these variables */ 323 __REFDATA 324 .balign 8 325 GLOBAL(initial_code) 326 .quad x86_64_start_kernel 327 GLOBAL(initial_gs) 328 .quad INIT_PER_CPU_VAR(irq_stack_union) 329 GLOBAL(initial_stack) 330 .quad init_thread_union+THREAD_SIZE-8 331 __FINITDATA 332 333bad_address: 334 jmp bad_address 335 336 __INIT 337ENTRY(early_idt_handler_array) 338 # 104(%rsp) %rflags 339 # 96(%rsp) %cs 340 # 88(%rsp) %rip 341 # 80(%rsp) error code 342 i = 0 343 .rept NUM_EXCEPTION_VECTORS 344 .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 345 pushq $0 # Dummy error code, to make stack frame uniform 346 .endif 347 pushq $i # 72(%rsp) Vector number 348 jmp early_idt_handler_common 349 i = i + 1 350 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 351 .endr 352ENDPROC(early_idt_handler_array) 353 354early_idt_handler_common: 355 /* 356 * The stack is the hardware frame, an error code or zero, and the 357 * vector number. 358 */ 359 cld 360 361 incl early_recursion_flag(%rip) 362 363 /* The vector number is currently in the pt_regs->di slot. */ 364 pushq %rsi /* pt_regs->si */ 365 movq 8(%rsp), %rsi /* RSI = vector number */ 366 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 367 pushq %rdx /* pt_regs->dx */ 368 pushq %rcx /* pt_regs->cx */ 369 pushq %rax /* pt_regs->ax */ 370 pushq %r8 /* pt_regs->r8 */ 371 pushq %r9 /* pt_regs->r9 */ 372 pushq %r10 /* pt_regs->r10 */ 373 pushq %r11 /* pt_regs->r11 */ 374 pushq %rbx /* pt_regs->bx */ 375 pushq %rbp /* pt_regs->bp */ 376 pushq %r12 /* pt_regs->r12 */ 377 pushq %r13 /* pt_regs->r13 */ 378 pushq %r14 /* pt_regs->r14 */ 379 pushq %r15 /* pt_regs->r15 */ 380 381 cmpq $14,%rsi /* Page fault? */ 382 jnz 10f 383 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 384 call early_make_pgtable 385 andl %eax,%eax 386 jz 20f /* All good */ 387 38810: 389 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 390 call early_fixup_exception 391 39220: 393 decl early_recursion_flag(%rip) 394 jmp restore_regs_and_iret 395ENDPROC(early_idt_handler_common) 396 397 __INITDATA 398 399 .balign 4 400GLOBAL(early_recursion_flag) 401 .long 0 402 403#define NEXT_PAGE(name) \ 404 .balign PAGE_SIZE; \ 405GLOBAL(name) 406 407/* Automate the creation of 1 to 1 mapping pmd entries */ 408#define PMDS(START, PERM, COUNT) \ 409 i = 0 ; \ 410 .rept (COUNT) ; \ 411 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 412 i = i + 1 ; \ 413 .endr 414 415 __INITDATA 416NEXT_PAGE(early_level4_pgt) 417 .fill 511,8,0 418 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 419 420NEXT_PAGE(early_dynamic_pgts) 421 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 422 423 .data 424 425#ifndef CONFIG_XEN 426NEXT_PAGE(init_level4_pgt) 427 .fill 512,8,0 428#else 429NEXT_PAGE(init_level4_pgt) 430 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 431 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 432 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 433 .org init_level4_pgt + L4_START_KERNEL*8, 0 434 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 435 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 436 437NEXT_PAGE(level3_ident_pgt) 438 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 439 .fill 511, 8, 0 440NEXT_PAGE(level2_ident_pgt) 441 /* Since I easily can, map the first 1G. 442 * Don't set NX because code runs from these pages. 443 */ 444 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 445#endif 446 447NEXT_PAGE(level3_kernel_pgt) 448 .fill L3_START_KERNEL,8,0 449 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 450 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 451 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 452 453NEXT_PAGE(level2_kernel_pgt) 454 /* 455 * 512 MB kernel mapping. We spend a full page on this pagetable 456 * anyway. 457 * 458 * The kernel code+data+bss must not be bigger than that. 459 * 460 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 461 * If you want to increase this then increase MODULES_VADDR 462 * too.) 463 */ 464 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 465 KERNEL_IMAGE_SIZE/PMD_SIZE) 466 467NEXT_PAGE(level2_fixmap_pgt) 468 .fill 506,8,0 469 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 470 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 471 .fill 5,8,0 472 473NEXT_PAGE(level1_fixmap_pgt) 474 .fill 512,8,0 475 476#undef PMDS 477 478 .data 479 .align 16 480 .globl early_gdt_descr 481early_gdt_descr: 482 .word GDT_ENTRIES*8-1 483early_gdt_descr_base: 484 .quad INIT_PER_CPU_VAR(gdt_page) 485 486ENTRY(phys_base) 487 /* This must match the first entry in level2_kernel_pgt */ 488 .quad 0x0000000000000000 489 490#include "../../x86/xen/xen-head.S" 491 492 __PAGE_ALIGNED_BSS 493NEXT_PAGE(empty_zero_page) 494 .skip PAGE_SIZE 495 496