1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <linux/pgtable.h> 17#include <asm/segment.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26#include <asm/nospec-branch.h> 27#include <asm/fixmap.h> 28 29/* 30 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 31 * because we need identity-mapped pages. 32 */ 33#define l4_index(x) (((x) >> 39) & 511) 34#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 35 36L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 37L4_START_KERNEL = l4_index(__START_KERNEL_map) 38 39L3_START_KERNEL = pud_index(__START_KERNEL_map) 40 41 .text 42 __HEAD 43 .code64 44SYM_CODE_START_NOALIGN(startup_64) 45 UNWIND_HINT_EMPTY 46 /* 47 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 48 * and someone has loaded an identity mapped page table 49 * for us. These identity mapped page tables map all of the 50 * kernel pages and possibly all of memory. 51 * 52 * %rsi holds a physical pointer to real_mode_data. 53 * 54 * We come here either directly from a 64bit bootloader, or from 55 * arch/x86/boot/compressed/head_64.S. 56 * 57 * We only come here initially at boot nothing else comes here. 58 * 59 * Since we may be loaded at an address different from what we were 60 * compiled to run at we first fixup the physical addresses in our page 61 * tables and then reload them. 62 */ 63 64 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 65 leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp 66 67 leaq _text(%rip), %rdi 68 pushq %rsi 69 call startup_64_setup_env 70 popq %rsi 71 72 /* Now switch to __KERNEL_CS so IRET works reliably */ 73 pushq $__KERNEL_CS 74 leaq .Lon_kernel_cs(%rip), %rax 75 pushq %rax 76 lretq 77 78.Lon_kernel_cs: 79 UNWIND_HINT_EMPTY 80 81 /* Sanitize CPU configuration */ 82 call verify_cpu 83 84 /* 85 * Perform pagetable fixups. Additionally, if SME is active, encrypt 86 * the kernel and retrieve the modifier (SME encryption mask if SME 87 * is active) to be added to the initial pgdir entry that will be 88 * programmed into CR3. 89 */ 90 leaq _text(%rip), %rdi 91 pushq %rsi 92 call __startup_64 93 popq %rsi 94 95 /* Form the CR3 value being sure to include the CR3 modifier */ 96 addq $(early_top_pgt - __START_KERNEL_map), %rax 97 jmp 1f 98SYM_CODE_END(startup_64) 99 100SYM_CODE_START(secondary_startup_64) 101 UNWIND_HINT_EMPTY 102 /* 103 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 104 * and someone has loaded a mapped page table. 105 * 106 * %rsi holds a physical pointer to real_mode_data. 107 * 108 * We come here either from startup_64 (using physical addresses) 109 * or from trampoline.S (using virtual addresses). 110 * 111 * Using virtual addresses from trampoline.S removes the need 112 * to have any identity mapped pages in the kernel page table 113 * after the boot processor executes this code. 114 */ 115 116 /* Sanitize CPU configuration */ 117 call verify_cpu 118 119 /* 120 * The secondary_startup_64_no_verify entry point is only used by 121 * SEV-ES guests. In those guests the call to verify_cpu() would cause 122 * #VC exceptions which can not be handled at this stage of secondary 123 * CPU bringup. 124 * 125 * All non SEV-ES systems, especially Intel systems, need to execute 126 * verify_cpu() above to make sure NX is enabled. 127 */ 128SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 129 UNWIND_HINT_EMPTY 130 131 /* 132 * Retrieve the modifier (SME encryption mask if SME is active) to be 133 * added to the initial pgdir entry that will be programmed into CR3. 134 */ 135 pushq %rsi 136 call __startup_secondary_64 137 popq %rsi 138 139 /* Form the CR3 value being sure to include the CR3 modifier */ 140 addq $(init_top_pgt - __START_KERNEL_map), %rax 1411: 142 143 /* Enable PAE mode, PGE and LA57 */ 144 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 145#ifdef CONFIG_X86_5LEVEL 146 testl $1, __pgtable_l5_enabled(%rip) 147 jz 1f 148 orl $X86_CR4_LA57, %ecx 1491: 150#endif 151 movq %rcx, %cr4 152 153 /* Setup early boot stage 4-/5-level pagetables. */ 154 addq phys_base(%rip), %rax 155 156 /* 157 * For SEV guests: Verify that the C-bit is correct. A malicious 158 * hypervisor could lie about the C-bit position to perform a ROP 159 * attack on the guest by writing to the unencrypted stack and wait for 160 * the next RET instruction. 161 * %rsi carries pointer to realmode data and is callee-clobbered. Save 162 * and restore it. 163 */ 164 pushq %rsi 165 movq %rax, %rdi 166 call sev_verify_cbit 167 popq %rsi 168 169 /* 170 * Switch to new page-table 171 * 172 * For the boot CPU this switches to early_top_pgt which still has the 173 * indentity mappings present. The secondary CPUs will switch to the 174 * init_top_pgt here, away from the trampoline_pgd and unmap the 175 * indentity mapped ranges. 176 */ 177 movq %rax, %cr3 178 179 /* 180 * Do a global TLB flush after the CR3 switch to make sure the TLB 181 * entries from the identity mapping are flushed. 182 */ 183 movq %cr4, %rcx 184 movq %rcx, %rax 185 xorq $X86_CR4_PGE, %rcx 186 movq %rcx, %cr4 187 movq %rax, %cr4 188 189 /* Ensure I am executing from virtual addresses */ 190 movq $1f, %rax 191 ANNOTATE_RETPOLINE_SAFE 192 jmp *%rax 1931: 194 UNWIND_HINT_EMPTY 195 196 /* 197 * We must switch to a new descriptor in kernel space for the GDT 198 * because soon the kernel won't have access anymore to the userspace 199 * addresses where we're currently running on. We have to do that here 200 * because in 32bit we couldn't load a 64bit linear address. 201 */ 202 lgdt early_gdt_descr(%rip) 203 204 /* set up data segments */ 205 xorl %eax,%eax 206 movl %eax,%ds 207 movl %eax,%ss 208 movl %eax,%es 209 210 /* 211 * We don't really need to load %fs or %gs, but load them anyway 212 * to kill any stale realmode selectors. This allows execution 213 * under VT hardware. 214 */ 215 movl %eax,%fs 216 movl %eax,%gs 217 218 /* Set up %gs. 219 * 220 * The base of %gs always points to fixed_percpu_data. If the 221 * stack protector canary is enabled, it is located at %gs:40. 222 * Note that, on SMP, the boot cpu uses init data section until 223 * the per cpu areas are set up. 224 */ 225 movl $MSR_GS_BASE,%ecx 226 movl initial_gs(%rip),%eax 227 movl initial_gs+4(%rip),%edx 228 wrmsr 229 230 /* 231 * Setup a boot time stack - Any secondary CPU will have lost its stack 232 * by now because the cr3-switch above unmaps the real-mode stack 233 */ 234 movq initial_stack(%rip), %rsp 235 236 /* Setup and Load IDT */ 237 pushq %rsi 238 call early_setup_idt 239 popq %rsi 240 241 /* Check if nx is implemented */ 242 movl $0x80000001, %eax 243 cpuid 244 movl %edx,%edi 245 246 /* Setup EFER (Extended Feature Enable Register) */ 247 movl $MSR_EFER, %ecx 248 rdmsr 249 btsl $_EFER_SCE, %eax /* Enable System Call */ 250 btl $20,%edi /* No Execute supported? */ 251 jnc 1f 252 btsl $_EFER_NX, %eax 253 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2541: wrmsr /* Make changes effective */ 255 256 /* Setup cr0 */ 257 movl $CR0_STATE, %eax 258 /* Make changes effective */ 259 movq %rax, %cr0 260 261 /* zero EFLAGS after setting rsp */ 262 pushq $0 263 popfq 264 265 /* rsi is pointer to real mode structure with interesting info. 266 pass it to C */ 267 movq %rsi, %rdi 268 269.Ljump_to_C_code: 270 /* 271 * Jump to run C code and to be on a real kernel address. 272 * Since we are running on identity-mapped space we have to jump 273 * to the full 64bit address, this is only possible as indirect 274 * jump. In addition we need to ensure %cs is set so we make this 275 * a far return. 276 * 277 * Note: do not change to far jump indirect with 64bit offset. 278 * 279 * AMD does not support far jump indirect with 64bit offset. 280 * AMD64 Architecture Programmer's Manual, Volume 3: states only 281 * JMP FAR mem16:16 FF /5 Far jump indirect, 282 * with the target specified by a far pointer in memory. 283 * JMP FAR mem16:32 FF /5 Far jump indirect, 284 * with the target specified by a far pointer in memory. 285 * 286 * Intel64 does support 64bit offset. 287 * Software Developer Manual Vol 2: states: 288 * FF /5 JMP m16:16 Jump far, absolute indirect, 289 * address given in m16:16 290 * FF /5 JMP m16:32 Jump far, absolute indirect, 291 * address given in m16:32. 292 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 293 * address given in m16:64. 294 */ 295 pushq $.Lafter_lret # put return address on stack for unwinder 296 xorl %ebp, %ebp # clear frame pointer 297 movq initial_code(%rip), %rax 298 pushq $__KERNEL_CS # set correct cs 299 pushq %rax # target address in negative space 300 lretq 301.Lafter_lret: 302SYM_CODE_END(secondary_startup_64) 303 304#include "verify_cpu.S" 305#include "sev_verify_cbit.S" 306 307#ifdef CONFIG_HOTPLUG_CPU 308/* 309 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 310 * up already except stack. We just set up stack here. Then call 311 * start_secondary() via .Ljump_to_C_code. 312 */ 313SYM_CODE_START(start_cpu0) 314 UNWIND_HINT_EMPTY 315 movq initial_stack(%rip), %rsp 316 jmp .Ljump_to_C_code 317SYM_CODE_END(start_cpu0) 318#endif 319 320#ifdef CONFIG_AMD_MEM_ENCRYPT 321/* 322 * VC Exception handler used during early boot when running on kernel 323 * addresses, but before the switch to the idt_table can be made. 324 * The early_idt_handler_array can't be used here because it calls into a lot 325 * of __init code and this handler is also used during CPU offlining/onlining. 326 * Therefore this handler ends up in the .text section so that it stays around 327 * when .init.text is freed. 328 */ 329SYM_CODE_START_NOALIGN(vc_boot_ghcb) 330 UNWIND_HINT_IRET_REGS offset=8 331 332 /* Build pt_regs */ 333 PUSH_AND_CLEAR_REGS 334 335 /* Call C handler */ 336 movq %rsp, %rdi 337 movq ORIG_RAX(%rsp), %rsi 338 movq initial_vc_handler(%rip), %rax 339 ANNOTATE_RETPOLINE_SAFE 340 call *%rax 341 342 /* Unwind pt_regs */ 343 POP_REGS 344 345 /* Remove Error Code */ 346 addq $8, %rsp 347 348 iretq 349SYM_CODE_END(vc_boot_ghcb) 350#endif 351 352 /* Both SMP bootup and ACPI suspend change these variables */ 353 __REFDATA 354 .balign 8 355SYM_DATA(initial_code, .quad x86_64_start_kernel) 356SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 357#ifdef CONFIG_AMD_MEM_ENCRYPT 358SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 359#endif 360 361/* 362 * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder 363 * reliably detect the end of the stack. 364 */ 365SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) 366 __FINITDATA 367 368 __INIT 369SYM_CODE_START(early_idt_handler_array) 370 i = 0 371 .rept NUM_EXCEPTION_VECTORS 372 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 373 UNWIND_HINT_IRET_REGS 374 ENDBR 375 pushq $0 # Dummy error code, to make stack frame uniform 376 .else 377 UNWIND_HINT_IRET_REGS offset=8 378 ENDBR 379 .endif 380 pushq $i # 72(%rsp) Vector number 381 jmp early_idt_handler_common 382 UNWIND_HINT_IRET_REGS 383 i = i + 1 384 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 385 .endr 386SYM_CODE_END(early_idt_handler_array) 387 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 388 389SYM_CODE_START_LOCAL(early_idt_handler_common) 390 UNWIND_HINT_IRET_REGS offset=16 391 /* 392 * The stack is the hardware frame, an error code or zero, and the 393 * vector number. 394 */ 395 cld 396 397 incl early_recursion_flag(%rip) 398 399 /* The vector number is currently in the pt_regs->di slot. */ 400 pushq %rsi /* pt_regs->si */ 401 movq 8(%rsp), %rsi /* RSI = vector number */ 402 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 403 pushq %rdx /* pt_regs->dx */ 404 pushq %rcx /* pt_regs->cx */ 405 pushq %rax /* pt_regs->ax */ 406 pushq %r8 /* pt_regs->r8 */ 407 pushq %r9 /* pt_regs->r9 */ 408 pushq %r10 /* pt_regs->r10 */ 409 pushq %r11 /* pt_regs->r11 */ 410 pushq %rbx /* pt_regs->bx */ 411 pushq %rbp /* pt_regs->bp */ 412 pushq %r12 /* pt_regs->r12 */ 413 pushq %r13 /* pt_regs->r13 */ 414 pushq %r14 /* pt_regs->r14 */ 415 pushq %r15 /* pt_regs->r15 */ 416 UNWIND_HINT_REGS 417 418 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 419 call do_early_exception 420 421 decl early_recursion_flag(%rip) 422 jmp restore_regs_and_return_to_kernel 423SYM_CODE_END(early_idt_handler_common) 424 425#ifdef CONFIG_AMD_MEM_ENCRYPT 426/* 427 * VC Exception handler used during very early boot. The 428 * early_idt_handler_array can't be used because it returns via the 429 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 430 * 431 * XXX it does, fix this. 432 * 433 * This handler will end up in the .init.text section and not be 434 * available to boot secondary CPUs. 435 */ 436SYM_CODE_START_NOALIGN(vc_no_ghcb) 437 UNWIND_HINT_IRET_REGS offset=8 438 439 /* Build pt_regs */ 440 PUSH_AND_CLEAR_REGS 441 442 /* Call C handler */ 443 movq %rsp, %rdi 444 movq ORIG_RAX(%rsp), %rsi 445 call do_vc_no_ghcb 446 447 /* Unwind pt_regs */ 448 POP_REGS 449 450 /* Remove Error Code */ 451 addq $8, %rsp 452 453 /* Pure iret required here - don't use INTERRUPT_RETURN */ 454 iretq 455SYM_CODE_END(vc_no_ghcb) 456#endif 457 458#define SYM_DATA_START_PAGE_ALIGNED(name) \ 459 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 460 461#ifdef CONFIG_PAGE_TABLE_ISOLATION 462/* 463 * Each PGD needs to be 8k long and 8k aligned. We do not 464 * ever go out to userspace with these, so we do not 465 * strictly *need* the second page, but this allows us to 466 * have a single set_pgd() implementation that does not 467 * need to worry about whether it has 4k or 8k to work 468 * with. 469 * 470 * This ensures PGDs are 8k long: 471 */ 472#define PTI_USER_PGD_FILL 512 473/* This ensures they are 8k-aligned: */ 474#define SYM_DATA_START_PTI_ALIGNED(name) \ 475 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 476#else 477#define SYM_DATA_START_PTI_ALIGNED(name) \ 478 SYM_DATA_START_PAGE_ALIGNED(name) 479#define PTI_USER_PGD_FILL 0 480#endif 481 482/* Automate the creation of 1 to 1 mapping pmd entries */ 483#define PMDS(START, PERM, COUNT) \ 484 i = 0 ; \ 485 .rept (COUNT) ; \ 486 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 487 i = i + 1 ; \ 488 .endr 489 490 __INITDATA 491 .balign 4 492 493SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 494 .fill 512,8,0 495 .fill PTI_USER_PGD_FILL,8,0 496SYM_DATA_END(early_top_pgt) 497 498SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 499 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 500SYM_DATA_END(early_dynamic_pgts) 501 502SYM_DATA(early_recursion_flag, .long 0) 503 504 .data 505 506#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 507SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 508 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 509 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 510 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 511 .org init_top_pgt + L4_START_KERNEL*8, 0 512 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 513 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 514 .fill PTI_USER_PGD_FILL,8,0 515SYM_DATA_END(init_top_pgt) 516 517SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 518 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 519 .fill 511, 8, 0 520SYM_DATA_END(level3_ident_pgt) 521SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 522 /* 523 * Since I easily can, map the first 1G. 524 * Don't set NX because code runs from these pages. 525 * 526 * Note: This sets _PAGE_GLOBAL despite whether 527 * the CPU supports it or it is enabled. But, 528 * the CPU should ignore the bit. 529 */ 530 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 531SYM_DATA_END(level2_ident_pgt) 532#else 533SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 534 .fill 512,8,0 535 .fill PTI_USER_PGD_FILL,8,0 536SYM_DATA_END(init_top_pgt) 537#endif 538 539#ifdef CONFIG_X86_5LEVEL 540SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 541 .fill 511,8,0 542 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 543SYM_DATA_END(level4_kernel_pgt) 544#endif 545 546SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 547 .fill L3_START_KERNEL,8,0 548 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 549 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 550 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 551SYM_DATA_END(level3_kernel_pgt) 552 553SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 554 /* 555 * Kernel high mapping. 556 * 557 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 558 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 559 * 512 MiB otherwise. 560 * 561 * (NOTE: after that starts the module area, see MODULES_VADDR.) 562 * 563 * This table is eventually used by the kernel during normal runtime. 564 * Care must be taken to clear out undesired bits later, like _PAGE_RW 565 * or _PAGE_GLOBAL in some cases. 566 */ 567 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 568SYM_DATA_END(level2_kernel_pgt) 569 570SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 571 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 572 pgtno = 0 573 .rept (FIXMAP_PMD_NUM) 574 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 575 + _PAGE_TABLE_NOENC; 576 pgtno = pgtno + 1 577 .endr 578 /* 6 MB reserved space + a 2MB hole */ 579 .fill 4,8,0 580SYM_DATA_END(level2_fixmap_pgt) 581 582SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 583 .rept (FIXMAP_PMD_NUM) 584 .fill 512,8,0 585 .endr 586SYM_DATA_END(level1_fixmap_pgt) 587 588#undef PMDS 589 590 .data 591 .align 16 592 593SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 594SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 595 596 .align 16 597/* This must match the first entry in level2_kernel_pgt */ 598SYM_DATA(phys_base, .quad 0x0) 599EXPORT_SYMBOL(phys_base) 600 601#include "../../x86/xen/xen-head.S" 602 603 __PAGE_ALIGNED_BSS 604SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 605 .skip PAGE_SIZE 606SYM_DATA_END(empty_zero_page) 607EXPORT_SYMBOL(empty_zero_page) 608 609