1/* 2 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 3 * 4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9 */ 10 11 12#include <linux/linkage.h> 13#include <linux/threads.h> 14#include <linux/init.h> 15#include <asm/segment.h> 16#include <asm/pgtable.h> 17#include <asm/page.h> 18#include <asm/msr.h> 19#include <asm/cache.h> 20#include <asm/processor-flags.h> 21#include <asm/percpu.h> 22#include <asm/nops.h> 23#include "../entry/calling.h" 24#include <asm/export.h> 25 26#ifdef CONFIG_PARAVIRT 27#include <asm/asm-offsets.h> 28#include <asm/paravirt.h> 29#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 30#else 31#define GET_CR2_INTO(reg) movq %cr2, reg 32#define INTERRUPT_RETURN iretq 33#endif 34 35/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 36 * because we need identity-mapped pages. 37 * 38 */ 39 40#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 41 42L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) 43L4_START_KERNEL = pgd_index(__START_KERNEL_map) 44L3_START_KERNEL = pud_index(__START_KERNEL_map) 45 46 .text 47 __HEAD 48 .code64 49 .globl startup_64 50startup_64: 51 /* 52 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 53 * and someone has loaded an identity mapped page table 54 * for us. These identity mapped page tables map all of the 55 * kernel pages and possibly all of memory. 56 * 57 * %rsi holds a physical pointer to real_mode_data. 58 * 59 * We come here either directly from a 64bit bootloader, or from 60 * arch/x86/boot/compressed/head_64.S. 61 * 62 * We only come here initially at boot nothing else comes here. 63 * 64 * Since we may be loaded at an address different from what we were 65 * compiled to run at we first fixup the physical addresses in our page 66 * tables and then reload them. 67 */ 68 69 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 70 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp 71 72 /* Sanitize CPU configuration */ 73 call verify_cpu 74 75 /* 76 * Compute the delta between the address I am compiled to run at and the 77 * address I am actually running at. 78 */ 79 leaq _text(%rip), %rbp 80 subq $_text - __START_KERNEL_map, %rbp 81 82 /* Is the address not 2M aligned? */ 83 testl $~PMD_PAGE_MASK, %ebp 84 jnz bad_address 85 86 /* 87 * Is the address too large? 88 */ 89 leaq _text(%rip), %rax 90 shrq $MAX_PHYSMEM_BITS, %rax 91 jnz bad_address 92 93 /* 94 * Fixup the physical addresses in the page table 95 */ 96 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) 97 98 addq %rbp, level3_kernel_pgt + (510*8)(%rip) 99 addq %rbp, level3_kernel_pgt + (511*8)(%rip) 100 101 addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 102 103 /* 104 * Set up the identity mapping for the switchover. These 105 * entries should *NOT* have the global bit set! This also 106 * creates a bunch of nonsense entries but that is fine -- 107 * it avoids problems around wraparound. 108 */ 109 leaq _text(%rip), %rdi 110 leaq early_level4_pgt(%rip), %rbx 111 112 movq %rdi, %rax 113 shrq $PGDIR_SHIFT, %rax 114 115 leaq (PAGE_SIZE + _KERNPG_TABLE)(%rbx), %rdx 116 movq %rdx, 0(%rbx,%rax,8) 117 movq %rdx, 8(%rbx,%rax,8) 118 119 addq $PAGE_SIZE, %rdx 120 movq %rdi, %rax 121 shrq $PUD_SHIFT, %rax 122 andl $(PTRS_PER_PUD-1), %eax 123 movq %rdx, PAGE_SIZE(%rbx,%rax,8) 124 incl %eax 125 andl $(PTRS_PER_PUD-1), %eax 126 movq %rdx, PAGE_SIZE(%rbx,%rax,8) 127 128 addq $PAGE_SIZE * 2, %rbx 129 movq %rdi, %rax 130 shrq $PMD_SHIFT, %rdi 131 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax 132 leaq (_end - 1)(%rip), %rcx 133 shrq $PMD_SHIFT, %rcx 134 subq %rdi, %rcx 135 incl %ecx 136 1371: 138 andq $(PTRS_PER_PMD - 1), %rdi 139 movq %rax, (%rbx,%rdi,8) 140 incq %rdi 141 addq $PMD_SIZE, %rax 142 decl %ecx 143 jnz 1b 144 145 test %rbp, %rbp 146 jz .Lskip_fixup 147 148 /* 149 * Fixup the kernel text+data virtual addresses. Note that 150 * we might write invalid pmds, when the kernel is relocated 151 * cleanup_highmap() fixes this up along with the mappings 152 * beyond _end. 153 */ 154 leaq level2_kernel_pgt(%rip), %rdi 155 leaq PAGE_SIZE(%rdi), %r8 156 /* See if it is a valid page table entry */ 1571: testb $_PAGE_PRESENT, 0(%rdi) 158 jz 2f 159 addq %rbp, 0(%rdi) 160 /* Go to the next page */ 1612: addq $8, %rdi 162 cmp %r8, %rdi 163 jne 1b 164 165 /* Fixup phys_base */ 166 addq %rbp, phys_base(%rip) 167 168.Lskip_fixup: 169 movq $(early_level4_pgt - __START_KERNEL_map), %rax 170 jmp 1f 171ENTRY(secondary_startup_64) 172 /* 173 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 174 * and someone has loaded a mapped page table. 175 * 176 * %rsi holds a physical pointer to real_mode_data. 177 * 178 * We come here either from startup_64 (using physical addresses) 179 * or from trampoline.S (using virtual addresses). 180 * 181 * Using virtual addresses from trampoline.S removes the need 182 * to have any identity mapped pages in the kernel page table 183 * after the boot processor executes this code. 184 */ 185 186 /* Sanitize CPU configuration */ 187 call verify_cpu 188 189 movq $(init_level4_pgt - __START_KERNEL_map), %rax 1901: 191 192 /* Enable PAE mode and PGE */ 193 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 194 movq %rcx, %cr4 195 196 /* Setup early boot stage 4 level pagetables. */ 197 addq phys_base(%rip), %rax 198 movq %rax, %cr3 199 200 /* Ensure I am executing from virtual addresses */ 201 movq $1f, %rax 202 jmp *%rax 2031: 204 205 /* Check if nx is implemented */ 206 movl $0x80000001, %eax 207 cpuid 208 movl %edx,%edi 209 210 /* Setup EFER (Extended Feature Enable Register) */ 211 movl $MSR_EFER, %ecx 212 rdmsr 213 btsl $_EFER_SCE, %eax /* Enable System Call */ 214 btl $20,%edi /* No Execute supported? */ 215 jnc 1f 216 btsl $_EFER_NX, %eax 217 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2181: wrmsr /* Make changes effective */ 219 220 /* Setup cr0 */ 221#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 222 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 223 X86_CR0_PG) 224 movl $CR0_STATE, %eax 225 /* Make changes effective */ 226 movq %rax, %cr0 227 228 /* Setup a boot time stack */ 229 movq initial_stack(%rip), %rsp 230 231 /* zero EFLAGS after setting rsp */ 232 pushq $0 233 popfq 234 235 /* 236 * We must switch to a new descriptor in kernel space for the GDT 237 * because soon the kernel won't have access anymore to the userspace 238 * addresses where we're currently running on. We have to do that here 239 * because in 32bit we couldn't load a 64bit linear address. 240 */ 241 lgdt early_gdt_descr(%rip) 242 243 /* set up data segments */ 244 xorl %eax,%eax 245 movl %eax,%ds 246 movl %eax,%ss 247 movl %eax,%es 248 249 /* 250 * We don't really need to load %fs or %gs, but load them anyway 251 * to kill any stale realmode selectors. This allows execution 252 * under VT hardware. 253 */ 254 movl %eax,%fs 255 movl %eax,%gs 256 257 /* Set up %gs. 258 * 259 * The base of %gs always points to the bottom of the irqstack 260 * union. If the stack protector canary is enabled, it is 261 * located at %gs:40. Note that, on SMP, the boot cpu uses 262 * init data section till per cpu areas are set up. 263 */ 264 movl $MSR_GS_BASE,%ecx 265 movl initial_gs(%rip),%eax 266 movl initial_gs+4(%rip),%edx 267 wrmsr 268 269 /* rsi is pointer to real mode structure with interesting info. 270 pass it to C */ 271 movq %rsi, %rdi 272 273.Ljump_to_C_code: 274 /* 275 * Jump to run C code and to be on a real kernel address. 276 * Since we are running on identity-mapped space we have to jump 277 * to the full 64bit address, this is only possible as indirect 278 * jump. In addition we need to ensure %cs is set so we make this 279 * a far return. 280 * 281 * Note: do not change to far jump indirect with 64bit offset. 282 * 283 * AMD does not support far jump indirect with 64bit offset. 284 * AMD64 Architecture Programmer's Manual, Volume 3: states only 285 * JMP FAR mem16:16 FF /5 Far jump indirect, 286 * with the target specified by a far pointer in memory. 287 * JMP FAR mem16:32 FF /5 Far jump indirect, 288 * with the target specified by a far pointer in memory. 289 * 290 * Intel64 does support 64bit offset. 291 * Software Developer Manual Vol 2: states: 292 * FF /5 JMP m16:16 Jump far, absolute indirect, 293 * address given in m16:16 294 * FF /5 JMP m16:32 Jump far, absolute indirect, 295 * address given in m16:32. 296 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 297 * address given in m16:64. 298 */ 299 pushq $.Lafter_lret # put return address on stack for unwinder 300 xorq %rbp, %rbp # clear frame pointer 301 movq initial_code(%rip), %rax 302 pushq $__KERNEL_CS # set correct cs 303 pushq %rax # target address in negative space 304 lretq 305.Lafter_lret: 306ENDPROC(secondary_startup_64) 307 308#include "verify_cpu.S" 309 310#ifdef CONFIG_HOTPLUG_CPU 311/* 312 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 313 * up already except stack. We just set up stack here. Then call 314 * start_secondary() via .Ljump_to_C_code. 315 */ 316ENTRY(start_cpu0) 317 movq initial_stack(%rip), %rsp 318 jmp .Ljump_to_C_code 319ENDPROC(start_cpu0) 320#endif 321 322 /* Both SMP bootup and ACPI suspend change these variables */ 323 __REFDATA 324 .balign 8 325 GLOBAL(initial_code) 326 .quad x86_64_start_kernel 327 GLOBAL(initial_gs) 328 .quad INIT_PER_CPU_VAR(irq_stack_union) 329 GLOBAL(initial_stack) 330 /* 331 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel 332 * unwinder reliably detect the end of the stack. 333 */ 334 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS 335 __FINITDATA 336 337bad_address: 338 jmp bad_address 339 340 __INIT 341ENTRY(early_idt_handler_array) 342 # 104(%rsp) %rflags 343 # 96(%rsp) %cs 344 # 88(%rsp) %rip 345 # 80(%rsp) error code 346 i = 0 347 .rept NUM_EXCEPTION_VECTORS 348 .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 349 pushq $0 # Dummy error code, to make stack frame uniform 350 .endif 351 pushq $i # 72(%rsp) Vector number 352 jmp early_idt_handler_common 353 i = i + 1 354 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 355 .endr 356ENDPROC(early_idt_handler_array) 357 358early_idt_handler_common: 359 /* 360 * The stack is the hardware frame, an error code or zero, and the 361 * vector number. 362 */ 363 cld 364 365 incl early_recursion_flag(%rip) 366 367 /* The vector number is currently in the pt_regs->di slot. */ 368 pushq %rsi /* pt_regs->si */ 369 movq 8(%rsp), %rsi /* RSI = vector number */ 370 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 371 pushq %rdx /* pt_regs->dx */ 372 pushq %rcx /* pt_regs->cx */ 373 pushq %rax /* pt_regs->ax */ 374 pushq %r8 /* pt_regs->r8 */ 375 pushq %r9 /* pt_regs->r9 */ 376 pushq %r10 /* pt_regs->r10 */ 377 pushq %r11 /* pt_regs->r11 */ 378 pushq %rbx /* pt_regs->bx */ 379 pushq %rbp /* pt_regs->bp */ 380 pushq %r12 /* pt_regs->r12 */ 381 pushq %r13 /* pt_regs->r13 */ 382 pushq %r14 /* pt_regs->r14 */ 383 pushq %r15 /* pt_regs->r15 */ 384 385 cmpq $14,%rsi /* Page fault? */ 386 jnz 10f 387 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 388 call early_make_pgtable 389 andl %eax,%eax 390 jz 20f /* All good */ 391 39210: 393 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 394 call early_fixup_exception 395 39620: 397 decl early_recursion_flag(%rip) 398 jmp restore_regs_and_iret 399ENDPROC(early_idt_handler_common) 400 401 __INITDATA 402 403 .balign 4 404GLOBAL(early_recursion_flag) 405 .long 0 406 407#define NEXT_PAGE(name) \ 408 .balign PAGE_SIZE; \ 409GLOBAL(name) 410 411/* Automate the creation of 1 to 1 mapping pmd entries */ 412#define PMDS(START, PERM, COUNT) \ 413 i = 0 ; \ 414 .rept (COUNT) ; \ 415 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 416 i = i + 1 ; \ 417 .endr 418 419 __INITDATA 420NEXT_PAGE(early_level4_pgt) 421 .fill 511,8,0 422 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 423 424NEXT_PAGE(early_dynamic_pgts) 425 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 426 427 .data 428 429#ifndef CONFIG_XEN 430NEXT_PAGE(init_level4_pgt) 431 .fill 512,8,0 432#else 433NEXT_PAGE(init_level4_pgt) 434 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 435 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 436 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 437 .org init_level4_pgt + L4_START_KERNEL*8, 0 438 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 439 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 440 441NEXT_PAGE(level3_ident_pgt) 442 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 443 .fill 511, 8, 0 444NEXT_PAGE(level2_ident_pgt) 445 /* Since I easily can, map the first 1G. 446 * Don't set NX because code runs from these pages. 447 */ 448 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 449#endif 450 451NEXT_PAGE(level3_kernel_pgt) 452 .fill L3_START_KERNEL,8,0 453 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 454 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 455 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 456 457NEXT_PAGE(level2_kernel_pgt) 458 /* 459 * 512 MB kernel mapping. We spend a full page on this pagetable 460 * anyway. 461 * 462 * The kernel code+data+bss must not be bigger than that. 463 * 464 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 465 * If you want to increase this then increase MODULES_VADDR 466 * too.) 467 */ 468 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 469 KERNEL_IMAGE_SIZE/PMD_SIZE) 470 471NEXT_PAGE(level2_fixmap_pgt) 472 .fill 506,8,0 473 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 474 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 475 .fill 5,8,0 476 477NEXT_PAGE(level1_fixmap_pgt) 478 .fill 512,8,0 479 480#undef PMDS 481 482 .data 483 .align 16 484 .globl early_gdt_descr 485early_gdt_descr: 486 .word GDT_ENTRIES*8-1 487early_gdt_descr_base: 488 .quad INIT_PER_CPU_VAR(gdt_page) 489 490ENTRY(phys_base) 491 /* This must match the first entry in level2_kernel_pgt */ 492 .quad 0x0000000000000000 493EXPORT_SYMBOL(phys_base) 494 495#include "../../x86/xen/xen-head.S" 496 497 __PAGE_ALIGNED_BSS 498NEXT_PAGE(empty_zero_page) 499 .skip PAGE_SIZE 500EXPORT_SYMBOL(empty_zero_page) 501 502