1/* 2 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 3 * 4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9 */ 10 11 12#include <linux/linkage.h> 13#include <linux/threads.h> 14#include <linux/init.h> 15#include <asm/segment.h> 16#include <asm/pgtable.h> 17#include <asm/page.h> 18#include <asm/msr.h> 19#include <asm/cache.h> 20#include <asm/processor-flags.h> 21#include <asm/percpu.h> 22#include <asm/nops.h> 23#include "../entry/calling.h" 24#include <asm/export.h> 25 26#ifdef CONFIG_PARAVIRT 27#include <asm/asm-offsets.h> 28#include <asm/paravirt.h> 29#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 30#else 31#define GET_CR2_INTO(reg) movq %cr2, reg 32#define INTERRUPT_RETURN iretq 33#endif 34 35/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 36 * because we need identity-mapped pages. 37 * 38 */ 39 40#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 41 42L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) 43L4_START_KERNEL = pgd_index(__START_KERNEL_map) 44L3_START_KERNEL = pud_index(__START_KERNEL_map) 45 46 .text 47 __HEAD 48 .code64 49 .globl startup_64 50startup_64: 51 /* 52 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 53 * and someone has loaded an identity mapped page table 54 * for us. These identity mapped page tables map all of the 55 * kernel pages and possibly all of memory. 56 * 57 * %rsi holds a physical pointer to real_mode_data. 58 * 59 * We come here either directly from a 64bit bootloader, or from 60 * arch/x86/boot/compressed/head_64.S. 61 * 62 * We only come here initially at boot nothing else comes here. 63 * 64 * Since we may be loaded at an address different from what we were 65 * compiled to run at we first fixup the physical addresses in our page 66 * tables and then reload them. 67 */ 68 69 /* 70 * Setup stack for verify_cpu(). "-8" because stack_start is defined 71 * this way, see below. Our best guess is a NULL ptr for stack 72 * termination heuristics and we don't want to break anything which 73 * might depend on it (kgdb, ...). 74 */ 75 leaq (__end_init_task - 8)(%rip), %rsp 76 77 /* Sanitize CPU configuration */ 78 call verify_cpu 79 80 /* 81 * Compute the delta between the address I am compiled to run at and the 82 * address I am actually running at. 83 */ 84 leaq _text(%rip), %rbp 85 subq $_text - __START_KERNEL_map, %rbp 86 87 /* Is the address not 2M aligned? */ 88 testl $~PMD_PAGE_MASK, %ebp 89 jnz bad_address 90 91 /* 92 * Is the address too large? 93 */ 94 leaq _text(%rip), %rax 95 shrq $MAX_PHYSMEM_BITS, %rax 96 jnz bad_address 97 98 /* 99 * Fixup the physical addresses in the page table 100 */ 101 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) 102 103 addq %rbp, level3_kernel_pgt + (510*8)(%rip) 104 addq %rbp, level3_kernel_pgt + (511*8)(%rip) 105 106 addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 107 108 /* 109 * Set up the identity mapping for the switchover. These 110 * entries should *NOT* have the global bit set! This also 111 * creates a bunch of nonsense entries but that is fine -- 112 * it avoids problems around wraparound. 113 */ 114 leaq _text(%rip), %rdi 115 leaq early_level4_pgt(%rip), %rbx 116 117 movq %rdi, %rax 118 shrq $PGDIR_SHIFT, %rax 119 120 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx 121 movq %rdx, 0(%rbx,%rax,8) 122 movq %rdx, 8(%rbx,%rax,8) 123 124 addq $4096, %rdx 125 movq %rdi, %rax 126 shrq $PUD_SHIFT, %rax 127 andl $(PTRS_PER_PUD-1), %eax 128 movq %rdx, 4096(%rbx,%rax,8) 129 incl %eax 130 andl $(PTRS_PER_PUD-1), %eax 131 movq %rdx, 4096(%rbx,%rax,8) 132 133 addq $8192, %rbx 134 movq %rdi, %rax 135 shrq $PMD_SHIFT, %rdi 136 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax 137 leaq (_end - 1)(%rip), %rcx 138 shrq $PMD_SHIFT, %rcx 139 subq %rdi, %rcx 140 incl %ecx 141 1421: 143 andq $(PTRS_PER_PMD - 1), %rdi 144 movq %rax, (%rbx,%rdi,8) 145 incq %rdi 146 addq $PMD_SIZE, %rax 147 decl %ecx 148 jnz 1b 149 150 /* 151 * Fixup the kernel text+data virtual addresses. Note that 152 * we might write invalid pmds, when the kernel is relocated 153 * cleanup_highmap() fixes this up along with the mappings 154 * beyond _end. 155 */ 156 leaq level2_kernel_pgt(%rip), %rdi 157 leaq 4096(%rdi), %r8 158 /* See if it is a valid page table entry */ 1591: testb $1, 0(%rdi) 160 jz 2f 161 addq %rbp, 0(%rdi) 162 /* Go to the next page */ 1632: addq $8, %rdi 164 cmp %r8, %rdi 165 jne 1b 166 167 /* Fixup phys_base */ 168 addq %rbp, phys_base(%rip) 169 170 movq $(early_level4_pgt - __START_KERNEL_map), %rax 171 jmp 1f 172ENTRY(secondary_startup_64) 173 /* 174 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 175 * and someone has loaded a mapped page table. 176 * 177 * %rsi holds a physical pointer to real_mode_data. 178 * 179 * We come here either from startup_64 (using physical addresses) 180 * or from trampoline.S (using virtual addresses). 181 * 182 * Using virtual addresses from trampoline.S removes the need 183 * to have any identity mapped pages in the kernel page table 184 * after the boot processor executes this code. 185 */ 186 187 /* Sanitize CPU configuration */ 188 call verify_cpu 189 190 movq $(init_level4_pgt - __START_KERNEL_map), %rax 1911: 192 193 /* Enable PAE mode and PGE */ 194 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 195 movq %rcx, %cr4 196 197 /* Setup early boot stage 4 level pagetables. */ 198 addq phys_base(%rip), %rax 199 movq %rax, %cr3 200 201 /* Ensure I am executing from virtual addresses */ 202 movq $1f, %rax 203 jmp *%rax 2041: 205 206 /* Check if nx is implemented */ 207 movl $0x80000001, %eax 208 cpuid 209 movl %edx,%edi 210 211 /* Setup EFER (Extended Feature Enable Register) */ 212 movl $MSR_EFER, %ecx 213 rdmsr 214 btsl $_EFER_SCE, %eax /* Enable System Call */ 215 btl $20,%edi /* No Execute supported? */ 216 jnc 1f 217 btsl $_EFER_NX, %eax 218 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2191: wrmsr /* Make changes effective */ 220 221 /* Setup cr0 */ 222#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 223 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 224 X86_CR0_PG) 225 movl $CR0_STATE, %eax 226 /* Make changes effective */ 227 movq %rax, %cr0 228 229 /* Setup a boot time stack */ 230 movq stack_start(%rip), %rsp 231 232 /* zero EFLAGS after setting rsp */ 233 pushq $0 234 popfq 235 236 /* 237 * We must switch to a new descriptor in kernel space for the GDT 238 * because soon the kernel won't have access anymore to the userspace 239 * addresses where we're currently running on. We have to do that here 240 * because in 32bit we couldn't load a 64bit linear address. 241 */ 242 lgdt early_gdt_descr(%rip) 243 244 /* set up data segments */ 245 xorl %eax,%eax 246 movl %eax,%ds 247 movl %eax,%ss 248 movl %eax,%es 249 250 /* 251 * We don't really need to load %fs or %gs, but load them anyway 252 * to kill any stale realmode selectors. This allows execution 253 * under VT hardware. 254 */ 255 movl %eax,%fs 256 movl %eax,%gs 257 258 /* Set up %gs. 259 * 260 * The base of %gs always points to the bottom of the irqstack 261 * union. If the stack protector canary is enabled, it is 262 * located at %gs:40. Note that, on SMP, the boot cpu uses 263 * init data section till per cpu areas are set up. 264 */ 265 movl $MSR_GS_BASE,%ecx 266 movl initial_gs(%rip),%eax 267 movl initial_gs+4(%rip),%edx 268 wrmsr 269 270 /* rsi is pointer to real mode structure with interesting info. 271 pass it to C */ 272 movq %rsi, %rdi 273 274 /* Finally jump to run C code and to be on real kernel address 275 * Since we are running on identity-mapped space we have to jump 276 * to the full 64bit address, this is only possible as indirect 277 * jump. In addition we need to ensure %cs is set so we make this 278 * a far return. 279 * 280 * Note: do not change to far jump indirect with 64bit offset. 281 * 282 * AMD does not support far jump indirect with 64bit offset. 283 * AMD64 Architecture Programmer's Manual, Volume 3: states only 284 * JMP FAR mem16:16 FF /5 Far jump indirect, 285 * with the target specified by a far pointer in memory. 286 * JMP FAR mem16:32 FF /5 Far jump indirect, 287 * with the target specified by a far pointer in memory. 288 * 289 * Intel64 does support 64bit offset. 290 * Software Developer Manual Vol 2: states: 291 * FF /5 JMP m16:16 Jump far, absolute indirect, 292 * address given in m16:16 293 * FF /5 JMP m16:32 Jump far, absolute indirect, 294 * address given in m16:32. 295 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 296 * address given in m16:64. 297 */ 298 movq initial_code(%rip),%rax 299 pushq $0 # fake return address to stop unwinder 300 pushq $__KERNEL_CS # set correct cs 301 pushq %rax # target address in negative space 302 lretq 303ENDPROC(secondary_startup_64) 304 305#include "verify_cpu.S" 306 307#ifdef CONFIG_HOTPLUG_CPU 308/* 309 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 310 * up already except stack. We just set up stack here. Then call 311 * start_secondary(). 312 */ 313ENTRY(start_cpu0) 314 movq stack_start(%rip),%rsp 315 movq initial_code(%rip),%rax 316 pushq $0 # fake return address to stop unwinder 317 pushq $__KERNEL_CS # set correct cs 318 pushq %rax # target address in negative space 319 lretq 320ENDPROC(start_cpu0) 321#endif 322 323 /* SMP bootup changes these two */ 324 __REFDATA 325 .balign 8 326 GLOBAL(initial_code) 327 .quad x86_64_start_kernel 328 GLOBAL(initial_gs) 329 .quad INIT_PER_CPU_VAR(irq_stack_union) 330 331 GLOBAL(stack_start) 332 .quad init_thread_union+THREAD_SIZE-8 333 .word 0 334 __FINITDATA 335 336bad_address: 337 jmp bad_address 338 339 __INIT 340ENTRY(early_idt_handler_array) 341 # 104(%rsp) %rflags 342 # 96(%rsp) %cs 343 # 88(%rsp) %rip 344 # 80(%rsp) error code 345 i = 0 346 .rept NUM_EXCEPTION_VECTORS 347 .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 348 pushq $0 # Dummy error code, to make stack frame uniform 349 .endif 350 pushq $i # 72(%rsp) Vector number 351 jmp early_idt_handler_common 352 i = i + 1 353 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 354 .endr 355ENDPROC(early_idt_handler_array) 356 357early_idt_handler_common: 358 /* 359 * The stack is the hardware frame, an error code or zero, and the 360 * vector number. 361 */ 362 cld 363 364 incl early_recursion_flag(%rip) 365 366 /* The vector number is currently in the pt_regs->di slot. */ 367 pushq %rsi /* pt_regs->si */ 368 movq 8(%rsp), %rsi /* RSI = vector number */ 369 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 370 pushq %rdx /* pt_regs->dx */ 371 pushq %rcx /* pt_regs->cx */ 372 pushq %rax /* pt_regs->ax */ 373 pushq %r8 /* pt_regs->r8 */ 374 pushq %r9 /* pt_regs->r9 */ 375 pushq %r10 /* pt_regs->r10 */ 376 pushq %r11 /* pt_regs->r11 */ 377 pushq %rbx /* pt_regs->bx */ 378 pushq %rbp /* pt_regs->bp */ 379 pushq %r12 /* pt_regs->r12 */ 380 pushq %r13 /* pt_regs->r13 */ 381 pushq %r14 /* pt_regs->r14 */ 382 pushq %r15 /* pt_regs->r15 */ 383 384 cmpq $14,%rsi /* Page fault? */ 385 jnz 10f 386 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 387 call early_make_pgtable 388 andl %eax,%eax 389 jz 20f /* All good */ 390 39110: 392 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 393 call early_fixup_exception 394 39520: 396 decl early_recursion_flag(%rip) 397 jmp restore_regs_and_iret 398ENDPROC(early_idt_handler_common) 399 400 __INITDATA 401 402 .balign 4 403GLOBAL(early_recursion_flag) 404 .long 0 405 406#define NEXT_PAGE(name) \ 407 .balign PAGE_SIZE; \ 408GLOBAL(name) 409 410/* Automate the creation of 1 to 1 mapping pmd entries */ 411#define PMDS(START, PERM, COUNT) \ 412 i = 0 ; \ 413 .rept (COUNT) ; \ 414 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 415 i = i + 1 ; \ 416 .endr 417 418 __INITDATA 419NEXT_PAGE(early_level4_pgt) 420 .fill 511,8,0 421 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 422 423NEXT_PAGE(early_dynamic_pgts) 424 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 425 426 .data 427 428#ifndef CONFIG_XEN 429NEXT_PAGE(init_level4_pgt) 430 .fill 512,8,0 431#else 432NEXT_PAGE(init_level4_pgt) 433 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 434 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 435 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 436 .org init_level4_pgt + L4_START_KERNEL*8, 0 437 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 438 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 439 440NEXT_PAGE(level3_ident_pgt) 441 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 442 .fill 511, 8, 0 443NEXT_PAGE(level2_ident_pgt) 444 /* Since I easily can, map the first 1G. 445 * Don't set NX because code runs from these pages. 446 */ 447 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 448#endif 449 450NEXT_PAGE(level3_kernel_pgt) 451 .fill L3_START_KERNEL,8,0 452 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 453 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 454 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 455 456NEXT_PAGE(level2_kernel_pgt) 457 /* 458 * 512 MB kernel mapping. We spend a full page on this pagetable 459 * anyway. 460 * 461 * The kernel code+data+bss must not be bigger than that. 462 * 463 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 464 * If you want to increase this then increase MODULES_VADDR 465 * too.) 466 */ 467 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 468 KERNEL_IMAGE_SIZE/PMD_SIZE) 469 470NEXT_PAGE(level2_fixmap_pgt) 471 .fill 506,8,0 472 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 473 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 474 .fill 5,8,0 475 476NEXT_PAGE(level1_fixmap_pgt) 477 .fill 512,8,0 478 479#undef PMDS 480 481 .data 482 .align 16 483 .globl early_gdt_descr 484early_gdt_descr: 485 .word GDT_ENTRIES*8-1 486early_gdt_descr_base: 487 .quad INIT_PER_CPU_VAR(gdt_page) 488 489ENTRY(phys_base) 490 /* This must match the first entry in level2_kernel_pgt */ 491 .quad 0x0000000000000000 492EXPORT_SYMBOL(phys_base) 493 494#include "../../x86/xen/xen-head.S" 495 496 __PAGE_ALIGNED_BSS 497NEXT_PAGE(empty_zero_page) 498 .skip PAGE_SIZE 499EXPORT_SYMBOL(empty_zero_page) 500 501