1/* 2 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 3 * 4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 9 */ 10 11 12#include <linux/linkage.h> 13#include <linux/threads.h> 14#include <linux/init.h> 15#include <asm/segment.h> 16#include <asm/pgtable.h> 17#include <asm/page.h> 18#include <asm/msr.h> 19#include <asm/cache.h> 20#include <asm/processor-flags.h> 21#include <asm/percpu.h> 22#include <asm/nops.h> 23#include "../entry/calling.h" 24#include <asm/export.h> 25 26#ifdef CONFIG_PARAVIRT 27#include <asm/asm-offsets.h> 28#include <asm/paravirt.h> 29#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg 30#else 31#define GET_CR2_INTO(reg) movq %cr2, reg 32#define INTERRUPT_RETURN iretq 33#endif 34 35/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE 36 * because we need identity-mapped pages. 37 * 38 */ 39 40#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 41 42L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) 43L4_START_KERNEL = pgd_index(__START_KERNEL_map) 44L3_START_KERNEL = pud_index(__START_KERNEL_map) 45 46 .text 47 __HEAD 48 .code64 49 .globl startup_64 50startup_64: 51 /* 52 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 53 * and someone has loaded an identity mapped page table 54 * for us. These identity mapped page tables map all of the 55 * kernel pages and possibly all of memory. 56 * 57 * %rsi holds a physical pointer to real_mode_data. 58 * 59 * We come here either directly from a 64bit bootloader, or from 60 * arch/x86/boot/compressed/head_64.S. 61 * 62 * We only come here initially at boot nothing else comes here. 63 * 64 * Since we may be loaded at an address different from what we were 65 * compiled to run at we first fixup the physical addresses in our page 66 * tables and then reload them. 67 */ 68 69 /* 70 * Setup stack for verify_cpu(). "-8" because initial_stack is defined 71 * this way, see below. Our best guess is a NULL ptr for stack 72 * termination heuristics and we don't want to break anything which 73 * might depend on it (kgdb, ...). 74 */ 75 leaq (__end_init_task - 8)(%rip), %rsp 76 77 /* Sanitize CPU configuration */ 78 call verify_cpu 79 80 /* 81 * Compute the delta between the address I am compiled to run at and the 82 * address I am actually running at. 83 */ 84 leaq _text(%rip), %rbp 85 subq $_text - __START_KERNEL_map, %rbp 86 87 /* Is the address not 2M aligned? */ 88 testl $~PMD_PAGE_MASK, %ebp 89 jnz bad_address 90 91 /* 92 * Is the address too large? 93 */ 94 leaq _text(%rip), %rax 95 shrq $MAX_PHYSMEM_BITS, %rax 96 jnz bad_address 97 98 /* 99 * Fixup the physical addresses in the page table 100 */ 101 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) 102 103 addq %rbp, level3_kernel_pgt + (510*8)(%rip) 104 addq %rbp, level3_kernel_pgt + (511*8)(%rip) 105 106 addq %rbp, level2_fixmap_pgt + (506*8)(%rip) 107 108 /* 109 * Set up the identity mapping for the switchover. These 110 * entries should *NOT* have the global bit set! This also 111 * creates a bunch of nonsense entries but that is fine -- 112 * it avoids problems around wraparound. 113 */ 114 leaq _text(%rip), %rdi 115 leaq early_level4_pgt(%rip), %rbx 116 117 movq %rdi, %rax 118 shrq $PGDIR_SHIFT, %rax 119 120 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx 121 movq %rdx, 0(%rbx,%rax,8) 122 movq %rdx, 8(%rbx,%rax,8) 123 124 addq $4096, %rdx 125 movq %rdi, %rax 126 shrq $PUD_SHIFT, %rax 127 andl $(PTRS_PER_PUD-1), %eax 128 movq %rdx, 4096(%rbx,%rax,8) 129 incl %eax 130 andl $(PTRS_PER_PUD-1), %eax 131 movq %rdx, 4096(%rbx,%rax,8) 132 133 addq $8192, %rbx 134 movq %rdi, %rax 135 shrq $PMD_SHIFT, %rdi 136 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax 137 leaq (_end - 1)(%rip), %rcx 138 shrq $PMD_SHIFT, %rcx 139 subq %rdi, %rcx 140 incl %ecx 141 1421: 143 andq $(PTRS_PER_PMD - 1), %rdi 144 movq %rax, (%rbx,%rdi,8) 145 incq %rdi 146 addq $PMD_SIZE, %rax 147 decl %ecx 148 jnz 1b 149 150 test %rbp, %rbp 151 jz .Lskip_fixup 152 153 /* 154 * Fixup the kernel text+data virtual addresses. Note that 155 * we might write invalid pmds, when the kernel is relocated 156 * cleanup_highmap() fixes this up along with the mappings 157 * beyond _end. 158 */ 159 leaq level2_kernel_pgt(%rip), %rdi 160 leaq PAGE_SIZE(%rdi), %r8 161 /* See if it is a valid page table entry */ 1621: testb $_PAGE_PRESENT, 0(%rdi) 163 jz 2f 164 addq %rbp, 0(%rdi) 165 /* Go to the next page */ 1662: addq $8, %rdi 167 cmp %r8, %rdi 168 jne 1b 169 170 /* Fixup phys_base */ 171 addq %rbp, phys_base(%rip) 172 173.Lskip_fixup: 174 movq $(early_level4_pgt - __START_KERNEL_map), %rax 175 jmp 1f 176ENTRY(secondary_startup_64) 177 /* 178 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 179 * and someone has loaded a mapped page table. 180 * 181 * %rsi holds a physical pointer to real_mode_data. 182 * 183 * We come here either from startup_64 (using physical addresses) 184 * or from trampoline.S (using virtual addresses). 185 * 186 * Using virtual addresses from trampoline.S removes the need 187 * to have any identity mapped pages in the kernel page table 188 * after the boot processor executes this code. 189 */ 190 191 /* Sanitize CPU configuration */ 192 call verify_cpu 193 194 movq $(init_level4_pgt - __START_KERNEL_map), %rax 1951: 196 197 /* Enable PAE mode and PGE */ 198 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 199 movq %rcx, %cr4 200 201 /* Setup early boot stage 4 level pagetables. */ 202 addq phys_base(%rip), %rax 203 movq %rax, %cr3 204 205 /* Ensure I am executing from virtual addresses */ 206 movq $1f, %rax 207 jmp *%rax 2081: 209 210 /* Check if nx is implemented */ 211 movl $0x80000001, %eax 212 cpuid 213 movl %edx,%edi 214 215 /* Setup EFER (Extended Feature Enable Register) */ 216 movl $MSR_EFER, %ecx 217 rdmsr 218 btsl $_EFER_SCE, %eax /* Enable System Call */ 219 btl $20,%edi /* No Execute supported? */ 220 jnc 1f 221 btsl $_EFER_NX, %eax 222 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2231: wrmsr /* Make changes effective */ 224 225 /* Setup cr0 */ 226#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ 227 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ 228 X86_CR0_PG) 229 movl $CR0_STATE, %eax 230 /* Make changes effective */ 231 movq %rax, %cr0 232 233 /* Setup a boot time stack */ 234 movq initial_stack(%rip), %rsp 235 236 /* zero EFLAGS after setting rsp */ 237 pushq $0 238 popfq 239 240 /* 241 * We must switch to a new descriptor in kernel space for the GDT 242 * because soon the kernel won't have access anymore to the userspace 243 * addresses where we're currently running on. We have to do that here 244 * because in 32bit we couldn't load a 64bit linear address. 245 */ 246 lgdt early_gdt_descr(%rip) 247 248 /* set up data segments */ 249 xorl %eax,%eax 250 movl %eax,%ds 251 movl %eax,%ss 252 movl %eax,%es 253 254 /* 255 * We don't really need to load %fs or %gs, but load them anyway 256 * to kill any stale realmode selectors. This allows execution 257 * under VT hardware. 258 */ 259 movl %eax,%fs 260 movl %eax,%gs 261 262 /* Set up %gs. 263 * 264 * The base of %gs always points to the bottom of the irqstack 265 * union. If the stack protector canary is enabled, it is 266 * located at %gs:40. Note that, on SMP, the boot cpu uses 267 * init data section till per cpu areas are set up. 268 */ 269 movl $MSR_GS_BASE,%ecx 270 movl initial_gs(%rip),%eax 271 movl initial_gs+4(%rip),%edx 272 wrmsr 273 274 /* rsi is pointer to real mode structure with interesting info. 275 pass it to C */ 276 movq %rsi, %rdi 277 278 /* Finally jump to run C code and to be on real kernel address 279 * Since we are running on identity-mapped space we have to jump 280 * to the full 64bit address, this is only possible as indirect 281 * jump. In addition we need to ensure %cs is set so we make this 282 * a far return. 283 * 284 * Note: do not change to far jump indirect with 64bit offset. 285 * 286 * AMD does not support far jump indirect with 64bit offset. 287 * AMD64 Architecture Programmer's Manual, Volume 3: states only 288 * JMP FAR mem16:16 FF /5 Far jump indirect, 289 * with the target specified by a far pointer in memory. 290 * JMP FAR mem16:32 FF /5 Far jump indirect, 291 * with the target specified by a far pointer in memory. 292 * 293 * Intel64 does support 64bit offset. 294 * Software Developer Manual Vol 2: states: 295 * FF /5 JMP m16:16 Jump far, absolute indirect, 296 * address given in m16:16 297 * FF /5 JMP m16:32 Jump far, absolute indirect, 298 * address given in m16:32. 299 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 300 * address given in m16:64. 301 */ 302 movq initial_code(%rip),%rax 303 pushq $0 # fake return address to stop unwinder 304 pushq $__KERNEL_CS # set correct cs 305 pushq %rax # target address in negative space 306 lretq 307ENDPROC(secondary_startup_64) 308 309#include "verify_cpu.S" 310 311#ifdef CONFIG_HOTPLUG_CPU 312/* 313 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 314 * up already except stack. We just set up stack here. Then call 315 * start_secondary(). 316 */ 317ENTRY(start_cpu0) 318 movq initial_stack(%rip),%rsp 319 movq initial_code(%rip),%rax 320 pushq $0 # fake return address to stop unwinder 321 pushq $__KERNEL_CS # set correct cs 322 pushq %rax # target address in negative space 323 lretq 324ENDPROC(start_cpu0) 325#endif 326 327 /* Both SMP bootup and ACPI suspend change these variables */ 328 __REFDATA 329 .balign 8 330 GLOBAL(initial_code) 331 .quad x86_64_start_kernel 332 GLOBAL(initial_gs) 333 .quad INIT_PER_CPU_VAR(irq_stack_union) 334 GLOBAL(initial_stack) 335 .quad init_thread_union+THREAD_SIZE-8 336 __FINITDATA 337 338bad_address: 339 jmp bad_address 340 341 __INIT 342ENTRY(early_idt_handler_array) 343 # 104(%rsp) %rflags 344 # 96(%rsp) %cs 345 # 88(%rsp) %rip 346 # 80(%rsp) error code 347 i = 0 348 .rept NUM_EXCEPTION_VECTORS 349 .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 350 pushq $0 # Dummy error code, to make stack frame uniform 351 .endif 352 pushq $i # 72(%rsp) Vector number 353 jmp early_idt_handler_common 354 i = i + 1 355 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 356 .endr 357ENDPROC(early_idt_handler_array) 358 359early_idt_handler_common: 360 /* 361 * The stack is the hardware frame, an error code or zero, and the 362 * vector number. 363 */ 364 cld 365 366 incl early_recursion_flag(%rip) 367 368 /* The vector number is currently in the pt_regs->di slot. */ 369 pushq %rsi /* pt_regs->si */ 370 movq 8(%rsp), %rsi /* RSI = vector number */ 371 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 372 pushq %rdx /* pt_regs->dx */ 373 pushq %rcx /* pt_regs->cx */ 374 pushq %rax /* pt_regs->ax */ 375 pushq %r8 /* pt_regs->r8 */ 376 pushq %r9 /* pt_regs->r9 */ 377 pushq %r10 /* pt_regs->r10 */ 378 pushq %r11 /* pt_regs->r11 */ 379 pushq %rbx /* pt_regs->bx */ 380 pushq %rbp /* pt_regs->bp */ 381 pushq %r12 /* pt_regs->r12 */ 382 pushq %r13 /* pt_regs->r13 */ 383 pushq %r14 /* pt_regs->r14 */ 384 pushq %r15 /* pt_regs->r15 */ 385 386 cmpq $14,%rsi /* Page fault? */ 387 jnz 10f 388 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ 389 call early_make_pgtable 390 andl %eax,%eax 391 jz 20f /* All good */ 392 39310: 394 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 395 call early_fixup_exception 396 39720: 398 decl early_recursion_flag(%rip) 399 jmp restore_regs_and_iret 400ENDPROC(early_idt_handler_common) 401 402 __INITDATA 403 404 .balign 4 405GLOBAL(early_recursion_flag) 406 .long 0 407 408#define NEXT_PAGE(name) \ 409 .balign PAGE_SIZE; \ 410GLOBAL(name) 411 412/* Automate the creation of 1 to 1 mapping pmd entries */ 413#define PMDS(START, PERM, COUNT) \ 414 i = 0 ; \ 415 .rept (COUNT) ; \ 416 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 417 i = i + 1 ; \ 418 .endr 419 420 __INITDATA 421NEXT_PAGE(early_level4_pgt) 422 .fill 511,8,0 423 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 424 425NEXT_PAGE(early_dynamic_pgts) 426 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 427 428 .data 429 430#ifndef CONFIG_XEN 431NEXT_PAGE(init_level4_pgt) 432 .fill 512,8,0 433#else 434NEXT_PAGE(init_level4_pgt) 435 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 436 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 437 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 438 .org init_level4_pgt + L4_START_KERNEL*8, 0 439 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 440 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE 441 442NEXT_PAGE(level3_ident_pgt) 443 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE 444 .fill 511, 8, 0 445NEXT_PAGE(level2_ident_pgt) 446 /* Since I easily can, map the first 1G. 447 * Don't set NX because code runs from these pages. 448 */ 449 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 450#endif 451 452NEXT_PAGE(level3_kernel_pgt) 453 .fill L3_START_KERNEL,8,0 454 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 455 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE 456 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 457 458NEXT_PAGE(level2_kernel_pgt) 459 /* 460 * 512 MB kernel mapping. We spend a full page on this pagetable 461 * anyway. 462 * 463 * The kernel code+data+bss must not be bigger than that. 464 * 465 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 466 * If you want to increase this then increase MODULES_VADDR 467 * too.) 468 */ 469 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 470 KERNEL_IMAGE_SIZE/PMD_SIZE) 471 472NEXT_PAGE(level2_fixmap_pgt) 473 .fill 506,8,0 474 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE 475 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ 476 .fill 5,8,0 477 478NEXT_PAGE(level1_fixmap_pgt) 479 .fill 512,8,0 480 481#undef PMDS 482 483 .data 484 .align 16 485 .globl early_gdt_descr 486early_gdt_descr: 487 .word GDT_ENTRIES*8-1 488early_gdt_descr_base: 489 .quad INIT_PER_CPU_VAR(gdt_page) 490 491ENTRY(phys_base) 492 /* This must match the first entry in level2_kernel_pgt */ 493 .quad 0x0000000000000000 494EXPORT_SYMBOL(phys_base) 495 496#include "../../x86/xen/xen-head.S" 497 498 __PAGE_ALIGNED_BSS 499NEXT_PAGE(empty_zero_page) 500 .skip PAGE_SIZE 501EXPORT_SYMBOL(empty_zero_page) 502 503