1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <linux/pgtable.h> 17#include <asm/segment.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26#include <asm/nospec-branch.h> 27#include <asm/fixmap.h> 28 29#ifdef CONFIG_PARAVIRT_XXL 30#include <asm/asm-offsets.h> 31#include <asm/paravirt.h> 32#define GET_CR2_INTO(reg) GET_CR2_INTO_AX ; _ASM_MOV %_ASM_AX, reg 33#else 34#define INTERRUPT_RETURN iretq 35#define GET_CR2_INTO(reg) _ASM_MOV %cr2, reg 36#endif 37 38/* 39 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 40 * because we need identity-mapped pages. 41 */ 42#define l4_index(x) (((x) >> 39) & 511) 43#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 44 45L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 46L4_START_KERNEL = l4_index(__START_KERNEL_map) 47 48L3_START_KERNEL = pud_index(__START_KERNEL_map) 49 50 .text 51 __HEAD 52 .code64 53SYM_CODE_START_NOALIGN(startup_64) 54 UNWIND_HINT_EMPTY 55 /* 56 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 57 * and someone has loaded an identity mapped page table 58 * for us. These identity mapped page tables map all of the 59 * kernel pages and possibly all of memory. 60 * 61 * %rsi holds a physical pointer to real_mode_data. 62 * 63 * We come here either directly from a 64bit bootloader, or from 64 * arch/x86/boot/compressed/head_64.S. 65 * 66 * We only come here initially at boot nothing else comes here. 67 * 68 * Since we may be loaded at an address different from what we were 69 * compiled to run at we first fixup the physical addresses in our page 70 * tables and then reload them. 71 */ 72 73 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 74 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp 75 76 leaq _text(%rip), %rdi 77 pushq %rsi 78 call startup_64_setup_env 79 popq %rsi 80 81 /* Now switch to __KERNEL_CS so IRET works reliably */ 82 pushq $__KERNEL_CS 83 leaq .Lon_kernel_cs(%rip), %rax 84 pushq %rax 85 lretq 86 87.Lon_kernel_cs: 88 UNWIND_HINT_EMPTY 89 90 /* Sanitize CPU configuration */ 91 call verify_cpu 92 93 /* 94 * Perform pagetable fixups. Additionally, if SME is active, encrypt 95 * the kernel and retrieve the modifier (SME encryption mask if SME 96 * is active) to be added to the initial pgdir entry that will be 97 * programmed into CR3. 98 */ 99 leaq _text(%rip), %rdi 100 pushq %rsi 101 call __startup_64 102 popq %rsi 103 104 /* Form the CR3 value being sure to include the CR3 modifier */ 105 addq $(early_top_pgt - __START_KERNEL_map), %rax 106 jmp 1f 107SYM_CODE_END(startup_64) 108 109SYM_CODE_START(secondary_startup_64) 110 UNWIND_HINT_EMPTY 111 /* 112 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 113 * and someone has loaded a mapped page table. 114 * 115 * %rsi holds a physical pointer to real_mode_data. 116 * 117 * We come here either from startup_64 (using physical addresses) 118 * or from trampoline.S (using virtual addresses). 119 * 120 * Using virtual addresses from trampoline.S removes the need 121 * to have any identity mapped pages in the kernel page table 122 * after the boot processor executes this code. 123 */ 124 125 /* Sanitize CPU configuration */ 126 call verify_cpu 127 128 /* 129 * The secondary_startup_64_no_verify entry point is only used by 130 * SEV-ES guests. In those guests the call to verify_cpu() would cause 131 * #VC exceptions which can not be handled at this stage of secondary 132 * CPU bringup. 133 * 134 * All non SEV-ES systems, especially Intel systems, need to execute 135 * verify_cpu() above to make sure NX is enabled. 136 */ 137SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 138 UNWIND_HINT_EMPTY 139 140 /* 141 * Retrieve the modifier (SME encryption mask if SME is active) to be 142 * added to the initial pgdir entry that will be programmed into CR3. 143 */ 144 pushq %rsi 145 call __startup_secondary_64 146 popq %rsi 147 148 /* Form the CR3 value being sure to include the CR3 modifier */ 149 addq $(init_top_pgt - __START_KERNEL_map), %rax 1501: 151 152 /* Enable PAE mode, PGE and LA57 */ 153 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 154#ifdef CONFIG_X86_5LEVEL 155 testl $1, __pgtable_l5_enabled(%rip) 156 jz 1f 157 orl $X86_CR4_LA57, %ecx 1581: 159#endif 160 movq %rcx, %cr4 161 162 /* Setup early boot stage 4-/5-level pagetables. */ 163 addq phys_base(%rip), %rax 164 movq %rax, %cr3 165 166 /* Ensure I am executing from virtual addresses */ 167 movq $1f, %rax 168 ANNOTATE_RETPOLINE_SAFE 169 jmp *%rax 1701: 171 UNWIND_HINT_EMPTY 172 173 /* 174 * We must switch to a new descriptor in kernel space for the GDT 175 * because soon the kernel won't have access anymore to the userspace 176 * addresses where we're currently running on. We have to do that here 177 * because in 32bit we couldn't load a 64bit linear address. 178 */ 179 lgdt early_gdt_descr(%rip) 180 181 /* set up data segments */ 182 xorl %eax,%eax 183 movl %eax,%ds 184 movl %eax,%ss 185 movl %eax,%es 186 187 /* 188 * We don't really need to load %fs or %gs, but load them anyway 189 * to kill any stale realmode selectors. This allows execution 190 * under VT hardware. 191 */ 192 movl %eax,%fs 193 movl %eax,%gs 194 195 /* Set up %gs. 196 * 197 * The base of %gs always points to fixed_percpu_data. If the 198 * stack protector canary is enabled, it is located at %gs:40. 199 * Note that, on SMP, the boot cpu uses init data section until 200 * the per cpu areas are set up. 201 */ 202 movl $MSR_GS_BASE,%ecx 203 movl initial_gs(%rip),%eax 204 movl initial_gs+4(%rip),%edx 205 wrmsr 206 207 /* 208 * Setup a boot time stack - Any secondary CPU will have lost its stack 209 * by now because the cr3-switch above unmaps the real-mode stack 210 */ 211 movq initial_stack(%rip), %rsp 212 213 /* Setup and Load IDT */ 214 pushq %rsi 215 call early_setup_idt 216 popq %rsi 217 218 /* Check if nx is implemented */ 219 movl $0x80000001, %eax 220 cpuid 221 movl %edx,%edi 222 223 /* Setup EFER (Extended Feature Enable Register) */ 224 movl $MSR_EFER, %ecx 225 rdmsr 226 btsl $_EFER_SCE, %eax /* Enable System Call */ 227 btl $20,%edi /* No Execute supported? */ 228 jnc 1f 229 btsl $_EFER_NX, %eax 230 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2311: wrmsr /* Make changes effective */ 232 233 /* Setup cr0 */ 234 movl $CR0_STATE, %eax 235 /* Make changes effective */ 236 movq %rax, %cr0 237 238 /* zero EFLAGS after setting rsp */ 239 pushq $0 240 popfq 241 242 /* rsi is pointer to real mode structure with interesting info. 243 pass it to C */ 244 movq %rsi, %rdi 245 246.Ljump_to_C_code: 247 /* 248 * Jump to run C code and to be on a real kernel address. 249 * Since we are running on identity-mapped space we have to jump 250 * to the full 64bit address, this is only possible as indirect 251 * jump. In addition we need to ensure %cs is set so we make this 252 * a far return. 253 * 254 * Note: do not change to far jump indirect with 64bit offset. 255 * 256 * AMD does not support far jump indirect with 64bit offset. 257 * AMD64 Architecture Programmer's Manual, Volume 3: states only 258 * JMP FAR mem16:16 FF /5 Far jump indirect, 259 * with the target specified by a far pointer in memory. 260 * JMP FAR mem16:32 FF /5 Far jump indirect, 261 * with the target specified by a far pointer in memory. 262 * 263 * Intel64 does support 64bit offset. 264 * Software Developer Manual Vol 2: states: 265 * FF /5 JMP m16:16 Jump far, absolute indirect, 266 * address given in m16:16 267 * FF /5 JMP m16:32 Jump far, absolute indirect, 268 * address given in m16:32. 269 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 270 * address given in m16:64. 271 */ 272 pushq $.Lafter_lret # put return address on stack for unwinder 273 xorl %ebp, %ebp # clear frame pointer 274 movq initial_code(%rip), %rax 275 pushq $__KERNEL_CS # set correct cs 276 pushq %rax # target address in negative space 277 lretq 278.Lafter_lret: 279SYM_CODE_END(secondary_startup_64) 280 281#include "verify_cpu.S" 282 283#ifdef CONFIG_HOTPLUG_CPU 284/* 285 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 286 * up already except stack. We just set up stack here. Then call 287 * start_secondary() via .Ljump_to_C_code. 288 */ 289SYM_CODE_START(start_cpu0) 290 UNWIND_HINT_EMPTY 291 movq initial_stack(%rip), %rsp 292 jmp .Ljump_to_C_code 293SYM_CODE_END(start_cpu0) 294#endif 295 296#ifdef CONFIG_AMD_MEM_ENCRYPT 297/* 298 * VC Exception handler used during early boot when running on kernel 299 * addresses, but before the switch to the idt_table can be made. 300 * The early_idt_handler_array can't be used here because it calls into a lot 301 * of __init code and this handler is also used during CPU offlining/onlining. 302 * Therefore this handler ends up in the .text section so that it stays around 303 * when .init.text is freed. 304 */ 305SYM_CODE_START_NOALIGN(vc_boot_ghcb) 306 UNWIND_HINT_IRET_REGS offset=8 307 308 /* Build pt_regs */ 309 PUSH_AND_CLEAR_REGS 310 311 /* Call C handler */ 312 movq %rsp, %rdi 313 movq ORIG_RAX(%rsp), %rsi 314 movq initial_vc_handler(%rip), %rax 315 ANNOTATE_RETPOLINE_SAFE 316 call *%rax 317 318 /* Unwind pt_regs */ 319 POP_REGS 320 321 /* Remove Error Code */ 322 addq $8, %rsp 323 324 /* Pure iret required here - don't use INTERRUPT_RETURN */ 325 iretq 326SYM_CODE_END(vc_boot_ghcb) 327#endif 328 329 /* Both SMP bootup and ACPI suspend change these variables */ 330 __REFDATA 331 .balign 8 332SYM_DATA(initial_code, .quad x86_64_start_kernel) 333SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 334#ifdef CONFIG_AMD_MEM_ENCRYPT 335SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 336#endif 337 338/* 339 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel unwinder 340 * reliably detect the end of the stack. 341 */ 342SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS) 343 __FINITDATA 344 345 __INIT 346SYM_CODE_START(early_idt_handler_array) 347 i = 0 348 .rept NUM_EXCEPTION_VECTORS 349 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 350 UNWIND_HINT_IRET_REGS 351 pushq $0 # Dummy error code, to make stack frame uniform 352 .else 353 UNWIND_HINT_IRET_REGS offset=8 354 .endif 355 pushq $i # 72(%rsp) Vector number 356 jmp early_idt_handler_common 357 UNWIND_HINT_IRET_REGS 358 i = i + 1 359 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 360 .endr 361 UNWIND_HINT_IRET_REGS offset=16 362SYM_CODE_END(early_idt_handler_array) 363 364SYM_CODE_START_LOCAL(early_idt_handler_common) 365 /* 366 * The stack is the hardware frame, an error code or zero, and the 367 * vector number. 368 */ 369 cld 370 371 incl early_recursion_flag(%rip) 372 373 /* The vector number is currently in the pt_regs->di slot. */ 374 pushq %rsi /* pt_regs->si */ 375 movq 8(%rsp), %rsi /* RSI = vector number */ 376 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 377 pushq %rdx /* pt_regs->dx */ 378 pushq %rcx /* pt_regs->cx */ 379 pushq %rax /* pt_regs->ax */ 380 pushq %r8 /* pt_regs->r8 */ 381 pushq %r9 /* pt_regs->r9 */ 382 pushq %r10 /* pt_regs->r10 */ 383 pushq %r11 /* pt_regs->r11 */ 384 pushq %rbx /* pt_regs->bx */ 385 pushq %rbp /* pt_regs->bp */ 386 pushq %r12 /* pt_regs->r12 */ 387 pushq %r13 /* pt_regs->r13 */ 388 pushq %r14 /* pt_regs->r14 */ 389 pushq %r15 /* pt_regs->r15 */ 390 UNWIND_HINT_REGS 391 392 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 393 call do_early_exception 394 395 decl early_recursion_flag(%rip) 396 jmp restore_regs_and_return_to_kernel 397SYM_CODE_END(early_idt_handler_common) 398 399#ifdef CONFIG_AMD_MEM_ENCRYPT 400/* 401 * VC Exception handler used during very early boot. The 402 * early_idt_handler_array can't be used because it returns via the 403 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 404 * 405 * This handler will end up in the .init.text section and not be 406 * available to boot secondary CPUs. 407 */ 408SYM_CODE_START_NOALIGN(vc_no_ghcb) 409 UNWIND_HINT_IRET_REGS offset=8 410 411 /* Build pt_regs */ 412 PUSH_AND_CLEAR_REGS 413 414 /* Call C handler */ 415 movq %rsp, %rdi 416 movq ORIG_RAX(%rsp), %rsi 417 call do_vc_no_ghcb 418 419 /* Unwind pt_regs */ 420 POP_REGS 421 422 /* Remove Error Code */ 423 addq $8, %rsp 424 425 /* Pure iret required here - don't use INTERRUPT_RETURN */ 426 iretq 427SYM_CODE_END(vc_no_ghcb) 428#endif 429 430#define SYM_DATA_START_PAGE_ALIGNED(name) \ 431 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 432 433#ifdef CONFIG_PAGE_TABLE_ISOLATION 434/* 435 * Each PGD needs to be 8k long and 8k aligned. We do not 436 * ever go out to userspace with these, so we do not 437 * strictly *need* the second page, but this allows us to 438 * have a single set_pgd() implementation that does not 439 * need to worry about whether it has 4k or 8k to work 440 * with. 441 * 442 * This ensures PGDs are 8k long: 443 */ 444#define PTI_USER_PGD_FILL 512 445/* This ensures they are 8k-aligned: */ 446#define SYM_DATA_START_PTI_ALIGNED(name) \ 447 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 448#else 449#define SYM_DATA_START_PTI_ALIGNED(name) \ 450 SYM_DATA_START_PAGE_ALIGNED(name) 451#define PTI_USER_PGD_FILL 0 452#endif 453 454/* Automate the creation of 1 to 1 mapping pmd entries */ 455#define PMDS(START, PERM, COUNT) \ 456 i = 0 ; \ 457 .rept (COUNT) ; \ 458 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 459 i = i + 1 ; \ 460 .endr 461 462 __INITDATA 463 .balign 4 464 465SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 466 .fill 512,8,0 467 .fill PTI_USER_PGD_FILL,8,0 468SYM_DATA_END(early_top_pgt) 469 470SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 471 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 472SYM_DATA_END(early_dynamic_pgts) 473 474SYM_DATA(early_recursion_flag, .long 0) 475 476 .data 477 478#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 479SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 480 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 481 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 482 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 483 .org init_top_pgt + L4_START_KERNEL*8, 0 484 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 485 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 486 .fill PTI_USER_PGD_FILL,8,0 487SYM_DATA_END(init_top_pgt) 488 489SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 490 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 491 .fill 511, 8, 0 492SYM_DATA_END(level3_ident_pgt) 493SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 494 /* 495 * Since I easily can, map the first 1G. 496 * Don't set NX because code runs from these pages. 497 * 498 * Note: This sets _PAGE_GLOBAL despite whether 499 * the CPU supports it or it is enabled. But, 500 * the CPU should ignore the bit. 501 */ 502 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 503SYM_DATA_END(level2_ident_pgt) 504#else 505SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 506 .fill 512,8,0 507 .fill PTI_USER_PGD_FILL,8,0 508SYM_DATA_END(init_top_pgt) 509#endif 510 511#ifdef CONFIG_X86_5LEVEL 512SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 513 .fill 511,8,0 514 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 515SYM_DATA_END(level4_kernel_pgt) 516#endif 517 518SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 519 .fill L3_START_KERNEL,8,0 520 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 521 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 522 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 523SYM_DATA_END(level3_kernel_pgt) 524 525SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 526 /* 527 * 512 MB kernel mapping. We spend a full page on this pagetable 528 * anyway. 529 * 530 * The kernel code+data+bss must not be bigger than that. 531 * 532 * (NOTE: at +512MB starts the module area, see MODULES_VADDR. 533 * If you want to increase this then increase MODULES_VADDR 534 * too.) 535 * 536 * This table is eventually used by the kernel during normal 537 * runtime. Care must be taken to clear out undesired bits 538 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases. 539 */ 540 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, 541 KERNEL_IMAGE_SIZE/PMD_SIZE) 542SYM_DATA_END(level2_kernel_pgt) 543 544SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 545 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 546 pgtno = 0 547 .rept (FIXMAP_PMD_NUM) 548 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 549 + _PAGE_TABLE_NOENC; 550 pgtno = pgtno + 1 551 .endr 552 /* 6 MB reserved space + a 2MB hole */ 553 .fill 4,8,0 554SYM_DATA_END(level2_fixmap_pgt) 555 556SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 557 .rept (FIXMAP_PMD_NUM) 558 .fill 512,8,0 559 .endr 560SYM_DATA_END(level1_fixmap_pgt) 561 562#undef PMDS 563 564 .data 565 .align 16 566 567SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 568SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 569 570 .align 16 571/* This must match the first entry in level2_kernel_pgt */ 572SYM_DATA(phys_base, .quad 0x0) 573EXPORT_SYMBOL(phys_base) 574 575#include "../../x86/xen/xen-head.S" 576 577 __PAGE_ALIGNED_BSS 578SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 579 .skip PAGE_SIZE 580SYM_DATA_END(empty_zero_page) 581EXPORT_SYMBOL(empty_zero_page) 582 583