xref: /openbmc/linux/arch/x86/kernel/head_64.S (revision 3e5d8f97) 
1/*
2 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
3 *
4 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/desc.h>
16#include <asm/segment.h>
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22
23#ifdef CONFIG_PARAVIRT
24#include <asm/asm-offsets.h>
25#include <asm/paravirt.h>
26#else
27#define GET_CR2_INTO_RCX movq %cr2, %rcx
28#endif
29
30/* we are not able to switch in one step to the final KERNEL ADRESS SPACE
31 * because we need identity-mapped pages.
32 *
33 */
34
35#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
36
37L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
38L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
39L4_START_KERNEL = pgd_index(__START_KERNEL_map)
40L3_START_KERNEL = pud_index(__START_KERNEL_map)
41
42	.text
43	.section .text.head
44	.code64
45	.globl startup_64
46startup_64:
47
48	/*
49	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
50	 * and someone has loaded an identity mapped page table
51	 * for us.  These identity mapped page tables map all of the
52	 * kernel pages and possibly all of memory.
53	 *
54	 * %esi holds a physical pointer to real_mode_data.
55	 *
56	 * We come here either directly from a 64bit bootloader, or from
57	 * arch/x86_64/boot/compressed/head.S.
58	 *
59	 * We only come here initially at boot nothing else comes here.
60	 *
61	 * Since we may be loaded at an address different from what we were
62	 * compiled to run at we first fixup the physical addresses in our page
63	 * tables and then reload them.
64	 */
65
66	/* Compute the delta between the address I am compiled to run at and the
67	 * address I am actually running at.
68	 */
69	leaq	_text(%rip), %rbp
70	subq	$_text - __START_KERNEL_map, %rbp
71
72	/* Is the address not 2M aligned? */
73	movq	%rbp, %rax
74	andl	$~PMD_PAGE_MASK, %eax
75	testl	%eax, %eax
76	jnz	bad_address
77
78	/* Is the address too large? */
79	leaq	_text(%rip), %rdx
80	movq	$PGDIR_SIZE, %rax
81	cmpq	%rax, %rdx
82	jae	bad_address
83
84	/* Fixup the physical addresses in the page table
85	 */
86	addq	%rbp, init_level4_pgt + 0(%rip)
87	addq	%rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
88	addq	%rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
89
90	addq	%rbp, level3_ident_pgt + 0(%rip)
91
92	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
93	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)
94
95	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)
96
97	/* Add an Identity mapping if I am above 1G */
98	leaq	_text(%rip), %rdi
99	andq	$PMD_PAGE_MASK, %rdi
100
101	movq	%rdi, %rax
102	shrq	$PUD_SHIFT, %rax
103	andq	$(PTRS_PER_PUD - 1), %rax
104	jz	ident_complete
105
106	leaq	(level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
107	leaq	level3_ident_pgt(%rip), %rbx
108	movq	%rdx, 0(%rbx, %rax, 8)
109
110	movq	%rdi, %rax
111	shrq	$PMD_SHIFT, %rax
112	andq	$(PTRS_PER_PMD - 1), %rax
113	leaq	__PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
114	leaq	level2_spare_pgt(%rip), %rbx
115	movq	%rdx, 0(%rbx, %rax, 8)
116ident_complete:
117
118	/*
119	 * Fixup the kernel text+data virtual addresses. Note that
120	 * we might write invalid pmds, when the kernel is relocated
121	 * cleanup_highmap() fixes this up along with the mappings
122	 * beyond _end.
123	 */
124
125	leaq	level2_kernel_pgt(%rip), %rdi
126	leaq	4096(%rdi), %r8
127	/* See if it is a valid page table entry */
1281:	testq	$1, 0(%rdi)
129	jz	2f
130	addq	%rbp, 0(%rdi)
131	/* Go to the next page */
1322:	addq	$8, %rdi
133	cmp	%r8, %rdi
134	jne	1b
135
136	/* Fixup phys_base */
137	addq	%rbp, phys_base(%rip)
138
139#ifdef CONFIG_X86_TRAMPOLINE
140	addq	%rbp, trampoline_level4_pgt + 0(%rip)
141	addq	%rbp, trampoline_level4_pgt + (511*8)(%rip)
142#endif
143
144	/* Due to ENTRY(), sometimes the empty space gets filled with
145	 * zeros. Better take a jmp than relying on empty space being
146	 * filled with 0x90 (nop)
147	 */
148	jmp secondary_startup_64
149ENTRY(secondary_startup_64)
150	/*
151	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
152	 * and someone has loaded a mapped page table.
153	 *
154	 * %esi holds a physical pointer to real_mode_data.
155	 *
156	 * We come here either from startup_64 (using physical addresses)
157	 * or from trampoline.S (using virtual addresses).
158	 *
159	 * Using virtual addresses from trampoline.S removes the need
160	 * to have any identity mapped pages in the kernel page table
161	 * after the boot processor executes this code.
162	 */
163
164	/* Enable PAE mode and PGE */
165	movl	$(X86_CR4_PAE | X86_CR4_PGE), %eax
166	movq	%rax, %cr4
167
168	/* Setup early boot stage 4 level pagetables. */
169	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
170	addq	phys_base(%rip), %rax
171	movq	%rax, %cr3
172
173	/* Ensure I am executing from virtual addresses */
174	movq	$1f, %rax
175	jmp	*%rax
1761:
177
178	/* Check if nx is implemented */
179	movl	$0x80000001, %eax
180	cpuid
181	movl	%edx,%edi
182
183	/* Setup EFER (Extended Feature Enable Register) */
184	movl	$MSR_EFER, %ecx
185	rdmsr
186	btsl	$_EFER_SCE, %eax	/* Enable System Call */
187	btl	$20,%edi		/* No Execute supported? */
188	jnc     1f
189	btsl	$_EFER_NX, %eax
1901:	wrmsr				/* Make changes effective */
191
192	/* Setup cr0 */
193#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
194			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
195			 X86_CR0_PG)
196	movl	$CR0_STATE, %eax
197	/* Make changes effective */
198	movq	%rax, %cr0
199
200	/* Setup a boot time stack */
201	movq stack_start(%rip),%rsp
202
203	/* zero EFLAGS after setting rsp */
204	pushq $0
205	popfq
206
207#ifdef CONFIG_SMP
208	/*
209	 * early_gdt_base should point to the gdt_page in static percpu init
210	 * data area.  Computing this requires two symbols - __per_cpu_load
211	 * and per_cpu__gdt_page.  As linker can't do no such relocation, do
212	 * it by hand.  As early_gdt_descr is manipulated by C code for
213	 * secondary CPUs, this should be done only once for the boot CPU
214	 * when early_gdt_descr_base contains zero.
215	 */
216	movq	early_gdt_descr_base(%rip), %rax
217	testq	%rax, %rax
218	jnz	1f
219	movq	$__per_cpu_load, %rax
220	addq	$per_cpu__gdt_page, %rax
221	movq	%rax, early_gdt_descr_base(%rip)
2221:
223#endif
224	/*
225	 * We must switch to a new descriptor in kernel space for the GDT
226	 * because soon the kernel won't have access anymore to the userspace
227	 * addresses where we're currently running on. We have to do that here
228	 * because in 32bit we couldn't load a 64bit linear address.
229	 */
230	lgdt	early_gdt_descr(%rip)
231
232	/* set up data segments. actually 0 would do too */
233	movl $__KERNEL_DS,%eax
234	movl %eax,%ds
235	movl %eax,%ss
236	movl %eax,%es
237
238	/*
239	 * We don't really need to load %fs or %gs, but load them anyway
240	 * to kill any stale realmode selectors.  This allows execution
241	 * under VT hardware.
242	 */
243	movl %eax,%fs
244	movl %eax,%gs
245
246	/*
247	 * Setup up a dummy PDA. this is just for some early bootup code
248	 * that does in_interrupt()
249	 */
250	movl	$MSR_GS_BASE,%ecx
251	movq	$empty_zero_page,%rax
252	movq    %rax,%rdx
253	shrq	$32,%rdx
254	wrmsr
255
256	/* esi is pointer to real mode structure with interesting info.
257	   pass it to C */
258	movl	%esi, %edi
259
260	/* Finally jump to run C code and to be on real kernel address
261	 * Since we are running on identity-mapped space we have to jump
262	 * to the full 64bit address, this is only possible as indirect
263	 * jump.  In addition we need to ensure %cs is set so we make this
264	 * a far return.
265	 */
266	movq	initial_code(%rip),%rax
267	pushq	$0		# fake return address to stop unwinder
268	pushq	$__KERNEL_CS	# set correct cs
269	pushq	%rax		# target address in negative space
270	lretq
271
272	/* SMP bootup changes these two */
273	__REFDATA
274	.align	8
275	ENTRY(initial_code)
276	.quad	x86_64_start_kernel
277	__FINITDATA
278
279	ENTRY(stack_start)
280	.quad  init_thread_union+THREAD_SIZE-8
281	.word  0
282
283bad_address:
284	jmp bad_address
285
286	.section ".init.text","ax"
287#ifdef CONFIG_EARLY_PRINTK
288	.globl early_idt_handlers
289early_idt_handlers:
290	i = 0
291	.rept NUM_EXCEPTION_VECTORS
292	movl $i, %esi
293	jmp early_idt_handler
294	i = i + 1
295	.endr
296#endif
297
298ENTRY(early_idt_handler)
299#ifdef CONFIG_EARLY_PRINTK
300	cmpl $2,early_recursion_flag(%rip)
301	jz  1f
302	incl early_recursion_flag(%rip)
303	GET_CR2_INTO_RCX
304	movq %rcx,%r9
305	xorl %r8d,%r8d		# zero for error code
306	movl %esi,%ecx		# get vector number
307	# Test %ecx against mask of vectors that push error code.
308	cmpl $31,%ecx
309	ja 0f
310	movl $1,%eax
311	salq %cl,%rax
312	testl $0x27d00,%eax
313	je 0f
314	popq %r8		# get error code
3150:	movq 0(%rsp),%rcx	# get ip
316	movq 8(%rsp),%rdx	# get cs
317	xorl %eax,%eax
318	leaq early_idt_msg(%rip),%rdi
319	call early_printk
320	cmpl $2,early_recursion_flag(%rip)
321	jz  1f
322	call dump_stack
323#ifdef CONFIG_KALLSYMS
324	leaq early_idt_ripmsg(%rip),%rdi
325	movq 0(%rsp),%rsi	# get rip again
326	call __print_symbol
327#endif
328#endif /* EARLY_PRINTK */
3291:	hlt
330	jmp 1b
331
332#ifdef CONFIG_EARLY_PRINTK
333early_recursion_flag:
334	.long 0
335
336early_idt_msg:
337	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
338early_idt_ripmsg:
339	.asciz "RIP %s\n"
340#endif /* CONFIG_EARLY_PRINTK */
341	.previous
342
343.balign PAGE_SIZE
344
345#define NEXT_PAGE(name) \
346	.balign	PAGE_SIZE; \
347ENTRY(name)
348
349/* Automate the creation of 1 to 1 mapping pmd entries */
350#define PMDS(START, PERM, COUNT)			\
351	i = 0 ;						\
352	.rept (COUNT) ;					\
353	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
354	i = i + 1 ;					\
355	.endr
356
357	/*
358	 * This default setting generates an ident mapping at address 0x100000
359	 * and a mapping for the kernel that precisely maps virtual address
360	 * 0xffffffff80000000 to physical address 0x000000. (always using
361	 * 2Mbyte large pages provided by PAE mode)
362	 */
363NEXT_PAGE(init_level4_pgt)
364	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
365	.org	init_level4_pgt + L4_PAGE_OFFSET*8, 0
366	.quad	level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
367	.org	init_level4_pgt + L4_START_KERNEL*8, 0
368	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
369	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
370
371NEXT_PAGE(level3_ident_pgt)
372	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
373	.fill	511,8,0
374
375NEXT_PAGE(level3_kernel_pgt)
376	.fill	L3_START_KERNEL,8,0
377	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
378	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
379	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
380
381NEXT_PAGE(level2_fixmap_pgt)
382	.fill	506,8,0
383	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
384	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
385	.fill	5,8,0
386
387NEXT_PAGE(level1_fixmap_pgt)
388	.fill	512,8,0
389
390NEXT_PAGE(level2_ident_pgt)
391	/* Since I easily can, map the first 1G.
392	 * Don't set NX because code runs from these pages.
393	 */
394	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
395
396NEXT_PAGE(level2_kernel_pgt)
397	/*
398	 * 512 MB kernel mapping. We spend a full page on this pagetable
399	 * anyway.
400	 *
401	 * The kernel code+data+bss must not be bigger than that.
402	 *
403	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
404	 *  If you want to increase this then increase MODULES_VADDR
405	 *  too.)
406	 */
407	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
408		KERNEL_IMAGE_SIZE/PMD_SIZE)
409
410NEXT_PAGE(level2_spare_pgt)
411	.fill   512, 8, 0
412
413#undef PMDS
414#undef NEXT_PAGE
415
416	.data
417	.align 16
418	.globl early_gdt_descr
419early_gdt_descr:
420	.word	GDT_ENTRIES*8-1
421#ifdef CONFIG_SMP
422early_gdt_descr_base:
423	.quad   0x0000000000000000
424#else
425	.quad	per_cpu__gdt_page
426#endif
427
428ENTRY(phys_base)
429	/* This must match the first entry in level2_kernel_pgt */
430	.quad   0x0000000000000000
431
432#include "../../x86/xen/xen-head.S"
433
434	.section .bss, "aw", @nobits
435	.align L1_CACHE_BYTES
436ENTRY(idt_table)
437	.skip 256 * 16
438
439	.section .bss.page_aligned, "aw", @nobits
440	.align PAGE_SIZE
441ENTRY(empty_zero_page)
442	.skip PAGE_SIZE
443