1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 13#include <linux/linkage.h> 14#include <linux/threads.h> 15#include <linux/init.h> 16#include <linux/pgtable.h> 17#include <asm/segment.h> 18#include <asm/page.h> 19#include <asm/msr.h> 20#include <asm/cache.h> 21#include <asm/processor-flags.h> 22#include <asm/percpu.h> 23#include <asm/nops.h> 24#include "../entry/calling.h" 25#include <asm/export.h> 26#include <asm/nospec-branch.h> 27#include <asm/fixmap.h> 28 29/* 30 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 31 * because we need identity-mapped pages. 32 */ 33#define l4_index(x) (((x) >> 39) & 511) 34#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 35 36L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 37L4_START_KERNEL = l4_index(__START_KERNEL_map) 38 39L3_START_KERNEL = pud_index(__START_KERNEL_map) 40 41 .text 42 __HEAD 43 .code64 44SYM_CODE_START_NOALIGN(startup_64) 45 UNWIND_HINT_EMPTY 46 /* 47 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 48 * and someone has loaded an identity mapped page table 49 * for us. These identity mapped page tables map all of the 50 * kernel pages and possibly all of memory. 51 * 52 * %rsi holds a physical pointer to real_mode_data. 53 * 54 * We come here either directly from a 64bit bootloader, or from 55 * arch/x86/boot/compressed/head_64.S. 56 * 57 * We only come here initially at boot nothing else comes here. 58 * 59 * Since we may be loaded at an address different from what we were 60 * compiled to run at we first fixup the physical addresses in our page 61 * tables and then reload them. 62 */ 63 64 /* Set up the stack for verify_cpu(), similar to initial_stack below */ 65 leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp 66 67 leaq _text(%rip), %rdi 68 pushq %rsi 69 call startup_64_setup_env 70 popq %rsi 71 72 /* Now switch to __KERNEL_CS so IRET works reliably */ 73 pushq $__KERNEL_CS 74 leaq .Lon_kernel_cs(%rip), %rax 75 pushq %rax 76 lretq 77 78.Lon_kernel_cs: 79 UNWIND_HINT_EMPTY 80 81 /* Sanitize CPU configuration */ 82 call verify_cpu 83 84 /* 85 * Perform pagetable fixups. Additionally, if SME is active, encrypt 86 * the kernel and retrieve the modifier (SME encryption mask if SME 87 * is active) to be added to the initial pgdir entry that will be 88 * programmed into CR3. 89 */ 90 leaq _text(%rip), %rdi 91 pushq %rsi 92 call __startup_64 93 popq %rsi 94 95 /* Form the CR3 value being sure to include the CR3 modifier */ 96 addq $(early_top_pgt - __START_KERNEL_map), %rax 97 jmp 1f 98SYM_CODE_END(startup_64) 99 100SYM_CODE_START(secondary_startup_64) 101 UNWIND_HINT_EMPTY 102 ANNOTATE_NOENDBR 103 /* 104 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 105 * and someone has loaded a mapped page table. 106 * 107 * %rsi holds a physical pointer to real_mode_data. 108 * 109 * We come here either from startup_64 (using physical addresses) 110 * or from trampoline.S (using virtual addresses). 111 * 112 * Using virtual addresses from trampoline.S removes the need 113 * to have any identity mapped pages in the kernel page table 114 * after the boot processor executes this code. 115 */ 116 117 /* Sanitize CPU configuration */ 118 call verify_cpu 119 120 /* 121 * The secondary_startup_64_no_verify entry point is only used by 122 * SEV-ES guests. In those guests the call to verify_cpu() would cause 123 * #VC exceptions which can not be handled at this stage of secondary 124 * CPU bringup. 125 * 126 * All non SEV-ES systems, especially Intel systems, need to execute 127 * verify_cpu() above to make sure NX is enabled. 128 */ 129SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 130 UNWIND_HINT_EMPTY 131 ANNOTATE_NOENDBR 132 133 /* 134 * Retrieve the modifier (SME encryption mask if SME is active) to be 135 * added to the initial pgdir entry that will be programmed into CR3. 136 */ 137 pushq %rsi 138 call __startup_secondary_64 139 popq %rsi 140 141 /* Form the CR3 value being sure to include the CR3 modifier */ 142 addq $(init_top_pgt - __START_KERNEL_map), %rax 1431: 144 145 /* Enable PAE mode, PGE and LA57 */ 146 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 147#ifdef CONFIG_X86_5LEVEL 148 testl $1, __pgtable_l5_enabled(%rip) 149 jz 1f 150 orl $X86_CR4_LA57, %ecx 1511: 152#endif 153 movq %rcx, %cr4 154 155 /* Setup early boot stage 4-/5-level pagetables. */ 156 addq phys_base(%rip), %rax 157 158 /* 159 * For SEV guests: Verify that the C-bit is correct. A malicious 160 * hypervisor could lie about the C-bit position to perform a ROP 161 * attack on the guest by writing to the unencrypted stack and wait for 162 * the next RET instruction. 163 * %rsi carries pointer to realmode data and is callee-clobbered. Save 164 * and restore it. 165 */ 166 pushq %rsi 167 movq %rax, %rdi 168 call sev_verify_cbit 169 popq %rsi 170 171 /* 172 * Switch to new page-table 173 * 174 * For the boot CPU this switches to early_top_pgt which still has the 175 * indentity mappings present. The secondary CPUs will switch to the 176 * init_top_pgt here, away from the trampoline_pgd and unmap the 177 * indentity mapped ranges. 178 */ 179 movq %rax, %cr3 180 181 /* 182 * Do a global TLB flush after the CR3 switch to make sure the TLB 183 * entries from the identity mapping are flushed. 184 */ 185 movq %cr4, %rcx 186 movq %rcx, %rax 187 xorq $X86_CR4_PGE, %rcx 188 movq %rcx, %cr4 189 movq %rax, %cr4 190 191 /* Ensure I am executing from virtual addresses */ 192 movq $1f, %rax 193 ANNOTATE_RETPOLINE_SAFE 194 jmp *%rax 1951: 196 UNWIND_HINT_EMPTY 197 ANNOTATE_NOENDBR // above 198 199 /* 200 * We must switch to a new descriptor in kernel space for the GDT 201 * because soon the kernel won't have access anymore to the userspace 202 * addresses where we're currently running on. We have to do that here 203 * because in 32bit we couldn't load a 64bit linear address. 204 */ 205 lgdt early_gdt_descr(%rip) 206 207 /* set up data segments */ 208 xorl %eax,%eax 209 movl %eax,%ds 210 movl %eax,%ss 211 movl %eax,%es 212 213 /* 214 * We don't really need to load %fs or %gs, but load them anyway 215 * to kill any stale realmode selectors. This allows execution 216 * under VT hardware. 217 */ 218 movl %eax,%fs 219 movl %eax,%gs 220 221 /* Set up %gs. 222 * 223 * The base of %gs always points to fixed_percpu_data. If the 224 * stack protector canary is enabled, it is located at %gs:40. 225 * Note that, on SMP, the boot cpu uses init data section until 226 * the per cpu areas are set up. 227 */ 228 movl $MSR_GS_BASE,%ecx 229 movl initial_gs(%rip),%eax 230 movl initial_gs+4(%rip),%edx 231 wrmsr 232 233 /* 234 * Setup a boot time stack - Any secondary CPU will have lost its stack 235 * by now because the cr3-switch above unmaps the real-mode stack 236 */ 237 movq initial_stack(%rip), %rsp 238 239 /* Setup and Load IDT */ 240 pushq %rsi 241 call early_setup_idt 242 popq %rsi 243 244 /* Check if nx is implemented */ 245 movl $0x80000001, %eax 246 cpuid 247 movl %edx,%edi 248 249 /* Setup EFER (Extended Feature Enable Register) */ 250 movl $MSR_EFER, %ecx 251 rdmsr 252 btsl $_EFER_SCE, %eax /* Enable System Call */ 253 btl $20,%edi /* No Execute supported? */ 254 jnc 1f 255 btsl $_EFER_NX, %eax 256 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 2571: wrmsr /* Make changes effective */ 258 259 /* Setup cr0 */ 260 movl $CR0_STATE, %eax 261 /* Make changes effective */ 262 movq %rax, %cr0 263 264 /* zero EFLAGS after setting rsp */ 265 pushq $0 266 popfq 267 268 /* rsi is pointer to real mode structure with interesting info. 269 pass it to C */ 270 movq %rsi, %rdi 271 272.Ljump_to_C_code: 273 /* 274 * Jump to run C code and to be on a real kernel address. 275 * Since we are running on identity-mapped space we have to jump 276 * to the full 64bit address, this is only possible as indirect 277 * jump. In addition we need to ensure %cs is set so we make this 278 * a far return. 279 * 280 * Note: do not change to far jump indirect with 64bit offset. 281 * 282 * AMD does not support far jump indirect with 64bit offset. 283 * AMD64 Architecture Programmer's Manual, Volume 3: states only 284 * JMP FAR mem16:16 FF /5 Far jump indirect, 285 * with the target specified by a far pointer in memory. 286 * JMP FAR mem16:32 FF /5 Far jump indirect, 287 * with the target specified by a far pointer in memory. 288 * 289 * Intel64 does support 64bit offset. 290 * Software Developer Manual Vol 2: states: 291 * FF /5 JMP m16:16 Jump far, absolute indirect, 292 * address given in m16:16 293 * FF /5 JMP m16:32 Jump far, absolute indirect, 294 * address given in m16:32. 295 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 296 * address given in m16:64. 297 */ 298 pushq $.Lafter_lret # put return address on stack for unwinder 299 xorl %ebp, %ebp # clear frame pointer 300 movq initial_code(%rip), %rax 301 pushq $__KERNEL_CS # set correct cs 302 pushq %rax # target address in negative space 303 lretq 304.Lafter_lret: 305 ANNOTATE_NOENDBR 306SYM_CODE_END(secondary_startup_64) 307 308#include "verify_cpu.S" 309#include "sev_verify_cbit.S" 310 311#ifdef CONFIG_HOTPLUG_CPU 312/* 313 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 314 * up already except stack. We just set up stack here. Then call 315 * start_secondary() via .Ljump_to_C_code. 316 */ 317SYM_CODE_START(start_cpu0) 318 UNWIND_HINT_EMPTY 319 movq initial_stack(%rip), %rsp 320 jmp .Ljump_to_C_code 321SYM_CODE_END(start_cpu0) 322#endif 323 324#ifdef CONFIG_AMD_MEM_ENCRYPT 325/* 326 * VC Exception handler used during early boot when running on kernel 327 * addresses, but before the switch to the idt_table can be made. 328 * The early_idt_handler_array can't be used here because it calls into a lot 329 * of __init code and this handler is also used during CPU offlining/onlining. 330 * Therefore this handler ends up in the .text section so that it stays around 331 * when .init.text is freed. 332 */ 333SYM_CODE_START_NOALIGN(vc_boot_ghcb) 334 UNWIND_HINT_IRET_REGS offset=8 335 336 /* Build pt_regs */ 337 PUSH_AND_CLEAR_REGS 338 339 /* Call C handler */ 340 movq %rsp, %rdi 341 movq ORIG_RAX(%rsp), %rsi 342 movq initial_vc_handler(%rip), %rax 343 ANNOTATE_RETPOLINE_SAFE 344 call *%rax 345 346 /* Unwind pt_regs */ 347 POP_REGS 348 349 /* Remove Error Code */ 350 addq $8, %rsp 351 352 iretq 353SYM_CODE_END(vc_boot_ghcb) 354#endif 355 356 /* Both SMP bootup and ACPI suspend change these variables */ 357 __REFDATA 358 .balign 8 359SYM_DATA(initial_code, .quad x86_64_start_kernel) 360SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 361#ifdef CONFIG_AMD_MEM_ENCRYPT 362SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 363#endif 364 365/* 366 * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder 367 * reliably detect the end of the stack. 368 */ 369SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) 370 __FINITDATA 371 372 __INIT 373SYM_CODE_START(early_idt_handler_array) 374 i = 0 375 .rept NUM_EXCEPTION_VECTORS 376 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 377 UNWIND_HINT_IRET_REGS 378 ENDBR 379 pushq $0 # Dummy error code, to make stack frame uniform 380 .else 381 UNWIND_HINT_IRET_REGS offset=8 382 ENDBR 383 .endif 384 pushq $i # 72(%rsp) Vector number 385 jmp early_idt_handler_common 386 UNWIND_HINT_IRET_REGS 387 i = i + 1 388 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 389 .endr 390SYM_CODE_END(early_idt_handler_array) 391 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 392 393SYM_CODE_START_LOCAL(early_idt_handler_common) 394 UNWIND_HINT_IRET_REGS offset=16 395 /* 396 * The stack is the hardware frame, an error code or zero, and the 397 * vector number. 398 */ 399 cld 400 401 incl early_recursion_flag(%rip) 402 403 /* The vector number is currently in the pt_regs->di slot. */ 404 pushq %rsi /* pt_regs->si */ 405 movq 8(%rsp), %rsi /* RSI = vector number */ 406 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 407 pushq %rdx /* pt_regs->dx */ 408 pushq %rcx /* pt_regs->cx */ 409 pushq %rax /* pt_regs->ax */ 410 pushq %r8 /* pt_regs->r8 */ 411 pushq %r9 /* pt_regs->r9 */ 412 pushq %r10 /* pt_regs->r10 */ 413 pushq %r11 /* pt_regs->r11 */ 414 pushq %rbx /* pt_regs->bx */ 415 pushq %rbp /* pt_regs->bp */ 416 pushq %r12 /* pt_regs->r12 */ 417 pushq %r13 /* pt_regs->r13 */ 418 pushq %r14 /* pt_regs->r14 */ 419 pushq %r15 /* pt_regs->r15 */ 420 UNWIND_HINT_REGS 421 422 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 423 call do_early_exception 424 425 decl early_recursion_flag(%rip) 426 jmp restore_regs_and_return_to_kernel 427SYM_CODE_END(early_idt_handler_common) 428 429#ifdef CONFIG_AMD_MEM_ENCRYPT 430/* 431 * VC Exception handler used during very early boot. The 432 * early_idt_handler_array can't be used because it returns via the 433 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 434 * 435 * XXX it does, fix this. 436 * 437 * This handler will end up in the .init.text section and not be 438 * available to boot secondary CPUs. 439 */ 440SYM_CODE_START_NOALIGN(vc_no_ghcb) 441 UNWIND_HINT_IRET_REGS offset=8 442 443 /* Build pt_regs */ 444 PUSH_AND_CLEAR_REGS 445 446 /* Call C handler */ 447 movq %rsp, %rdi 448 movq ORIG_RAX(%rsp), %rsi 449 call do_vc_no_ghcb 450 451 /* Unwind pt_regs */ 452 POP_REGS 453 454 /* Remove Error Code */ 455 addq $8, %rsp 456 457 /* Pure iret required here - don't use INTERRUPT_RETURN */ 458 iretq 459SYM_CODE_END(vc_no_ghcb) 460#endif 461 462#define SYM_DATA_START_PAGE_ALIGNED(name) \ 463 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 464 465#ifdef CONFIG_PAGE_TABLE_ISOLATION 466/* 467 * Each PGD needs to be 8k long and 8k aligned. We do not 468 * ever go out to userspace with these, so we do not 469 * strictly *need* the second page, but this allows us to 470 * have a single set_pgd() implementation that does not 471 * need to worry about whether it has 4k or 8k to work 472 * with. 473 * 474 * This ensures PGDs are 8k long: 475 */ 476#define PTI_USER_PGD_FILL 512 477/* This ensures they are 8k-aligned: */ 478#define SYM_DATA_START_PTI_ALIGNED(name) \ 479 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 480#else 481#define SYM_DATA_START_PTI_ALIGNED(name) \ 482 SYM_DATA_START_PAGE_ALIGNED(name) 483#define PTI_USER_PGD_FILL 0 484#endif 485 486/* Automate the creation of 1 to 1 mapping pmd entries */ 487#define PMDS(START, PERM, COUNT) \ 488 i = 0 ; \ 489 .rept (COUNT) ; \ 490 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 491 i = i + 1 ; \ 492 .endr 493 494 __INITDATA 495 .balign 4 496 497SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 498 .fill 512,8,0 499 .fill PTI_USER_PGD_FILL,8,0 500SYM_DATA_END(early_top_pgt) 501 502SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 503 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 504SYM_DATA_END(early_dynamic_pgts) 505 506SYM_DATA(early_recursion_flag, .long 0) 507 508 .data 509 510#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 511SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 512 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 513 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 514 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 515 .org init_top_pgt + L4_START_KERNEL*8, 0 516 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 517 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 518 .fill PTI_USER_PGD_FILL,8,0 519SYM_DATA_END(init_top_pgt) 520 521SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 522 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 523 .fill 511, 8, 0 524SYM_DATA_END(level3_ident_pgt) 525SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 526 /* 527 * Since I easily can, map the first 1G. 528 * Don't set NX because code runs from these pages. 529 * 530 * Note: This sets _PAGE_GLOBAL despite whether 531 * the CPU supports it or it is enabled. But, 532 * the CPU should ignore the bit. 533 */ 534 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 535SYM_DATA_END(level2_ident_pgt) 536#else 537SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 538 .fill 512,8,0 539 .fill PTI_USER_PGD_FILL,8,0 540SYM_DATA_END(init_top_pgt) 541#endif 542 543#ifdef CONFIG_X86_5LEVEL 544SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 545 .fill 511,8,0 546 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 547SYM_DATA_END(level4_kernel_pgt) 548#endif 549 550SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 551 .fill L3_START_KERNEL,8,0 552 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 553 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 554 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 555SYM_DATA_END(level3_kernel_pgt) 556 557SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 558 /* 559 * Kernel high mapping. 560 * 561 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 562 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 563 * 512 MiB otherwise. 564 * 565 * (NOTE: after that starts the module area, see MODULES_VADDR.) 566 * 567 * This table is eventually used by the kernel during normal runtime. 568 * Care must be taken to clear out undesired bits later, like _PAGE_RW 569 * or _PAGE_GLOBAL in some cases. 570 */ 571 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 572SYM_DATA_END(level2_kernel_pgt) 573 574SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 575 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 576 pgtno = 0 577 .rept (FIXMAP_PMD_NUM) 578 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 579 + _PAGE_TABLE_NOENC; 580 pgtno = pgtno + 1 581 .endr 582 /* 6 MB reserved space + a 2MB hole */ 583 .fill 4,8,0 584SYM_DATA_END(level2_fixmap_pgt) 585 586SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 587 .rept (FIXMAP_PMD_NUM) 588 .fill 512,8,0 589 .endr 590SYM_DATA_END(level1_fixmap_pgt) 591 592#undef PMDS 593 594 .data 595 .align 16 596 597SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 598SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 599 600 .align 16 601/* This must match the first entry in level2_kernel_pgt */ 602SYM_DATA(phys_base, .quad 0x0) 603EXPORT_SYMBOL(phys_base) 604 605#include "../../x86/xen/xen-head.S" 606 607 __PAGE_ALIGNED_BSS 608SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 609 .skip PAGE_SIZE 610SYM_DATA_END(empty_zero_page) 611EXPORT_SYMBOL(empty_zero_page) 612 613