xref: /openbmc/linux/arch/x86/kernel/head_64.S (revision 18a44a7f) 
1/*
2 *  linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
3 *
4 *  Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 *  Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 *  Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 *  Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 *  Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/segment.h>
16#include <asm/pgtable.h>
17#include <asm/page.h>
18#include <asm/msr.h>
19#include <asm/cache.h>
20#include <asm/processor-flags.h>
21#include <asm/percpu.h>
22#include <asm/nops.h>
23
24#ifdef CONFIG_PARAVIRT
25#include <asm/asm-offsets.h>
26#include <asm/paravirt.h>
27#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
28#else
29#define GET_CR2_INTO(reg) movq %cr2, reg
30#define INTERRUPT_RETURN iretq
31#endif
32
33/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
34 * because we need identity-mapped pages.
35 *
36 */
37
38#define pud_index(x)	(((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
39
40L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
41L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
42L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43L3_START_KERNEL = pud_index(__START_KERNEL_map)
44
45	.text
46	__HEAD
47	.code64
48	.globl startup_64
49startup_64:
50	/*
51	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
52	 * and someone has loaded an identity mapped page table
53	 * for us.  These identity mapped page tables map all of the
54	 * kernel pages and possibly all of memory.
55	 *
56	 * %rsi holds a physical pointer to real_mode_data.
57	 *
58	 * We come here either directly from a 64bit bootloader, or from
59	 * arch/x86_64/boot/compressed/head.S.
60	 *
61	 * We only come here initially at boot nothing else comes here.
62	 *
63	 * Since we may be loaded at an address different from what we were
64	 * compiled to run at we first fixup the physical addresses in our page
65	 * tables and then reload them.
66	 */
67
68	/*
69	 * Compute the delta between the address I am compiled to run at and the
70	 * address I am actually running at.
71	 */
72	leaq	_text(%rip), %rbp
73	subq	$_text - __START_KERNEL_map, %rbp
74
75	/* Is the address not 2M aligned? */
76	movq	%rbp, %rax
77	andl	$~PMD_PAGE_MASK, %eax
78	testl	%eax, %eax
79	jnz	bad_address
80
81	/*
82	 * Is the address too large?
83	 */
84	leaq	_text(%rip), %rax
85	shrq	$MAX_PHYSMEM_BITS, %rax
86	jnz	bad_address
87
88	/*
89	 * Fixup the physical addresses in the page table
90	 */
91	addq	%rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
92
93	addq	%rbp, level3_kernel_pgt + (510*8)(%rip)
94	addq	%rbp, level3_kernel_pgt + (511*8)(%rip)
95
96	addq	%rbp, level2_fixmap_pgt + (506*8)(%rip)
97
98	/*
99	 * Set up the identity mapping for the switchover.  These
100	 * entries should *NOT* have the global bit set!  This also
101	 * creates a bunch of nonsense entries but that is fine --
102	 * it avoids problems around wraparound.
103	 */
104	leaq	_text(%rip), %rdi
105	leaq	early_level4_pgt(%rip), %rbx
106
107	movq	%rdi, %rax
108	shrq	$PGDIR_SHIFT, %rax
109
110	leaq	(4096 + _KERNPG_TABLE)(%rbx), %rdx
111	movq	%rdx, 0(%rbx,%rax,8)
112	movq	%rdx, 8(%rbx,%rax,8)
113
114	addq	$4096, %rdx
115	movq	%rdi, %rax
116	shrq	$PUD_SHIFT, %rax
117	andl	$(PTRS_PER_PUD-1), %eax
118	movq	%rdx, (4096+0)(%rbx,%rax,8)
119	movq	%rdx, (4096+8)(%rbx,%rax,8)
120
121	addq	$8192, %rbx
122	movq	%rdi, %rax
123	shrq	$PMD_SHIFT, %rdi
124	addq	$(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
125	leaq	(_end - 1)(%rip), %rcx
126	shrq	$PMD_SHIFT, %rcx
127	subq	%rdi, %rcx
128	incl	%ecx
129
1301:
131	andq	$(PTRS_PER_PMD - 1), %rdi
132	movq	%rax, (%rbx,%rdi,8)
133	incq	%rdi
134	addq	$PMD_SIZE, %rax
135	decl	%ecx
136	jnz	1b
137
138	/*
139	 * Fixup the kernel text+data virtual addresses. Note that
140	 * we might write invalid pmds, when the kernel is relocated
141	 * cleanup_highmap() fixes this up along with the mappings
142	 * beyond _end.
143	 */
144	leaq	level2_kernel_pgt(%rip), %rdi
145	leaq	4096(%rdi), %r8
146	/* See if it is a valid page table entry */
1471:	testq	$1, 0(%rdi)
148	jz	2f
149	addq	%rbp, 0(%rdi)
150	/* Go to the next page */
1512:	addq	$8, %rdi
152	cmp	%r8, %rdi
153	jne	1b
154
155	/* Fixup phys_base */
156	addq	%rbp, phys_base(%rip)
157
158	movq	$(early_level4_pgt - __START_KERNEL_map), %rax
159	jmp 1f
160ENTRY(secondary_startup_64)
161	/*
162	 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
163	 * and someone has loaded a mapped page table.
164	 *
165	 * %rsi holds a physical pointer to real_mode_data.
166	 *
167	 * We come here either from startup_64 (using physical addresses)
168	 * or from trampoline.S (using virtual addresses).
169	 *
170	 * Using virtual addresses from trampoline.S removes the need
171	 * to have any identity mapped pages in the kernel page table
172	 * after the boot processor executes this code.
173	 */
174
175	movq	$(init_level4_pgt - __START_KERNEL_map), %rax
1761:
177
178	/* Enable PAE mode and PGE */
179	movl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
180	movq	%rcx, %cr4
181
182	/* Setup early boot stage 4 level pagetables. */
183	addq	phys_base(%rip), %rax
184	movq	%rax, %cr3
185
186	/* Ensure I am executing from virtual addresses */
187	movq	$1f, %rax
188	jmp	*%rax
1891:
190
191	/* Check if nx is implemented */
192	movl	$0x80000001, %eax
193	cpuid
194	movl	%edx,%edi
195
196	/* Setup EFER (Extended Feature Enable Register) */
197	movl	$MSR_EFER, %ecx
198	rdmsr
199	btsl	$_EFER_SCE, %eax	/* Enable System Call */
200	btl	$20,%edi		/* No Execute supported? */
201	jnc     1f
202	btsl	$_EFER_NX, %eax
2031:	wrmsr				/* Make changes effective */
204
205	/* Setup cr0 */
206#define CR0_STATE	(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
207			 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
208			 X86_CR0_PG)
209	movl	$CR0_STATE, %eax
210	/* Make changes effective */
211	movq	%rax, %cr0
212
213	/* Setup a boot time stack */
214	movq stack_start(%rip), %rsp
215
216	/* zero EFLAGS after setting rsp */
217	pushq $0
218	popfq
219
220	/*
221	 * We must switch to a new descriptor in kernel space for the GDT
222	 * because soon the kernel won't have access anymore to the userspace
223	 * addresses where we're currently running on. We have to do that here
224	 * because in 32bit we couldn't load a 64bit linear address.
225	 */
226	lgdt	early_gdt_descr(%rip)
227
228	/* set up data segments */
229	xorl %eax,%eax
230	movl %eax,%ds
231	movl %eax,%ss
232	movl %eax,%es
233
234	/*
235	 * We don't really need to load %fs or %gs, but load them anyway
236	 * to kill any stale realmode selectors.  This allows execution
237	 * under VT hardware.
238	 */
239	movl %eax,%fs
240	movl %eax,%gs
241
242	/* Set up %gs.
243	 *
244	 * The base of %gs always points to the bottom of the irqstack
245	 * union.  If the stack protector canary is enabled, it is
246	 * located at %gs:40.  Note that, on SMP, the boot cpu uses
247	 * init data section till per cpu areas are set up.
248	 */
249	movl	$MSR_GS_BASE,%ecx
250	movl	initial_gs(%rip),%eax
251	movl	initial_gs+4(%rip),%edx
252	wrmsr
253
254	/* rsi is pointer to real mode structure with interesting info.
255	   pass it to C */
256	movq	%rsi, %rdi
257
258	/* Finally jump to run C code and to be on real kernel address
259	 * Since we are running on identity-mapped space we have to jump
260	 * to the full 64bit address, this is only possible as indirect
261	 * jump.  In addition we need to ensure %cs is set so we make this
262	 * a far return.
263	 *
264	 * Note: do not change to far jump indirect with 64bit offset.
265	 *
266	 * AMD does not support far jump indirect with 64bit offset.
267	 * AMD64 Architecture Programmer's Manual, Volume 3: states only
268	 *	JMP FAR mem16:16 FF /5 Far jump indirect,
269	 *		with the target specified by a far pointer in memory.
270	 *	JMP FAR mem16:32 FF /5 Far jump indirect,
271	 *		with the target specified by a far pointer in memory.
272	 *
273	 * Intel64 does support 64bit offset.
274	 * Software Developer Manual Vol 2: states:
275	 *	FF /5 JMP m16:16 Jump far, absolute indirect,
276	 *		address given in m16:16
277	 *	FF /5 JMP m16:32 Jump far, absolute indirect,
278	 *		address given in m16:32.
279	 *	REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
280	 *		address given in m16:64.
281	 */
282	movq	initial_code(%rip),%rax
283	pushq	$0		# fake return address to stop unwinder
284	pushq	$__KERNEL_CS	# set correct cs
285	pushq	%rax		# target address in negative space
286	lretq
287
288#ifdef CONFIG_HOTPLUG_CPU
289/*
290 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
291 * up already except stack. We just set up stack here. Then call
292 * start_secondary().
293 */
294ENTRY(start_cpu0)
295	movq stack_start(%rip),%rsp
296	movq	initial_code(%rip),%rax
297	pushq	$0		# fake return address to stop unwinder
298	pushq	$__KERNEL_CS	# set correct cs
299	pushq	%rax		# target address in negative space
300	lretq
301ENDPROC(start_cpu0)
302#endif
303
304	/* SMP bootup changes these two */
305	__REFDATA
306	.balign	8
307	GLOBAL(initial_code)
308	.quad	x86_64_start_kernel
309	GLOBAL(initial_gs)
310	.quad	INIT_PER_CPU_VAR(irq_stack_union)
311
312	GLOBAL(stack_start)
313	.quad  init_thread_union+THREAD_SIZE-8
314	.word  0
315	__FINITDATA
316
317bad_address:
318	jmp bad_address
319
320	__INIT
321	.globl early_idt_handlers
322early_idt_handlers:
323	# 104(%rsp) %rflags
324	#  96(%rsp) %cs
325	#  88(%rsp) %rip
326	#  80(%rsp) error code
327	i = 0
328	.rept NUM_EXCEPTION_VECTORS
329	.if (EXCEPTION_ERRCODE_MASK >> i) & 1
330	ASM_NOP2
331	.else
332	pushq $0		# Dummy error code, to make stack frame uniform
333	.endif
334	pushq $i		# 72(%rsp) Vector number
335	jmp early_idt_handler
336	i = i + 1
337	.endr
338
339/* This is global to keep gas from relaxing the jumps */
340ENTRY(early_idt_handler)
341	cld
342
343	cmpl $2,early_recursion_flag(%rip)
344	jz  1f
345	incl early_recursion_flag(%rip)
346
347	pushq %rax		# 64(%rsp)
348	pushq %rcx		# 56(%rsp)
349	pushq %rdx		# 48(%rsp)
350	pushq %rsi		# 40(%rsp)
351	pushq %rdi		# 32(%rsp)
352	pushq %r8		# 24(%rsp)
353	pushq %r9		# 16(%rsp)
354	pushq %r10		#  8(%rsp)
355	pushq %r11		#  0(%rsp)
356
357	cmpl $__KERNEL_CS,96(%rsp)
358	jne 11f
359
360	cmpl $14,72(%rsp)	# Page fault?
361	jnz 10f
362	GET_CR2_INTO(%rdi)	# can clobber any volatile register if pv
363	call early_make_pgtable
364	andl %eax,%eax
365	jz 20f			# All good
366
36710:
368	leaq 88(%rsp),%rdi	# Pointer to %rip
369	call early_fixup_exception
370	andl %eax,%eax
371	jnz 20f			# Found an exception entry
372
37311:
374#ifdef CONFIG_EARLY_PRINTK
375	GET_CR2_INTO(%r9)	# can clobber any volatile register if pv
376	movl 80(%rsp),%r8d	# error code
377	movl 72(%rsp),%esi	# vector number
378	movl 96(%rsp),%edx	# %cs
379	movq 88(%rsp),%rcx	# %rip
380	xorl %eax,%eax
381	leaq early_idt_msg(%rip),%rdi
382	call early_printk
383	cmpl $2,early_recursion_flag(%rip)
384	jz  1f
385	call dump_stack
386#ifdef CONFIG_KALLSYMS
387	leaq early_idt_ripmsg(%rip),%rdi
388	movq 40(%rsp),%rsi	# %rip again
389	call __print_symbol
390#endif
391#endif /* EARLY_PRINTK */
3921:	hlt
393	jmp 1b
394
39520:	# Exception table entry found or page table generated
396	popq %r11
397	popq %r10
398	popq %r9
399	popq %r8
400	popq %rdi
401	popq %rsi
402	popq %rdx
403	popq %rcx
404	popq %rax
405	addq $16,%rsp		# drop vector number and error code
406	decl early_recursion_flag(%rip)
407	INTERRUPT_RETURN
408ENDPROC(early_idt_handler)
409
410	__INITDATA
411
412	.balign 4
413early_recursion_flag:
414	.long 0
415
416#ifdef CONFIG_EARLY_PRINTK
417early_idt_msg:
418	.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
419early_idt_ripmsg:
420	.asciz "RIP %s\n"
421#endif /* CONFIG_EARLY_PRINTK */
422
423#define NEXT_PAGE(name) \
424	.balign	PAGE_SIZE; \
425GLOBAL(name)
426
427/* Automate the creation of 1 to 1 mapping pmd entries */
428#define PMDS(START, PERM, COUNT)			\
429	i = 0 ;						\
430	.rept (COUNT) ;					\
431	.quad	(START) + (i << PMD_SHIFT) + (PERM) ;	\
432	i = i + 1 ;					\
433	.endr
434
435	__INITDATA
436NEXT_PAGE(early_level4_pgt)
437	.fill	511,8,0
438	.quad	level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
439
440NEXT_PAGE(early_dynamic_pgts)
441	.fill	512*EARLY_DYNAMIC_PAGE_TABLES,8,0
442
443	.data
444
445#ifndef CONFIG_XEN
446NEXT_PAGE(init_level4_pgt)
447	.fill	512,8,0
448#else
449NEXT_PAGE(init_level4_pgt)
450	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
451	.org    init_level4_pgt + L4_PAGE_OFFSET*8, 0
452	.quad   level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
453	.org    init_level4_pgt + L4_START_KERNEL*8, 0
454	/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
455	.quad   level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
456
457NEXT_PAGE(level3_ident_pgt)
458	.quad	level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
459	.fill	511, 8, 0
460NEXT_PAGE(level2_ident_pgt)
461	/* Since I easily can, map the first 1G.
462	 * Don't set NX because code runs from these pages.
463	 */
464	PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
465#endif
466
467NEXT_PAGE(level3_kernel_pgt)
468	.fill	L3_START_KERNEL,8,0
469	/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
470	.quad	level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
471	.quad	level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
472
473NEXT_PAGE(level2_kernel_pgt)
474	/*
475	 * 512 MB kernel mapping. We spend a full page on this pagetable
476	 * anyway.
477	 *
478	 * The kernel code+data+bss must not be bigger than that.
479	 *
480	 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
481	 *  If you want to increase this then increase MODULES_VADDR
482	 *  too.)
483	 */
484	PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
485		KERNEL_IMAGE_SIZE/PMD_SIZE)
486
487NEXT_PAGE(level2_fixmap_pgt)
488	.fill	506,8,0
489	.quad	level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
490	/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
491	.fill	5,8,0
492
493NEXT_PAGE(level1_fixmap_pgt)
494	.fill	512,8,0
495
496#undef PMDS
497
498	.data
499	.align 16
500	.globl early_gdt_descr
501early_gdt_descr:
502	.word	GDT_ENTRIES*8-1
503early_gdt_descr_base:
504	.quad	INIT_PER_CPU_VAR(gdt_page)
505
506ENTRY(phys_base)
507	/* This must match the first entry in level2_kernel_pgt */
508	.quad   0x0000000000000000
509
510#include "../../x86/xen/xen-head.S"
511
512	.section .bss, "aw", @nobits
513	.align L1_CACHE_BYTES
514ENTRY(idt_table)
515	.skip IDT_ENTRIES * 16
516
517	.align L1_CACHE_BYTES
518ENTRY(nmi_idt_table)
519	.skip IDT_ENTRIES * 16
520
521	__PAGE_ALIGNED_BSS
522NEXT_PAGE(empty_zero_page)
523	.skip PAGE_SIZE
524