1b2441318SGreg Kroah-Hartman/* SPDX-License-Identifier: GPL-2.0 */ 2250c2277SThomas Gleixner/* 35b171e82SAlexander Kuleshov * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4250c2277SThomas Gleixner * 5250c2277SThomas Gleixner * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6250c2277SThomas Gleixner * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7250c2277SThomas Gleixner * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8250c2277SThomas Gleixner * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9250c2277SThomas Gleixner * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10250c2277SThomas Gleixner */ 11250c2277SThomas Gleixner 12250c2277SThomas Gleixner 13250c2277SThomas Gleixner#include <linux/linkage.h> 14250c2277SThomas Gleixner#include <linux/threads.h> 15250c2277SThomas Gleixner#include <linux/init.h> 16ca5999fdSMike Rapoport#include <linux/pgtable.h> 1765fddcfcSMike Rapoport#include <asm/segment.h> 18250c2277SThomas Gleixner#include <asm/page.h> 19250c2277SThomas Gleixner#include <asm/msr.h> 20250c2277SThomas Gleixner#include <asm/cache.h> 21369101daSCyrill Gorcunov#include <asm/processor-flags.h> 22b12d8db8STejun Heo#include <asm/percpu.h> 239900aa2fSH. Peter Anvin#include <asm/nops.h> 247bbcdb1cSAndy Lutomirski#include "../entry/calling.h" 25784d5699SAl Viro#include <asm/export.h> 26bd89004fSPeter Zijlstra#include <asm/nospec-branch.h> 2705ab1d8aSFeng Tang#include <asm/fixmap.h> 28250c2277SThomas Gleixner 2975da04f7SThomas Gleixner/* 3075da04f7SThomas Gleixner * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 31250c2277SThomas Gleixner * because we need identity-mapped pages. 32250c2277SThomas Gleixner */ 33b9952ec7SKirill A. Shutemov#define l4_index(x) (((x) >> 39) & 511) 34a6523748SEduardo Habkost#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) 35a6523748SEduardo Habkost 36b9952ec7SKirill A. ShutemovL4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) 37b9952ec7SKirill A. ShutemovL4_START_KERNEL = l4_index(__START_KERNEL_map) 38b9952ec7SKirill A. Shutemov 39a6523748SEduardo HabkostL3_START_KERNEL = pud_index(__START_KERNEL_map) 40a6523748SEduardo Habkost 41250c2277SThomas Gleixner .text 424ae59b91STim Abbott __HEAD 43250c2277SThomas Gleixner .code64 4437818afdSJiri SlabySYM_CODE_START_NOALIGN(startup_64) 452704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 46250c2277SThomas Gleixner /* 471256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 48250c2277SThomas Gleixner * and someone has loaded an identity mapped page table 49250c2277SThomas Gleixner * for us. These identity mapped page tables map all of the 50250c2277SThomas Gleixner * kernel pages and possibly all of memory. 51250c2277SThomas Gleixner * 528170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 53250c2277SThomas Gleixner * 54250c2277SThomas Gleixner * We come here either directly from a 64bit bootloader, or from 555b171e82SAlexander Kuleshov * arch/x86/boot/compressed/head_64.S. 56250c2277SThomas Gleixner * 57250c2277SThomas Gleixner * We only come here initially at boot nothing else comes here. 58250c2277SThomas Gleixner * 59250c2277SThomas Gleixner * Since we may be loaded at an address different from what we were 60250c2277SThomas Gleixner * compiled to run at we first fixup the physical addresses in our page 61250c2277SThomas Gleixner * tables and then reload them. 62250c2277SThomas Gleixner */ 63250c2277SThomas Gleixner 6422dc3918SJosh Poimboeuf /* Set up the stack for verify_cpu(), similar to initial_stack below */ 656627eb25SH. Peter Anvin (Intel) leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp 6691ed140dSBorislav Petkov 67866b556eSJoerg Roedel leaq _text(%rip), %rdi 68866b556eSJoerg Roedel pushq %rsi 69866b556eSJoerg Roedel call startup_64_setup_env 70866b556eSJoerg Roedel popq %rsi 71866b556eSJoerg Roedel 72866b556eSJoerg Roedel /* Now switch to __KERNEL_CS so IRET works reliably */ 73866b556eSJoerg Roedel pushq $__KERNEL_CS 74866b556eSJoerg Roedel leaq .Lon_kernel_cs(%rip), %rax 75866b556eSJoerg Roedel pushq %rax 76866b556eSJoerg Roedel lretq 77866b556eSJoerg Roedel 78866b556eSJoerg Roedel.Lon_kernel_cs: 79866b556eSJoerg Roedel UNWIND_HINT_EMPTY 80866b556eSJoerg Roedel 8104633df0SBorislav Petkov /* Sanitize CPU configuration */ 8204633df0SBorislav Petkov call verify_cpu 8304633df0SBorislav Petkov 845868f365STom Lendacky /* 855868f365STom Lendacky * Perform pagetable fixups. Additionally, if SME is active, encrypt 865868f365STom Lendacky * the kernel and retrieve the modifier (SME encryption mask if SME 875868f365STom Lendacky * is active) to be added to the initial pgdir entry that will be 885868f365STom Lendacky * programmed into CR3. 895868f365STom Lendacky */ 90250c2277SThomas Gleixner leaq _text(%rip), %rdi 91c88d7150SKirill A. Shutemov pushq %rsi 92c88d7150SKirill A. Shutemov call __startup_64 93c88d7150SKirill A. Shutemov popq %rsi 94250c2277SThomas Gleixner 955868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 965868f365STom Lendacky addq $(early_top_pgt - __START_KERNEL_map), %rax 978170e6beSH. Peter Anvin jmp 1f 9837818afdSJiri SlabySYM_CODE_END(startup_64) 9937818afdSJiri Slaby 100bc7b11c0SJiri SlabySYM_CODE_START(secondary_startup_64) 1012704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 1023e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 103250c2277SThomas Gleixner /* 1041256276cSKonrad Rzeszutek Wilk * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 105250c2277SThomas Gleixner * and someone has loaded a mapped page table. 106250c2277SThomas Gleixner * 1078170e6beSH. Peter Anvin * %rsi holds a physical pointer to real_mode_data. 108250c2277SThomas Gleixner * 109250c2277SThomas Gleixner * We come here either from startup_64 (using physical addresses) 110250c2277SThomas Gleixner * or from trampoline.S (using virtual addresses). 111250c2277SThomas Gleixner * 112250c2277SThomas Gleixner * Using virtual addresses from trampoline.S removes the need 113250c2277SThomas Gleixner * to have any identity mapped pages in the kernel page table 114250c2277SThomas Gleixner * after the boot processor executes this code. 115250c2277SThomas Gleixner */ 116250c2277SThomas Gleixner 11704633df0SBorislav Petkov /* Sanitize CPU configuration */ 11804633df0SBorislav Petkov call verify_cpu 11904633df0SBorislav Petkov 1205868f365STom Lendacky /* 1213ecacdbdSJoerg Roedel * The secondary_startup_64_no_verify entry point is only used by 1223ecacdbdSJoerg Roedel * SEV-ES guests. In those guests the call to verify_cpu() would cause 1233ecacdbdSJoerg Roedel * #VC exceptions which can not be handled at this stage of secondary 1243ecacdbdSJoerg Roedel * CPU bringup. 1253ecacdbdSJoerg Roedel * 1263ecacdbdSJoerg Roedel * All non SEV-ES systems, especially Intel systems, need to execute 1273ecacdbdSJoerg Roedel * verify_cpu() above to make sure NX is enabled. 1283ecacdbdSJoerg Roedel */ 1293ecacdbdSJoerg RoedelSYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 1303ecacdbdSJoerg Roedel UNWIND_HINT_EMPTY 1313e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 1323ecacdbdSJoerg Roedel 1333ecacdbdSJoerg Roedel /* 1345868f365STom Lendacky * Retrieve the modifier (SME encryption mask if SME is active) to be 1355868f365STom Lendacky * added to the initial pgdir entry that will be programmed into CR3. 1365868f365STom Lendacky */ 1375868f365STom Lendacky pushq %rsi 1385868f365STom Lendacky call __startup_secondary_64 1395868f365STom Lendacky popq %rsi 1405868f365STom Lendacky 1415868f365STom Lendacky /* Form the CR3 value being sure to include the CR3 modifier */ 1425868f365STom Lendacky addq $(init_top_pgt - __START_KERNEL_map), %rax 1438170e6beSH. Peter Anvin1: 1448170e6beSH. Peter Anvin 145032370b9SKirill A. Shutemov /* Enable PAE mode, PGE and LA57 */ 1468170e6beSH. Peter Anvin movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx 147032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 14839b95522SKirill A. Shutemov testl $1, __pgtable_l5_enabled(%rip) 1496f9dd329SKirill A. Shutemov jz 1f 150032370b9SKirill A. Shutemov orl $X86_CR4_LA57, %ecx 1516f9dd329SKirill A. Shutemov1: 152032370b9SKirill A. Shutemov#endif 1538170e6beSH. Peter Anvin movq %rcx, %cr4 154250c2277SThomas Gleixner 155032370b9SKirill A. Shutemov /* Setup early boot stage 4-/5-level pagetables. */ 156250c2277SThomas Gleixner addq phys_base(%rip), %rax 157c9f09539SJoerg Roedel 158c9f09539SJoerg Roedel /* 159c9f09539SJoerg Roedel * For SEV guests: Verify that the C-bit is correct. A malicious 160c9f09539SJoerg Roedel * hypervisor could lie about the C-bit position to perform a ROP 161c9f09539SJoerg Roedel * attack on the guest by writing to the unencrypted stack and wait for 162c9f09539SJoerg Roedel * the next RET instruction. 163c9f09539SJoerg Roedel * %rsi carries pointer to realmode data and is callee-clobbered. Save 164c9f09539SJoerg Roedel * and restore it. 165c9f09539SJoerg Roedel */ 166c9f09539SJoerg Roedel pushq %rsi 167c9f09539SJoerg Roedel movq %rax, %rdi 168c9f09539SJoerg Roedel call sev_verify_cbit 169c9f09539SJoerg Roedel popq %rsi 170c9f09539SJoerg Roedel 171f154f290SJoerg Roedel /* 172f154f290SJoerg Roedel * Switch to new page-table 173f154f290SJoerg Roedel * 174f154f290SJoerg Roedel * For the boot CPU this switches to early_top_pgt which still has the 175f154f290SJoerg Roedel * indentity mappings present. The secondary CPUs will switch to the 176f154f290SJoerg Roedel * init_top_pgt here, away from the trampoline_pgd and unmap the 177f154f290SJoerg Roedel * indentity mapped ranges. 178f154f290SJoerg Roedel */ 179250c2277SThomas Gleixner movq %rax, %cr3 180250c2277SThomas Gleixner 181f154f290SJoerg Roedel /* 182f154f290SJoerg Roedel * Do a global TLB flush after the CR3 switch to make sure the TLB 183f154f290SJoerg Roedel * entries from the identity mapping are flushed. 184f154f290SJoerg Roedel */ 185f154f290SJoerg Roedel movq %cr4, %rcx 186f154f290SJoerg Roedel movq %rcx, %rax 187f154f290SJoerg Roedel xorq $X86_CR4_PGE, %rcx 188f154f290SJoerg Roedel movq %rcx, %cr4 189f154f290SJoerg Roedel movq %rax, %cr4 190f154f290SJoerg Roedel 191250c2277SThomas Gleixner /* Ensure I am executing from virtual addresses */ 192250c2277SThomas Gleixner movq $1f, %rax 193bd89004fSPeter Zijlstra ANNOTATE_RETPOLINE_SAFE 194250c2277SThomas Gleixner jmp *%rax 195250c2277SThomas Gleixner1: 1962704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 1973e3f0695SPeter Zijlstra ANNOTATE_NOENDBR // above 198250c2277SThomas Gleixner 199e04b8833SJoerg Roedel /* 200e04b8833SJoerg Roedel * We must switch to a new descriptor in kernel space for the GDT 201e04b8833SJoerg Roedel * because soon the kernel won't have access anymore to the userspace 202e04b8833SJoerg Roedel * addresses where we're currently running on. We have to do that here 203e04b8833SJoerg Roedel * because in 32bit we couldn't load a 64bit linear address. 204e04b8833SJoerg Roedel */ 205e04b8833SJoerg Roedel lgdt early_gdt_descr(%rip) 206e04b8833SJoerg Roedel 2077b99819dSJoerg Roedel /* set up data segments */ 2087b99819dSJoerg Roedel xorl %eax,%eax 2097b99819dSJoerg Roedel movl %eax,%ds 2107b99819dSJoerg Roedel movl %eax,%ss 2117b99819dSJoerg Roedel movl %eax,%es 2127b99819dSJoerg Roedel 2137b99819dSJoerg Roedel /* 2147b99819dSJoerg Roedel * We don't really need to load %fs or %gs, but load them anyway 2157b99819dSJoerg Roedel * to kill any stale realmode selectors. This allows execution 2167b99819dSJoerg Roedel * under VT hardware. 2177b99819dSJoerg Roedel */ 2187b99819dSJoerg Roedel movl %eax,%fs 2197b99819dSJoerg Roedel movl %eax,%gs 2207b99819dSJoerg Roedel 2217b99819dSJoerg Roedel /* Set up %gs. 2227b99819dSJoerg Roedel * 2237b99819dSJoerg Roedel * The base of %gs always points to fixed_percpu_data. If the 2247b99819dSJoerg Roedel * stack protector canary is enabled, it is located at %gs:40. 2257b99819dSJoerg Roedel * Note that, on SMP, the boot cpu uses init data section until 2267b99819dSJoerg Roedel * the per cpu areas are set up. 2277b99819dSJoerg Roedel */ 2287b99819dSJoerg Roedel movl $MSR_GS_BASE,%ecx 2297b99819dSJoerg Roedel movl initial_gs(%rip),%eax 2307b99819dSJoerg Roedel movl initial_gs+4(%rip),%edx 2317b99819dSJoerg Roedel wrmsr 2327b99819dSJoerg Roedel 2333add38cbSJoerg Roedel /* 2343add38cbSJoerg Roedel * Setup a boot time stack - Any secondary CPU will have lost its stack 2353add38cbSJoerg Roedel * by now because the cr3-switch above unmaps the real-mode stack 2363add38cbSJoerg Roedel */ 2373add38cbSJoerg Roedel movq initial_stack(%rip), %rsp 2383add38cbSJoerg Roedel 239f5963ba7SJoerg Roedel /* Setup and Load IDT */ 240f5963ba7SJoerg Roedel pushq %rsi 241f5963ba7SJoerg Roedel call early_setup_idt 242f5963ba7SJoerg Roedel popq %rsi 243f5963ba7SJoerg Roedel 244250c2277SThomas Gleixner /* Check if nx is implemented */ 245250c2277SThomas Gleixner movl $0x80000001, %eax 246250c2277SThomas Gleixner cpuid 247250c2277SThomas Gleixner movl %edx,%edi 248250c2277SThomas Gleixner 249250c2277SThomas Gleixner /* Setup EFER (Extended Feature Enable Register) */ 250250c2277SThomas Gleixner movl $MSR_EFER, %ecx 251250c2277SThomas Gleixner rdmsr 252250c2277SThomas Gleixner btsl $_EFER_SCE, %eax /* Enable System Call */ 253250c2277SThomas Gleixner btl $20,%edi /* No Execute supported? */ 254250c2277SThomas Gleixner jnc 1f 255250c2277SThomas Gleixner btsl $_EFER_NX, %eax 25678d77df7SH. Peter Anvin btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 257250c2277SThomas Gleixner1: wrmsr /* Make changes effective */ 258250c2277SThomas Gleixner 259250c2277SThomas Gleixner /* Setup cr0 */ 260369101daSCyrill Gorcunov movl $CR0_STATE, %eax 261250c2277SThomas Gleixner /* Make changes effective */ 262250c2277SThomas Gleixner movq %rax, %cr0 263250c2277SThomas Gleixner 264250c2277SThomas Gleixner /* zero EFLAGS after setting rsp */ 265250c2277SThomas Gleixner pushq $0 266250c2277SThomas Gleixner popfq 267250c2277SThomas Gleixner 2688170e6beSH. Peter Anvin /* rsi is pointer to real mode structure with interesting info. 269250c2277SThomas Gleixner pass it to C */ 2708170e6beSH. Peter Anvin movq %rsi, %rdi 271250c2277SThomas Gleixner 27279d243a0SBorislav Petkov.Ljump_to_C_code: 273a9468df5SJosh Poimboeuf /* 274a9468df5SJosh Poimboeuf * Jump to run C code and to be on a real kernel address. 275250c2277SThomas Gleixner * Since we are running on identity-mapped space we have to jump 276250c2277SThomas Gleixner * to the full 64bit address, this is only possible as indirect 277250c2277SThomas Gleixner * jump. In addition we need to ensure %cs is set so we make this 278250c2277SThomas Gleixner * a far return. 2798170e6beSH. Peter Anvin * 2808170e6beSH. Peter Anvin * Note: do not change to far jump indirect with 64bit offset. 2818170e6beSH. Peter Anvin * 2828170e6beSH. Peter Anvin * AMD does not support far jump indirect with 64bit offset. 2838170e6beSH. Peter Anvin * AMD64 Architecture Programmer's Manual, Volume 3: states only 2848170e6beSH. Peter Anvin * JMP FAR mem16:16 FF /5 Far jump indirect, 2858170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2868170e6beSH. Peter Anvin * JMP FAR mem16:32 FF /5 Far jump indirect, 2878170e6beSH. Peter Anvin * with the target specified by a far pointer in memory. 2888170e6beSH. Peter Anvin * 2898170e6beSH. Peter Anvin * Intel64 does support 64bit offset. 2908170e6beSH. Peter Anvin * Software Developer Manual Vol 2: states: 2918170e6beSH. Peter Anvin * FF /5 JMP m16:16 Jump far, absolute indirect, 2928170e6beSH. Peter Anvin * address given in m16:16 2938170e6beSH. Peter Anvin * FF /5 JMP m16:32 Jump far, absolute indirect, 2948170e6beSH. Peter Anvin * address given in m16:32. 2958170e6beSH. Peter Anvin * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, 2968170e6beSH. Peter Anvin * address given in m16:64. 297250c2277SThomas Gleixner */ 29831dcfec1SJosh Poimboeuf pushq $.Lafter_lret # put return address on stack for unwinder 299a7bea830SJan Beulich xorl %ebp, %ebp # clear frame pointer 300250c2277SThomas Gleixner movq initial_code(%rip), %rax 301250c2277SThomas Gleixner pushq $__KERNEL_CS # set correct cs 302250c2277SThomas Gleixner pushq %rax # target address in negative space 303250c2277SThomas Gleixner lretq 30431dcfec1SJosh Poimboeuf.Lafter_lret: 3053e3f0695SPeter Zijlstra ANNOTATE_NOENDBR 306bc7b11c0SJiri SlabySYM_CODE_END(secondary_startup_64) 307250c2277SThomas Gleixner 30804633df0SBorislav Petkov#include "verify_cpu.S" 309c9f09539SJoerg Roedel#include "sev_verify_cbit.S" 31004633df0SBorislav Petkov 31142e78e97SFenghua Yu#ifdef CONFIG_HOTPLUG_CPU 31242e78e97SFenghua Yu/* 31342e78e97SFenghua Yu * Boot CPU0 entry point. It's called from play_dead(). Everything has been set 31442e78e97SFenghua Yu * up already except stack. We just set up stack here. Then call 31579d243a0SBorislav Petkov * start_secondary() via .Ljump_to_C_code. 31642e78e97SFenghua Yu */ 317bc7b11c0SJiri SlabySYM_CODE_START(start_cpu0) 3182704fbb6SJosh Poimboeuf UNWIND_HINT_EMPTY 31961a73f5cSJosh Poimboeuf movq initial_stack(%rip), %rsp 32079d243a0SBorislav Petkov jmp .Ljump_to_C_code 321bc7b11c0SJiri SlabySYM_CODE_END(start_cpu0) 32242e78e97SFenghua Yu#endif 32342e78e97SFenghua Yu 3241aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 3251aa9aa8eSJoerg Roedel/* 3261aa9aa8eSJoerg Roedel * VC Exception handler used during early boot when running on kernel 3271aa9aa8eSJoerg Roedel * addresses, but before the switch to the idt_table can be made. 3281aa9aa8eSJoerg Roedel * The early_idt_handler_array can't be used here because it calls into a lot 3291aa9aa8eSJoerg Roedel * of __init code and this handler is also used during CPU offlining/onlining. 3301aa9aa8eSJoerg Roedel * Therefore this handler ends up in the .text section so that it stays around 3311aa9aa8eSJoerg Roedel * when .init.text is freed. 3321aa9aa8eSJoerg Roedel */ 3331aa9aa8eSJoerg RoedelSYM_CODE_START_NOALIGN(vc_boot_ghcb) 3341aa9aa8eSJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 335*e8d61bdfSPeter Zijlstra ENDBR 3361aa9aa8eSJoerg Roedel 3371aa9aa8eSJoerg Roedel /* Build pt_regs */ 3381aa9aa8eSJoerg Roedel PUSH_AND_CLEAR_REGS 3391aa9aa8eSJoerg Roedel 3401aa9aa8eSJoerg Roedel /* Call C handler */ 3411aa9aa8eSJoerg Roedel movq %rsp, %rdi 3421aa9aa8eSJoerg Roedel movq ORIG_RAX(%rsp), %rsi 3431aa9aa8eSJoerg Roedel movq initial_vc_handler(%rip), %rax 3441aa9aa8eSJoerg Roedel ANNOTATE_RETPOLINE_SAFE 3451aa9aa8eSJoerg Roedel call *%rax 3461aa9aa8eSJoerg Roedel 3471aa9aa8eSJoerg Roedel /* Unwind pt_regs */ 3481aa9aa8eSJoerg Roedel POP_REGS 3491aa9aa8eSJoerg Roedel 3501aa9aa8eSJoerg Roedel /* Remove Error Code */ 3511aa9aa8eSJoerg Roedel addq $8, %rsp 3521aa9aa8eSJoerg Roedel 3531aa9aa8eSJoerg Roedel iretq 3541aa9aa8eSJoerg RoedelSYM_CODE_END(vc_boot_ghcb) 3551aa9aa8eSJoerg Roedel#endif 3561aa9aa8eSJoerg Roedel 357b32f96c7SJosh Poimboeuf /* Both SMP bootup and ACPI suspend change these variables */ 358da5968aeSSam Ravnborg __REFDATA 3598170e6beSH. Peter Anvin .balign 8 360b1bd27b9SJiri SlabySYM_DATA(initial_code, .quad x86_64_start_kernel) 361b1bd27b9SJiri SlabySYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) 3621aa9aa8eSJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 3631aa9aa8eSJoerg RoedelSYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 3641aa9aa8eSJoerg Roedel#endif 365b1bd27b9SJiri Slaby 36622dc3918SJosh Poimboeuf/* 3676627eb25SH. Peter Anvin (Intel) * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder 368b1bd27b9SJiri Slaby * reliably detect the end of the stack. 36922dc3918SJosh Poimboeuf */ 3706627eb25SH. Peter Anvin (Intel)SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) 371b9af7c0dSSuresh Siddha __FINITDATA 372250c2277SThomas Gleixner 3738170e6beSH. Peter Anvin __INIT 374bc7b11c0SJiri SlabySYM_CODE_START(early_idt_handler_array) 375749c970aSAndi Kleen i = 0 376749c970aSAndi Kleen .rept NUM_EXCEPTION_VECTORS 37782c62fa0SJosh Poimboeuf .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 3782704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 3798f93402bSPeter Zijlstra ENDBR 3809900aa2fSH. Peter Anvin pushq $0 # Dummy error code, to make stack frame uniform 3812704fbb6SJosh Poimboeuf .else 3822704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS offset=8 3838f93402bSPeter Zijlstra ENDBR 3849900aa2fSH. Peter Anvin .endif 3859900aa2fSH. Peter Anvin pushq $i # 72(%rsp) Vector number 386cdeb6048SAndy Lutomirski jmp early_idt_handler_common 3872704fbb6SJosh Poimboeuf UNWIND_HINT_IRET_REGS 388749c970aSAndi Kleen i = i + 1 389cdeb6048SAndy Lutomirski .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 390749c970aSAndi Kleen .endr 391bc7b11c0SJiri SlabySYM_CODE_END(early_idt_handler_array) 3925b2fc515SPeter Zijlstra ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 3938866cd9dSRoland McGrath 394ef77e688SJiri SlabySYM_CODE_START_LOCAL(early_idt_handler_common) 3958f93402bSPeter Zijlstra UNWIND_HINT_IRET_REGS offset=16 396cdeb6048SAndy Lutomirski /* 397cdeb6048SAndy Lutomirski * The stack is the hardware frame, an error code or zero, and the 398cdeb6048SAndy Lutomirski * vector number. 399cdeb6048SAndy Lutomirski */ 4009900aa2fSH. Peter Anvin cld 4019900aa2fSH. Peter Anvin 402250c2277SThomas Gleixner incl early_recursion_flag(%rip) 4039900aa2fSH. Peter Anvin 4047bbcdb1cSAndy Lutomirski /* The vector number is currently in the pt_regs->di slot. */ 4057bbcdb1cSAndy Lutomirski pushq %rsi /* pt_regs->si */ 4067bbcdb1cSAndy Lutomirski movq 8(%rsp), %rsi /* RSI = vector number */ 4077bbcdb1cSAndy Lutomirski movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 4087bbcdb1cSAndy Lutomirski pushq %rdx /* pt_regs->dx */ 4097bbcdb1cSAndy Lutomirski pushq %rcx /* pt_regs->cx */ 4107bbcdb1cSAndy Lutomirski pushq %rax /* pt_regs->ax */ 4117bbcdb1cSAndy Lutomirski pushq %r8 /* pt_regs->r8 */ 4127bbcdb1cSAndy Lutomirski pushq %r9 /* pt_regs->r9 */ 4137bbcdb1cSAndy Lutomirski pushq %r10 /* pt_regs->r10 */ 4147bbcdb1cSAndy Lutomirski pushq %r11 /* pt_regs->r11 */ 4157bbcdb1cSAndy Lutomirski pushq %rbx /* pt_regs->bx */ 4167bbcdb1cSAndy Lutomirski pushq %rbp /* pt_regs->bp */ 4177bbcdb1cSAndy Lutomirski pushq %r12 /* pt_regs->r12 */ 4187bbcdb1cSAndy Lutomirski pushq %r13 /* pt_regs->r13 */ 4197bbcdb1cSAndy Lutomirski pushq %r14 /* pt_regs->r14 */ 4207bbcdb1cSAndy Lutomirski pushq %r15 /* pt_regs->r15 */ 4212704fbb6SJosh Poimboeuf UNWIND_HINT_REGS 4229900aa2fSH. Peter Anvin 4237bbcdb1cSAndy Lutomirski movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 4244b47cdbdSJoerg Roedel call do_early_exception 4259900aa2fSH. Peter Anvin 4269900aa2fSH. Peter Anvin decl early_recursion_flag(%rip) 42726c4ef9cSAndy Lutomirski jmp restore_regs_and_return_to_kernel 428ef77e688SJiri SlabySYM_CODE_END(early_idt_handler_common) 4299900aa2fSH. Peter Anvin 43074d8d9d5SJoerg Roedel#ifdef CONFIG_AMD_MEM_ENCRYPT 43174d8d9d5SJoerg Roedel/* 43274d8d9d5SJoerg Roedel * VC Exception handler used during very early boot. The 43374d8d9d5SJoerg Roedel * early_idt_handler_array can't be used because it returns via the 43474d8d9d5SJoerg Roedel * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 43574d8d9d5SJoerg Roedel * 4368b87d8ceSPeter Zijlstra * XXX it does, fix this. 4378b87d8ceSPeter Zijlstra * 43874d8d9d5SJoerg Roedel * This handler will end up in the .init.text section and not be 43974d8d9d5SJoerg Roedel * available to boot secondary CPUs. 44074d8d9d5SJoerg Roedel */ 44174d8d9d5SJoerg RoedelSYM_CODE_START_NOALIGN(vc_no_ghcb) 44274d8d9d5SJoerg Roedel UNWIND_HINT_IRET_REGS offset=8 443*e8d61bdfSPeter Zijlstra ENDBR 44474d8d9d5SJoerg Roedel 44574d8d9d5SJoerg Roedel /* Build pt_regs */ 44674d8d9d5SJoerg Roedel PUSH_AND_CLEAR_REGS 44774d8d9d5SJoerg Roedel 44874d8d9d5SJoerg Roedel /* Call C handler */ 44974d8d9d5SJoerg Roedel movq %rsp, %rdi 45074d8d9d5SJoerg Roedel movq ORIG_RAX(%rsp), %rsi 45174d8d9d5SJoerg Roedel call do_vc_no_ghcb 45274d8d9d5SJoerg Roedel 45374d8d9d5SJoerg Roedel /* Unwind pt_regs */ 45474d8d9d5SJoerg Roedel POP_REGS 45574d8d9d5SJoerg Roedel 45674d8d9d5SJoerg Roedel /* Remove Error Code */ 45774d8d9d5SJoerg Roedel addq $8, %rsp 45874d8d9d5SJoerg Roedel 45974d8d9d5SJoerg Roedel /* Pure iret required here - don't use INTERRUPT_RETURN */ 46074d8d9d5SJoerg Roedel iretq 46174d8d9d5SJoerg RoedelSYM_CODE_END(vc_no_ghcb) 46274d8d9d5SJoerg Roedel#endif 463b1bd27b9SJiri Slaby 464b1bd27b9SJiri Slaby#define SYM_DATA_START_PAGE_ALIGNED(name) \ 465b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) 466250c2277SThomas Gleixner 467d9e9a641SDave Hansen#ifdef CONFIG_PAGE_TABLE_ISOLATION 468d9e9a641SDave Hansen/* 469d9e9a641SDave Hansen * Each PGD needs to be 8k long and 8k aligned. We do not 470d9e9a641SDave Hansen * ever go out to userspace with these, so we do not 471d9e9a641SDave Hansen * strictly *need* the second page, but this allows us to 472d9e9a641SDave Hansen * have a single set_pgd() implementation that does not 473d9e9a641SDave Hansen * need to worry about whether it has 4k or 8k to work 474d9e9a641SDave Hansen * with. 475d9e9a641SDave Hansen * 476d9e9a641SDave Hansen * This ensures PGDs are 8k long: 477d9e9a641SDave Hansen */ 478d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 512 479d9e9a641SDave Hansen/* This ensures they are 8k-aligned: */ 480b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 481b1bd27b9SJiri Slaby SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 482d9e9a641SDave Hansen#else 483b1bd27b9SJiri Slaby#define SYM_DATA_START_PTI_ALIGNED(name) \ 484b1bd27b9SJiri Slaby SYM_DATA_START_PAGE_ALIGNED(name) 485d9e9a641SDave Hansen#define PTI_USER_PGD_FILL 0 486d9e9a641SDave Hansen#endif 487d9e9a641SDave Hansen 488250c2277SThomas Gleixner/* Automate the creation of 1 to 1 mapping pmd entries */ 489250c2277SThomas Gleixner#define PMDS(START, PERM, COUNT) \ 490250c2277SThomas Gleixner i = 0 ; \ 491250c2277SThomas Gleixner .rept (COUNT) ; \ 4920e192b99SCyrill Gorcunov .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ 493250c2277SThomas Gleixner i = i + 1 ; \ 494250c2277SThomas Gleixner .endr 495250c2277SThomas Gleixner 4968170e6beSH. Peter Anvin __INITDATA 4971a8770b7SJiri Slaby .balign 4 4981a8770b7SJiri Slaby 499b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(early_top_pgt) 5006f9dd329SKirill A. Shutemov .fill 512,8,0 501d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 502b1bd27b9SJiri SlabySYM_DATA_END(early_top_pgt) 5038170e6beSH. Peter Anvin 504b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 5058170e6beSH. Peter Anvin .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 506b1bd27b9SJiri SlabySYM_DATA_END(early_dynamic_pgts) 5078170e6beSH. Peter Anvin 508b1bd27b9SJiri SlabySYM_DATA(early_recursion_flag, .long 0) 5091a8770b7SJiri Slaby 510b9af7c0dSSuresh Siddha .data 5118170e6beSH. Peter Anvin 5127733607fSMaran Wilson#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 513b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 51421729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 515b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_PAGE_OFFSET*8, 0 51621729f81STom Lendacky .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 517b9952ec7SKirill A. Shutemov .org init_top_pgt + L4_START_KERNEL*8, 0 518250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 51921729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 520d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 521b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 522250c2277SThomas Gleixner 523b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 52421729f81STom Lendacky .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 525250c2277SThomas Gleixner .fill 511, 8, 0 526b1bd27b9SJiri SlabySYM_DATA_END(level3_ident_pgt) 527b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 528430d4005SDave Hansen /* 529430d4005SDave Hansen * Since I easily can, map the first 1G. 5308170e6beSH. Peter Anvin * Don't set NX because code runs from these pages. 531430d4005SDave Hansen * 532430d4005SDave Hansen * Note: This sets _PAGE_GLOBAL despite whether 533430d4005SDave Hansen * the CPU supports it or it is enabled. But, 534430d4005SDave Hansen * the CPU should ignore the bit. 5358170e6beSH. Peter Anvin */ 5368170e6beSH. Peter Anvin PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 537b1bd27b9SJiri SlabySYM_DATA_END(level2_ident_pgt) 5384375c299SKirill A. Shutemov#else 539b1bd27b9SJiri SlabySYM_DATA_START_PTI_ALIGNED(init_top_pgt) 5404375c299SKirill A. Shutemov .fill 512,8,0 541d9e9a641SDave Hansen .fill PTI_USER_PGD_FILL,8,0 542b1bd27b9SJiri SlabySYM_DATA_END(init_top_pgt) 5438170e6beSH. Peter Anvin#endif 544250c2277SThomas Gleixner 545032370b9SKirill A. Shutemov#ifdef CONFIG_X86_5LEVEL 546b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 547032370b9SKirill A. Shutemov .fill 511,8,0 54821729f81STom Lendacky .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 549b1bd27b9SJiri SlabySYM_DATA_END(level4_kernel_pgt) 550032370b9SKirill A. Shutemov#endif 551032370b9SKirill A. Shutemov 552b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 553a6523748SEduardo Habkost .fill L3_START_KERNEL,8,0 554250c2277SThomas Gleixner /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 55521729f81STom Lendacky .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 55621729f81STom Lendacky .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 557b1bd27b9SJiri SlabySYM_DATA_END(level3_kernel_pgt) 558250c2277SThomas Gleixner 559b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 56088f3aec7SIngo Molnar /* 561ea3186b9SArvind Sankar * Kernel high mapping. 56288f3aec7SIngo Molnar * 563ea3186b9SArvind Sankar * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 564ea3186b9SArvind Sankar * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 565ea3186b9SArvind Sankar * 512 MiB otherwise. 56688f3aec7SIngo Molnar * 567ea3186b9SArvind Sankar * (NOTE: after that starts the module area, see MODULES_VADDR.) 568430d4005SDave Hansen * 569ea3186b9SArvind Sankar * This table is eventually used by the kernel during normal runtime. 570ea3186b9SArvind Sankar * Care must be taken to clear out undesired bits later, like _PAGE_RW 571ea3186b9SArvind Sankar * or _PAGE_GLOBAL in some cases. 57288f3aec7SIngo Molnar */ 573ea3186b9SArvind Sankar PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 574b1bd27b9SJiri SlabySYM_DATA_END(level2_kernel_pgt) 575250c2277SThomas Gleixner 576b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 57705ab1d8aSFeng Tang .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 57805ab1d8aSFeng Tang pgtno = 0 57905ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 58005ab1d8aSFeng Tang .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 58105ab1d8aSFeng Tang + _PAGE_TABLE_NOENC; 58205ab1d8aSFeng Tang pgtno = pgtno + 1 58305ab1d8aSFeng Tang .endr 58405ab1d8aSFeng Tang /* 6 MB reserved space + a 2MB hole */ 58505ab1d8aSFeng Tang .fill 4,8,0 586b1bd27b9SJiri SlabySYM_DATA_END(level2_fixmap_pgt) 5878170e6beSH. Peter Anvin 588b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 58905ab1d8aSFeng Tang .rept (FIXMAP_PMD_NUM) 590250c2277SThomas Gleixner .fill 512,8,0 59105ab1d8aSFeng Tang .endr 592b1bd27b9SJiri SlabySYM_DATA_END(level1_fixmap_pgt) 593250c2277SThomas Gleixner 594250c2277SThomas Gleixner#undef PMDS 595250c2277SThomas Gleixner 596250c2277SThomas Gleixner .data 597250c2277SThomas Gleixner .align 16 598250c2277SThomas Gleixner 599b1bd27b9SJiri SlabySYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) 600b1bd27b9SJiri SlabySYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) 601b1bd27b9SJiri Slaby 602b1bd27b9SJiri Slaby .align 16 603250c2277SThomas Gleixner/* This must match the first entry in level2_kernel_pgt */ 604b1bd27b9SJiri SlabySYM_DATA(phys_base, .quad 0x0) 605784d5699SAl ViroEXPORT_SYMBOL(phys_base) 606250c2277SThomas Gleixner 6078c5e5ac3SJeremy Fitzhardinge#include "../../x86/xen/xen-head.S" 608250c2277SThomas Gleixner 60902b7da37STim Abbott __PAGE_ALIGNED_BSS 610b1bd27b9SJiri SlabySYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 611250c2277SThomas Gleixner .skip PAGE_SIZE 612b1bd27b9SJiri SlabySYM_DATA_END(empty_zero_page) 613784d5699SAl ViroEXPORT_SYMBOL(empty_zero_page) 614ef7f0d6aSAndrey Ryabinin 615